diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2009-07-17 17:08:34 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2009-07-17 17:08:34 +0000 |
| commit | 9afe6eb82f6abc63f7235771b803497ebb6455f2 (patch) | |
| tree | cd91bf01f591fd19d99c73c129e3c21e8f31d100 /gas | |
| parent | 831a0c44472cd3c9933a6e0d2d55d4c9d68f0645 (diff) | |
| download | gdb-9afe6eb82f6abc63f7235771b803497ebb6455f2.zip gdb-9afe6eb82f6abc63f7235771b803497ebb6455f2.tar.gz gdb-9afe6eb82f6abc63f7235771b803497ebb6455f2.tar.bz2 | |
2009-07-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Check implicit registers
only for instructions with 3 operands or less.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 15 |
2 files changed, 14 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 576c858..dba01f6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2009-07-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (md_assemble): Check implicit registers + only for instructions with 3 operands or less. + 2009-07-17 Nick Clifton <nickc@redhat.com> * config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index f4660b4..0862ab0 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2821,12 +2821,15 @@ md_assemble (char *line) if (i.types[0].bitfield.imm1) i.imm_operands = 0; /* kludge for shift insns. */ - for (j = 0; j < i.operands; j++) - if (i.types[j].bitfield.inoutportreg - || i.types[j].bitfield.shiftcount - || i.types[j].bitfield.acc - || i.types[j].bitfield.floatacc) - i.reg_operands--; + /* We only need to check those implicit registers for instructions + with 3 operands or less. */ + if (i.operands <= 3) + for (j = 0; j < i.operands; j++) + if (i.types[j].bitfield.inoutportreg + || i.types[j].bitfield.shiftcount + || i.types[j].bitfield.acc + || i.types[j].bitfield.floatacc) + i.reg_operands--; /* ImmExt should be processed after SSE2AVX. */ if (!i.tm.opcode_modifier.sse2avx |