Add support for unindexed form of Addressing Mode 5

6 files changed, 150 insertions, 9 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c8b45f9..b6662d4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-19  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (cp_address_required_here): Add code to handle
+	unindexed addressing mode.
+
 2003-08-19  Alan Modra  <amodra@bigpond.net.au>
 
 	* config/tc-ppc.c (md_parse_option): Handle -m440.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 907191a..948c699 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -3329,22 +3329,96 @@ cp_address_required_here (str, wb_ok)
 	{
 	  p++;
 
-	  if (wb_ok && skip_past_comma (& p) == SUCCESS)
+	  skip_whitespace (p);
+
+	  if (*p == '\0')
 	    {
-	      /* [Rn], #expr  */
-	      write_back = WRITE_BACK;
+	      /* As an extension to the official ARM syntax we allow:
+		 
+		   [Rn]
+		   
+	         as a short hand for:
+
+		   [Rn,#0]  */
+	      inst.instruction |= PRE_INDEX | INDEX_UP;
+	      *str = p;
+	      return SUCCESS;
+	    }
+	  
+	  if (skip_past_comma (& p) == FAIL)
+	    {
+	      inst.error = _("comma expected after closing square bracket");
+	      return FAIL;
+	    }
 
-	      if (reg == REG_PC)
+	  skip_whitespace (p);
+
+	  if (*p == '#')
+	    {
+	      if (wb_ok)
 		{
-		  inst.error = _("pc may not be used in post-increment");
-		  return FAIL;
+		  /* [Rn], #expr  */
+		  write_back = WRITE_BACK;
+
+		  if (reg == REG_PC)
+		    {
+		      inst.error = _("pc may not be used in post-increment");
+		      return FAIL;
+		    }
+
+		  if (cp_address_offset (& p) == FAIL)
+		    return FAIL;
 		}
+	      else
+		pre_inc = PRE_INDEX | INDEX_UP;
+	    }
+	  else if (*p == '{')
+	    {
+	      int option;
 
-	      if (cp_address_offset (& p) == FAIL)
+	      /* [Rn], {<expr>}  */
+	      p++;
+
+	      skip_whitespace (p);
+
+	      if (my_get_expression (& inst.reloc.exp, & p))
 		return FAIL;
+
+	      if (inst.reloc.exp.X_op == O_constant)
+		{
+		  option = inst.reloc.exp.X_add_number;
+
+		  if (option > 255 || option < 0)
+		    {
+		      inst.error = _("'option' field too large");
+		      return FAIL;
+		    }
+
+		  skip_whitespace (p);
+
+		  if (*p != '}')
+		    {
+		      inst.error = _("'}' expected at end of 'option' field");
+		      return FAIL;
+		    }
+		  else
+		    {
+		      p++;
+		      inst.instruction |= option;
+		      inst.instruction |= INDEX_UP;
+		    }
+		}
+	      else
+		{
+		  inst.error = _("non-constant expressions for 'option' field not supported");
+		  return FAIL;
+		}
 	    }
 	  else
-	    pre_inc = PRE_INDEX | INDEX_UP;
+	    {
+	      inst.error = _("# or { expected after comma");
+	      return FAIL;	      
+	    }
 	}
       else
 	{
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 160a222..e068922 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-08-19  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/copro.s: Add tests of Addressing Mode 5 (Unindexed).
+	* gas/arm/arm.exp: Run copro.s as a dump test.
+	* gas/arm/copro.d: New file: expected disassembly of copro.s
+
 2003-08-16  Jason Eckhardt  <jle@rice.edu>
 
 	* gas/i860/pseudo-ops01.{s,d}: New files.
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index d721501..0db080b 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -40,7 +40,7 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
 
     run_dump_test "arch5tej"
 
-    gas_test "copro.s" "" $stdoptlist "Co processor instructions"
+    run_dump_test "copro"
 
     gas_test "immed.s" "" $stdoptlist "immediate expressions"
 
diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
new file mode 100644
index 0000000..ea2282c
--- /dev/null
+++ b/gas/testsuite/gas/arm/copro.d
@@ -0,0 +1,39 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM CoProcessor Instructions
+#as: -march=armv5te -EL
+
+# Test the standard ARM co-processor instructions:
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
+0+004 <[^>]*> 0e3414a5 	cfadddeq	mvd1, mvd4, mvd5
+0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
+0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
+0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
+0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
+0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, -#4\]
+0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
+0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
+0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!
+0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48
+0+02c <[^>]*> ed0f7101 	stfs	f7, \[pc, -#4\]
+0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
+0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
+0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
+0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
+0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
+0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
+0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
+0+04c <[^>]*> fc834603 	stc2	6, cr4, \[r3\], \{3\}
+0+050 <[^>]*> ecd43704 	ldcl	7, cr3, \[r4\], \{4\}
+0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
+0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
+0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
+0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
+0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
+0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
+0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
+0+070 <[^>]*> ec507fff 	mrrc	15, 15, r7, r0, cr15
+0+074 <[^>]*> ec407efe 	mcrr	14, 15, r7, r0, cr14
diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s
index 46c9b92..af3440d 100644
--- a/gas/testsuite/gas/arm/copro.s
+++ b/gas/testsuite/gas/arm/copro.s
@@ -22,3 +22,20 @@ bar:
 
 	mcr	p7, 1, r15, cr1, cr1
 	mcrlt	5, 1, r8, cr2, cr9, 0
+
+	@ The following patterns test Addressing Mode 5 "Unindexed"
+	
+        ldc     3,   c7, [r0], {0}
+        stc     p14, c6, [r1], {1}
+        ldc2    5,   c5, [r2], {2}
+        stc2    p6,  c4, [r3], {3}
+        ldcl    7,   c3, [r4], {4}
+        stcl    p8,  c2, [r5], {5}
+        ldc2l   9,   c1, [r6], {6}
+        stc2l   p10, c0, [r7], {7}
+        ldcl    11,  c8, [r8], {255}
+        stcl    p12, c9, [r9], {254}
+        mrrc    13,   0, r7, r0, cr4
+        mcrr    p14,  0, r7, r0, cr5
+        mrrc    15,  15, r7, r0, cr15
+        mcrr    p14, 15, r7, r0, cr14