[ gas/ChangeLog ]

2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
	(mips_opts): Initialize "ase_mdmx" member.
	(file_ase_mdmx): New variable.
	(CPU_HAS_MDMX): New macro.
	(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
	based on command line options and configuration defaults.
	(macro_build): Note in comment that use of MDMX in macros is
	not currently allowed.
	(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
	"Z" MDMX operand types.
	(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
	and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
	types.
	(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
	Add support for "-mdmx" and "-no-mdmx" options.
	(OPTION_ELF_BASE): Move to accomodate new options.
	(s_mipsset): Support ".set mdmx" and ".set nomdmx".
	(mips_elf_final_processing): Set MDMX ASE ELF header flag if
	file_ase_mdmx was set.
	* doc/as.texinfo: Document -mdmx and -no-mdmx options.
	* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
	nomdmx" directives.

[ gas/testsuite/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* gas/mips/mips64-mdmx.s: New file.
	* gas/mips/mips64-mdmx.d: Likewise.
	* gas/mips/mips.exp: Run new "mips64-mdmx" test.

[ include/opcode/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
	(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
	(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
	(INSN_MDMX): New constants, for MDMX support.
	(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.

[ opcodes/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
	and 'Z' formats, for MDMX.
        (mips_isa_type): Add MDMX instructions to the ISA
	bit mask for bfd_mach_mipsisa64.
	* mips-opc.c: Add support for MDMX instructions.
	(MX): New definition.

	* mips-dis.c: Update copyright years to include 2002.

8 files changed, 695 insertions, 6 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index da7c4b8..3c281f8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,29 @@
+2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
+            Ed Satterthwaite  <ehs@broadcom.com>
+
+	* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
+	(mips_opts): Initialize "ase_mdmx" member.
+	(file_ase_mdmx): New variable.
+	(CPU_HAS_MDMX): New macro.
+	(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
+	based on command line options and configuration defaults.
+	(macro_build): Note in comment that use of MDMX in macros is
+	not currently allowed.
+	(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
+	"Z" MDMX operand types.
+	(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
+	and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
+	types.
+	(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
+	Add support for "-mdmx" and "-no-mdmx" options.
+	(OPTION_ELF_BASE): Move to accomodate new options.
+	(s_mipsset): Support ".set mdmx" and ".set nomdmx".
+	(mips_elf_final_processing): Set MDMX ASE ELF header flag if
+	file_ase_mdmx was set.
+	* doc/as.texinfo: Document -mdmx and -no-mdmx options.
+	* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
+	nomdmx" directives.
+
 2002-05-31  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
 
 	* config/tc-mips.c (OPTION_NO_M7000_HILO_FIX): Rename to
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 02ec3f1..c742089 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -141,6 +141,7 @@ struct mips_set_options
      if they have not been initialized.  Changed by `.set <asename>', by
      command line options, and based on the default architecture.  */
   int ase_mips3d;
+  int ase_mdmx;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
      Changed by `.set mips16' and `.set nomips16', and the -mips16 and
@@ -189,7 +190,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
+  ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -205,6 +206,10 @@ static int file_mips_isa = ISA_UNKNOWN;
    command line (e.g., by -march).  */
 static int file_ase_mips3d;
 
+/* True if -mdmx was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_mdmx;
+
 /* The argument of the -mcpu= flag.  Historical for code generation.  */
 static int mips_cpu = CPU_UNKNOWN;
 
@@ -275,6 +280,10 @@ static int mips_32bitmode = 0;
 #define CPU_HAS_MIPS3D(cpu)	((cpu) == CPU_SB1      \
 				 )
 
+/* Return true if the given CPU supports the MDMX ASE.  */
+#define CPU_HAS_MDMX(cpu)	(0		      \
+				 )
+
 /* Whether the processor uses hardware interlocks to protect
    reads from the HI and LO registers, and thus does not
    require nops to be inserted.  */
@@ -1241,6 +1250,8 @@ md_begin ()
      generation of code for them.  */
   if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
     mips_opts.ase_mips3d = 1;
+  if (mips_opts.ase_mdmx == -1 && CPU_HAS_MDMX (mips_arch))
+    mips_opts.ase_mdmx = 1;
 
   if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
     as_warn (_("Could not set architecture and machine"));
@@ -1253,6 +1264,7 @@ md_begin ()
   file_mips_isa = mips_opts.isa;
   file_mips_abi = mips_opts.abi;
   file_ase_mips3d = mips_opts.ase_mips3d;
+  file_ase_mdmx = mips_opts.ase_mdmx;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
 
@@ -2917,8 +2929,8 @@ macro_build (place, counter, ep, name, fmt, va_alist)
   /* Search until we get a match for NAME.  */
   while (1)
     {
-      /* It is assumed here that macros will never generate
-         MIPS-3D instructions.  */
+      /* It is assumed here that macros will never generate 
+         MDMX or MIPS-3D instructions.  */
       if (strcmp (fmt, insn.insn_mo->args) == 0
 	  && insn.insn_mo->pinfo != INSN_MACRO
 	  && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
@@ -7795,11 +7807,17 @@ validate_mips_insn (opc)
       case 'L': break;
       case 'M':	USE_BITS (OP_MASK_CCC,		OP_SH_CCC);	break;
       case 'N':	USE_BITS (OP_MASK_BCC,		OP_SH_BCC);	break;
+      case 'O':	USE_BITS (OP_MASK_ALN,		OP_SH_ALN);	break;
+      case 'Q':	USE_BITS (OP_MASK_VSEL,		OP_SH_VSEL);
+		USE_BITS (OP_MASK_FT,		OP_SH_FT);	break;
       case 'R':	USE_BITS (OP_MASK_FR,		OP_SH_FR);	break;
       case 'S':	USE_BITS (OP_MASK_FS,		OP_SH_FS);	break;
       case 'T':	USE_BITS (OP_MASK_FT,		OP_SH_FT);	break;
       case 'V':	USE_BITS (OP_MASK_FS,		OP_SH_FS);	break;
       case 'W':	USE_BITS (OP_MASK_FT,		OP_SH_FT);	break;
+      case 'X':	USE_BITS (OP_MASK_FD,		OP_SH_FD);	break;
+      case 'Y':	USE_BITS (OP_MASK_FS,		OP_SH_FS);	break;
+      case 'Z':	USE_BITS (OP_MASK_FT,		OP_SH_FT);	break;
       case 'a':	USE_BITS (OP_MASK_TARGET,	OP_SH_TARGET);	break;
       case 'b':	USE_BITS (OP_MASK_RS,		OP_SH_RS);	break;
       case 'c':	USE_BITS (OP_MASK_CODE,		OP_SH_CODE);	break;
@@ -7918,6 +7936,7 @@ mips_ip (str, ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
 			    mips_arch))
 	ok = true;
@@ -7961,7 +7980,10 @@ mips_ip (str, ip)
       insn_error = NULL;
       for (args = insn->args;; ++args)
 	{
+	  int is_mdmx;
+
 	  s += strspn (s, " \t");
+	  is_mdmx = 0;
 	  switch (*args)
 	    {
 	    case '\0':		/* end of args */
@@ -8310,6 +8332,47 @@ mips_ip (str, ip)
 		}
 	      break;
 
+	    case 'O':		/* MDMX alignment immediate constant.  */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
+		{
+		  as_warn ("Improper align amount (%ld), using low bits",
+			   (long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_ALN;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case 'Q':		/* MDMX vector, element sel, or const.  */
+	      if (s[0] != '$')
+		{
+		  /* MDMX Immediate.  */
+		  my_getExpression (&imm_expr, s);
+		  check_absolute_expr (ip, &imm_expr);
+		  if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
+		    {
+		      as_warn (_("Invalid MDMX Immediate (%ld)"),
+			       (long) imm_expr.X_add_number);
+		      imm_expr.X_add_number &= OP_MASK_FT;
+		    }
+		  imm_expr.X_add_number &= OP_MASK_FT;
+		  if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
+		    ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
+		  else
+		    ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
+		  ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
+		  imm_expr.X_op = O_absent;
+		  s = expr_end;
+		  continue;
+		}
+	      /* Not MDMX Immediate.  Fall through.  */
+	    case 'X':           /* MDMX destination register.  */
+	    case 'Y':           /* MDMX source register.  */
+	    case 'Z':           /* MDMX target register.  */
+	      is_mdmx = 1;
 	    case 'D':		/* floating point destination register */
 	    case 'S':		/* floating point source register */
 	    case 'T':		/* floating point target register */
@@ -8317,8 +8380,11 @@ mips_ip (str, ip)
 	    case 'V':
 	    case 'W':
 	      s_reset = s;
-	      if (s[0] == '$' && s[1] == 'f'
-		  && ISDIGIT (s[2]))
+	      /* Accept $fN for FP and MDMX register numbers, and in
+                 addition accept $vN for MDMX register numbers.  */
+	      if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
+		  || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
+		      && ISDIGIT (s[2])))
 		{
 		  s += 2;
 		  regno = 0;
@@ -8359,14 +8425,51 @@ mips_ip (str, ip)
 		  switch (c)
 		    {
 		    case 'D':
+		    case 'X':
 		      ip->insn_opcode |= regno << OP_SH_FD;
 		      break;
 		    case 'V':
 		    case 'S':
+		    case 'Y':
 		      ip->insn_opcode |= regno << OP_SH_FS;
 		      break;
+		    case 'Q':
+		      /* This is like 'Z', but also needs to fix the MDMX
+			 vector/scalar select bits.  Note that the
+			 scalar immediate case is handled above.  */
+		      if (*s == '[')
+			{
+			  int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
+			  int max_el = (is_qh ? 3 : 7);
+			  s++;
+			  my_getExpression(&imm_expr, s);
+			  check_absolute_expr (ip, &imm_expr);
+			  s = expr_end;
+			  if (imm_expr.X_add_number > max_el)
+			    as_bad(_("Bad element selector %ld"),
+				   (long) imm_expr.X_add_number);
+			  imm_expr.X_add_number &= max_el;
+			  ip->insn_opcode |= (imm_expr.X_add_number
+					      << (OP_SH_VSEL +
+						  (is_qh ? 2 : 1)));
+			  if (*s != ']')
+			    as_warn(_("Expecting ']' found '%s'"), s);
+			  else
+			    s++;
+			}
+		      else
+                        {
+                          if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
+                            ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
+						<< OP_SH_VSEL);
+			  else
+			    ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
+						OP_SH_VSEL);
+			}
+                      /* Fall through */
 		    case 'W':
 		    case 'T':
+		    case 'Z':
 		      ip->insn_opcode |= regno << OP_SH_FT;
 		      break;
 		    case 'R':
@@ -9992,8 +10095,12 @@ struct option md_longopts[] =
   {"mips3d", no_argument, NULL, OPTION_MIPS3D},
 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
   {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
+#define OPTION_MDMX (OPTION_MD_BASE + 35)
+  {"mdmx", no_argument, NULL, OPTION_MDMX},
+#define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
+  {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
 #ifdef OBJ_ELF
-#define OPTION_ELF_BASE    (OPTION_MD_BASE + 35)
+#define OPTION_ELF_BASE    (OPTION_MD_BASE + 37)
 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
   {"KPIC",        no_argument, NULL, OPTION_CALL_SHARED},
   {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
@@ -10198,6 +10305,14 @@ md_parse_option (c, arg)
     case OPTION_NO_M3900:
       break;
 
+    case OPTION_MDMX:
+      mips_opts.ase_mdmx = 1;
+      break;
+
+    case OPTION_NO_MDMX:
+      mips_opts.ase_mdmx = 0;
+      break;
+
     case OPTION_MIPS16:
       mips_opts.mips16 = 1;
       mips_no_prev_insn (false);
@@ -11532,6 +11647,10 @@ s_mipsset (x)
     {
       mips_opts.nobopt = 1;
     }
+  else if (strcmp (name, "mdmx") == 0)
+    mips_opts.ase_mdmx = 1;
+  else if (strcmp (name, "nomdmx") == 0)
+    mips_opts.ase_mdmx = 0;
   else if (strcmp (name, "mips16") == 0
 	   || strcmp (name, "MIPS-16") == 0)
     mips_opts.mips16 = 1;
@@ -13021,6 +13140,8 @@ mips_elf_final_processing ()
   if (file_ase_mips3d)
     elf_elfheader (stdoutput)->e_flags |= ???;
 #endif
+  if (file_ase_mdmx)
+    elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
 
   /* Set the MIPS ELF ABI flags.  */
   if (file_mips_abi == NO_ABI)
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 7bd85d7..2b37eb4 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -375,6 +375,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mips32}] [@b{-mips64}]
    [@b{-m4650}] [@b{-no-m4650}]
    [@b{-mips3d}] [@b{-no-mips3d}]
+   [@b{-mdmx}] [@b{-no-mdmx}]
    [@b{--trap}] [@b{--break}] [@b{-n}]
    [@b{--emulation}=@var{name} ]
 @end ifset
@@ -888,6 +889,12 @@ Generate code for the MIPS-3D Application Specific Extension.
 This tells the assembler to accept MIPS-3D instructions.
 @samp{-no-mips3d} turns off this option.
 
+@item -mdmx
+@itemx -no-mdmx
+Generate code for the MDMX Application Specific Extension.
+This tells the assembler to accept MDMX instructions.
+@samp{-no-mdmx} turns off this option.
+
 @item -mcpu=@var{CPU}
 Generate code for a particular MIPS cpu.  It is exactly equivalent to
 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index c81d0ab..7bf75b3 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -105,6 +105,12 @@ Generate code for the MIPS-3D Application Specific Extension.
 This tells the assembler to accept MIPS-3D instructions.
 @samp{-no-mips3d} turns off this option.
 
+@item -mdmx
+@itemx -no-mdmx
+Generate code for the MDMX Application Specific Extension.
+This tells the assembler to accept MDMX instructions.
+@samp{-no-mdmx} turns off this option.
+
 @item -mfix7000
 @itemx -mno-fix7000
 Cause nops to be inserted if the read of the destination register
@@ -343,4 +349,12 @@ from the MIPS-3D Application Specific Extension from that point on
 in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
 instructions from being accepted.
 
+@cindex MIPS MDMX instruction generation override
+@kindex @code{.set mdmx}
+@kindex @code{.set nomdmx}
+The directive @code{.set mdmx} makes the assembler accept instructions
+from the MDMX Application Specific Extension from that point on
+in the assembly.  The @code{.set nomdmx} directive prevents MDMX
+instructions from being accepted.
+
 Traditional @sc{mips} assemblers do not support these directives.
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 9554e69..26af36c 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* gas/mips/mips64-mdmx.s: New file.
+	* gas/mips/mips64-mdmx.d: Likewise.
+	* gas/mips/mips.exp: Run new "mips64-mdmx" test.
+
 2002-05-30  Richard Henderson  <rth@redhat.com>
 
 	* gas/alpha/elf-tls-1.s, gas/alpha/elf-tls-1.d: New.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 37a945a..b357dec 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -152,6 +152,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "mips32"
     run_dump_test "mips64"
     run_dump_test "mips64-mips3d"
+    run_dump_test "mips64-mdmx"
     run_dump_test "sb1-ext-ps"
 
     # It will always fail until someone fixes it.
diff --git a/gas/testsuite/gas/mips/mips64-mdmx.d b/gas/testsuite/gas/mips/mips64-mdmx.d
new file mode 100644
index 0000000..66bc896
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-mdmx.d
@@ -0,0 +1,215 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64
+#name: MIPS MIPS64 MDMX ASE instructions
+#as: -mips64 -mdmx
+
+# Check MIPS64 MDMX ASE instruction assembly and disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46b46051 	movf\.l	\$f1,\$f12,\$fcc5
+0+0004 <[^>]*> 46b26053 	movn\.l	\$f1,\$f12,s2
+0+0008 <[^>]*> 46b56051 	movt\.l	\$f1,\$f12,\$fcc5
+0+000c <[^>]*> 46b26052 	movz\.l	\$f1,\$f12,s2
+0+0010 <[^>]*> 7ad2604b 	add\.ob	\$v1,\$v12,\$v18
+0+0014 <[^>]*> 7ad2604b 	add\.ob	\$v1,\$v12,\$v18
+0+0018 <[^>]*> 7992604b 	add\.ob	\$v1,\$v12,\$v18\[6\]
+0+001c <[^>]*> 7bb2604b 	add\.qh	\$v1,\$v12,0x12
+0+0020 <[^>]*> 7932604b 	add\.qh	\$v1,\$v12,\$v18\[2\]
+0+0024 <[^>]*> 7bb2604b 	add\.qh	\$v1,\$v12,0x12
+0+0028 <[^>]*> 7ad26037 	adda\.ob	\$v12,\$v18
+0+002c <[^>]*> 7ad26037 	adda\.ob	\$v12,\$v18
+0+0030 <[^>]*> 79926037 	adda\.ob	\$v12,\$v18\[6\]
+0+0034 <[^>]*> 7ab26037 	adda\.qh	\$v12,\$v18
+0+0038 <[^>]*> 7ab26037 	adda\.qh	\$v12,\$v18
+0+003c <[^>]*> 79326037 	adda\.qh	\$v12,\$v18\[2\]
+0+0040 <[^>]*> 7ad26437 	addl\.ob	\$v12,\$v18
+0+0044 <[^>]*> 7ad26437 	addl\.ob	\$v12,\$v18
+0+0048 <[^>]*> 79926437 	addl\.ob	\$v12,\$v18\[6\]
+0+004c <[^>]*> 7ab26437 	addl\.qh	\$v12,\$v18
+0+0050 <[^>]*> 7ab26437 	addl\.qh	\$v12,\$v18
+0+0054 <[^>]*> 79326437 	addl\.qh	\$v12,\$v18\[2\]
+0+0058 <[^>]*> 78d26058 	alni\.ob	\$v1,\$v12,\$v18,6
+0+005c <[^>]*> 7852605a 	alni\.qh	\$v1,\$v12,\$v18,2
+0+0060 <[^>]*> 7ab26059 	alnv\.ob	\$v1,\$v12,\$v18,s5
+0+0064 <[^>]*> 7ab2605b 	alnv\.qh	\$v1,\$v12,\$v18,s5
+0+0068 <[^>]*> 7ad2604c 	and\.ob	\$v1,\$v12,\$v18
+0+006c <[^>]*> 7ad2604c 	and\.ob	\$v1,\$v12,\$v18
+0+0070 <[^>]*> 7992604c 	and\.ob	\$v1,\$v12,\$v18\[6\]
+0+0074 <[^>]*> 7bb2604c 	and\.qh	\$v1,\$v12,0x12
+0+0078 <[^>]*> 7932604c 	and\.qh	\$v1,\$v12,\$v18\[2\]
+0+007c <[^>]*> 7bb2604c 	and\.qh	\$v1,\$v12,0x12
+0+0080 <[^>]*> 7ad26001 	c\.eq\.ob	\$v12,\$v18
+0+0084 <[^>]*> 7ad26001 	c\.eq\.ob	\$v12,\$v18
+0+0088 <[^>]*> 79926001 	c\.eq\.ob	\$v12,\$v18\[6\]
+0+008c <[^>]*> 7ab26001 	c\.eq\.qh	\$v12,\$v18
+0+0090 <[^>]*> 7ab26001 	c\.eq\.qh	\$v12,\$v18
+0+0094 <[^>]*> 79326001 	c\.eq\.qh	\$v12,\$v18\[2\]
+0+0098 <[^>]*> 7ad26005 	c\.le\.ob	\$v12,\$v18
+0+009c <[^>]*> 7ad26005 	c\.le\.ob	\$v12,\$v18
+0+00a0 <[^>]*> 79926005 	c\.le\.ob	\$v12,\$v18\[6\]
+0+00a4 <[^>]*> 7ab26005 	c\.le\.qh	\$v12,\$v18
+0+00a8 <[^>]*> 7ab26005 	c\.le\.qh	\$v12,\$v18
+0+00ac <[^>]*> 79326005 	c\.le\.qh	\$v12,\$v18\[2\]
+0+00b0 <[^>]*> 7ad26004 	c\.lt\.ob	\$v12,\$v18
+0+00b4 <[^>]*> 7ad26004 	c\.lt\.ob	\$v12,\$v18
+0+00b8 <[^>]*> 79926004 	c\.lt\.ob	\$v12,\$v18\[6\]
+0+00bc <[^>]*> 7ab26004 	c\.lt\.qh	\$v12,\$v18
+0+00c0 <[^>]*> 7ab26004 	c\.lt\.qh	\$v12,\$v18
+0+00c4 <[^>]*> 79326004 	c\.lt\.qh	\$v12,\$v18\[2\]
+0+00c8 <[^>]*> 7ad26047 	max\.ob	\$v1,\$v12,\$v18
+0+00cc <[^>]*> 7ad26047 	max\.ob	\$v1,\$v12,\$v18
+0+00d0 <[^>]*> 79926047 	max\.ob	\$v1,\$v12,\$v18\[6\]
+0+00d4 <[^>]*> 7bb26047 	max\.qh	\$v1,\$v12,0x12
+0+00d8 <[^>]*> 79326047 	max\.qh	\$v1,\$v12,\$v18\[2\]
+0+00dc <[^>]*> 7bb26047 	max\.qh	\$v1,\$v12,0x12
+0+00e0 <[^>]*> 7ad26046 	min\.ob	\$v1,\$v12,\$v18
+0+00e4 <[^>]*> 7ad26046 	min\.ob	\$v1,\$v12,\$v18
+0+00e8 <[^>]*> 79926046 	min\.ob	\$v1,\$v12,\$v18\[6\]
+0+00ec <[^>]*> 7bb26046 	min\.qh	\$v1,\$v12,0x12
+0+00f0 <[^>]*> 79326046 	min\.qh	\$v1,\$v12,\$v18\[2\]
+0+00f4 <[^>]*> 7bb26046 	min\.qh	\$v1,\$v12,0x12
+0+00f8 <[^>]*> 7bb26040 	msgn\.qh	\$v1,\$v12,0x12
+0+00fc <[^>]*> 79326040 	msgn\.qh	\$v1,\$v12,\$v18\[2\]
+0+0100 <[^>]*> 7bb26040 	msgn\.qh	\$v1,\$v12,0x12
+0+0104 <[^>]*> 7ad26070 	mul\.ob	\$v1,\$v12,\$v18
+0+0108 <[^>]*> 7ad26070 	mul\.ob	\$v1,\$v12,\$v18
+0+010c <[^>]*> 79926070 	mul\.ob	\$v1,\$v12,\$v18\[6\]
+0+0110 <[^>]*> 7bb26070 	mul\.qh	\$v1,\$v12,0x12
+0+0114 <[^>]*> 79326070 	mul\.qh	\$v1,\$v12,\$v18\[2\]
+0+0118 <[^>]*> 7bb26070 	mul\.qh	\$v1,\$v12,0x12
+0+011c <[^>]*> 7ad26033 	mula\.ob	\$v12,\$v18
+0+0120 <[^>]*> 7ad26033 	mula\.ob	\$v12,\$v18
+0+0124 <[^>]*> 79926033 	mula\.ob	\$v12,\$v18\[6\]
+0+0128 <[^>]*> 7ab26033 	mula\.qh	\$v12,\$v18
+0+012c <[^>]*> 7ab26033 	mula\.qh	\$v12,\$v18
+0+0130 <[^>]*> 79326033 	mula\.qh	\$v12,\$v18\[2\]
+0+0134 <[^>]*> 7ad26433 	mull\.ob	\$v12,\$v18
+0+0138 <[^>]*> 7ad26433 	mull\.ob	\$v12,\$v18
+0+013c <[^>]*> 79926433 	mull\.ob	\$v12,\$v18\[6\]
+0+0140 <[^>]*> 7ab26433 	mull\.qh	\$v12,\$v18
+0+0144 <[^>]*> 7ab26433 	mull\.qh	\$v12,\$v18
+0+0148 <[^>]*> 79326433 	mull\.qh	\$v12,\$v18\[2\]
+0+014c <[^>]*> 7ad26032 	muls\.ob	\$v12,\$v18
+0+0150 <[^>]*> 7ad26032 	muls\.ob	\$v12,\$v18
+0+0154 <[^>]*> 79926032 	muls\.ob	\$v12,\$v18\[6\]
+0+0158 <[^>]*> 7ab26032 	muls\.qh	\$v12,\$v18
+0+015c <[^>]*> 7ab26032 	muls\.qh	\$v12,\$v18
+0+0160 <[^>]*> 79326032 	muls\.qh	\$v12,\$v18\[2\]
+0+0164 <[^>]*> 7ad26432 	mulsl\.ob	\$v12,\$v18
+0+0168 <[^>]*> 7ad26432 	mulsl\.ob	\$v12,\$v18
+0+016c <[^>]*> 79926432 	mulsl\.ob	\$v12,\$v18\[6\]
+0+0170 <[^>]*> 7ab26432 	mulsl\.qh	\$v12,\$v18
+0+0174 <[^>]*> 7ab26432 	mulsl\.qh	\$v12,\$v18
+0+0178 <[^>]*> 79326432 	mulsl\.qh	\$v12,\$v18\[2\]
+0+017c <[^>]*> 7ad2604f 	nor\.ob	\$v1,\$v12,\$v18
+0+0180 <[^>]*> 7ad2604f 	nor\.ob	\$v1,\$v12,\$v18
+0+0184 <[^>]*> 7992604f 	nor\.ob	\$v1,\$v12,\$v18\[6\]
+0+0188 <[^>]*> 7bb2604f 	nor\.qh	\$v1,\$v12,0x12
+0+018c <[^>]*> 7932604f 	nor\.qh	\$v1,\$v12,\$v18\[2\]
+0+0190 <[^>]*> 7bb2604f 	nor\.qh	\$v1,\$v12,0x12
+0+0194 <[^>]*> 7ad2604e 	or\.ob	\$v1,\$v12,\$v18
+0+0198 <[^>]*> 7ad2604e 	or\.ob	\$v1,\$v12,\$v18
+0+019c <[^>]*> 7992604e 	or\.ob	\$v1,\$v12,\$v18\[6\]
+0+01a0 <[^>]*> 7bb2604e 	or\.qh	\$v1,\$v12,0x12
+0+01a4 <[^>]*> 7932604e 	or\.qh	\$v1,\$v12,\$v18\[2\]
+0+01a8 <[^>]*> 7bb2604e 	or\.qh	\$v1,\$v12,0x12
+0+01ac <[^>]*> 7ad26042 	pickf\.ob	\$v1,\$v12,\$v18
+0+01b0 <[^>]*> 7ad26042 	pickf\.ob	\$v1,\$v12,\$v18
+0+01b4 <[^>]*> 79926042 	pickf\.ob	\$v1,\$v12,\$v18\[6\]
+0+01b8 <[^>]*> 7bb26042 	pickf\.qh	\$v1,\$v12,0x12
+0+01bc <[^>]*> 79326042 	pickf\.qh	\$v1,\$v12,\$v18\[2\]
+0+01c0 <[^>]*> 7bb26042 	pickf\.qh	\$v1,\$v12,0x12
+0+01c4 <[^>]*> 7ad26043 	pickt\.ob	\$v1,\$v12,\$v18
+0+01c8 <[^>]*> 7ad26043 	pickt\.ob	\$v1,\$v12,\$v18
+0+01cc <[^>]*> 79926043 	pickt\.ob	\$v1,\$v12,\$v18\[6\]
+0+01d0 <[^>]*> 7bb26043 	pickt\.qh	\$v1,\$v12,0x12
+0+01d4 <[^>]*> 79326043 	pickt\.qh	\$v1,\$v12,\$v18\[2\]
+0+01d8 <[^>]*> 7bb26043 	pickt\.qh	\$v1,\$v12,0x12
+0+01dc <[^>]*> 7a00007f 	rach\.ob	\$v1
+0+01e0 <[^>]*> 7a20007f 	rach\.qh	\$v1
+0+01e4 <[^>]*> 7800007f 	racl\.ob	\$v1
+0+01e8 <[^>]*> 7820007f 	racl\.qh	\$v1
+0+01ec <[^>]*> 7900007f 	racm\.ob	\$v1
+0+01f0 <[^>]*> 7920007f 	racm\.qh	\$v1
+0+01f4 <[^>]*> 7bb20065 	rnas\.qh	\$v1,0x12
+0+01f8 <[^>]*> 79320065 	rnas\.qh	\$v1,\$v18\[2\]
+0+01fc <[^>]*> 7bb20065 	rnas\.qh	\$v1,0x12
+0+0200 <[^>]*> 7bd20061 	rnau\.ob	\$v1,0x12
+0+0204 <[^>]*> 78920061 	rnau\.ob	\$v1,\$v18\[2\]
+0+0208 <[^>]*> 7bd20061 	rnau\.ob	\$v1,0x12
+0+020c <[^>]*> 7bb20061 	rnau\.qh	\$v1,0x12
+0+0210 <[^>]*> 79320061 	rnau\.qh	\$v1,\$v18\[2\]
+0+0214 <[^>]*> 7bb20061 	rnau\.qh	\$v1,0x12
+0+0218 <[^>]*> 7bb20066 	rnes\.qh	\$v1,0x12
+0+021c <[^>]*> 79320066 	rnes\.qh	\$v1,\$v18\[2\]
+0+0220 <[^>]*> 7bb20066 	rnes\.qh	\$v1,0x12
+0+0224 <[^>]*> 7bd20062 	rneu\.ob	\$v1,0x12
+0+0228 <[^>]*> 78920062 	rneu\.ob	\$v1,\$v18\[2\]
+0+022c <[^>]*> 7bd20062 	rneu\.ob	\$v1,0x12
+0+0230 <[^>]*> 7bb20062 	rneu\.qh	\$v1,0x12
+0+0234 <[^>]*> 79320062 	rneu\.qh	\$v1,\$v18\[2\]
+0+0238 <[^>]*> 7bb20062 	rneu\.qh	\$v1,0x12
+0+023c <[^>]*> 7bb20064 	rzs\.qh	\$v1,0x12
+0+0240 <[^>]*> 79320064 	rzs\.qh	\$v1,\$v18\[2\]
+0+0244 <[^>]*> 7bb20064 	rzs\.qh	\$v1,0x12
+0+0248 <[^>]*> 7bd20060 	rzu\.ob	\$v1,0x12
+0+024c <[^>]*> 78920060 	rzu\.ob	\$v1,\$v18\[2\]
+0+0250 <[^>]*> 7bd20060 	rzu\.ob	\$v1,0x12
+0+0254 <[^>]*> 7bb20060 	rzu\.qh	\$v1,0x12
+0+0258 <[^>]*> 79320060 	rzu\.qh	\$v1,\$v18\[2\]
+0+025c <[^>]*> 7bb20060 	rzu\.qh	\$v1,0x12
+0+0260 <[^>]*> 7a32605f 	shfl\.bfla\.qh	\$v1,\$v12,\$v18
+0+0264 <[^>]*> 7992605f 	shfl\.mixh\.ob	\$v1,\$v12,\$v18
+0+0268 <[^>]*> 7832605f 	shfl\.mixh\.qh	\$v1,\$v12,\$v18
+0+026c <[^>]*> 79d2605f 	shfl\.mixl\.ob	\$v1,\$v12,\$v18
+0+0270 <[^>]*> 78b2605f 	shfl\.mixl\.qh	\$v1,\$v12,\$v18
+0+0274 <[^>]*> 7912605f 	shfl\.pach\.ob	\$v1,\$v12,\$v18
+0+0278 <[^>]*> 7932605f 	shfl\.pach\.qh	\$v1,\$v12,\$v18
+0+027c <[^>]*> 7b32605f 	shfl\.repa\.qh	\$v1,\$v12,\$v18
+0+0280 <[^>]*> 7bb2605f 	shfl\.repb\.qh	\$v1,\$v12,\$v18
+0+0284 <[^>]*> 78d2605f 	shfl\.upsl\.ob	\$v1,\$v12,\$v18
+0+0288 <[^>]*> 7ad26050 	sll\.ob	\$v1,\$v12,\$v18
+0+028c <[^>]*> 7ad26050 	sll\.ob	\$v1,\$v12,\$v18
+0+0290 <[^>]*> 79926050 	sll\.ob	\$v1,\$v12,\$v18\[6\]
+0+0294 <[^>]*> 7bb26050 	sll\.qh	\$v1,\$v12,0x12
+0+0298 <[^>]*> 79326050 	sll\.qh	\$v1,\$v12,\$v18\[2\]
+0+029c <[^>]*> 7bb26050 	sll\.qh	\$v1,\$v12,0x12
+0+02a0 <[^>]*> 7bb26053 	sra\.qh	\$v1,\$v12,0x12
+0+02a4 <[^>]*> 79326053 	sra\.qh	\$v1,\$v12,\$v18\[2\]
+0+02a8 <[^>]*> 7bb26053 	sra\.qh	\$v1,\$v12,0x12
+0+02ac <[^>]*> 7ad26052 	srl\.ob	\$v1,\$v12,\$v18
+0+02b0 <[^>]*> 7ad26052 	srl\.ob	\$v1,\$v12,\$v18
+0+02b4 <[^>]*> 79926052 	srl\.ob	\$v1,\$v12,\$v18\[6\]
+0+02b8 <[^>]*> 7bb26052 	srl\.qh	\$v1,\$v12,0x12
+0+02bc <[^>]*> 79326052 	srl\.qh	\$v1,\$v12,\$v18\[2\]
+0+02c0 <[^>]*> 7bb26052 	srl\.qh	\$v1,\$v12,0x12
+0+02c4 <[^>]*> 7ad2604a 	sub\.ob	\$v1,\$v12,\$v18
+0+02c8 <[^>]*> 7ad2604a 	sub\.ob	\$v1,\$v12,\$v18
+0+02cc <[^>]*> 7992604a 	sub\.ob	\$v1,\$v12,\$v18\[6\]
+0+02d0 <[^>]*> 7bb2604a 	sub\.qh	\$v1,\$v12,0x12
+0+02d4 <[^>]*> 7932604a 	sub\.qh	\$v1,\$v12,\$v18\[2\]
+0+02d8 <[^>]*> 7bb2604a 	sub\.qh	\$v1,\$v12,0x12
+0+02dc <[^>]*> 7ad26036 	suba\.ob	\$v12,\$v18
+0+02e0 <[^>]*> 7ad26036 	suba\.ob	\$v12,\$v18
+0+02e4 <[^>]*> 79926036 	suba\.ob	\$v12,\$v18\[6\]
+0+02e8 <[^>]*> 7ab26036 	suba\.qh	\$v12,\$v18
+0+02ec <[^>]*> 7ab26036 	suba\.qh	\$v12,\$v18
+0+02f0 <[^>]*> 79326036 	suba\.qh	\$v12,\$v18\[2\]
+0+02f4 <[^>]*> 7ad26436 	subl\.ob	\$v12,\$v18
+0+02f8 <[^>]*> 7ad26436 	subl\.ob	\$v12,\$v18
+0+02fc <[^>]*> 79926436 	subl\.ob	\$v12,\$v18\[6\]
+0+0300 <[^>]*> 7ab26436 	subl\.qh	\$v12,\$v18
+0+0304 <[^>]*> 7ab26436 	subl\.qh	\$v12,\$v18
+0+0308 <[^>]*> 79326436 	subl\.qh	\$v12,\$v18\[2\]
+0+030c <[^>]*> 7a00603e 	wach\.ob	\$v12
+0+0310 <[^>]*> 7a20603e 	wach\.qh	\$v12
+0+0314 <[^>]*> 7812603e 	wacl\.ob	\$v12,\$v18
+0+0318 <[^>]*> 7832603e 	wacl\.qh	\$v12,\$v18
+0+031c <[^>]*> 7ad2604d 	xor\.ob	\$v1,\$v12,\$v18
+0+0320 <[^>]*> 7ad2604d 	xor\.ob	\$v1,\$v12,\$v18
+0+0324 <[^>]*> 7992604d 	xor\.ob	\$v1,\$v12,\$v18\[6\]
+0+0328 <[^>]*> 7bb2604d 	xor\.qh	\$v1,\$v12,0x12
+0+032c <[^>]*> 7932604d 	xor\.qh	\$v1,\$v12,\$v18\[2\]
+0+0330 <[^>]*> 7bb2604d 	xor\.qh	\$v1,\$v12,0x12
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips64-mdmx.s b/gas/testsuite/gas/mips/mips64-mdmx.s
new file mode 100644
index 0000000..7ba494e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-mdmx.s
@@ -0,0 +1,299 @@
+# source file to test assembly of MIPS64 MDMX ASE instructions
+
+	.set noreorder
+	.set noat
+
+	.globl text_label .text
+text_label:
+
+	movf.l		$v1, $v12, $fcc5
+
+	movn.l		$v1, $v12, $18
+
+	movt.l		$v1, $v12, $fcc5
+
+	movz.l		$v1, $v12, $18
+
+	add.ob		$v1, $v12, $v18
+	add.ob		$v1, $v12, $v18
+	add.ob		$v1, $v12, $v18[6]
+
+	add.qh		$v1, $v12, 18
+	add.qh		$v1, $v12, $v18[2]
+	add.qh		$v1, $v12, 18
+
+	adda.ob		$v12, $v18
+	adda.ob		$v12, $v18
+	adda.ob		$v12, $v18[6]
+
+	adda.qh		$v12, $v18
+	adda.qh		$v12, $v18
+	adda.qh		$v12, $v18[2]
+
+	addl.ob		$v12, $v18
+	addl.ob		$v12, $v18
+	addl.ob		$v12, $v18[6]
+
+	addl.qh		$v12, $v18
+	addl.qh		$v12, $v18
+	addl.qh		$v12, $v18[2]
+
+	alni.ob		$v1, $v12, $v18, 6
+
+	alni.qh		$v1, $v12, $v18, 2
+
+	alnv.ob		$v1, $v12, $v18, $21
+
+	alnv.qh		$v1, $v12, $v18, $21
+
+	and.ob		$v1, $v12, $v18
+	and.ob		$v1, $v12, $v18
+	and.ob		$v1, $v12, $v18[6]
+
+	and.qh		$v1, $v12, 18
+	and.qh		$v1, $v12, $v18[2]
+	and.qh		$v1, $v12, 18
+
+	c.eq.ob		$v12, $v18
+	c.eq.ob		$v12, $v18
+	c.eq.ob		$v12, $v18[6]
+
+	c.eq.qh		$v12, $v18
+	c.eq.qh		$v12, $v18
+	c.eq.qh		$v12, $v18[2]
+
+	c.le.ob		$v12, $v18
+	c.le.ob		$v12, $v18
+	c.le.ob		$v12, $v18[6]
+
+	c.le.qh		$v12, $v18
+	c.le.qh		$v12, $v18
+	c.le.qh		$v12, $v18[2]
+
+	c.lt.ob		$v12, $v18
+	c.lt.ob		$v12, $v18
+	c.lt.ob		$v12, $v18[6]
+
+	c.lt.qh		$v12, $v18
+	c.lt.qh		$v12, $v18
+	c.lt.qh		$v12, $v18[2]
+
+	max.ob		$v1, $v12, $v18
+	max.ob		$v1, $v12, $v18
+	max.ob		$v1, $v12, $v18[6]
+
+	max.qh		$v1, $v12, 18
+	max.qh		$v1, $v12, $v18[2]
+	max.qh		$v1, $v12, 18
+
+	min.ob		$v1, $v12, $v18
+	min.ob		$v1, $v12, $v18
+	min.ob		$v1, $v12, $v18[6]
+
+	min.qh		$v1, $v12, 18
+	min.qh		$v1, $v12, $v18[2]
+	min.qh		$v1, $v12, 18
+
+	msgn.qh		$v1, $v12, 18
+	msgn.qh		$v1, $v12, $v18[2]
+	msgn.qh		$v1, $v12, 18
+
+	mul.ob		$v1, $v12, $v18
+	mul.ob		$v1, $v12, $v18
+	mul.ob		$v1, $v12, $v18[6]
+
+	mul.qh		$v1, $v12, 18
+	mul.qh		$v1, $v12, $v18[2]
+	mul.qh		$v1, $v12, 18
+
+	mula.ob		$v12, $v18
+	mula.ob		$v12, $v18
+	mula.ob		$v12, $v18[6]
+
+	mula.qh		$v12, $v18
+	mula.qh		$v12, $v18
+	mula.qh		$v12, $v18[2]
+
+	mull.ob		$v12, $v18
+	mull.ob		$v12, $v18
+	mull.ob		$v12, $v18[6]
+
+	mull.qh		$v12, $v18
+	mull.qh		$v12, $v18
+	mull.qh		$v12, $v18[2]
+
+	muls.ob		$v12, $v18
+	muls.ob		$v12, $v18
+	muls.ob		$v12, $v18[6]
+
+	muls.qh		$v12, $v18
+	muls.qh		$v12, $v18
+	muls.qh		$v12, $v18[2]
+
+	mulsl.ob	$v12, $v18
+	mulsl.ob	$v12, $v18
+	mulsl.ob	$v12, $v18[6]
+
+	mulsl.qh	$v12, $v18
+	mulsl.qh	$v12, $v18
+	mulsl.qh	$v12, $v18[2]
+
+	nor.ob		$v1, $v12, $v18
+	nor.ob		$v1, $v12, $v18
+	nor.ob		$v1, $v12, $v18[6]
+
+	nor.qh		$v1, $v12, 18
+	nor.qh		$v1, $v12, $v18[2]
+	nor.qh		$v1, $v12, 18
+
+	or.ob		$v1, $v12, $v18
+	or.ob		$v1, $v12, $v18
+	or.ob		$v1, $v12, $v18[6]
+
+	or.qh		$v1, $v12, 18
+	or.qh		$v1, $v12, $v18[2]
+	or.qh		$v1, $v12, 18
+
+	pickf.ob	$v1, $v12, $v18
+	pickf.ob	$v1, $v12, $v18
+	pickf.ob	$v1, $v12, $v18[6]
+
+	pickf.qh	$v1, $v12, 18
+	pickf.qh	$v1, $v12, $v18[2]
+	pickf.qh	$v1, $v12, 18
+
+	pickt.ob	$v1, $v12, $v18
+	pickt.ob	$v1, $v12, $v18
+	pickt.ob	$v1, $v12, $v18[6]
+
+	pickt.qh	$v1, $v12, 18
+	pickt.qh	$v1, $v12, $v18[2]
+	pickt.qh	$v1, $v12, 18
+
+	rach.ob		$v1
+
+	rach.qh		$v1
+
+	racl.ob		$v1
+
+	racl.qh		$v1
+
+	racm.ob		$v1
+
+	racm.qh		$v1
+
+	rnas.qh		$v1, 18
+	rnas.qh		$v1, $v18[2]
+	rnas.qh		$v1, 18
+
+	rnau.ob		$v1, 18
+	rnau.ob		$v1, $v18[2]
+	rnau.ob		$v1, 18
+
+	rnau.qh		$v1, 18
+	rnau.qh		$v1, $v18[2]
+	rnau.qh		$v1, 18
+
+	rnes.qh		$v1, 18
+	rnes.qh		$v1, $v18[2]
+	rnes.qh		$v1, 18
+
+	rneu.ob		$v1, 18
+	rneu.ob		$v1, $v18[2]
+	rneu.ob		$v1, 18
+
+	rneu.qh		$v1, 18
+	rneu.qh		$v1, $v18[2]
+	rneu.qh		$v1, 18
+
+	rzs.qh		$v1, 18
+	rzs.qh		$v1, $v18[2]
+	rzs.qh		$v1, 18
+
+	rzu.ob		$v1, 18
+	rzu.ob		$v1, $v18[2]
+	rzu.ob		$v1, 18
+
+	rzu.qh		$v1, 18
+	rzu.qh		$v1, $v18[2]
+	rzu.qh		$v1, 18
+
+	shfl.bfla.qh	$v1, $v12, $v18
+
+	shfl.mixh.ob	$v1, $v12, $v18
+	shfl.mixh.qh	$v1, $v12, $v18
+
+	shfl.mixl.ob	$v1, $v12, $v18
+	shfl.mixl.qh	$v1, $v12, $v18
+
+	shfl.pach.ob	$v1, $v12, $v18
+	shfl.pach.qh	$v1, $v12, $v18
+
+	shfl.repa.qh	$v1, $v12, $v18
+
+	shfl.repb.qh	$v1, $v12, $v18
+
+	shfl.upsl.ob	$v1, $v12, $v18
+
+	sll.ob		$v1, $v12, $v18
+	sll.ob		$v1, $v12, $v18
+	sll.ob		$v1, $v12, $v18[6]
+
+	sll.qh		$v1, $v12, 18
+	sll.qh		$v1, $v12, $v18[2]
+	sll.qh		$v1, $v12, 18
+
+	sra.qh		$v1, $v12, 18
+	sra.qh		$v1, $v12, $v18[2]
+	sra.qh		$v1, $v12, 18
+
+	srl.ob		$v1, $v12, $v18
+	srl.ob		$v1, $v12, $v18
+	srl.ob		$v1, $v12, $v18[6]
+
+	srl.qh		$v1, $v12, 18
+	srl.qh		$v1, $v12, $v18[2]
+	srl.qh		$v1, $v12, 18
+
+	sub.ob		$v1, $v12, $v18
+	sub.ob		$v1, $v12, $v18
+	sub.ob		$v1, $v12, $v18[6]
+
+	sub.qh		$v1, $v12, 18
+	sub.qh		$v1, $v12, $v18[2]
+	sub.qh		$v1, $v12, 18
+
+	suba.ob		$v12, $v18
+	suba.ob		$v12, $v18
+	suba.ob		$v12, $v18[6]
+
+	suba.qh		$v12, $v18
+	suba.qh		$v12, $v18
+	suba.qh		$v12, $v18[2]
+
+	subl.ob		$v12, $v18
+	subl.ob		$v12, $v18
+	subl.ob		$v12, $v18[6]
+
+	subl.qh		$v12, $v18
+	subl.qh		$v12, $v18
+	subl.qh		$v12, $v18[2]
+
+	wach.ob		$v12
+
+	wach.qh		$v12
+
+	wacl.ob		$v12, $v18
+
+	wacl.qh		$v12, $v18
+
+	xor.ob		$v1, $v12, $v18
+	xor.ob		$v1, $v12, $v18
+	xor.ob		$v1, $v12, $v18[6]
+
+	xor.qh		$v1, $v12, 18
+	xor.qh		$v1, $v12, $v18[2]
+	xor.qh		$v1, $v12, 18
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8