aboutsummaryrefslogtreecommitdiff
path: root/gas
diff options
context:
space:
mode:
authorTristan Gingold <gingold@adacore.com>2017-03-02 10:17:52 +0100
committerTristan Gingold <gingold@adacore.com>2017-03-02 10:17:52 +0100
commit7fa393306ed8b93019d225548474c0540b8928f7 (patch)
treefa43f39b21c55af265889ee090518c62326d386d /gas
parent95e5850793fc6979cf9fc089ca5f625ec30043bb (diff)
downloadgdb-7fa393306ed8b93019d225548474c0540b8928f7.zip
gdb-7fa393306ed8b93019d225548474c0540b8928f7.tar.gz
gdb-7fa393306ed8b93019d225548474c0540b8928f7.tar.bz2
Add generated filesbinutils-2_28
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog4
-rw-r--r--gas/bfin-lex.c3553
-rw-r--r--gas/bfin-parse.c7972
-rw-r--r--gas/bfin-parse.h422
-rwxr-xr-xgas/configure20
-rw-r--r--gas/doc/as.12073
-rw-r--r--gas/doc/as.info28078
-rw-r--r--gas/doc/asconfig.texi108
-rw-r--r--gas/itbl-lex.c1919
-rw-r--r--gas/itbl-parse.c1906
-rw-r--r--gas/itbl-parse.h96
-rw-r--r--gas/m68k-parse.c2772
-rw-r--r--gas/po/es.gmobin0 -> 438926 bytes
-rw-r--r--gas/po/fi.gmobin0 -> 442741 bytes
-rw-r--r--gas/po/fr.gmobin0 -> 501939 bytes
-rw-r--r--gas/po/id.gmobin0 -> 389863 bytes
-rw-r--r--gas/po/ja.gmobin0 -> 23726 bytes
-rw-r--r--gas/po/ru.gmobin0 -> 23024 bytes
-rw-r--r--gas/po/rw.gmobin0 -> 396 bytes
-rw-r--r--gas/po/tr.gmobin0 -> 220920 bytes
-rw-r--r--gas/po/uk.gmobin0 -> 647441 bytes
-rw-r--r--gas/po/zh_CN.gmobin0 -> 3779 bytes
-rw-r--r--gas/rl78-parse.c4786
-rw-r--r--gas/rl78-parse.h307
-rw-r--r--gas/rx-parse.c4678
-rw-r--r--gas/rx-parse.h335
26 files changed, 59019 insertions, 10 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7e2948d..8a586ad 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2017-03-02 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
2017-02-28 Alan Modra <amodra@gmail.com>
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
diff --git a/gas/bfin-lex.c b/gas/bfin-lex.c
new file mode 100644
index 0000000..cd680d9
--- /dev/null
+++ b/gas/bfin-lex.c
@@ -0,0 +1,3553 @@
+
+#line 3 "bfin-lex.c"
+
+#define YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types.
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+typedef uint64_t flex_uint64_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t;
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else /* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif /* defined (__STDC__) */
+#endif /* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index. If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition. This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state. The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart(yyin )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+extern yy_size_t yyleng;
+
+extern FILE *yyin, *yyout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+ #define YY_LESS_LINENO(n)
+
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ *yy_cp = (yy_hold_char); \
+ YY_RESTORE_YY_MORE_OFFSET \
+ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+ YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+ } \
+ while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr) )
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+ {
+ FILE *yy_input_file;
+
+ char *yy_ch_buf; /* input buffer */
+ char *yy_buf_pos; /* current position in input buffer */
+
+ /* Size of input buffer in bytes, not including room for EOB
+ * characters.
+ */
+ yy_size_t yy_buf_size;
+
+ /* Number of characters read into yy_ch_buf, not including EOB
+ * characters.
+ */
+ yy_size_t yy_n_chars;
+
+ /* Whether we "own" the buffer - i.e., we know we created it,
+ * and can realloc() it to grow it, and should free() it to
+ * delete it.
+ */
+ int yy_is_our_buffer;
+
+ /* Whether this is an "interactive" input source; if so, and
+ * if we're using stdio for input, then we want to use getc()
+ * instead of fread(), to make sure we stop fetching input after
+ * each newline.
+ */
+ int yy_is_interactive;
+
+ /* Whether we're considered to be at the beginning of a line.
+ * If so, '^' rules will be active on the next match, otherwise
+ * not.
+ */
+ int yy_at_bol;
+
+ int yy_bs_lineno; /**< The line count. */
+ int yy_bs_column; /**< The column count. */
+
+ /* Whether to try to fill the input buffer when we reach the
+ * end of it.
+ */
+ int yy_fill_buffer;
+
+ int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+ /* When an EOF's been seen but there's still some text to process
+ * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+ * shouldn't try reading from the input source any more. We might
+ * still have a bunch of tokens to match, though, because of
+ * possible backing-up.
+ *
+ * When we actually see the EOF, we change the status to "new"
+ * (via yyrestart()), so that the user can continue scanning by
+ * just pointing yyin at a new input file.
+ */
+#define YY_BUFFER_EOF_PENDING 2
+
+ };
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+ : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */
+yy_size_t yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0; /* whether we need to initialize */
+static int yy_start = 0; /* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin. A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void yyrestart (FILE *input_file );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size );
+void yy_delete_buffer (YY_BUFFER_STATE b );
+void yy_flush_buffer (YY_BUFFER_STATE b );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer );
+void yypop_buffer_state (void );
+
+static void yyensure_buffer_stack (void );
+static void yy_load_buffer_state (void );
+static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file );
+
+#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,yy_size_t len );
+
+void *yyalloc (yy_size_t );
+void *yyrealloc (void *,yy_size_t );
+void yyfree (void * );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){ \
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+ }
+
+#define yy_set_bol(at_bol) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){\
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+ }
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+#define yywrap(n) 1
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int yylineno;
+
+int yylineno = 1;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[] );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+ (yytext_ptr) = yy_bp; \
+ yyleng = (yy_size_t) (yy_cp - yy_bp); \
+ (yy_hold_char) = *yy_cp; \
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 239
+#define YY_END_OF_BUFFER 240
+/* This struct is not used in this scanner,
+ but its presence is necessary. */
+struct yy_trans_info
+ {
+ flex_int32_t yy_verify;
+ flex_int32_t yy_nxt;
+ };
+static yyconst flex_int16_t yy_accept[571] =
+ { 0,
+ 0, 0, 0, 0, 0, 0, 240, 238, 236, 236,
+ 221, 234, 220, 219, 201, 202, 217, 215, 212, 211,
+ 204, 233, 233, 203, 222, 200, 196, 238, 225, 234,
+ 147, 234, 234, 234, 234, 234, 234, 234, 234, 234,
+ 234, 234, 234, 234, 54, 234, 234, 234, 12, 10,
+ 190, 189, 188, 186, 184, 234, 234, 234, 234, 234,
+ 70, 19, 18, 8, 7, 234, 218, 216, 214, 213,
+ 0, 210, 205, 0, 0, 0, 233, 235, 0, 199,
+ 197, 223, 195, 194, 179, 176, 234, 234, 234, 149,
+ 152, 234, 234, 148, 0, 146, 234, 139, 234, 234,
+
+ 135, 234, 125, 234, 123, 234, 234, 234, 234, 234,
+ 234, 234, 103, 102, 101, 234, 100, 99, 234, 234,
+ 97, 234, 95, 94, 93, 91, 234, 85, 234, 234,
+ 77, 86, 234, 71, 69, 234, 234, 234, 234, 65,
+ 234, 234, 234, 59, 234, 56, 234, 234, 53, 234,
+ 234, 234, 234, 234, 234, 234, 234, 234, 234, 234,
+ 234, 25, 234, 234, 234, 234, 234, 15, 14, 234,
+ 234, 159, 234, 234, 187, 185, 224, 234, 234, 95,
+ 234, 234, 234, 206, 208, 207, 209, 0, 0, 233,
+ 233, 198, 192, 193, 234, 234, 234, 172, 153, 154,
+
+ 234, 234, 163, 164, 234, 155, 157, 233, 234, 234,
+ 234, 234, 234, 234, 124, 234, 234, 119, 234, 234,
+ 234, 234, 234, 234, 234, 234, 234, 180, 98, 234,
+ 234, 234, 234, 234, 234, 80, 83, 78, 81, 234,
+ 234, 234, 79, 82, 234, 67, 66, 234, 63, 62,
+ 234, 234, 234, 234, 234, 234, 234, 234, 234, 234,
+ 44, 39, 38, 37, 36, 35, 34, 234, 32, 31,
+ 234, 234, 234, 234, 234, 234, 234, 21, 234, 234,
+ 16, 13, 234, 234, 9, 234, 234, 234, 234, 234,
+ 234, 237, 191, 171, 169, 178, 177, 170, 168, 175,
+
+ 174, 234, 234, 234, 234, 234, 156, 158, 145, 234,
+ 234, 234, 234, 138, 137, 234, 127, 234, 234, 118,
+ 234, 234, 234, 234, 111, 110, 234, 234, 234, 234,
+ 234, 234, 234, 105, 104, 234, 234, 234, 96, 234,
+ 92, 89, 84, 74, 234, 234, 68, 64, 234, 61,
+ 60, 58, 57, 234, 55, 45, 234, 50, 47, 49,
+ 46, 48, 234, 234, 43, 42, 234, 234, 234, 234,
+ 234, 234, 27, 24, 23, 234, 234, 234, 234, 234,
+ 234, 229, 234, 228, 234, 234, 173, 234, 234, 234,
+ 161, 234, 234, 234, 234, 234, 234, 234, 234, 234,
+
+ 234, 122, 234, 117, 116, 234, 234, 234, 234, 234,
+ 234, 234, 234, 108, 234, 234, 234, 234, 234, 234,
+ 234, 234, 234, 234, 2, 183, 52, 41, 40, 234,
+ 33, 234, 234, 234, 30, 234, 22, 234, 234, 234,
+ 234, 232, 234, 234, 234, 234, 234, 234, 165, 162,
+ 144, 143, 142, 141, 140, 234, 234, 234, 234, 126,
+ 121, 234, 234, 234, 234, 234, 51, 234, 234, 107,
+ 234, 234, 234, 234, 234, 88, 87, 90, 234, 234,
+ 73, 72, 234, 29, 234, 234, 234, 20, 234, 234,
+ 151, 234, 230, 234, 227, 234, 166, 167, 234, 234,
+
+ 234, 234, 234, 234, 120, 234, 114, 113, 234, 234,
+ 234, 5, 106, 234, 181, 234, 234, 234, 234, 160,
+ 28, 234, 234, 17, 11, 234, 234, 150, 234, 234,
+ 134, 133, 132, 129, 234, 115, 234, 6, 109, 234,
+ 234, 3, 234, 76, 1, 26, 231, 226, 136, 130,
+ 131, 234, 234, 234, 234, 234, 128, 234, 234, 4,
+ 75, 234, 234, 112, 234, 234, 234, 234, 182, 0
+ } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 2, 4, 1, 5, 6, 7, 8, 1, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 1, 32, 33, 34, 35, 36, 37, 38,
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
+ 59, 1, 60, 61, 62, 1, 33, 34, 35, 36,
+
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,
+ 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+ 57, 58, 1, 63, 1, 64, 1, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6
+ } ;
+
+static yyconst flex_int32_t yy_meta[65] =
+ { 0,
+ 1, 1, 2, 1, 1, 3, 1, 1, 1, 1,
+ 1, 1, 1, 1, 4, 1, 5, 5, 5, 5,
+ 5, 5, 5, 5, 5, 5, 1, 1, 1, 1,
+ 1, 1, 6, 7, 6, 6, 6, 7, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 4, 3, 3, 1, 1,
+ 1, 3, 1, 1
+ } ;
+
+static yyconst flex_int16_t yy_base[577] =
+ { 0,
+ 0, 0, 27, 28, 32, 40, 666, 667, 667, 667,
+ 667, 0, 667, 635, 667, 667, 634, 67, 667, 56,
+ 652, 67, 72, 667, 667, 44, 63, 631, 667, 114,
+ 168, 67, 99, 33, 89, 70, 111, 157, 608, 209,
+ 161, 48, 98, 245, 279, 313, 101, 609, 84, 639,
+ 667, 667, 628, 90, 667, 152, 77, 616, 606, 75,
+ 235, 0, 175, 0, 0, 0, 667, 667, 667, 667,
+ 115, 667, 667, 142, 644, 0, 74, 667, 0, 624,
+ 667, 667, 667, 131, 638, 637, 120, 152, 610, 0,
+ 0, 190, 165, 0, 0, 635, 597, 0, 611, 600,
+
+ 594, 601, 0, 603, 0, 586, 607, 602, 592, 96,
+ 586, 169, 623, 591, 0, 584, 0, 0, 583, 597,
+ 618, 588, 0, 0, 580, 0, 585, 614, 172, 174,
+ 0, 581, 161, 205, 612, 570, 579, 577, 151, 0,
+ 576, 585, 569, 605, 584, 0, 566, 571, 601, 574,
+ 562, 577, 560, 236, 561, 577, 562, 187, 556, 566,
+ 567, 590, 547, 562, 551, 550, 547, 0, 0, 551,
+ 546, 0, 562, 577, 667, 667, 667, 542, 550, 549,
+ 546, 195, 547, 667, 667, 667, 667, 579, 148, 0,
+ 0, 667, 667, 559, 193, 195, 538, 0, 525, 0,
+
+ 547, 544, 0, 0, 551, 532, 531, 0, 230, 234,
+ 527, 530, 542, 534, 0, 531, 532, 271, 528, 541,
+ 196, 222, 242, 540, 522, 244, 536, 552, 0, 519,
+ 265, 531, 548, 518, 270, 0, 0, 0, 0, 517,
+ 512, 522, 0, 0, 273, 0, 0, 514, 0, 0,
+ 525, 509, 524, 275, 515, 509, 504, 284, 504, 293,
+ 318, 0, 0, 0, 0, 0, 0, 508, 0, 0,
+ 503, 501, 501, 512, 503, 283, 502, 0, 512, 494,
+ 0, 0, 483, 497, 0, 492, 505, 488, 497, 501,
+ 497, 526, 667, 0, 0, 0, 0, 0, 0, 0,
+
+ 0, 484, 500, 488, 495, 480, 0, 0, 0, 487,
+ 477, 492, 232, 0, 477, 294, 512, 491, 488, 289,
+ 479, 490, 471, 477, 0, 0, 487, 486, 462, 464,
+ 464, 479, 481, 0, 0, 477, 488, 461, 0, 448,
+ 0, 494, 0, 446, 454, 468, 0, 0, 468, 0,
+ 0, 0, 0, 469, 0, 0, 466, 0, 0, 0,
+ 0, 0, 483, 484, 0, 0, 455, 463, 463, 445,
+ 459, 443, 460, 0, 0, 458, 454, 440, 445, 441,
+ 448, 425, 435, 0, 448, 438, 0, 436, 338, 430,
+ 0, 431, 424, 427, 434, 425, 436, 427, 441, 427,
+
+ 416, 0, 420, 0, 0, 422, 425, 427, 428, 413,
+ 413, 429, 412, 0, 420, 426, 423, 414, 423, 407,
+ 315, 177, 408, 403, 0, 0, 0, 0, 0, 407,
+ 0, 413, 419, 400, 0, 409, 0, 410, 411, 414,
+ 389, 404, 404, 391, 399, 393, 417, 418, 0, 0,
+ 0, 0, 0, 0, 0, 397, 302, 402, 388, 0,
+ 416, 390, 381, 380, 385, 379, 0, 381, 391, 0,
+ 375, 375, 404, 391, 386, 0, 0, 0, 385, 375,
+ 0, 0, 384, 0, 367, 381, 365, 0, 364, 359,
+ 0, 368, 0, 378, 0, 355, 0, 0, 373, 86,
+
+ 362, 361, 365, 374, 0, 350, 0, 0, 368, 367,
+ 351, 0, 0, 356, 0, 335, 330, 339, 341, 0,
+ 0, 324, 324, 0, 0, 320, 333, 0, 320, 246,
+ 0, 0, 0, 0, 334, 0, 312, 0, 0, 305,
+ 309, 0, 314, 0, 0, 0, 0, 0, 0, 0,
+ 0, 309, 310, 304, 303, 292, 0, 287, 261, 0,
+ 0, 255, 241, 0, 254, 214, 186, 185, 0, 667,
+ 378, 382, 389, 179, 392, 395
+ } ;
+
+static yyconst flex_int16_t yy_def[577] =
+ { 0,
+ 570, 1, 1, 1, 1, 1, 570, 570, 570, 570,
+ 570, 571, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 572, 572, 570, 570, 570, 570, 570, 570, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 570, 570, 570, 570, 570, 571, 38, 40, 44, 571,
+ 571, 46, 571, 571, 571, 571, 570, 570, 570, 570,
+ 570, 570, 570, 570, 573, 574, 23, 570, 575, 570,
+ 570, 570, 570, 570, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 576, 571, 571, 571, 571, 571,
+
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 570, 570, 570, 571, 571, 571,
+ 571, 571, 571, 570, 570, 570, 570, 573, 573, 574,
+ 575, 570, 570, 570, 571, 571, 571, 571, 571, 571,
+
+ 571, 571, 571, 571, 571, 571, 571, 576, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 573, 570, 571, 571, 571, 571, 571, 571, 571,
+
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 571,
+ 571, 571, 571, 571, 571, 571, 571, 571, 571, 0,
+ 570, 570, 570, 570, 570, 570
+ } ;
+
+static yyconst flex_int16_t yy_nxt[732] =
+ { 0,
+ 8, 9, 10, 11, 8, 12, 13, 14, 15, 16,
+ 17, 18, 19, 20, 12, 21, 22, 23, 23, 23,
+ 23, 23, 23, 23, 23, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+ 38, 39, 12, 40, 41, 42, 43, 44, 12, 45,
+ 46, 47, 48, 49, 50, 12, 12, 12, 51, 52,
+ 53, 12, 54, 55, 56, 56, 82, 57, 57, 72,
+ 58, 58, 80, 81, 59, 59, 61, 111, 69, 60,
+ 60, 76, 62, 63, 61, 73, 570, 64, 112, 65,
+ 62, 63, 83, 95, 139, 64, 70, 65, 140, 102,
+
+ 78, 103, 95, 95, 78, 78, 115, 570, 530, 78,
+ 104, 570, 179, 105, 180, 95, 116, 106, 74, 176,
+ 183, 117, 79, 107, 171, 170, 184, 570, 185, 71,
+ 85, 86, 108, 531, 172, 109, 113, 166, 167, 110,
+ 168, 114, 141, 142, 169, 173, 220, 87, 88, 221,
+ 143, 118, 177, 186, 119, 187, 95, 89, 189, 90,
+ 193, 194, 91, 292, 92, 120, 197, 93, 199, 200,
+ 198, 94, 95, 121, 121, 121, 121, 135, 135, 135,
+ 135, 206, 207, 190, 96, 96, 96, 96, 236, 237,
+ 238, 239, 122, 136, 123, 178, 124, 241, 249, 113,
+
+ 242, 137, 250, 223, 114, 569, 138, 125, 97, 126,
+ 479, 166, 167, 480, 168, 98, 224, 99, 169, 271,
+ 225, 243, 244, 100, 101, 128, 128, 128, 128, 202,
+ 568, 290, 294, 203, 298, 272, 295, 567, 299, 204,
+ 257, 205, 129, 130, 325, 131, 326, 296, 297, 300,
+ 301, 135, 135, 135, 135, 132, 327, 328, 329, 133,
+ 134, 144, 144, 144, 144, 144, 144, 136, 310, 309,
+ 395, 566, 263, 309, 330, 137, 264, 145, 311, 146,
+ 138, 265, 396, 334, 312, 313, 266, 335, 147, 331,
+ 550, 267, 565, 551, 148, 149, 149, 149, 149, 149,
+
+ 149, 149, 149, 320, 339, 321, 564, 563, 339, 343,
+ 322, 150, 347, 343, 352, 151, 347, 356, 352, 500,
+ 501, 502, 374, 356, 152, 153, 375, 356, 404, 358,
+ 154, 155, 405, 359, 562, 363, 364, 561, 360, 560,
+ 398, 399, 559, 361, 558, 156, 400, 157, 362, 158,
+ 159, 557, 160, 161, 556, 447, 448, 365, 476, 555,
+ 162, 366, 449, 163, 164, 477, 554, 553, 552, 165,
+ 478, 549, 548, 547, 546, 545, 544, 543, 542, 367,
+ 66, 66, 66, 66, 66, 77, 77, 541, 77, 188,
+ 540, 188, 188, 188, 188, 188, 191, 191, 191, 208,
+
+ 208, 208, 539, 538, 537, 536, 535, 534, 533, 532,
+ 529, 528, 527, 526, 525, 524, 523, 522, 521, 520,
+ 519, 518, 517, 516, 515, 514, 513, 512, 511, 510,
+ 509, 508, 507, 506, 505, 504, 503, 499, 498, 497,
+ 496, 495, 494, 493, 492, 491, 490, 489, 488, 487,
+ 486, 485, 484, 483, 482, 481, 475, 474, 473, 472,
+ 471, 470, 469, 468, 467, 466, 465, 464, 463, 462,
+ 461, 460, 459, 458, 457, 456, 455, 454, 453, 452,
+ 451, 450, 446, 445, 444, 443, 420, 442, 441, 440,
+ 439, 438, 437, 436, 435, 434, 433, 432, 431, 430,
+
+ 429, 428, 427, 426, 425, 424, 423, 422, 421, 420,
+ 419, 418, 417, 416, 415, 414, 413, 412, 411, 410,
+ 409, 408, 407, 406, 403, 402, 401, 397, 394, 393,
+ 392, 391, 390, 389, 388, 387, 189, 386, 385, 384,
+ 383, 382, 381, 380, 379, 378, 377, 376, 373, 372,
+ 371, 370, 369, 368, 357, 355, 354, 353, 351, 350,
+ 349, 348, 346, 345, 344, 342, 341, 340, 338, 337,
+ 336, 333, 332, 324, 323, 319, 318, 317, 316, 315,
+ 314, 308, 307, 306, 305, 304, 303, 302, 293, 189,
+ 291, 289, 288, 287, 286, 285, 284, 283, 282, 281,
+
+ 280, 279, 278, 277, 276, 275, 274, 273, 270, 269,
+ 268, 262, 261, 260, 259, 258, 257, 256, 255, 254,
+ 253, 252, 251, 248, 247, 246, 245, 240, 235, 234,
+ 233, 232, 231, 230, 229, 228, 227, 226, 222, 219,
+ 218, 217, 216, 215, 214, 213, 212, 211, 210, 209,
+ 201, 196, 195, 192, 189, 182, 181, 175, 174, 170,
+ 127, 84, 75, 68, 67, 570, 7, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570
+ } ;
+
+static yyconst flex_int16_t yy_chk[732] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 3, 4, 27, 3, 4, 20,
+ 3, 4, 26, 26, 3, 4, 5, 34, 18, 3,
+ 4, 22, 5, 5, 6, 20, 23, 5, 34, 5,
+ 6, 6, 27, 35, 42, 6, 18, 6, 42, 32,
+
+ 22, 32, 43, 33, 22, 23, 36, 77, 500, 23,
+ 32, 77, 57, 32, 57, 37, 36, 32, 20, 54,
+ 60, 36, 22, 32, 49, 60, 71, 23, 71, 18,
+ 30, 30, 33, 500, 49, 33, 35, 47, 47, 33,
+ 47, 35, 43, 43, 47, 49, 110, 30, 30, 110,
+ 43, 37, 54, 74, 37, 74, 56, 30, 189, 30,
+ 84, 84, 30, 189, 30, 37, 87, 30, 88, 88,
+ 87, 30, 31, 38, 38, 38, 38, 41, 41, 41,
+ 41, 93, 93, 574, 31, 31, 31, 31, 129, 129,
+ 130, 130, 38, 41, 38, 56, 38, 133, 139, 56,
+
+ 133, 41, 139, 112, 56, 568, 41, 38, 31, 38,
+ 422, 63, 63, 422, 63, 31, 112, 31, 63, 158,
+ 112, 134, 134, 31, 31, 40, 40, 40, 40, 92,
+ 567, 182, 195, 92, 196, 158, 195, 566, 196, 92,
+ 182, 92, 40, 40, 221, 40, 221, 195, 195, 196,
+ 196, 61, 61, 61, 61, 40, 222, 222, 222, 40,
+ 40, 44, 44, 44, 44, 44, 44, 61, 210, 209,
+ 313, 565, 154, 209, 223, 61, 154, 44, 210, 44,
+ 61, 154, 313, 226, 210, 210, 154, 226, 44, 223,
+ 530, 154, 563, 530, 44, 45, 45, 45, 45, 45,
+
+ 45, 45, 45, 218, 231, 218, 562, 559, 231, 235,
+ 218, 45, 245, 235, 254, 45, 245, 258, 254, 457,
+ 457, 457, 276, 258, 45, 45, 276, 258, 320, 260,
+ 45, 46, 320, 260, 558, 261, 261, 556, 260, 555,
+ 316, 316, 554, 260, 553, 46, 316, 46, 260, 46,
+ 46, 552, 46, 46, 543, 389, 389, 261, 421, 541,
+ 46, 261, 389, 46, 46, 421, 540, 537, 535, 46,
+ 421, 529, 527, 526, 523, 522, 519, 518, 517, 261,
+ 571, 571, 571, 571, 571, 572, 572, 516, 572, 573,
+ 514, 573, 573, 573, 573, 573, 575, 575, 575, 576,
+
+ 576, 576, 511, 510, 509, 506, 504, 503, 502, 501,
+ 499, 496, 494, 492, 490, 489, 487, 486, 485, 483,
+ 480, 479, 475, 474, 473, 472, 471, 469, 468, 466,
+ 465, 464, 463, 462, 461, 459, 458, 456, 448, 447,
+ 446, 445, 444, 443, 442, 441, 440, 439, 438, 436,
+ 434, 433, 432, 430, 424, 423, 420, 419, 418, 417,
+ 416, 415, 413, 412, 411, 410, 409, 408, 407, 406,
+ 403, 401, 400, 399, 398, 397, 396, 395, 394, 393,
+ 392, 390, 388, 386, 385, 383, 382, 381, 380, 379,
+ 378, 377, 376, 373, 372, 371, 370, 369, 368, 367,
+
+ 364, 363, 357, 354, 349, 346, 345, 344, 342, 340,
+ 338, 337, 336, 333, 332, 331, 330, 329, 328, 327,
+ 324, 323, 322, 321, 319, 318, 317, 315, 312, 311,
+ 310, 306, 305, 304, 303, 302, 292, 291, 290, 289,
+ 288, 287, 286, 284, 283, 280, 279, 277, 275, 274,
+ 273, 272, 271, 268, 259, 257, 256, 255, 253, 252,
+ 251, 248, 242, 241, 240, 234, 233, 232, 230, 228,
+ 227, 225, 224, 220, 219, 217, 216, 214, 213, 212,
+ 211, 207, 206, 205, 202, 201, 199, 197, 194, 188,
+ 183, 181, 180, 179, 178, 174, 173, 171, 170, 167,
+
+ 166, 165, 164, 163, 162, 161, 160, 159, 157, 156,
+ 155, 153, 152, 151, 150, 149, 148, 147, 145, 144,
+ 143, 142, 141, 138, 137, 136, 135, 132, 128, 127,
+ 125, 122, 121, 120, 119, 116, 114, 113, 111, 109,
+ 108, 107, 106, 104, 102, 101, 100, 99, 97, 96,
+ 89, 86, 85, 80, 75, 59, 58, 53, 50, 48,
+ 39, 28, 21, 17, 14, 7, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570, 570, 570, 570, 570, 570, 570, 570, 570, 570,
+ 570
+ } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int yy_flex_debug;
+int yy_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "./config/bfin-lex.l"
+/* bfin-lex.l ADI Blackfin lexer
+ Copyright (C) 2005-2017 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+#line 23 "./config/bfin-lex.l"
+
+#include "as.h"
+#include "bfin-defs.h"
+#include "bfin-parse.h"
+
+static long parse_int (char **end);
+static int parse_halfreg (Register *r, int cl, char *hr);
+static int parse_reg (Register *r, int type, char *rt);
+int yylex (void);
+
+#define _REG yylval.reg
+
+
+/* Define Start States ... Actually we will use exclusion.
+ If no start state is specified it should match any state
+ and <INITIAL> would match some keyword rules only with
+ initial. */
+
+
+#line 843 "bfin-lex.c"
+
+#define INITIAL 0
+#define KEYWORD 1
+#define FLAGS 2
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Accessor methods to globals.
+ These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined );
+
+FILE *yyget_in (void );
+
+void yyset_in (FILE * in_str );
+
+FILE *yyget_out (void );
+
+void yyset_out (FILE * out_str );
+
+yy_size_t yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+ static void yyunput (int c,char *buf_ptr );
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO fwrite( yytext, yyleng, 1, yyout )
+#endif
+
+/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+ { \
+ int c = '*'; \
+ yy_size_t n; \
+ for ( n = 0; n < max_size && \
+ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+ buf[n] = (char) c; \
+ if ( c == '\n' ) \
+ buf[n++] = (char) c; \
+ if ( c == EOF && ferror( yyin ) ) \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ result = n; \
+ } \
+ else \
+ { \
+ errno=0; \
+ while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+ { \
+ if( errno != EINTR) \
+ { \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ break; \
+ } \
+ errno=0; \
+ clearerr(yyin); \
+ } \
+ }\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+ YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp, *yy_bp;
+ register int yy_act;
+
+#line 45 "./config/bfin-lex.l"
+
+#line 1029 "bfin-lex.c"
+
+ if ( !(yy_init) )
+ {
+ (yy_init) = 1;
+
+#ifdef YY_USER_INIT
+ YY_USER_INIT;
+#endif
+
+ if ( ! (yy_start) )
+ (yy_start) = 1; /* first start state */
+
+ if ( ! yyin )
+ yyin = stdin;
+
+ if ( ! yyout )
+ yyout = stdout;
+
+ if ( ! YY_CURRENT_BUFFER ) {
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer(yyin,YY_BUF_SIZE );
+ }
+
+ yy_load_buffer_state( );
+ }
+
+ while ( 1 ) /* loops until end-of-file is reached */
+ {
+ yy_cp = (yy_c_buf_p);
+
+ /* Support of yytext. */
+ *yy_cp = (yy_hold_char);
+
+ /* yy_bp points to the position in yy_ch_buf of the start of
+ * the current run.
+ */
+ yy_bp = yy_cp;
+
+ yy_current_state = (yy_start);
+yy_match:
+ do
+ {
+ register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 571 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ ++yy_cp;
+ }
+ while ( yy_base[yy_current_state] != 667 );
+
+yy_find_action:
+ yy_act = yy_accept[yy_current_state];
+ if ( yy_act == 0 )
+ { /* have to back up */
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ yy_act = yy_accept[yy_current_state];
+ }
+
+ YY_DO_BEFORE_ACTION;
+
+do_action: /* This label is used only to access EOF actions. */
+
+ switch ( yy_act )
+ { /* beginning of action switch */
+ case 0: /* must back up */
+ /* undo the effects of YY_DO_BEFORE_ACTION */
+ *yy_cp = (yy_hold_char);
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 46 "./config/bfin-lex.l"
+_REG.regno = REG_sftreset; return REG;
+ YY_BREAK
+case 2:
+YY_RULE_SETUP
+#line 47 "./config/bfin-lex.l"
+_REG.regno = REG_omode; return REG;
+ YY_BREAK
+case 3:
+YY_RULE_SETUP
+#line 48 "./config/bfin-lex.l"
+_REG.regno = REG_idle_req; return REG;
+ YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 49 "./config/bfin-lex.l"
+_REG.regno = REG_hwerrcause; return REG;
+ YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 50 "./config/bfin-lex.l"
+_REG.regno = REG_excause; return REG;
+ YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 51 "./config/bfin-lex.l"
+_REG.regno = REG_emucause; return REG;
+ YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 52 "./config/bfin-lex.l"
+return Z;
+ YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 53 "./config/bfin-lex.l"
+return X;
+ YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 54 "./config/bfin-lex.l"
+yylval.value = M_W32; return MMOD;
+ YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 55 "./config/bfin-lex.l"
+return W;
+ YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 56 "./config/bfin-lex.l"
+return VIT_MAX;
+ YY_BREAK
+case 12:
+YY_RULE_SETUP
+#line 57 "./config/bfin-lex.l"
+return V; /* Special: V is a statflag and a modifier. */
+ YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 58 "./config/bfin-lex.l"
+_REG.regno = REG_USP; return REG;
+ YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 59 "./config/bfin-lex.l"
+return TL;
+ YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 60 "./config/bfin-lex.l"
+return TH;
+ YY_BREAK
+case 16:
+YY_RULE_SETUP
+#line 61 "./config/bfin-lex.l"
+yylval.value = M_TFU; return MMOD;
+ YY_BREAK
+case 17:
+YY_RULE_SETUP
+#line 62 "./config/bfin-lex.l"
+return TESTSET;
+ YY_BREAK
+case 18:
+YY_RULE_SETUP
+#line 63 "./config/bfin-lex.l"
+yylval.value = M_T; return MMOD;
+ YY_BREAK
+case 19:
+YY_RULE_SETUP
+#line 64 "./config/bfin-lex.l"
+return S;
+ YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 65 "./config/bfin-lex.l"
+_REG.regno = REG_SYSCFG; return REG;
+ YY_BREAK
+case 21:
+YY_RULE_SETUP
+#line 66 "./config/bfin-lex.l"
+return STI;
+ YY_BREAK
+case 22:
+YY_RULE_SETUP
+#line 67 "./config/bfin-lex.l"
+return SSYNC;
+ YY_BREAK
+case 23:
+YY_RULE_SETUP
+#line 68 "./config/bfin-lex.l"
+_REG.regno = REG_SP; _REG.flags = F_REG_LOW; return HALF_REG;
+ YY_BREAK
+case 24:
+YY_RULE_SETUP
+#line 69 "./config/bfin-lex.l"
+_REG.regno = REG_SP; _REG.flags = F_REG_HIGH; return HALF_REG;
+ YY_BREAK
+case 25:
+YY_RULE_SETUP
+#line 70 "./config/bfin-lex.l"
+_REG.regno = REG_SP; return REG;
+ YY_BREAK
+case 26:
+YY_RULE_SETUP
+#line 71 "./config/bfin-lex.l"
+return SIGNBITS;
+ YY_BREAK
+case 27:
+YY_RULE_SETUP
+#line 72 "./config/bfin-lex.l"
+return SIGN;
+ YY_BREAK
+case 28:
+YY_RULE_SETUP
+#line 73 "./config/bfin-lex.l"
+_REG.regno = REG_SEQSTAT; return REG;
+ YY_BREAK
+case 29:
+YY_RULE_SETUP
+#line 74 "./config/bfin-lex.l"
+return SEARCH;
+ YY_BREAK
+case 30:
+YY_RULE_SETUP
+#line 75 "./config/bfin-lex.l"
+return SHIFT;
+ YY_BREAK
+case 31:
+YY_RULE_SETUP
+#line 76 "./config/bfin-lex.l"
+return SCO;
+ YY_BREAK
+case 32:
+YY_RULE_SETUP
+#line 78 "./config/bfin-lex.l"
+return SAA;
+ YY_BREAK
+case 33:
+YY_RULE_SETUP
+#line 79 "./config/bfin-lex.l"
+yylval.value = M_S2RND; return MMOD;
+ YY_BREAK
+case 34:
+YY_RULE_SETUP
+#line 80 "./config/bfin-lex.l"
+return RTX;
+ YY_BREAK
+case 35:
+YY_RULE_SETUP
+#line 81 "./config/bfin-lex.l"
+return RTS;
+ YY_BREAK
+case 36:
+YY_RULE_SETUP
+#line 82 "./config/bfin-lex.l"
+return RTN;
+ YY_BREAK
+case 37:
+YY_RULE_SETUP
+#line 83 "./config/bfin-lex.l"
+return RTI;
+ YY_BREAK
+case 38:
+YY_RULE_SETUP
+#line 84 "./config/bfin-lex.l"
+return RTE;
+ YY_BREAK
+case 39:
+YY_RULE_SETUP
+#line 85 "./config/bfin-lex.l"
+return ROT;
+ YY_BREAK
+case 40:
+YY_RULE_SETUP
+#line 86 "./config/bfin-lex.l"
+return RND20;
+ YY_BREAK
+case 41:
+YY_RULE_SETUP
+#line 87 "./config/bfin-lex.l"
+return RND12;
+ YY_BREAK
+case 42:
+YY_RULE_SETUP
+#line 88 "./config/bfin-lex.l"
+return RNDL;
+ YY_BREAK
+case 43:
+YY_RULE_SETUP
+#line 89 "./config/bfin-lex.l"
+return RNDH;
+ YY_BREAK
+case 44:
+YY_RULE_SETUP
+#line 90 "./config/bfin-lex.l"
+return RND;
+ YY_BREAK
+case 45:
+YY_RULE_SETUP
+#line 92 "./config/bfin-lex.l"
+return parse_halfreg(&yylval.reg, T_REG_R, yytext);
+ YY_BREAK
+case 46:
+YY_RULE_SETUP
+#line 94 "./config/bfin-lex.l"
+_REG.regno = REG_RETS; return REG;
+ YY_BREAK
+case 47:
+YY_RULE_SETUP
+#line 95 "./config/bfin-lex.l"
+_REG.regno = REG_RETI; return REG;
+ YY_BREAK
+case 48:
+YY_RULE_SETUP
+#line 96 "./config/bfin-lex.l"
+_REG.regno = REG_RETX; return REG;
+ YY_BREAK
+case 49:
+YY_RULE_SETUP
+#line 97 "./config/bfin-lex.l"
+_REG.regno = REG_RETN; return REG;
+ YY_BREAK
+case 50:
+YY_RULE_SETUP
+#line 98 "./config/bfin-lex.l"
+_REG.regno = REG_RETE; return REG;
+ YY_BREAK
+case 51:
+YY_RULE_SETUP
+#line 99 "./config/bfin-lex.l"
+_REG.regno = REG_EMUDAT; return REG;
+ YY_BREAK
+case 52:
+YY_RULE_SETUP
+#line 100 "./config/bfin-lex.l"
+return RAISE;
+ YY_BREAK
+case 53:
+YY_RULE_SETUP
+#line 102 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_R, yytext);
+ YY_BREAK
+case 54:
+YY_RULE_SETUP
+#line 104 "./config/bfin-lex.l"
+return R;
+ YY_BREAK
+case 55:
+YY_RULE_SETUP
+#line 105 "./config/bfin-lex.l"
+return PRNT;
+ YY_BREAK
+case 56:
+YY_RULE_SETUP
+#line 106 "./config/bfin-lex.l"
+return PC;
+ YY_BREAK
+case 57:
+YY_RULE_SETUP
+#line 107 "./config/bfin-lex.l"
+return PACK;
+ YY_BREAK
+case 58:
+YY_RULE_SETUP
+#line 109 "./config/bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_P, yytext);
+ YY_BREAK
+case 59:
+YY_RULE_SETUP
+#line 110 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_P, yytext);
+ YY_BREAK
+case 60:
+YY_RULE_SETUP
+#line 112 "./config/bfin-lex.l"
+return OUTC;
+ YY_BREAK
+case 61:
+YY_RULE_SETUP
+#line 113 "./config/bfin-lex.l"
+return ONES;
+ YY_BREAK
+case 62:
+YY_RULE_SETUP
+#line 115 "./config/bfin-lex.l"
+return NOT;
+ YY_BREAK
+case 63:
+YY_RULE_SETUP
+#line 116 "./config/bfin-lex.l"
+return NOP;
+ YY_BREAK
+case 64:
+YY_RULE_SETUP
+#line 117 "./config/bfin-lex.l"
+return MNOP;
+ YY_BREAK
+case 65:
+YY_RULE_SETUP
+#line 118 "./config/bfin-lex.l"
+return NS;
+ YY_BREAK
+case 66:
+YY_RULE_SETUP
+#line 121 "./config/bfin-lex.l"
+return MIN;
+ YY_BREAK
+case 67:
+YY_RULE_SETUP
+#line 122 "./config/bfin-lex.l"
+return MAX;
+ YY_BREAK
+case 68:
+YY_RULE_SETUP
+#line 124 "./config/bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_M, yytext);
+ YY_BREAK
+case 69:
+YY_RULE_SETUP
+#line 125 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_M, yytext);
+ YY_BREAK
+case 70:
+YY_RULE_SETUP
+#line 127 "./config/bfin-lex.l"
+return M;
+ YY_BREAK
+case 71:
+YY_RULE_SETUP
+#line 128 "./config/bfin-lex.l"
+return LT;
+ YY_BREAK
+case 72:
+YY_RULE_SETUP
+#line 129 "./config/bfin-lex.l"
+return LSHIFT;
+ YY_BREAK
+case 73:
+YY_RULE_SETUP
+#line 130 "./config/bfin-lex.l"
+return LSETUP;
+ YY_BREAK
+case 74:
+YY_RULE_SETUP
+#line 131 "./config/bfin-lex.l"
+return LOOP;
+ YY_BREAK
+case 75:
+YY_RULE_SETUP
+#line 132 "./config/bfin-lex.l"
+return LOOP_BEGIN;
+ YY_BREAK
+case 76:
+YY_RULE_SETUP
+#line 133 "./config/bfin-lex.l"
+return LOOP_END;
+ YY_BREAK
+case 77:
+YY_RULE_SETUP
+#line 135 "./config/bfin-lex.l"
+return LE;
+ YY_BREAK
+case 78:
+YY_RULE_SETUP
+#line 136 "./config/bfin-lex.l"
+_REG.regno = REG_LC0; return REG;
+ YY_BREAK
+case 79:
+YY_RULE_SETUP
+#line 137 "./config/bfin-lex.l"
+_REG.regno = REG_LT0; return REG;
+ YY_BREAK
+case 80:
+YY_RULE_SETUP
+#line 138 "./config/bfin-lex.l"
+_REG.regno = REG_LB0; return REG;
+ YY_BREAK
+case 81:
+YY_RULE_SETUP
+#line 139 "./config/bfin-lex.l"
+_REG.regno = REG_LC1; return REG;
+ YY_BREAK
+case 82:
+YY_RULE_SETUP
+#line 140 "./config/bfin-lex.l"
+_REG.regno = REG_LT1; return REG;
+ YY_BREAK
+case 83:
+YY_RULE_SETUP
+#line 141 "./config/bfin-lex.l"
+_REG.regno = REG_LB1; return REG;
+ YY_BREAK
+case 84:
+YY_RULE_SETUP
+#line 143 "./config/bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_L, yytext);
+ YY_BREAK
+case 85:
+YY_RULE_SETUP
+#line 144 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_L, yytext);
+ YY_BREAK
+case 86:
+YY_RULE_SETUP
+#line 145 "./config/bfin-lex.l"
+return LO;
+ YY_BREAK
+case 87:
+YY_RULE_SETUP
+#line 146 "./config/bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_S;}
+ YY_BREAK
+case 88:
+YY_RULE_SETUP
+#line 147 "./config/bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_L;}
+ YY_BREAK
+case 89:
+YY_RULE_SETUP
+#line 148 "./config/bfin-lex.l"
+{ BEGIN 0; return JUMP;}
+ YY_BREAK
+case 90:
+YY_RULE_SETUP
+#line 149 "./config/bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_L; }
+ YY_BREAK
+case 91:
+YY_RULE_SETUP
+#line 150 "./config/bfin-lex.l"
+yylval.value = M_IU; return MMOD;
+ YY_BREAK
+case 92:
+YY_RULE_SETUP
+#line 151 "./config/bfin-lex.l"
+yylval.value = M_ISS2; return MMOD;
+ YY_BREAK
+case 93:
+YY_RULE_SETUP
+#line 152 "./config/bfin-lex.l"
+yylval.value = M_IS; return MMOD;
+ YY_BREAK
+case 94:
+YY_RULE_SETUP
+#line 153 "./config/bfin-lex.l"
+yylval.value = M_IH; return MMOD;
+ YY_BREAK
+case 95:
+YY_RULE_SETUP
+#line 154 "./config/bfin-lex.l"
+return IF;
+ YY_BREAK
+case 96:
+YY_RULE_SETUP
+#line 155 "./config/bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_I, yytext);
+ YY_BREAK
+case 97:
+YY_RULE_SETUP
+#line 156 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_I, yytext);
+ YY_BREAK
+case 98:
+YY_RULE_SETUP
+#line 157 "./config/bfin-lex.l"
+return HLT;
+ YY_BREAK
+case 99:
+YY_RULE_SETUP
+#line 158 "./config/bfin-lex.l"
+return HI;
+ YY_BREAK
+case 100:
+YY_RULE_SETUP
+#line 159 "./config/bfin-lex.l"
+return GT;
+ YY_BREAK
+case 101:
+YY_RULE_SETUP
+#line 160 "./config/bfin-lex.l"
+return GE;
+ YY_BREAK
+case 102:
+YY_RULE_SETUP
+#line 161 "./config/bfin-lex.l"
+yylval.value = M_FU; return MMOD;
+ YY_BREAK
+case 103:
+YY_RULE_SETUP
+#line 162 "./config/bfin-lex.l"
+_REG.regno = REG_FP; return REG;
+ YY_BREAK
+case 104:
+YY_RULE_SETUP
+#line 163 "./config/bfin-lex.l"
+_REG.regno = REG_FP; _REG.flags = F_REG_LOW; return HALF_REG;
+ YY_BREAK
+case 105:
+YY_RULE_SETUP
+#line 164 "./config/bfin-lex.l"
+_REG.regno = REG_FP; _REG.flags = F_REG_HIGH; return HALF_REG;
+ YY_BREAK
+case 106:
+YY_RULE_SETUP
+#line 166 "./config/bfin-lex.l"
+return EXTRACT;
+ YY_BREAK
+case 107:
+YY_RULE_SETUP
+#line 167 "./config/bfin-lex.l"
+return EXPADJ;
+ YY_BREAK
+case 108:
+YY_RULE_SETUP
+#line 168 "./config/bfin-lex.l"
+return EXCPT;
+ YY_BREAK
+case 109:
+YY_RULE_SETUP
+#line 169 "./config/bfin-lex.l"
+return EMUEXCPT;
+ YY_BREAK
+case 110:
+YY_RULE_SETUP
+#line 170 "./config/bfin-lex.l"
+return DIVS;
+ YY_BREAK
+case 111:
+YY_RULE_SETUP
+#line 171 "./config/bfin-lex.l"
+return DIVQ;
+ YY_BREAK
+case 112:
+YY_RULE_SETUP
+#line 172 "./config/bfin-lex.l"
+return DISALGNEXCPT;
+ YY_BREAK
+case 113:
+YY_RULE_SETUP
+#line 173 "./config/bfin-lex.l"
+return DEPOSIT;
+ YY_BREAK
+case 114:
+YY_RULE_SETUP
+#line 174 "./config/bfin-lex.l"
+return DBGHALT;
+ YY_BREAK
+case 115:
+YY_RULE_SETUP
+#line 175 "./config/bfin-lex.l"
+return DBGCMPLX;
+ YY_BREAK
+case 116:
+YY_RULE_SETUP
+#line 176 "./config/bfin-lex.l"
+return DBGAL;
+ YY_BREAK
+case 117:
+YY_RULE_SETUP
+#line 177 "./config/bfin-lex.l"
+return DBGAH;
+ YY_BREAK
+case 118:
+YY_RULE_SETUP
+#line 178 "./config/bfin-lex.l"
+return DBGA;
+ YY_BREAK
+case 119:
+YY_RULE_SETUP
+#line 179 "./config/bfin-lex.l"
+return DBG;
+ YY_BREAK
+case 120:
+YY_RULE_SETUP
+#line 180 "./config/bfin-lex.l"
+{ _REG.regno = REG_CYCLES2; return REG; }
+ YY_BREAK
+case 121:
+YY_RULE_SETUP
+#line 181 "./config/bfin-lex.l"
+{ _REG.regno = REG_CYCLES; return REG; }
+ YY_BREAK
+case 122:
+YY_RULE_SETUP
+#line 182 "./config/bfin-lex.l"
+return CSYNC;
+ YY_BREAK
+case 123:
+YY_RULE_SETUP
+#line 183 "./config/bfin-lex.l"
+return CO;
+ YY_BREAK
+case 124:
+YY_RULE_SETUP
+#line 184 "./config/bfin-lex.l"
+return CLI;
+ YY_BREAK
+case 125:
+YY_RULE_SETUP
+#line 186 "./config/bfin-lex.l"
+_REG.regno = REG_CC; return CCREG;
+ YY_BREAK
+case 126:
+YY_RULE_SETUP
+#line 187 "./config/bfin-lex.l"
+{ BEGIN 0; return CALL;}
+ YY_BREAK
+case 127:
+YY_RULE_SETUP
+#line 188 "./config/bfin-lex.l"
+{ BEGIN 0; return CALL;}
+ YY_BREAK
+case 128:
+YY_RULE_SETUP
+#line 189 "./config/bfin-lex.l"
+return BYTEUNPACK;
+ YY_BREAK
+case 129:
+YY_RULE_SETUP
+#line 190 "./config/bfin-lex.l"
+return BYTEPACK;
+ YY_BREAK
+case 130:
+YY_RULE_SETUP
+#line 191 "./config/bfin-lex.l"
+return BYTEOP16M;
+ YY_BREAK
+case 131:
+YY_RULE_SETUP
+#line 192 "./config/bfin-lex.l"
+return BYTEOP16P;
+ YY_BREAK
+case 132:
+YY_RULE_SETUP
+#line 193 "./config/bfin-lex.l"
+return BYTEOP3P;
+ YY_BREAK
+case 133:
+YY_RULE_SETUP
+#line 194 "./config/bfin-lex.l"
+return BYTEOP2P;
+ YY_BREAK
+case 134:
+YY_RULE_SETUP
+#line 195 "./config/bfin-lex.l"
+return BYTEOP1P;
+ YY_BREAK
+case 135:
+YY_RULE_SETUP
+#line 196 "./config/bfin-lex.l"
+return BY;
+ YY_BREAK
+case 136:
+YY_RULE_SETUP
+#line 197 "./config/bfin-lex.l"
+return BXORSHIFT;
+ YY_BREAK
+case 137:
+YY_RULE_SETUP
+#line 198 "./config/bfin-lex.l"
+return BXOR;
+ YY_BREAK
+case 138:
+YY_RULE_SETUP
+#line 200 "./config/bfin-lex.l"
+return BREV;
+ YY_BREAK
+case 139:
+YY_RULE_SETUP
+#line 201 "./config/bfin-lex.l"
+return BP;
+ YY_BREAK
+case 140:
+YY_RULE_SETUP
+#line 202 "./config/bfin-lex.l"
+return BITTST;
+ YY_BREAK
+case 141:
+YY_RULE_SETUP
+#line 203 "./config/bfin-lex.l"
+return BITTGL;
+ YY_BREAK
+case 142:
+YY_RULE_SETUP
+#line 204 "./config/bfin-lex.l"
+return BITSET;
+ YY_BREAK
+case 143:
+YY_RULE_SETUP
+#line 205 "./config/bfin-lex.l"
+return BITMUX;
+ YY_BREAK
+case 144:
+YY_RULE_SETUP
+#line 206 "./config/bfin-lex.l"
+return BITCLR;
+ YY_BREAK
+case 145:
+YY_RULE_SETUP
+#line 207 "./config/bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_B, yytext);
+ YY_BREAK
+case 146:
+YY_RULE_SETUP
+#line 208 "./config/bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_B, yytext);
+ YY_BREAK
+case 147:
+YY_RULE_SETUP
+#line 209 "./config/bfin-lex.l"
+return B;
+ YY_BREAK
+case 148:
+YY_RULE_SETUP
+#line 210 "./config/bfin-lex.l"
+_REG.regno = S_AZ; return STATUS_REG;
+ YY_BREAK
+case 149:
+YY_RULE_SETUP
+#line 211 "./config/bfin-lex.l"
+_REG.regno = S_AN; return STATUS_REG;
+ YY_BREAK
+case 150:
+YY_RULE_SETUP
+#line 212 "./config/bfin-lex.l"
+_REG.regno = S_AC0_COPY; return STATUS_REG;
+ YY_BREAK
+case 151:
+YY_RULE_SETUP
+#line 213 "./config/bfin-lex.l"
+_REG.regno = S_V_COPY; return STATUS_REG;
+ YY_BREAK
+case 152:
+YY_RULE_SETUP
+#line 214 "./config/bfin-lex.l"
+_REG.regno = S_AQ; return STATUS_REG;
+ YY_BREAK
+case 153:
+YY_RULE_SETUP
+#line 215 "./config/bfin-lex.l"
+_REG.regno = S_AC0; return STATUS_REG;
+ YY_BREAK
+case 154:
+YY_RULE_SETUP
+#line 216 "./config/bfin-lex.l"
+_REG.regno = S_AC1; return STATUS_REG;
+ YY_BREAK
+case 155:
+YY_RULE_SETUP
+#line 217 "./config/bfin-lex.l"
+_REG.regno = S_AV0; return STATUS_REG;
+ YY_BREAK
+case 156:
+YY_RULE_SETUP
+#line 218 "./config/bfin-lex.l"
+_REG.regno = S_AV0S; return STATUS_REG;
+ YY_BREAK
+case 157:
+YY_RULE_SETUP
+#line 219 "./config/bfin-lex.l"
+_REG.regno = S_AV1; return STATUS_REG;
+ YY_BREAK
+case 158:
+YY_RULE_SETUP
+#line 220 "./config/bfin-lex.l"
+_REG.regno = S_AV1S; return STATUS_REG;
+ YY_BREAK
+case 159:
+YY_RULE_SETUP
+#line 221 "./config/bfin-lex.l"
+_REG.regno = S_VS; return STATUS_REG;
+ YY_BREAK
+case 160:
+YY_RULE_SETUP
+#line 222 "./config/bfin-lex.l"
+_REG.regno = S_RND_MOD; return STATUS_REG;
+ YY_BREAK
+case 161:
+YY_RULE_SETUP
+#line 225 "./config/bfin-lex.l"
+_REG.regno = REG_ASTAT; return REG;
+ YY_BREAK
+case 162:
+YY_RULE_SETUP
+#line 226 "./config/bfin-lex.l"
+return ASHIFT;
+ YY_BREAK
+case 163:
+YY_RULE_SETUP
+#line 227 "./config/bfin-lex.l"
+return ASL;
+ YY_BREAK
+case 164:
+YY_RULE_SETUP
+#line 228 "./config/bfin-lex.l"
+return ASR;
+ YY_BREAK
+case 165:
+YY_RULE_SETUP
+#line 229 "./config/bfin-lex.l"
+return ALIGN8;
+ YY_BREAK
+case 166:
+YY_RULE_SETUP
+#line 230 "./config/bfin-lex.l"
+return ALIGN16;
+ YY_BREAK
+case 167:
+YY_RULE_SETUP
+#line 231 "./config/bfin-lex.l"
+return ALIGN24;
+ YY_BREAK
+case 168:
+YY_RULE_SETUP
+#line 232 "./config/bfin-lex.l"
+return A_ONE_DOT_L;
+ YY_BREAK
+case 169:
+YY_RULE_SETUP
+#line 233 "./config/bfin-lex.l"
+return A_ZERO_DOT_L;
+ YY_BREAK
+case 170:
+YY_RULE_SETUP
+#line 234 "./config/bfin-lex.l"
+return A_ONE_DOT_H;
+ YY_BREAK
+case 171:
+YY_RULE_SETUP
+#line 235 "./config/bfin-lex.l"
+return A_ZERO_DOT_H;
+ YY_BREAK
+case 172:
+YY_RULE_SETUP
+#line 236 "./config/bfin-lex.l"
+return ABS;
+ YY_BREAK
+case 173:
+YY_RULE_SETUP
+#line 237 "./config/bfin-lex.l"
+return ABORT;
+ YY_BREAK
+case 174:
+YY_RULE_SETUP
+#line 238 "./config/bfin-lex.l"
+_REG.regno = REG_A1x; return REG;
+ YY_BREAK
+case 175:
+YY_RULE_SETUP
+#line 239 "./config/bfin-lex.l"
+_REG.regno = REG_A1w; return REG;
+ YY_BREAK
+case 176:
+YY_RULE_SETUP
+#line 240 "./config/bfin-lex.l"
+_REG.regno = REG_A1; return REG_A_DOUBLE_ONE;
+ YY_BREAK
+case 177:
+YY_RULE_SETUP
+#line 241 "./config/bfin-lex.l"
+_REG.regno = REG_A0x; return REG;
+ YY_BREAK
+case 178:
+YY_RULE_SETUP
+#line 242 "./config/bfin-lex.l"
+_REG.regno = REG_A0w; return REG;
+ YY_BREAK
+case 179:
+YY_RULE_SETUP
+#line 243 "./config/bfin-lex.l"
+_REG.regno = REG_A0; return REG_A_DOUBLE_ZERO;
+ YY_BREAK
+case 180:
+YY_RULE_SETUP
+#line 244 "./config/bfin-lex.l"
+return GOT;
+ YY_BREAK
+case 181:
+YY_RULE_SETUP
+#line 245 "./config/bfin-lex.l"
+return GOT17M4;
+ YY_BREAK
+case 182:
+YY_RULE_SETUP
+#line 246 "./config/bfin-lex.l"
+return FUNCDESC_GOT17M4;
+ YY_BREAK
+case 183:
+YY_RULE_SETUP
+#line 247 "./config/bfin-lex.l"
+return PLTPC;
+ YY_BREAK
+case 184:
+YY_RULE_SETUP
+#line 250 "./config/bfin-lex.l"
+return TILDA;
+ YY_BREAK
+case 185:
+YY_RULE_SETUP
+#line 251 "./config/bfin-lex.l"
+return _BAR_ASSIGN;
+ YY_BREAK
+case 186:
+YY_RULE_SETUP
+#line 252 "./config/bfin-lex.l"
+return BAR;
+ YY_BREAK
+case 187:
+YY_RULE_SETUP
+#line 253 "./config/bfin-lex.l"
+return _CARET_ASSIGN;
+ YY_BREAK
+case 188:
+YY_RULE_SETUP
+#line 254 "./config/bfin-lex.l"
+return CARET;
+ YY_BREAK
+case 189:
+YY_RULE_SETUP
+#line 255 "./config/bfin-lex.l"
+return RBRACK;
+ YY_BREAK
+case 190:
+YY_RULE_SETUP
+#line 256 "./config/bfin-lex.l"
+return LBRACK;
+ YY_BREAK
+case 191:
+YY_RULE_SETUP
+#line 257 "./config/bfin-lex.l"
+return _GREATER_GREATER_GREATER_THAN_ASSIGN;
+ YY_BREAK
+case 192:
+YY_RULE_SETUP
+#line 258 "./config/bfin-lex.l"
+return _GREATER_GREATER_ASSIGN;
+ YY_BREAK
+case 193:
+YY_RULE_SETUP
+#line 259 "./config/bfin-lex.l"
+return _GREATER_GREATER_GREATER;
+ YY_BREAK
+case 194:
+YY_RULE_SETUP
+#line 260 "./config/bfin-lex.l"
+return GREATER_GREATER;
+ YY_BREAK
+case 195:
+YY_RULE_SETUP
+#line 261 "./config/bfin-lex.l"
+return _ASSIGN_ASSIGN;
+ YY_BREAK
+case 196:
+YY_RULE_SETUP
+#line 262 "./config/bfin-lex.l"
+return ASSIGN;
+ YY_BREAK
+case 197:
+YY_RULE_SETUP
+#line 263 "./config/bfin-lex.l"
+return _LESS_THAN_ASSIGN;
+ YY_BREAK
+case 198:
+YY_RULE_SETUP
+#line 264 "./config/bfin-lex.l"
+return _LESS_LESS_ASSIGN;
+ YY_BREAK
+case 199:
+YY_RULE_SETUP
+#line 265 "./config/bfin-lex.l"
+return LESS_LESS;
+ YY_BREAK
+case 200:
+YY_RULE_SETUP
+#line 266 "./config/bfin-lex.l"
+return LESS_THAN;
+ YY_BREAK
+case 201:
+YY_RULE_SETUP
+#line 267 "./config/bfin-lex.l"
+BEGIN(FLAGS); return LPAREN;
+ YY_BREAK
+case 202:
+YY_RULE_SETUP
+#line 268 "./config/bfin-lex.l"
+BEGIN(INITIAL); return RPAREN;
+ YY_BREAK
+case 203:
+YY_RULE_SETUP
+#line 269 "./config/bfin-lex.l"
+return COLON;
+ YY_BREAK
+case 204:
+YY_RULE_SETUP
+#line 270 "./config/bfin-lex.l"
+return SLASH;
+ YY_BREAK
+case 205:
+YY_RULE_SETUP
+#line 271 "./config/bfin-lex.l"
+return _MINUS_ASSIGN;
+ YY_BREAK
+case 206:
+YY_RULE_SETUP
+#line 272 "./config/bfin-lex.l"
+return _PLUS_BAR_PLUS;
+ YY_BREAK
+case 207:
+YY_RULE_SETUP
+#line 273 "./config/bfin-lex.l"
+return _MINUS_BAR_PLUS;
+ YY_BREAK
+case 208:
+YY_RULE_SETUP
+#line 274 "./config/bfin-lex.l"
+return _PLUS_BAR_MINUS;
+ YY_BREAK
+case 209:
+YY_RULE_SETUP
+#line 275 "./config/bfin-lex.l"
+return _MINUS_BAR_MINUS;
+ YY_BREAK
+case 210:
+YY_RULE_SETUP
+#line 276 "./config/bfin-lex.l"
+return _MINUS_MINUS;
+ YY_BREAK
+case 211:
+YY_RULE_SETUP
+#line 277 "./config/bfin-lex.l"
+return MINUS;
+ YY_BREAK
+case 212:
+YY_RULE_SETUP
+#line 278 "./config/bfin-lex.l"
+return COMMA;
+ YY_BREAK
+case 213:
+YY_RULE_SETUP
+#line 279 "./config/bfin-lex.l"
+return _PLUS_ASSIGN;
+ YY_BREAK
+case 214:
+YY_RULE_SETUP
+#line 280 "./config/bfin-lex.l"
+return _PLUS_PLUS;
+ YY_BREAK
+case 215:
+YY_RULE_SETUP
+#line 281 "./config/bfin-lex.l"
+return PLUS;
+ YY_BREAK
+case 216:
+YY_RULE_SETUP
+#line 282 "./config/bfin-lex.l"
+return _STAR_ASSIGN;
+ YY_BREAK
+case 217:
+YY_RULE_SETUP
+#line 283 "./config/bfin-lex.l"
+return STAR;
+ YY_BREAK
+case 218:
+YY_RULE_SETUP
+#line 284 "./config/bfin-lex.l"
+return _AMPERSAND_ASSIGN;
+ YY_BREAK
+case 219:
+YY_RULE_SETUP
+#line 285 "./config/bfin-lex.l"
+return AMPERSAND;
+ YY_BREAK
+case 220:
+YY_RULE_SETUP
+#line 286 "./config/bfin-lex.l"
+return PERCENT;
+ YY_BREAK
+case 221:
+YY_RULE_SETUP
+#line 287 "./config/bfin-lex.l"
+return BANG;
+ YY_BREAK
+case 222:
+YY_RULE_SETUP
+#line 288 "./config/bfin-lex.l"
+return SEMICOLON;
+ YY_BREAK
+case 223:
+YY_RULE_SETUP
+#line 289 "./config/bfin-lex.l"
+return _ASSIGN_BANG;
+ YY_BREAK
+case 224:
+YY_RULE_SETUP
+#line 290 "./config/bfin-lex.l"
+return DOUBLE_BAR;
+ YY_BREAK
+case 225:
+YY_RULE_SETUP
+#line 291 "./config/bfin-lex.l"
+return AT;
+ YY_BREAK
+case 226:
+YY_RULE_SETUP
+#line 292 "./config/bfin-lex.l"
+return PREFETCH;
+ YY_BREAK
+case 227:
+YY_RULE_SETUP
+#line 293 "./config/bfin-lex.l"
+return UNLINK;
+ YY_BREAK
+case 228:
+YY_RULE_SETUP
+#line 294 "./config/bfin-lex.l"
+return LINK;
+ YY_BREAK
+case 229:
+YY_RULE_SETUP
+#line 295 "./config/bfin-lex.l"
+return IDLE;
+ YY_BREAK
+case 230:
+YY_RULE_SETUP
+#line 296 "./config/bfin-lex.l"
+return IFLUSH;
+ YY_BREAK
+case 231:
+YY_RULE_SETUP
+#line 297 "./config/bfin-lex.l"
+return FLUSHINV;
+ YY_BREAK
+case 232:
+YY_RULE_SETUP
+#line 298 "./config/bfin-lex.l"
+return FLUSH;
+ YY_BREAK
+case 233:
+YY_RULE_SETUP
+#line 299 "./config/bfin-lex.l"
+{
+ yylval.value = parse_int (&yytext);
+ return NUMBER;
+ }
+ YY_BREAK
+case 234:
+YY_RULE_SETUP
+#line 303 "./config/bfin-lex.l"
+{
+ yylval.symbol = symbol_find_or_make (yytext);
+ symbol_mark_used (yylval.symbol);
+ return SYMBOL;
+ }
+ YY_BREAK
+case 235:
+YY_RULE_SETUP
+#line 308 "./config/bfin-lex.l"
+{
+ char *name;
+ char *ref = strdup (yytext);
+ if (ref[1] == 'b' || ref[1] == 'B')
+ {
+ name = fb_label_name ((int) (ref[0] - '0'), 0);
+ yylval.symbol = symbol_find (name);
+
+ if ((yylval.symbol != NULL)
+ && (S_IS_DEFINED (yylval.symbol)))
+ return SYMBOL;
+ as_bad ("backward reference to unknown label %d:",
+ (int) (ref[0] - '0'));
+ }
+ else if (ref[1] == 'f' || ref[1] == 'F')
+ {
+ /* Forward reference. Expect symbol to be undefined or
+ unknown. undefined: seen it before. unknown: never seen
+ it before.
+
+ Construct a local label name, then an undefined symbol.
+ Just return it as never seen before. */
+
+ name = fb_label_name ((int) (ref[0] - '0'), 1);
+ yylval.symbol = symbol_find_or_make (name);
+ /* We have no need to check symbol properties. */
+ return SYMBOL;
+ }
+ }
+ YY_BREAK
+case 236:
+/* rule 236 can match eol */
+YY_RULE_SETUP
+#line 337 "./config/bfin-lex.l"
+;
+ YY_BREAK
+case 237:
+YY_RULE_SETUP
+#line 338 "./config/bfin-lex.l"
+;
+ YY_BREAK
+case 238:
+YY_RULE_SETUP
+#line 339 "./config/bfin-lex.l"
+return yytext[0];
+ YY_BREAK
+case 239:
+YY_RULE_SETUP
+#line 340 "./config/bfin-lex.l"
+ECHO;
+ YY_BREAK
+#line 2343 "bfin-lex.c"
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(KEYWORD):
+case YY_STATE_EOF(FLAGS):
+ yyterminate();
+
+ case YY_END_OF_BUFFER:
+ {
+ /* Amount of text matched not including the EOB char. */
+ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+ /* Undo the effects of YY_DO_BEFORE_ACTION. */
+ *yy_cp = (yy_hold_char);
+ YY_RESTORE_YY_MORE_OFFSET
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+ {
+ /* We're scanning a new file or input source. It's
+ * possible that this happened because the user
+ * just pointed yyin at a new source and called
+ * yylex(). If so, then we have to assure
+ * consistency between YY_CURRENT_BUFFER and our
+ * globals. Here is the right place to do so, because
+ * this is the first action (other than possibly a
+ * back-up) that will match for the new input source.
+ */
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+ }
+
+ /* Note that here we test for yy_c_buf_p "<=" to the position
+ * of the first EOB in the buffer, since yy_c_buf_p will
+ * already have been incremented past the NUL character
+ * (since all states make transitions on EOB to the
+ * end-of-buffer state). Contrast this with the test
+ * in input().
+ */
+ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ { /* This was really a NUL. */
+ yy_state_type yy_next_state;
+
+ (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ /* Okay, we're now positioned to make the NUL
+ * transition. We couldn't have
+ * yy_get_previous_state() go ahead and do it
+ * for us because it doesn't know how to deal
+ * with the possibility of jamming (and we don't
+ * want to build jamming into it because then it
+ * will run more slowly).
+ */
+
+ yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+ if ( yy_next_state )
+ {
+ /* Consume the NUL. */
+ yy_cp = ++(yy_c_buf_p);
+ yy_current_state = yy_next_state;
+ goto yy_match;
+ }
+
+ else
+ {
+ yy_cp = (yy_c_buf_p);
+ goto yy_find_action;
+ }
+ }
+
+ else switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_END_OF_FILE:
+ {
+ (yy_did_buffer_switch_on_eof) = 0;
+
+ if ( yywrap( ) )
+ {
+ /* Note: because we've taken care in
+ * yy_get_next_buffer() to have set up
+ * yytext, we can now set up
+ * yy_c_buf_p so that if some total
+ * hoser (like flex itself) wants to
+ * call the scanner after we return the
+ * YY_NULL, it'll still work - another
+ * YY_NULL will get returned.
+ */
+ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+ yy_act = YY_STATE_EOF(YY_START);
+ goto do_action;
+ }
+
+ else
+ {
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+ }
+ break;
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) =
+ (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_match;
+
+ case EOB_ACT_LAST_MATCH:
+ (yy_c_buf_p) =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_find_action;
+ }
+ break;
+ }
+
+ default:
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--no action found" );
+ } /* end of action switch */
+ } /* end of scanning one token */
+} /* end of yylex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ * EOB_ACT_LAST_MATCH -
+ * EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ * EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+ register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+ register char *source = (yytext_ptr);
+ register int number_to_move, i;
+ int ret_val;
+
+ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--end of buffer missed" );
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+ { /* Don't try to fill the buffer, so this is an EOF. */
+ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+ {
+ /* We matched a single character, the EOB, so
+ * treat this as a final EOF.
+ */
+ return EOB_ACT_END_OF_FILE;
+ }
+
+ else
+ {
+ /* We matched some text prior to the EOB, first
+ * process it.
+ */
+ return EOB_ACT_LAST_MATCH;
+ }
+ }
+
+ /* Try to read more data. */
+
+ /* First move last chars to start of buffer. */
+ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+ for ( i = 0; i < number_to_move; ++i )
+ *(dest++) = *(source++);
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+ /* don't do the read, it's not guaranteed to return an EOF,
+ * just force an EOF
+ */
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+ else
+ {
+ yy_size_t num_to_read =
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+ while ( num_to_read <= 0 )
+ { /* Not enough room in the buffer - grow it. */
+
+ /* just a shorter name for the current buffer */
+ YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+ int yy_c_buf_p_offset =
+ (int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+ if ( b->yy_is_our_buffer )
+ {
+ yy_size_t new_size = b->yy_buf_size * 2;
+
+ if ( new_size <= 0 )
+ b->yy_buf_size += b->yy_buf_size / 8;
+ else
+ b->yy_buf_size *= 2;
+
+ b->yy_ch_buf = (char *)
+ /* Include room in for 2 EOB chars. */
+ yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
+ }
+ else
+ /* Can't grow it, we don't own it. */
+ b->yy_ch_buf = 0;
+
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR(
+ "fatal error - scanner input buffer overflow" );
+
+ (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+ num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+ number_to_move - 1;
+
+ }
+
+ if ( num_to_read > YY_READ_BUF_SIZE )
+ num_to_read = YY_READ_BUF_SIZE;
+
+ /* Read in more data. */
+ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+ (yy_n_chars), num_to_read );
+
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ if ( (yy_n_chars) == 0 )
+ {
+ if ( number_to_move == YY_MORE_ADJ )
+ {
+ ret_val = EOB_ACT_END_OF_FILE;
+ yyrestart(yyin );
+ }
+
+ else
+ {
+ ret_val = EOB_ACT_LAST_MATCH;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+ YY_BUFFER_EOF_PENDING;
+ }
+ }
+
+ else
+ ret_val = EOB_ACT_CONTINUE_SCAN;
+
+ if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+ /* Extend the array by 50%, plus the number we really need. */
+ yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size );
+ if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+ }
+
+ (yy_n_chars) += number_to_move;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+ (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+ return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+ static yy_state_type yy_get_previous_state (void)
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp;
+
+ yy_current_state = (yy_start);
+
+ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+ {
+ register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 571 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ }
+
+ return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ * next_state = yy_try_NUL_trans( current_state );
+ */
+ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
+{
+ register int yy_is_jam;
+ register char *yy_cp = (yy_c_buf_p);
+
+ register YY_CHAR yy_c = 1;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 571 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ yy_is_jam = (yy_current_state == 570);
+
+ return yy_is_jam ? 0 : yy_current_state;
+}
+
+ static void yyunput (int c, register char * yy_bp )
+{
+ register char *yy_cp;
+
+ yy_cp = (yy_c_buf_p);
+
+ /* undo effects of setting up yytext */
+ *yy_cp = (yy_hold_char);
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ { /* need to shift things up to make room */
+ /* +2 for EOB chars. */
+ register yy_size_t number_to_move = (yy_n_chars) + 2;
+ register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+ register char *source =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+ while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ *--dest = *--source;
+
+ yy_cp += (int) (dest - source);
+ yy_bp += (int) (dest - source);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ YY_FATAL_ERROR( "flex scanner push-back overflow" );
+ }
+
+ *--yy_cp = (char) c;
+
+ (yytext_ptr) = yy_bp;
+ (yy_hold_char) = *yy_cp;
+ (yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+ static int yyinput (void)
+#else
+ static int input (void)
+#endif
+
+{
+ int c;
+
+ *(yy_c_buf_p) = (yy_hold_char);
+
+ if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+ {
+ /* yy_c_buf_p now points to the character we want to return.
+ * If this occurs *before* the EOB characters, then it's a
+ * valid NUL; if not, then we've hit the end of the buffer.
+ */
+ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ /* This was really a NUL. */
+ *(yy_c_buf_p) = '\0';
+
+ else
+ { /* need more input */
+ yy_size_t offset = (yy_c_buf_p) - (yytext_ptr);
+ ++(yy_c_buf_p);
+
+ switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_LAST_MATCH:
+ /* This happens because yy_g_n_b()
+ * sees that we've accumulated a
+ * token and flags that we need to
+ * try matching the token before
+ * proceeding. But for input(),
+ * there's no matching to consider.
+ * So convert the EOB_ACT_LAST_MATCH
+ * to EOB_ACT_END_OF_FILE.
+ */
+
+ /* Reset buffer status. */
+ yyrestart(yyin );
+
+ /*FALLTHROUGH*/
+
+ case EOB_ACT_END_OF_FILE:
+ {
+ if ( yywrap( ) )
+ return 0;
+
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+#ifdef __cplusplus
+ return yyinput();
+#else
+ return input();
+#endif
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) = (yytext_ptr) + offset;
+ break;
+ }
+ }
+ }
+
+ c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
+ *(yy_c_buf_p) = '\0'; /* preserve yytext */
+ (yy_hold_char) = *++(yy_c_buf_p);
+
+ return c;
+}
+#endif /* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ *
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+ void yyrestart (FILE * input_file )
+{
+
+ if ( ! YY_CURRENT_BUFFER ){
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer(yyin,YY_BUF_SIZE );
+ }
+
+ yy_init_buffer(YY_CURRENT_BUFFER,input_file );
+ yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ *
+ */
+ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer )
+{
+
+ /* TODO. We should be able to replace this entire function body
+ * with
+ * yypop_buffer_state();
+ * yypush_buffer_state(new_buffer);
+ */
+ yyensure_buffer_stack ();
+ if ( YY_CURRENT_BUFFER == new_buffer )
+ return;
+
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+ yy_load_buffer_state( );
+
+ /* We don't actually know whether we did this switch during
+ * EOF (yywrap()) processing, but the only time this flag
+ * is looked at is after yywrap() is called, so it's safe
+ * to go ahead and always set it.
+ */
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void yy_load_buffer_state (void)
+{
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+ yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+ (yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ *
+ * @return the allocated buffer state.
+ */
+ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size )
+{
+ YY_BUFFER_STATE b;
+
+ b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_buf_size = size;
+
+ /* yy_ch_buf has to be 2 characters longer than the size given because
+ * we need to put in 2 end-of-buffer characters.
+ */
+ b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 );
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_is_our_buffer = 1;
+
+ yy_init_buffer(b,file );
+
+ return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ *
+ */
+ void yy_delete_buffer (YY_BUFFER_STATE b )
+{
+
+ if ( ! b )
+ return;
+
+ if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+ if ( b->yy_is_our_buffer )
+ yyfree((void *) b->yy_ch_buf );
+
+ yyfree((void *) b );
+}
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+ static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file )
+
+{
+ int oerrno = errno;
+
+ yy_flush_buffer(b );
+
+ b->yy_input_file = file;
+ b->yy_fill_buffer = 1;
+
+ /* If b is the current buffer, then yy_init_buffer was _probably_
+ * called from yyrestart() or through yy_get_next_buffer.
+ * In that case, we don't want to reset the lineno or column.
+ */
+ if (b != YY_CURRENT_BUFFER){
+ b->yy_bs_lineno = 1;
+ b->yy_bs_column = 0;
+ }
+
+ b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+
+ errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ *
+ */
+ void yy_flush_buffer (YY_BUFFER_STATE b )
+{
+ if ( ! b )
+ return;
+
+ b->yy_n_chars = 0;
+
+ /* We always need two end-of-buffer characters. The first causes
+ * a transition to the end-of-buffer state. The second causes
+ * a jam in that state.
+ */
+ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+ b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+ b->yy_buf_pos = &b->yy_ch_buf[0];
+
+ b->yy_at_bol = 1;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ if ( b == YY_CURRENT_BUFFER )
+ yy_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ * the current state. This function will allocate the stack
+ * if necessary.
+ * @param new_buffer The new state.
+ *
+ */
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+ if (new_buffer == NULL)
+ return;
+
+ yyensure_buffer_stack();
+
+ /* This block is copied from yy_switch_to_buffer. */
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ /* Only push if top exists. Otherwise, replace top. */
+ if (YY_CURRENT_BUFFER)
+ (yy_buffer_stack_top)++;
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+ /* copied from yy_switch_to_buffer. */
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ * The next element becomes the new top.
+ *
+ */
+void yypop_buffer_state (void)
+{
+ if (!YY_CURRENT_BUFFER)
+ return;
+
+ yy_delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ if ((yy_buffer_stack_top) > 0)
+ --(yy_buffer_stack_top);
+
+ if (YY_CURRENT_BUFFER) {
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+ }
+}
+
+/* Allocates the stack if it does not exist.
+ * Guarantees space for at least one push.
+ */
+static void yyensure_buffer_stack (void)
+{
+ yy_size_t num_to_alloc;
+
+ if (!(yy_buffer_stack)) {
+
+ /* First allocation is just for 2 elements, since we don't know if this
+ * scanner will even need a stack. We use 2 instead of 1 to avoid an
+ * immediate realloc on the next call.
+ */
+ num_to_alloc = 1;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+ (num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+
+ (yy_buffer_stack_max) = num_to_alloc;
+ (yy_buffer_stack_top) = 0;
+ return;
+ }
+
+ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+ /* Increase the buffer to prepare for a possible push. */
+ int grow_size = 8 /* arbitrary grow size */;
+
+ num_to_alloc = (yy_buffer_stack_max) + grow_size;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+ ((yy_buffer_stack),
+ num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ /* zero only the new slots.*/
+ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+ (yy_buffer_stack_max) = num_to_alloc;
+ }
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size )
+{
+ YY_BUFFER_STATE b;
+
+ if ( size < 2 ||
+ base[size-2] != YY_END_OF_BUFFER_CHAR ||
+ base[size-1] != YY_END_OF_BUFFER_CHAR )
+ /* They forgot to leave room for the EOB's. */
+ return 0;
+
+ b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+ b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
+ b->yy_buf_pos = b->yy_ch_buf = base;
+ b->yy_is_our_buffer = 0;
+ b->yy_input_file = 0;
+ b->yy_n_chars = b->yy_buf_size;
+ b->yy_is_interactive = 0;
+ b->yy_at_bol = 1;
+ b->yy_fill_buffer = 0;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ yy_switch_to_buffer(b );
+
+ return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to yylex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ *
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ * yy_scan_bytes() instead.
+ */
+YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+{
+
+ return yy_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len )
+{
+ YY_BUFFER_STATE b;
+ char *buf;
+ yy_size_t n, i;
+
+ /* Get memory for full buffer, including space for trailing EOB's. */
+ n = _yybytes_len + 2;
+ buf = (char *) yyalloc(n );
+ if ( ! buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+ for ( i = 0; i < _yybytes_len; ++i )
+ buf[i] = yybytes[i];
+
+ buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+ b = yy_scan_buffer(buf,n );
+ if ( ! b )
+ YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+ /* It's okay to grow etc. this buffer, and we should throw it
+ * away when we're done.
+ */
+ b->yy_is_our_buffer = 1;
+
+ return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+ (void) fprintf( stderr, "%s\n", msg );
+ exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ yytext[yyleng] = (yy_hold_char); \
+ (yy_c_buf_p) = yytext + yyless_macro_arg; \
+ (yy_hold_char) = *(yy_c_buf_p); \
+ *(yy_c_buf_p) = '\0'; \
+ yyleng = yyless_macro_arg; \
+ } \
+ while ( 0 )
+
+/* Accessor methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ *
+ */
+int yyget_lineno (void)
+{
+
+ return yylineno;
+}
+
+/** Get the input stream.
+ *
+ */
+FILE *yyget_in (void)
+{
+ return yyin;
+}
+
+/** Get the output stream.
+ *
+ */
+FILE *yyget_out (void)
+{
+ return yyout;
+}
+
+/** Get the length of the current token.
+ *
+ */
+yy_size_t yyget_leng (void)
+{
+ return yyleng;
+}
+
+/** Get the current token.
+ *
+ */
+
+char *yyget_text (void)
+{
+ return yytext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ *
+ */
+void yyset_lineno (int line_number )
+{
+
+ yylineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ *
+ * @see yy_switch_to_buffer
+ */
+void yyset_in (FILE * in_str )
+{
+ yyin = in_str ;
+}
+
+void yyset_out (FILE * out_str )
+{
+ yyout = out_str ;
+}
+
+int yyget_debug (void)
+{
+ return yy_flex_debug;
+}
+
+void yyset_debug (int bdebug )
+{
+ yy_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+ /* Initialization is the same as for the non-reentrant scanner.
+ * This function is called from yylex_destroy(), so don't allocate here.
+ */
+
+ (yy_buffer_stack) = 0;
+ (yy_buffer_stack_top) = 0;
+ (yy_buffer_stack_max) = 0;
+ (yy_c_buf_p) = (char *) 0;
+ (yy_init) = 0;
+ (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+ yyin = stdin;
+ yyout = stdout;
+#else
+ yyin = (FILE *) 0;
+ yyout = (FILE *) 0;
+#endif
+
+ /* For future reference: Set errno on error, since we are called by
+ * yylex_init()
+ */
+ return 0;
+}
+
+/* yylex_destroy is for both reentrant and non-reentrant scanners. */
+int yylex_destroy (void)
+{
+
+ /* Pop the buffer stack, destroying each element. */
+ while(YY_CURRENT_BUFFER){
+ yy_delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ yypop_buffer_state();
+ }
+
+ /* Destroy the stack itself. */
+ yyfree((yy_buffer_stack) );
+ (yy_buffer_stack) = NULL;
+
+ /* Reset the globals. This is important in a non-reentrant scanner so the next time
+ * yylex() is called, initialization will occur. */
+ yy_init_globals( );
+
+ return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+ register int i;
+ for ( i = 0; i < n; ++i )
+ s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+ register int n;
+ for ( n = 0; s[n]; ++n )
+ ;
+
+ return n;
+}
+#endif
+
+void *yyalloc (yy_size_t size )
+{
+ return (void *) malloc( size );
+}
+
+void *yyrealloc (void * ptr, yy_size_t size )
+{
+ /* The cast to (char *) in the following accommodates both
+ * implementations that use char* generic pointers, and those
+ * that use void* generic pointers. It works with the latter
+ * because both ANSI C and C++ allow castless assignment from
+ * any pointer type to void*, and deal with argument conversions
+ * as though doing an assignment.
+ */
+ return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+ free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 340 "./config/bfin-lex.l"
+
+
+static long parse_int (char **end)
+{
+ char fmt = '\0';
+ int not_done = 1;
+ int shiftvalue = 0;
+ char * char_bag;
+ long value = 0;
+ char *arg = *end;
+
+ while (*arg && *arg == ' ')
+ arg++;
+
+ switch (*arg)
+ {
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ fmt = 'd';
+ break;
+
+ case '0': /* Accept different formatted integers hex octal and binary. */
+ {
+ char c = *++arg;
+ arg++;
+ if (c == 'x' || c == 'X') /* Hex input. */
+ fmt = 'h';
+ else if (c == 'b' || c == 'B')
+ fmt = 'b';
+ else if (c == '.')
+ fmt = 'f';
+ else
+ { /* Octal. */
+ arg--;
+ fmt = 'o';
+ }
+ break;
+ }
+
+ case 'd':
+ case 'D':
+ case 'h':
+ case 'H':
+ case 'o':
+ case 'O':
+ case 'b':
+ case 'B':
+ case 'f':
+ case 'F':
+ {
+ fmt = *arg++;
+ if (*arg == '#')
+ arg++;
+ }
+ }
+
+ switch (fmt)
+ {
+ case 'h':
+ case 'H':
+ shiftvalue = 4;
+ char_bag = "0123456789ABCDEFabcdef";
+ break;
+
+ case 'o':
+ case 'O':
+ shiftvalue = 3;
+ char_bag = "01234567";
+ break;
+
+ case 'b':
+ case 'B':
+ shiftvalue = 1;
+ char_bag = "01";
+ break;
+
+/* The assembler allows for fractional constants to be created
+ by either the 0.xxxx or the f#xxxx format
+
+ i.e. 0.5 would result in 0x4000
+
+ note .5 would result in the identifier .5.
+
+ The assembler converts to fractional format 1.15 by the simple rule:
+
+ value = (short) (finput * (1 << 15)). */
+
+ case 'f':
+ case 'F':
+ {
+ float fval = 0.0;
+ float pos = 10.0;
+ while (1)
+ {
+ int c;
+ c = *arg++;
+
+ if (c >= '0' && c <= '9')
+ {
+ float digit = (c - '0') / pos;
+ fval = fval + digit;
+ pos = pos * 10.0;
+ }
+ else
+ {
+ *--arg = c;
+ value = (short) (fval * (1 << 15));
+ break;
+ }
+ }
+ *end = arg+1;
+ return value;
+ }
+
+ case 'd':
+ case 'D':
+ default:
+ {
+ while (1)
+ {
+ char c;
+ c = *arg++;
+ if (c >= '0' && c <= '9')
+ value = (value * 10) + (c - '0');
+ else
+ {
+ /* Constants that are suffixed with k|K are multiplied by 1024
+ This suffix is only allowed on decimal constants. */
+ if (c == 'k' || c == 'K')
+ value *= 1024;
+ else
+ *--arg = c;
+ break;
+ }
+ }
+ *end = arg+1;
+ return value;
+ }
+ }
+
+ while (not_done)
+ {
+ char c;
+ c = *arg++;
+ if (c == 0 || !strchr (char_bag, c))
+ {
+ not_done = 0;
+ *--arg = c;
+ }
+ else
+ {
+ if (c >= 'a' && c <= 'z')
+ c = c - ('a' - '9') + 1;
+ else if (c >= 'A' && c <= 'Z')
+ c = c - ('A' - '9') + 1;
+
+ c -= '0';
+ value = (value << shiftvalue) + c;
+ }
+ }
+ *end = arg+1;
+ return value;
+}
+
+
+static int parse_reg (Register *r, int cl, char *rt)
+{
+ r->regno = cl | (rt[1] - '0');
+ r->flags = F_REG_NONE;
+ return REG;
+}
+
+static int parse_halfreg (Register *r, int cl, char *rt)
+{
+ r->regno = cl | (rt[1] - '0');
+
+ switch (rt[3])
+ {
+ case 'b':
+ case 'B':
+ return BYTE_DREG;
+
+ case 'l':
+ case 'L':
+ r->flags = F_REG_LOW;
+ break;
+
+ case 'h':
+ case 'H':
+ r->flags = F_REG_HIGH;
+ break;
+ }
+
+ return HALF_REG;
+}
+
+/* Our start state is KEYWORD as we have
+ command keywords such as PREFETCH. */
+
+void
+set_start_state (void)
+{
+ BEGIN KEYWORD;
+}
+
diff --git a/gas/bfin-parse.c b/gas/bfin-parse.c
new file mode 100644
index 0000000..921ab84
--- /dev/null
+++ b/gas/bfin-parse.c
@@ -0,0 +1,7972 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison implementation for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "3.0"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Push parsers. */
+#define YYPUSH 0
+
+/* Pull parsers. */
+#define YYPULL 1
+
+
+
+
+/* Copy the first part of user declarations. */
+#line 20 "./config/bfin-parse.y" /* yacc.c:339 */
+
+
+#include "as.h"
+
+#include "bfin-aux.h" /* Opcode generating auxiliaries. */
+#include "elf/common.h"
+#include "elf/bfin.h"
+
+#define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
+ bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
+
+#define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+ bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+ dst, src0, src1, w0)
+
+#define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+ bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+ dst, src0, src1, w0)
+
+#define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
+ bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
+
+#define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
+ bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
+
+#define LDIMMHALF_R(reg, h, s, z, hword) \
+ bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
+
+#define LDIMMHALF_R5(reg, h, s, z, hword) \
+ bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
+
+#define LDSTIDXI(ptr, reg, w, sz, z, offset) \
+ bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
+
+#define LDST(ptr, reg, aop, sz, z, w) \
+ bfin_gen_ldst (ptr, reg, aop, sz, z, w)
+
+#define LDSTII(ptr, reg, offset, w, op) \
+ bfin_gen_ldstii (ptr, reg, offset, w, op)
+
+#define DSPLDST(i, m, reg, aop, w) \
+ bfin_gen_dspldst (i, reg, aop, w, m)
+
+#define LDSTPMOD(ptr, reg, idx, aop, w) \
+ bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
+
+#define LDSTIIFP(offset, reg, w) \
+ bfin_gen_ldstiifp (reg, offset, w)
+
+#define LOGI2OP(dst, src, opc) \
+ bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
+
+#define ALU2OP(dst, src, opc) \
+ bfin_gen_alu2op (dst, src, opc)
+
+#define BRCC(t, b, offset) \
+ bfin_gen_brcc (t, b, offset)
+
+#define UJUMP(offset) \
+ bfin_gen_ujump (offset)
+
+#define PROGCTRL(prgfunc, poprnd) \
+ bfin_gen_progctrl (prgfunc, poprnd)
+
+#define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
+ bfin_gen_pushpopmultiple (dr, pr, d, p, w)
+
+#define PUSHPOPREG(reg, w) \
+ bfin_gen_pushpopreg (reg, w)
+
+#define CALLA(addr, s) \
+ bfin_gen_calla (addr, s)
+
+#define LINKAGE(r, framesize) \
+ bfin_gen_linkage (r, framesize)
+
+#define COMPI2OPD(dst, src, op) \
+ bfin_gen_compi2opd (dst, src, op)
+
+#define COMPI2OPP(dst, src, op) \
+ bfin_gen_compi2opp (dst, src, op)
+
+#define DAGMODIK(i, op) \
+ bfin_gen_dagmodik (i, op)
+
+#define DAGMODIM(i, m, op, br) \
+ bfin_gen_dagmodim (i, m, op, br)
+
+#define COMP3OP(dst, src0, src1, opc) \
+ bfin_gen_comp3op (src0, src1, dst, opc)
+
+#define PTR2OP(dst, src, opc) \
+ bfin_gen_ptr2op (dst, src, opc)
+
+#define CCFLAG(x, y, opc, i, g) \
+ bfin_gen_ccflag (x, y, opc, i, g)
+
+#define CCMV(src, dst, t) \
+ bfin_gen_ccmv (src, dst, t)
+
+#define CACTRL(reg, a, op) \
+ bfin_gen_cactrl (reg, a, op)
+
+#define LOOPSETUP(soffset, c, rop, eoffset, reg) \
+ bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
+
+#define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
+#define IS_RANGE(bits, expr, sign, mul) \
+ value_match(expr, bits, sign, mul, 1)
+#define IS_URANGE(bits, expr, sign, mul) \
+ value_match(expr, bits, sign, mul, 0)
+#define IS_CONST(expr) (expr->type == Expr_Node_Constant)
+#define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
+#define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
+#define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
+
+#define IS_PCREL4(expr) \
+ (value_match (expr, 4, 0, 2, 0))
+
+#define IS_LPPCREL10(expr) \
+ (value_match (expr, 10, 0, 2, 0))
+
+#define IS_PCREL10(expr) \
+ (value_match (expr, 10, 0, 2, 1))
+
+#define IS_PCREL12(expr) \
+ (value_match (expr, 12, 0, 2, 1))
+
+#define IS_PCREL24(expr) \
+ (value_match (expr, 24, 0, 2, 1))
+
+
+static int value_match (Expr_Node *, int, int, int, int);
+
+extern FILE *errorf;
+extern INSTR_T insn;
+
+static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
+static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
+
+static void notethat (const char *, ...);
+
+extern char *yytext;
+int yyerror (const char *);
+
+/* Used to set SRCx fields to all 1s as described in the PRM. */
+static Register reg7 = {REG_R7, 0};
+
+void error (const char *format, ...)
+{
+ va_list ap;
+ static char buffer[2000];
+
+ va_start (ap, format);
+ vsprintf (buffer, format, ap);
+ va_end (ap);
+
+ as_bad ("%s", buffer);
+}
+
+int
+yyerror (const char *msg)
+{
+ if (msg[0] == '\0')
+ error ("%s", msg);
+
+ else if (yytext[0] != ';')
+ error ("%s. Input text was %s.", msg, yytext);
+ else
+ error ("%s.", msg);
+
+ return -1;
+}
+
+static int
+in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
+{
+ int val = EXPR_VALUE (exp);
+ if (exp->type != Expr_Node_Constant)
+ return 0;
+ if (val < from || val > to)
+ return 0;
+ return (val & mask) == 0;
+}
+
+extern int yylex (void);
+
+#define imm3(x) EXPR_VALUE (x)
+#define imm4(x) EXPR_VALUE (x)
+#define uimm4(x) EXPR_VALUE (x)
+#define imm5(x) EXPR_VALUE (x)
+#define uimm5(x) EXPR_VALUE (x)
+#define imm6(x) EXPR_VALUE (x)
+#define imm7(x) EXPR_VALUE (x)
+#define uimm8(x) EXPR_VALUE (x)
+#define imm16(x) EXPR_VALUE (x)
+#define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
+#define uimm16(x) EXPR_VALUE (x)
+
+/* Return true if a value is inside a range. */
+#define IN_RANGE(x, low, high) \
+ (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
+
+/* Auxiliary functions. */
+
+static int
+valid_dreg_pair (Register *reg1, Expr_Node *reg2)
+{
+ if (!IS_DREG (*reg1))
+ {
+ yyerror ("Dregs expected");
+ return 0;
+ }
+
+ if (reg1->regno != 1 && reg1->regno != 3)
+ {
+ yyerror ("Bad register pair");
+ return 0;
+ }
+
+ if (imm7 (reg2) != reg1->regno - 1)
+ {
+ yyerror ("Bad register pair");
+ return 0;
+ }
+
+ reg1->regno--;
+ return 1;
+}
+
+static int
+check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
+{
+ if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
+ || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
+ return yyerror ("Source multiplication register mismatch");
+
+ return 0;
+}
+
+
+/* Check mac option. */
+
+static int
+check_macfunc_option (Macfunc *a, Opt_mode *opt)
+{
+ /* Default option is always valid. */
+ if (opt->mod == 0)
+ return 0;
+
+ if ((a->w == 1 && a->P == 1
+ && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
+ && opt->mod != M_S2RND && opt->mod != M_ISS2)
+ || (a->w == 1 && a->P == 0
+ && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
+ && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
+ && opt->mod != M_ISS2 && opt->mod != M_IH)
+ || (a->w == 0 && a->P == 0
+ && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
+ return -1;
+
+ return 0;
+}
+
+/* Check (vector) mac funcs and ops. */
+
+static int
+check_macfuncs (Macfunc *aa, Opt_mode *opa,
+ Macfunc *ab, Opt_mode *opb)
+{
+ /* Variables for swapping. */
+ Macfunc mtmp;
+ Opt_mode otmp;
+
+ /* The option mode should be put at the end of the second instruction
+ of the vector except M, which should follow MAC1 instruction. */
+ if (opa->mod != 0)
+ return yyerror ("Bad opt mode");
+
+ /* If a0macfunc comes before a1macfunc, swap them. */
+
+ if (aa->n == 0)
+ {
+ /* (M) is not allowed here. */
+ if (opa->MM != 0)
+ return yyerror ("(M) not allowed with A0MAC");
+ if (ab->n != 1)
+ return yyerror ("Vector AxMACs can't be same");
+
+ mtmp = *aa; *aa = *ab; *ab = mtmp;
+ otmp = *opa; *opa = *opb; *opb = otmp;
+ }
+ else
+ {
+ if (opb->MM != 0)
+ return yyerror ("(M) not allowed with A0MAC");
+ if (ab->n != 0)
+ return yyerror ("Vector AxMACs can't be same");
+ }
+
+ /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
+ assignment_or_macfuncs. */
+ if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
+ && (ab->op == 0 || ab->op == 1 || ab->op == 2))
+ {
+ if (check_multiply_halfregs (aa, ab) < 0)
+ return -1;
+ }
+ else
+ {
+ /* Only one of the assign_macfuncs has a half reg multiply
+ Evil trick: Just 'OR' their source register codes:
+ We can do that, because we know they were initialized to 0
+ in the rules that don't use multiply_halfregs. */
+ aa->s0.regno |= (ab->s0.regno & CODE_MASK);
+ aa->s1.regno |= (ab->s1.regno & CODE_MASK);
+ }
+
+ if (aa->w == ab->w && aa->P != ab->P)
+ return yyerror ("Destination Dreg sizes (full or half) must match");
+
+ if (aa->w && ab->w)
+ {
+ if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
+ return yyerror ("Destination Dregs (full) must differ by one");
+ if (!aa->P && aa->dst.regno != ab->dst.regno)
+ return yyerror ("Destination Dregs (half) must match");
+ }
+
+ /* Make sure mod flags get ORed, too. */
+ opb->mod |= opa->mod;
+
+ /* Check option. */
+ if (check_macfunc_option (aa, opb) < 0
+ && check_macfunc_option (ab, opb) < 0)
+ return yyerror ("bad option");
+
+ /* Make sure first macfunc has got both P flags ORed. */
+ aa->P |= ab->P;
+
+ return 0;
+}
+
+
+static int
+is_group1 (INSTR_T x)
+{
+ /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
+ if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
+ return 1;
+
+ return 0;
+}
+
+static int
+is_group2 (INSTR_T x)
+{
+ if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
+ && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
+ && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
+ && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
+ || (x->value == 0x0000))
+ return 1;
+ return 0;
+}
+
+static int
+is_store (INSTR_T x)
+{
+ if (!x)
+ return 0;
+
+ if ((x->value & 0xf000) == 0x8000)
+ {
+ int aop = ((x->value >> 9) & 0x3);
+ int w = ((x->value >> 11) & 0x1);
+ if (!w || aop == 3)
+ return 0;
+ return 1;
+ }
+
+ if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
+ ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
+ return 0;
+
+ /* decode_dspLDST_0 */
+ if ((x->value & 0xFC00) == 0x9C00)
+ {
+ int w = ((x->value >> 9) & 0x1);
+ if (w)
+ return 1;
+ }
+
+ return 0;
+}
+
+static INSTR_T
+gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
+{
+ int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
+ int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
+ int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
+
+ if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
+ yyerror ("resource conflict in multi-issue instruction");
+
+ /* Anomaly 05000074 */
+ if (ENABLE_AC_05000074
+ && dsp32 != NULL && dsp16_grp1 != NULL
+ && (dsp32->value & 0xf780) == 0xc680
+ && ((dsp16_grp1->value & 0xfe40) == 0x9240
+ || (dsp16_grp1->value & 0xfe08) == 0xba08
+ || (dsp16_grp1->value & 0xfc00) == 0xbc00))
+ yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
+dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
+
+ if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
+ yyerror ("Only one instruction in multi-issue instruction can be a store");
+
+ return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
+}
+
+
+#line 490 "bfin-parse.c" /* yacc.c:339 */
+
+# ifndef YY_NULL
+# if defined __cplusplus && 201103L <= __cplusplus
+# define YY_NULL nullptr
+# else
+# define YY_NULL 0
+# endif
+# endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* In a future release of Bison, this section will be replaced
+ by #include "y.tab.h". */
+#ifndef YY_YY_BFIN_PARSE_H_INCLUDED
+# define YY_YY_BFIN_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ BYTEOP16P = 258,
+ BYTEOP16M = 259,
+ BYTEOP1P = 260,
+ BYTEOP2P = 261,
+ BYTEOP3P = 262,
+ BYTEUNPACK = 263,
+ BYTEPACK = 264,
+ PACK = 265,
+ SAA = 266,
+ ALIGN8 = 267,
+ ALIGN16 = 268,
+ ALIGN24 = 269,
+ VIT_MAX = 270,
+ EXTRACT = 271,
+ DEPOSIT = 272,
+ EXPADJ = 273,
+ SEARCH = 274,
+ ONES = 275,
+ SIGN = 276,
+ SIGNBITS = 277,
+ LINK = 278,
+ UNLINK = 279,
+ REG = 280,
+ PC = 281,
+ CCREG = 282,
+ BYTE_DREG = 283,
+ REG_A_DOUBLE_ZERO = 284,
+ REG_A_DOUBLE_ONE = 285,
+ A_ZERO_DOT_L = 286,
+ A_ZERO_DOT_H = 287,
+ A_ONE_DOT_L = 288,
+ A_ONE_DOT_H = 289,
+ HALF_REG = 290,
+ NOP = 291,
+ RTI = 292,
+ RTS = 293,
+ RTX = 294,
+ RTN = 295,
+ RTE = 296,
+ HLT = 297,
+ IDLE = 298,
+ STI = 299,
+ CLI = 300,
+ CSYNC = 301,
+ SSYNC = 302,
+ EMUEXCPT = 303,
+ RAISE = 304,
+ EXCPT = 305,
+ LSETUP = 306,
+ LOOP = 307,
+ LOOP_BEGIN = 308,
+ LOOP_END = 309,
+ DISALGNEXCPT = 310,
+ JUMP = 311,
+ JUMP_DOT_S = 312,
+ JUMP_DOT_L = 313,
+ CALL = 314,
+ ABORT = 315,
+ NOT = 316,
+ TILDA = 317,
+ BANG = 318,
+ AMPERSAND = 319,
+ BAR = 320,
+ PERCENT = 321,
+ CARET = 322,
+ BXOR = 323,
+ MINUS = 324,
+ PLUS = 325,
+ STAR = 326,
+ SLASH = 327,
+ NEG = 328,
+ MIN = 329,
+ MAX = 330,
+ ABS = 331,
+ DOUBLE_BAR = 332,
+ _PLUS_BAR_PLUS = 333,
+ _PLUS_BAR_MINUS = 334,
+ _MINUS_BAR_PLUS = 335,
+ _MINUS_BAR_MINUS = 336,
+ _MINUS_MINUS = 337,
+ _PLUS_PLUS = 338,
+ SHIFT = 339,
+ LSHIFT = 340,
+ ASHIFT = 341,
+ BXORSHIFT = 342,
+ _GREATER_GREATER_GREATER_THAN_ASSIGN = 343,
+ ROT = 344,
+ LESS_LESS = 345,
+ GREATER_GREATER = 346,
+ _GREATER_GREATER_GREATER = 347,
+ _LESS_LESS_ASSIGN = 348,
+ _GREATER_GREATER_ASSIGN = 349,
+ DIVS = 350,
+ DIVQ = 351,
+ ASSIGN = 352,
+ _STAR_ASSIGN = 353,
+ _BAR_ASSIGN = 354,
+ _CARET_ASSIGN = 355,
+ _AMPERSAND_ASSIGN = 356,
+ _MINUS_ASSIGN = 357,
+ _PLUS_ASSIGN = 358,
+ _ASSIGN_BANG = 359,
+ _LESS_THAN_ASSIGN = 360,
+ _ASSIGN_ASSIGN = 361,
+ GE = 362,
+ LT = 363,
+ LE = 364,
+ GT = 365,
+ LESS_THAN = 366,
+ FLUSHINV = 367,
+ FLUSH = 368,
+ IFLUSH = 369,
+ PREFETCH = 370,
+ PRNT = 371,
+ OUTC = 372,
+ WHATREG = 373,
+ TESTSET = 374,
+ ASL = 375,
+ ASR = 376,
+ B = 377,
+ W = 378,
+ NS = 379,
+ S = 380,
+ CO = 381,
+ SCO = 382,
+ TH = 383,
+ TL = 384,
+ BP = 385,
+ BREV = 386,
+ X = 387,
+ Z = 388,
+ M = 389,
+ MMOD = 390,
+ R = 391,
+ RND = 392,
+ RNDL = 393,
+ RNDH = 394,
+ RND12 = 395,
+ RND20 = 396,
+ V = 397,
+ LO = 398,
+ HI = 399,
+ BITTGL = 400,
+ BITCLR = 401,
+ BITSET = 402,
+ BITTST = 403,
+ BITMUX = 404,
+ DBGAL = 405,
+ DBGAH = 406,
+ DBGHALT = 407,
+ DBG = 408,
+ DBGA = 409,
+ DBGCMPLX = 410,
+ IF = 411,
+ COMMA = 412,
+ BY = 413,
+ COLON = 414,
+ SEMICOLON = 415,
+ RPAREN = 416,
+ LPAREN = 417,
+ LBRACK = 418,
+ RBRACK = 419,
+ STATUS_REG = 420,
+ MNOP = 421,
+ SYMBOL = 422,
+ NUMBER = 423,
+ GOT = 424,
+ GOT17M4 = 425,
+ FUNCDESC_GOT17M4 = 426,
+ AT = 427,
+ PLTPC = 428
+ };
+#endif
+/* Tokens. */
+#define BYTEOP16P 258
+#define BYTEOP16M 259
+#define BYTEOP1P 260
+#define BYTEOP2P 261
+#define BYTEOP3P 262
+#define BYTEUNPACK 263
+#define BYTEPACK 264
+#define PACK 265
+#define SAA 266
+#define ALIGN8 267
+#define ALIGN16 268
+#define ALIGN24 269
+#define VIT_MAX 270
+#define EXTRACT 271
+#define DEPOSIT 272
+#define EXPADJ 273
+#define SEARCH 274
+#define ONES 275
+#define SIGN 276
+#define SIGNBITS 277
+#define LINK 278
+#define UNLINK 279
+#define REG 280
+#define PC 281
+#define CCREG 282
+#define BYTE_DREG 283
+#define REG_A_DOUBLE_ZERO 284
+#define REG_A_DOUBLE_ONE 285
+#define A_ZERO_DOT_L 286
+#define A_ZERO_DOT_H 287
+#define A_ONE_DOT_L 288
+#define A_ONE_DOT_H 289
+#define HALF_REG 290
+#define NOP 291
+#define RTI 292
+#define RTS 293
+#define RTX 294
+#define RTN 295
+#define RTE 296
+#define HLT 297
+#define IDLE 298
+#define STI 299
+#define CLI 300
+#define CSYNC 301
+#define SSYNC 302
+#define EMUEXCPT 303
+#define RAISE 304
+#define EXCPT 305
+#define LSETUP 306
+#define LOOP 307
+#define LOOP_BEGIN 308
+#define LOOP_END 309
+#define DISALGNEXCPT 310
+#define JUMP 311
+#define JUMP_DOT_S 312
+#define JUMP_DOT_L 313
+#define CALL 314
+#define ABORT 315
+#define NOT 316
+#define TILDA 317
+#define BANG 318
+#define AMPERSAND 319
+#define BAR 320
+#define PERCENT 321
+#define CARET 322
+#define BXOR 323
+#define MINUS 324
+#define PLUS 325
+#define STAR 326
+#define SLASH 327
+#define NEG 328
+#define MIN 329
+#define MAX 330
+#define ABS 331
+#define DOUBLE_BAR 332
+#define _PLUS_BAR_PLUS 333
+#define _PLUS_BAR_MINUS 334
+#define _MINUS_BAR_PLUS 335
+#define _MINUS_BAR_MINUS 336
+#define _MINUS_MINUS 337
+#define _PLUS_PLUS 338
+#define SHIFT 339
+#define LSHIFT 340
+#define ASHIFT 341
+#define BXORSHIFT 342
+#define _GREATER_GREATER_GREATER_THAN_ASSIGN 343
+#define ROT 344
+#define LESS_LESS 345
+#define GREATER_GREATER 346
+#define _GREATER_GREATER_GREATER 347
+#define _LESS_LESS_ASSIGN 348
+#define _GREATER_GREATER_ASSIGN 349
+#define DIVS 350
+#define DIVQ 351
+#define ASSIGN 352
+#define _STAR_ASSIGN 353
+#define _BAR_ASSIGN 354
+#define _CARET_ASSIGN 355
+#define _AMPERSAND_ASSIGN 356
+#define _MINUS_ASSIGN 357
+#define _PLUS_ASSIGN 358
+#define _ASSIGN_BANG 359
+#define _LESS_THAN_ASSIGN 360
+#define _ASSIGN_ASSIGN 361
+#define GE 362
+#define LT 363
+#define LE 364
+#define GT 365
+#define LESS_THAN 366
+#define FLUSHINV 367
+#define FLUSH 368
+#define IFLUSH 369
+#define PREFETCH 370
+#define PRNT 371
+#define OUTC 372
+#define WHATREG 373
+#define TESTSET 374
+#define ASL 375
+#define ASR 376
+#define B 377
+#define W 378
+#define NS 379
+#define S 380
+#define CO 381
+#define SCO 382
+#define TH 383
+#define TL 384
+#define BP 385
+#define BREV 386
+#define X 387
+#define Z 388
+#define M 389
+#define MMOD 390
+#define R 391
+#define RND 392
+#define RNDL 393
+#define RNDH 394
+#define RND12 395
+#define RND20 396
+#define V 397
+#define LO 398
+#define HI 399
+#define BITTGL 400
+#define BITCLR 401
+#define BITSET 402
+#define BITTST 403
+#define BITMUX 404
+#define DBGAL 405
+#define DBGAH 406
+#define DBGHALT 407
+#define DBG 408
+#define DBGA 409
+#define DBGCMPLX 410
+#define IF 411
+#define COMMA 412
+#define BY 413
+#define COLON 414
+#define SEMICOLON 415
+#define RPAREN 416
+#define LPAREN 417
+#define LBRACK 418
+#define RBRACK 419
+#define STATUS_REG 420
+#define MNOP 421
+#define SYMBOL 422
+#define NUMBER 423
+#define GOT 424
+#define GOT17M4 425
+#define FUNCDESC_GOT17M4 426
+#define AT 427
+#define PLTPC 428
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 444 "./config/bfin-parse.y" /* yacc.c:355 */
+
+ INSTR_T instr;
+ Expr_Node *expr;
+ SYMBOL_T symbol;
+ long value;
+ Register reg;
+ Macfunc macfunc;
+ struct { int r0; int s0; int x0; int aop; } modcodes;
+ struct { int r0; } r0;
+ Opt_mode mod;
+
+#line 888 "bfin-parse.c" /* yacc.c:355 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_BFIN_PARSE_H_INCLUDED */
+
+/* Copy the second part of user declarations. */
+
+#line 903 "bfin-parse.c" /* yacc.c:358 */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef __attribute__
+/* This feature is available in gcc versions 2.5 and later. */
+# if (! defined __GNUC__ || __GNUC__ < 2 \
+ || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+# define __attribute__(Spec) /* empty */
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+ _Pragma ("GCC diagnostic push") \
+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+ _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's 'empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+ Stack = &yyptr->Stack_alloc; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(Dst, Src, Count) \
+ __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+# else
+# define YYCOPY(Dst, Src, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 156
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 1309
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 174
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 47
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 354
+/* YYNSTATES -- Number of states. */
+#define YYNSTATES 1021
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+ by yylex, with out-of-bounds checking. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 428
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, without out-of-bounds checking. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
+ 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+ 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
+ 115, 116, 117, 118, 119, 120, 121, 122, 123, 124,
+ 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
+ 135, 136, 137, 138, 139, 140, 141, 142, 143, 144,
+ 145, 146, 147, 148, 149, 150, 151, 152, 153, 154,
+ 155, 156, 157, 158, 159, 160, 161, 162, 163, 164,
+ 165, 166, 167, 168, 169, 170, 171, 172, 173
+};
+
+#if YYDEBUG
+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 645, 645, 646, 658, 660, 693, 720, 731, 735,
+ 773, 793, 798, 808, 818, 823, 828, 846, 864, 878,
+ 891, 907, 929, 947, 972, 994, 999, 1009, 1020, 1031,
+ 1045, 1060, 1076, 1092, 1103, 1117, 1143, 1161, 1166, 1172,
+ 1184, 1195, 1206, 1217, 1228, 1239, 1250, 1276, 1290, 1300,
+ 1345, 1364, 1375, 1386, 1397, 1408, 1419, 1435, 1452, 1468,
+ 1479, 1490, 1523, 1534, 1547, 1558, 1597, 1607, 1617, 1637,
+ 1647, 1657, 1668, 1682, 1693, 1706, 1716, 1728, 1743, 1754,
+ 1760, 1782, 1793, 1804, 1812, 1838, 1868, 1897, 1928, 1942,
+ 1953, 1967, 2001, 2019, 2044, 2056, 2074, 2085, 2096, 2107,
+ 2120, 2131, 2142, 2153, 2164, 2175, 2208, 2218, 2231, 2251,
+ 2262, 2273, 2286, 2299, 2310, 2321, 2332, 2343, 2353, 2364,
+ 2375, 2387, 2398, 2409, 2423, 2436, 2448, 2460, 2471, 2482,
+ 2493, 2505, 2517, 2528, 2539, 2550, 2560, 2566, 2572, 2578,
+ 2584, 2590, 2596, 2602, 2608, 2614, 2620, 2631, 2642, 2653,
+ 2664, 2675, 2686, 2697, 2703, 2717, 2728, 2739, 2750, 2761,
+ 2771, 2784, 2792, 2800, 2824, 2835, 2846, 2857, 2868, 2879,
+ 2891, 2904, 2913, 2924, 2935, 2947, 2958, 2969, 2980, 2994,
+ 3006, 3032, 3062, 3073, 3098, 3135, 3163, 3188, 3199, 3210,
+ 3221, 3247, 3266, 3280, 3304, 3316, 3335, 3381, 3418, 3434,
+ 3453, 3467, 3486, 3502, 3510, 3519, 3530, 3542, 3556, 3564,
+ 3574, 3586, 3597, 3607, 3618, 3629, 3635, 3640, 3645, 3651,
+ 3659, 3665, 3671, 3677, 3683, 3689, 3697, 3711, 3715, 3725,
+ 3729, 3734, 3739, 3744, 3751, 3755, 3762, 3766, 3771, 3776,
+ 3784, 3788, 3795, 3799, 3807, 3812, 3818, 3827, 3832, 3838,
+ 3844, 3850, 3859, 3862, 3866, 3873, 3876, 3880, 3887, 3892,
+ 3898, 3904, 3910, 3915, 3923, 3926, 3933, 3936, 3943, 3947,
+ 3951, 3955, 3962, 3965, 3972, 3977, 3984, 3991, 4003, 4007,
+ 4011, 4018, 4021, 4031, 4034, 4043, 4049, 4058, 4062, 4069,
+ 4073, 4077, 4081, 4088, 4092, 4099, 4107, 4115, 4123, 4131,
+ 4138, 4145, 4153, 4163, 4168, 4173, 4178, 4186, 4189, 4193,
+ 4202, 4209, 4216, 4223, 4238, 4244, 4257, 4270, 4288, 4295,
+ 4302, 4312, 4325, 4329, 4333, 4337, 4344, 4350, 4356, 4362,
+ 4372, 4381, 4383, 4385, 4389, 4397, 4401, 4408, 4414, 4420,
+ 4424, 4428, 4432, 4438, 4444, 4448, 4452, 4456, 4460, 4464,
+ 4468, 4472, 4476, 4480, 4484
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "BYTEOP16P", "BYTEOP16M", "BYTEOP1P",
+ "BYTEOP2P", "BYTEOP3P", "BYTEUNPACK", "BYTEPACK", "PACK", "SAA",
+ "ALIGN8", "ALIGN16", "ALIGN24", "VIT_MAX", "EXTRACT", "DEPOSIT",
+ "EXPADJ", "SEARCH", "ONES", "SIGN", "SIGNBITS", "LINK", "UNLINK", "REG",
+ "PC", "CCREG", "BYTE_DREG", "REG_A_DOUBLE_ZERO", "REG_A_DOUBLE_ONE",
+ "A_ZERO_DOT_L", "A_ZERO_DOT_H", "A_ONE_DOT_L", "A_ONE_DOT_H", "HALF_REG",
+ "NOP", "RTI", "RTS", "RTX", "RTN", "RTE", "HLT", "IDLE", "STI", "CLI",
+ "CSYNC", "SSYNC", "EMUEXCPT", "RAISE", "EXCPT", "LSETUP", "LOOP",
+ "LOOP_BEGIN", "LOOP_END", "DISALGNEXCPT", "JUMP", "JUMP_DOT_S",
+ "JUMP_DOT_L", "CALL", "ABORT", "NOT", "TILDA", "BANG", "AMPERSAND",
+ "BAR", "PERCENT", "CARET", "BXOR", "MINUS", "PLUS", "STAR", "SLASH",
+ "NEG", "MIN", "MAX", "ABS", "DOUBLE_BAR", "_PLUS_BAR_PLUS",
+ "_PLUS_BAR_MINUS", "_MINUS_BAR_PLUS", "_MINUS_BAR_MINUS", "_MINUS_MINUS",
+ "_PLUS_PLUS", "SHIFT", "LSHIFT", "ASHIFT", "BXORSHIFT",
+ "_GREATER_GREATER_GREATER_THAN_ASSIGN", "ROT", "LESS_LESS",
+ "GREATER_GREATER", "_GREATER_GREATER_GREATER", "_LESS_LESS_ASSIGN",
+ "_GREATER_GREATER_ASSIGN", "DIVS", "DIVQ", "ASSIGN", "_STAR_ASSIGN",
+ "_BAR_ASSIGN", "_CARET_ASSIGN", "_AMPERSAND_ASSIGN", "_MINUS_ASSIGN",
+ "_PLUS_ASSIGN", "_ASSIGN_BANG", "_LESS_THAN_ASSIGN", "_ASSIGN_ASSIGN",
+ "GE", "LT", "LE", "GT", "LESS_THAN", "FLUSHINV", "FLUSH", "IFLUSH",
+ "PREFETCH", "PRNT", "OUTC", "WHATREG", "TESTSET", "ASL", "ASR", "B", "W",
+ "NS", "S", "CO", "SCO", "TH", "TL", "BP", "BREV", "X", "Z", "M", "MMOD",
+ "R", "RND", "RNDL", "RNDH", "RND12", "RND20", "V", "LO", "HI", "BITTGL",
+ "BITCLR", "BITSET", "BITTST", "BITMUX", "DBGAL", "DBGAH", "DBGHALT",
+ "DBG", "DBGA", "DBGCMPLX", "IF", "COMMA", "BY", "COLON", "SEMICOLON",
+ "RPAREN", "LPAREN", "LBRACK", "RBRACK", "STATUS_REG", "MNOP", "SYMBOL",
+ "NUMBER", "GOT", "GOT17M4", "FUNCDESC_GOT17M4", "AT", "PLTPC", "$accept",
+ "statement", "asm", "asm_1", "REG_A", "opt_mode", "asr_asl", "sco",
+ "asr_asl_0", "amod0", "amod1", "amod2", "xpmod", "xpmod1", "vsmod",
+ "vmod", "smod", "searchmod", "aligndir", "byteop_mod", "c_align",
+ "w32_or_nothing", "iu_or_nothing", "reg_with_predec", "reg_with_postinc",
+ "min_max", "op_bar_op", "plus_minus", "rnd_op", "b3_op", "post_op",
+ "a_assign", "a_minusassign", "a_plusassign", "assign_macfunc",
+ "a_macfunc", "multiply_halfregs", "cc_op", "ccstat", "symbol",
+ "any_gotrel", "got", "got_or_expr", "pltpc", "eterm", "expr", "expr_1", YY_NULL
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+ (internal) symbol number NUM (which must be that of a token). */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
+ 275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
+ 285, 286, 287, 288, 289, 290, 291, 292, 293, 294,
+ 295, 296, 297, 298, 299, 300, 301, 302, 303, 304,
+ 305, 306, 307, 308, 309, 310, 311, 312, 313, 314,
+ 315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
+ 325, 326, 327, 328, 329, 330, 331, 332, 333, 334,
+ 335, 336, 337, 338, 339, 340, 341, 342, 343, 344,
+ 345, 346, 347, 348, 349, 350, 351, 352, 353, 354,
+ 355, 356, 357, 358, 359, 360, 361, 362, 363, 364,
+ 365, 366, 367, 368, 369, 370, 371, 372, 373, 374,
+ 375, 376, 377, 378, 379, 380, 381, 382, 383, 384,
+ 385, 386, 387, 388, 389, 390, 391, 392, 393, 394,
+ 395, 396, 397, 398, 399, 400, 401, 402, 403, 404,
+ 405, 406, 407, 408, 409, 410, 411, 412, 413, 414,
+ 415, 416, 417, 418, 419, 420, 421, 422, 423, 424,
+ 425, 426, 427, 428
+};
+# endif
+
+#define YYPACT_NINF -869
+
+#define yypact_value_is_default(Yystate) \
+ (!!((Yystate) == (-869)))
+
+#define YYTABLE_NINF -214
+
+#define yytable_value_is_error(Yytable_value) \
+ 0
+
+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+static const yytype_int16 yypact[] =
+{
+ 862, -869, -96, -14, -869, 653, 618, -869, -869, -22,
+ -7, 20, 71, 85, -869, -869, -869, -869, -869, -869,
+ -869, -869, 58, 176, -869, -869, -869, -14, -14, 48,
+ -14, 167, 231, -869, 327, -14, -14, 376, -869, 53,
+ 56, 94, 96, 120, 126, 114, 64, 139, 144, 419,
+ 115, 171, 185, 199, 207, 230, -869, 324, 250, 258,
+ 43, 358, 25, 419, -869, 387, -869, -39, 13, 325,
+ 223, 245, 390, 300, -869, -869, 443, -14, -14, -14,
+ -869, -869, -869, -869, -869, 582, 152, 170, 178, 496,
+ 453, 203, 259, 7, -869, -869, -869, 26, -46, 448,
+ 455, 458, 464, 111, -869, -869, -869, -869, -14, 463,
+ -10, -869, -9, -869, 32, -869, -869, 308, -869, -869,
+ 102, -869, -869, 479, 492, 497, -869, 505, -869, 508,
+ -869, 523, -869, -869, -869, 526, 541, 561, -869, 530,
+ 567, 581, 586, 602, 611, 625, -869, -869, 549, 632,
+ 57, 589, 221, 172, 637, 614, -869, 1008, -869, -869,
+ -869, 365, 4, -869, 584, 394, 365, 365, 365, 498,
+ 365, -6, -14, -869, -869, 507, -869, -869, 301, 510,
+ 519, -869, -869, 524, -14, -14, -14, -14, -14, -14,
+ -14, -14, -14, -14, -869, -869, -869, -869, -869, -869,
+ 548, 554, 563, 576, 583, -869, -869, -869, 587, 592,
+ 597, 601, -869, 598, 673, -19, 279, 293, -869, -869,
+ 663, 698, 719, 723, 728, 594, 599, 63, 733, 691,
+ 603, 604, 300, 605, -869, -869, -869, 606, -869, 225,
+ 607, 271, -869, 608, -869, -869, -869, -869, -869, -869,
+ 609, 610, 739, 208, -25, 676, 538, 740, 741, 615,
+ 394, -869, 300, -869, 617, 680, 620, 709, 612, 621,
+ 710, 626, 627, -41, -3, 14, 17, 628, 281, 349,
+ -869, 631, 633, 634, 636, 638, 639, 640, 641, 690,
+ -14, 62, 767, -14, -869, -869, -869, 769, -14, 643,
+ 644, -869, -8, 507, -869, 773, 764, 646, 647, 648,
+ 651, 365, 652, -14, -14, -14, 675, -869, 666, -869,
+ 134, 166, 276, -14, -869, 630, 642, -869, 483, 368,
+ 368, -869, -869, 532, 532, 780, 786, 787, 788, 779,
+ 790, 791, 792, 793, 794, 795, 659, -869, -869, -869,
+ -869, -14, -14, -14, 797, 798, 318, -869, 799, -869,
+ -869, 662, 664, 667, 669, 670, 671, 806, 807, 765,
+ 340, 390, 390, 245, 677, 384, 365, 809, 811, 682,
+ 493, -869, 706, 297, 317, 319, 815, 365, 365, 365,
+ 816, 817, 226, -869, -869, -869, -869, 707, 818, 37,
+ -14, -14, -14, 824, 812, 688, 692, 823, 245, 693,
+ 694, -14, 827, -869, 828, -869, -869, 830, 831, 833,
+ 685, -869, -869, -869, -869, -869, -869, -14, 697, 842,
+ -14, 704, -14, -14, -14, 844, -14, -14, -14, -869,
+ 845, 712, 774, -14, 714, 182, 715, 716, 785, -869,
+ 1008, -869, -869, 724, -869, 365, 365, 849, 853, 766,
+ 100, -869, -869, -869, 729, 763, 796, -869, 800, -869,
+ 829, 832, 300, 768, 771, 776, 777, 770, 775, 781,
+ 783, 784, -869, -869, -869, 903, 662, 664, 662, -58,
+ -15, 772, 782, 789, 33, -869, 802, -869, 902, 907,
+ 910, 472, 281, 445, 924, -869, 801, -869, 925, -14,
+ 803, 804, 808, 813, 926, 805, 810, 819, 820, 820,
+ -869, -869, 820, 820, 821, -869, -869, -869, 826, 825,
+ 834, 835, 836, 837, 838, 839, 840, -869, 840, 841,
+ 843, 917, 918, 562, 859, -869, 919, 860, 864, 861,
+ 865, 868, 869, -869, 846, 863, 870, 872, 866, 908,
+ 909, 911, 914, 912, 913, 915, -869, 857, 931, 916,
+ 867, 934, 871, 875, 876, 944, 920, -14, 891, 921,
+ 922, -869, -869, 365, -869, -869, 927, -869, 928, 929,
+ 5, 10, -869, 964, -14, -14, -14, 968, 959, 970,
+ 961, 981, 933, -869, -869, -869, 1050, 119, -869, 1052,
+ 559, -869, -869, -869, 1054, 930, 211, 247, 932, -869,
+ 664, 662, -869, -869, -14, 923, 1056, -14, 935, 936,
+ -869, 937, 938, -869, 941, -869, -869, 1057, 1058, 1060,
+ 989, -869, -869, -869, 953, -869, -869, -869, -869, -14,
+ -14, 940, 1059, 1061, -869, 546, 365, 365, 967, -869,
+ -869, 1063, -869, -869, 840, 1070, 942, -869, 1003, 1082,
+ -14, -869, -869, -869, -869, 1011, 1084, 1014, 1015, 278,
+ -869, -869, -869, 365, -869, -869, -869, 952, -869, 984,
+ 216, 956, 954, 1091, 1093, -869, -869, 287, 365, 365,
+ 962, 365, -869, -869, 365, -869, 365, 965, 969, 971,
+ 972, 973, 974, 975, 976, 977, -14, 1035, -869, -869,
+ -869, 978, 1036, 979, 980, 1045, -869, 1001, -869, 1019,
+ -869, -869, -869, -869, 982, 598, 983, 985, 598, 1055,
+ -869, 407, -869, 1051, 990, 991, 390, 995, 1004, 1005,
+ 574, -869, 1006, 1007, 1016, 1017, 1012, 1018, 1020, 1021,
+ -869, 1022, -869, 390, 1075, -869, 1151, -869, 1144, 1155,
+ -869, -869, 1023, -869, 1024, 1025, 1026, 1158, 1164, -14,
+ 1165, -869, -869, -869, 1166, -869, -869, -869, 1167, 365,
+ -14, 1168, 1170, 1171, -869, -869, 940, 598, 1030, 1037,
+ 1172, -869, 1174, -869, -869, 1169, 1040, 1041, 598, -869,
+ 598, 598, -869, -14, -869, -869, -869, -869, 365, -869,
+ 664, 300, -869, -869, -869, 1042, 1043, 664, -869, -869,
+ -869, 372, 1180, -869, 1135, -869, 300, 1182, -869, -869,
+ -869, 940, -869, 1183, 1184, 1053, 1048, 1062, 1128, 1065,
+ 1064, 1066, 1068, 1067, 1071, 1072, -869, -869, 1081, -869,
+ 596, 635, 1145, -869, -869, -869, -869, -869, -869, 1147,
+ -869, -869, -869, -869, -869, 1073, 1076, 1074, 1179, -869,
+ 1126, -869, 1077, 1078, -14, 619, 1121, -14, -869, 1094,
+ 1079, -14, -14, -14, 1083, 1195, 1196, 1190, 365, -869,
+ 1200, -869, 1162, -14, -14, -14, 1079, -869, -869, -869,
+ -869, 1085, 954, 1086, 1087, 1102, -869, 1088, 1089, 1090,
+ -869, 1080, 843, -869, 843, 1092, 1218, -869, 1095, 1097,
+ -869, -869, -869, -869, -869, 1096, 1098, 1099, 1100, 350,
+ -869, -869, -869, -869, 1101, 1215, 1220, -869, 595, -869,
+ 84, -869, 591, -869, -869, -869, 312, 375, 1208, 1105,
+ 1106, 378, 402, 403, 418, 426, 460, 476, 481, 616,
+ -869, 119, -869, 1107, -14, -14, 1119, -869, 1123, -869,
+ 1120, -869, 1130, -869, 1131, -869, 1133, -869, 1134, -869,
+ 1136, -869, 1110, 1112, 1188, 1113, 1114, 1115, 1116, 1117,
+ 1118, 1122, 1124, 1125, 1127, -869, -869, 1245, 1079, 1079,
+ -869, -869, -869, -869, -869, -869, -869, -869, -869, -869,
+ -869
+};
+
+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+ Performed when YYTABLE does not specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint16 yydefact[] =
+{
+ 0, 7, 0, 0, 204, 0, 0, 227, 228, 0,
+ 0, 0, 0, 0, 136, 138, 137, 139, 140, 141,
+ 221, 142, 0, 0, 143, 144, 145, 0, 0, 0,
+ 0, 0, 0, 11, 0, 0, 0, 0, 215, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 220, 216, 0, 0,
+ 0, 0, 0, 0, 8, 0, 3, 0, 0, 0,
+ 0, 0, 0, 229, 314, 79, 0, 0, 0, 0,
+ 330, 338, 339, 354, 203, 343, 0, 0, 0, 0,
+ 0, 0, 0, 322, 323, 325, 324, 0, 0, 0,
+ 0, 0, 0, 0, 147, 146, 152, 153, 0, 0,
+ 338, 212, 338, 214, 0, 155, 156, 339, 158, 157,
+ 0, 160, 159, 0, 0, 0, 174, 0, 172, 0,
+ 176, 0, 178, 226, 225, 0, 0, 0, 322, 0,
+ 0, 0, 0, 0, 0, 0, 218, 217, 0, 0,
+ 0, 0, 0, 307, 0, 0, 1, 0, 4, 310,
+ 311, 312, 0, 45, 0, 0, 0, 0, 0, 0,
+ 0, 44, 0, 318, 48, 281, 320, 319, 0, 9,
+ 0, 341, 342, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 167, 170, 168, 169, 165, 166,
+ 0, 0, 0, 0, 0, 278, 279, 280, 0, 0,
+ 0, 80, 82, 252, 0, 252, 0, 0, 287, 288,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 313,
+ 0, 0, 229, 255, 62, 58, 56, 60, 61, 81,
+ 0, 0, 83, 0, 327, 326, 26, 14, 27, 15,
+ 0, 0, 0, 0, 50, 0, 0, 0, 0, 0,
+ 0, 317, 229, 47, 0, 208, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 307, 307,
+ 329, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 294, 293, 309, 308, 0, 0,
+ 0, 328, 0, 281, 202, 0, 0, 37, 25, 0,
+ 0, 0, 0, 0, 0, 0, 0, 39, 0, 55,
+ 0, 0, 0, 0, 340, 351, 353, 346, 352, 348,
+ 347, 344, 345, 349, 350, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 293, 289, 290, 291,
+ 292, 0, 0, 0, 0, 0, 0, 52, 0, 46,
+ 164, 258, 264, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 307, 0, 0, 0, 85,
+ 0, 49, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 109, 119, 120, 118, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 84, 0, 0, 148, 0, 337, 149, 0, 0, 0,
+ 0, 173, 171, 175, 177, 154, 308, 0, 0, 308,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 219,
+ 0, 134, 0, 0, 0, 0, 0, 0, 0, 285,
+ 0, 6, 59, 0, 321, 0, 0, 0, 0, 0,
+ 0, 90, 104, 99, 0, 0, 0, 233, 0, 232,
+ 0, 0, 229, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 78, 66, 67, 0, 258, 264, 258, 242,
+ 244, 0, 0, 0, 0, 163, 0, 24, 0, 0,
+ 0, 0, 307, 307, 0, 312, 0, 315, 308, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 283, 283,
+ 73, 74, 283, 283, 0, 75, 69, 70, 0, 0,
+ 0, 0, 0, 0, 0, 0, 266, 106, 266, 0,
+ 244, 0, 0, 307, 0, 316, 0, 0, 209, 0,
+ 0, 0, 0, 286, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 131, 0, 0, 132,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 100, 88, 0, 114, 116, 40, 282, 0, 0,
+ 0, 0, 10, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 91, 105, 108, 0, 236, 51, 0,
+ 0, 35, 254, 253, 0, 0, 0, 0, 0, 103,
+ 264, 258, 115, 117, 0, 0, 308, 0, 0, 0,
+ 12, 0, 339, 335, 0, 336, 197, 0, 0, 0,
+ 0, 256, 257, 57, 0, 76, 77, 71, 72, 0,
+ 0, 0, 0, 0, 41, 0, 0, 0, 0, 92,
+ 107, 0, 38, 101, 266, 308, 0, 13, 0, 0,
+ 0, 151, 150, 162, 161, 0, 0, 0, 0, 0,
+ 127, 125, 126, 0, 224, 223, 222, 0, 130, 0,
+ 0, 0, 0, 0, 0, 190, 5, 0, 0, 0,
+ 0, 0, 230, 231, 0, 313, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 237, 238,
+ 239, 0, 0, 0, 0, 0, 259, 0, 260, 0,
+ 261, 265, 102, 93, 0, 252, 0, 0, 252, 0,
+ 195, 0, 196, 0, 0, 0, 0, 0, 0, 0,
+ 0, 121, 0, 0, 0, 0, 0, 0, 0, 0,
+ 89, 0, 186, 0, 205, 210, 0, 179, 0, 0,
+ 182, 183, 0, 135, 0, 0, 0, 0, 0, 0,
+ 0, 201, 191, 184, 0, 199, 54, 53, 0, 0,
+ 0, 0, 0, 0, 33, 110, 0, 252, 96, 0,
+ 0, 243, 0, 245, 246, 0, 0, 0, 252, 194,
+ 252, 252, 187, 0, 331, 332, 333, 334, 0, 28,
+ 264, 229, 284, 129, 128, 0, 0, 264, 95, 42,
+ 43, 0, 0, 267, 0, 189, 229, 0, 180, 192,
+ 181, 0, 133, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 122, 98, 0, 68,
+ 0, 0, 0, 263, 262, 193, 188, 185, 65, 0,
+ 36, 87, 234, 235, 94, 0, 0, 0, 0, 86,
+ 206, 123, 0, 0, 0, 0, 0, 0, 124, 0,
+ 272, 0, 0, 0, 0, 0, 0, 0, 0, 112,
+ 0, 111, 0, 0, 0, 0, 272, 268, 271, 270,
+ 269, 0, 0, 0, 0, 0, 63, 0, 0, 0,
+ 97, 247, 244, 20, 244, 0, 0, 207, 0, 0,
+ 18, 19, 200, 198, 64, 0, 30, 0, 0, 236,
+ 23, 22, 21, 113, 0, 0, 0, 273, 0, 29,
+ 0, 31, 0, 32, 240, 241, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 249, 236, 248, 0, 0, 0, 0, 275, 0, 274,
+ 0, 296, 0, 298, 0, 297, 0, 295, 0, 303,
+ 0, 304, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 251, 250, 0, 272, 272,
+ 276, 277, 300, 302, 301, 299, 305, 306, 34, 16,
+ 17
+};
+
+ /* YYPGOTO[NTERM-NUM]. */
+static const yytype_int16 yypgoto[] =
+{
+ -869, -869, -869, -133, 41, -216, -733, -868, 313, -869,
+ -509, -869, -198, -869, -458, -460, -515, -869, -804, -869,
+ -869, 986, 23, -869, -31, -869, 421, -205, -869, -869,
+ -253, 2, 22, -171, 987, -206, -56, 46, -869, -17,
+ -869, -869, -869, 1247, -869, -27, 0
+};
+
+ /* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int16 yydefgoto[] =
+{
+ -1, 65, 66, 67, 370, 179, 751, 721, 957, 608,
+ 611, 940, 357, 381, 495, 497, 659, 911, 916, 949,
+ 230, 319, 645, 69, 126, 231, 354, 298, 951, 953,
+ 299, 371, 372, 72, 73, 74, 177, 98, 75, 82,
+ 817, 633, 634, 118, 83, 84, 85
+};
+
+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule whose
+ number is the opposite. If YYTABLE_NINF, syntax error. */
+static const yytype_int16 yytable[] =
+{
+ 106, 107, 70, 109, 111, 113, 355, 115, 116, 119,
+ 122, 128, 130, 132, 173, 176, 379, 359, 134, 117,
+ 117, 374, 71, 660, 302, 428, 431, 604, 603, 304,
+ 605, 662, 239, 232, 7, 8, 7, 8, 157, 7,
+ 8, 68, 420, 174, 294, 295, 410, 262, 77, 398,
+ 153, 404, 306, 242, 409, 78, 373, 266, 267, 195,
+ 197, 199, 233, 856, 236, 238, 76, -211, -213, 450,
+ 150, 956, 172, 427, 430, 99, 263, 181, 182, 183,
+ 420, 264, 289, 104, 313, 314, 315, 442, 369, 408,
+ 100, 159, 7, 8, 77, 139, 244, 420, 147, 606,
+ 420, 78, 930, 993, 607, 534, 151, 154, 881, 155,
+ 159, 171, 175, 290, 183, 160, 161, 101, 443, 245,
+ 183, 158, 510, 421, 535, 77, 250, 269, 270, 251,
+ 229, 252, 78, 253, 241, 584, 254, 397, 255, 133,
+ 7, 8, 609, 356, 261, 317, 256, 610, 79, 760,
+ -211, -213, 451, 80, 81, 240, 316, 615, 616, 70,
+ 732, 422, 77, 733, 77, 182, 305, 704, 102, 78,
+ 509, 78, 706, 77, 243, 617, 77, 194, 423, 71,
+ 78, 424, 103, 78, 325, 326, 327, 328, 329, 330,
+ 331, 332, 333, 334, 79, 196, 257, 258, 68, 80,
+ 81, 105, 303, 198, 1019, 1020, 307, 308, 309, 310,
+ 108, 312, 963, 964, 77, 123, 181, 182, 124, 775,
+ 776, 78, 965, 966, 777, 79, 135, 183, 235, 77,
+ 80, 81, 77, 394, 259, 778, 78, 7, 8, 78,
+ 77, 294, 295, 395, 718, 719, 720, 78, 163, 625,
+ 628, 530, 7, 8, 296, 297, 592, 125, 164, 127,
+ 183, 531, 79, 441, 79, 77, 445, 80, 81, 80,
+ 81, 447, 78, 260, 7, 8, 79, 140, 80, 81,
+ 164, 80, 81, 129, 237, 77, 461, 462, 463, 131,
+ 666, 466, 165, 77, 396, 467, 473, 624, 627, 166,
+ 78, 470, 136, 770, 360, 7, 8, 137, 167, 168,
+ 169, 471, 170, 771, 79, 173, 176, 576, 361, 80,
+ 81, 77, 518, 468, 486, 487, 488, 469, 78, 79,
+ 383, 384, 79, 141, 80, 110, 385, 80, 81, 571,
+ 79, 77, 520, 572, 522, 80, 81, 142, 78, 146,
+ 294, 295, 459, 7, 8, 77, 519, 521, 523, 77,
+ 870, 143, 78, 296, 426, 79, 78, 874, 727, 144,
+ 80, 81, 728, 536, 537, 538, 387, 388, 292, 77,
+ 293, 77, 389, 152, 547, 79, 78, 156, 78, 77,
+ 80, 81, 145, 79, 7, 8, 78, 875, 80, 112,
+ 554, 7, 8, 557, 729, 559, 560, 561, 730, 563,
+ 564, 565, 148, 941, 506, 942, 569, 511, 294, 295,
+ 149, 79, 162, 7, 8, 164, 80, 81, 525, 526,
+ 527, 296, 429, 585, 186, 320, 321, 159, 77, 190,
+ 191, 79, 160, 505, 784, 78, 80, 81, 785, 544,
+ 491, 492, 70, 294, 295, 79, 77, 579, 580, 79,
+ 80, 81, 178, 78, 80, 81, 296, 508, 180, 969,
+ 954, 955, 71, 970, 623, 718, 719, 720, 234, 79,
+ 268, 79, 635, 246, 80, 81, 80, 81, 265, 114,
+ 247, 68, 632, 248, 80, 81, 578, 578, 374, 249,
+ 409, 200, 201, 202, 271, 203, 204, 622, 205, 206,
+ 207, 208, 209, 210, 294, 295, 138, 272, 94, 95,
+ 96, 211, 273, 212, 213, 7, 8, 296, 626, 214,
+ 274, 215, 971, 275, 77, 976, 972, 809, 120, 977,
+ 812, 78, 646, 80, 81, 647, 648, 184, 276, 186,
+ 697, 277, 188, 189, 190, 191, 79, 280, 216, 978,
+ 980, 80, 81, 979, 981, 217, 278, 708, 709, 710,
+ 218, 219, 220, 192, 193, 982, 814, 815, 816, 983,
+ 221, 222, 223, 984, 287, 224, 279, 985, 184, 185,
+ 186, 187, 281, 188, 189, 190, 191, 734, 186, 857,
+ 737, 188, 189, 190, 191, 871, 282, 294, 295, 306,
+ 865, 283, 866, 867, 192, 193, 291, 986, 225, 226,
+ 879, 987, 748, 749, 700, 515, 516, 284, 400, 401,
+ 402, 705, 261, 988, 79, 403, 285, 989, 990, 80,
+ 81, 301, 991, 765, 296, 665, 184, 185, 186, 187,
+ 286, 188, 189, 190, 191, 306, 896, 288, 227, 228,
+ 311, 781, 300, 80, 81, 343, 344, 322, 345, 318,
+ 294, 346, 192, 193, 347, 348, 349, 350, 323, 347,
+ 348, 349, 350, 723, 724, 324, 754, 755, 362, 799,
+ 821, 351, 352, 353, 825, 826, 186, 756, 757, 188,
+ 189, 190, 191, 789, 294, 295, 184, 836, 186, 187,
+ 335, 188, 189, 190, 191, 93, 336, 94, 95, 96,
+ 192, 193, 97, 363, 772, 337, 907, 908, 909, 910,
+ 961, 962, 192, 193, 967, 968, 954, 955, 338, 786,
+ 787, 86, 578, 358, 364, 339, 87, 88, 365, 340,
+ 89, 90, 847, 366, 341, 91, 92, 367, 375, 342,
+ 356, 376, 368, 852, 393, 377, 378, 380, 382, 386,
+ 390, 391, 392, 399, 411, 405, 406, 412, 407, 414,
+ 417, 413, 416, 418, 419, 415, 868, 440, 432, 425,
+ 433, 434, 444, 435, 446, 436, 437, 438, 453, 454,
+ 464, 465, 439, 455, 456, 474, 457, 448, 449, 458,
+ 460, 475, 476, 477, 478, 479, 480, 481, 482, 483,
+ 484, 485, 489, 490, 494, 498, 496, 499, 500, 501,
+ 851, 502, 503, 493, 512, 504, 513, 517, 507, 514,
+ 524, 528, 529, 533, 532, 539, 541, 540, 543, 553,
+ 542, 546, 548, 549, 545, 550, 551, 906, 552, 869,
+ 913, 555, -2, 1, 917, 918, 919, 556, 558, 562,
+ 566, 568, 876, 2, 567, 570, 927, 928, 929, 573,
+ 574, 932, 575, 577, 581, 3, 4, 5, 582, 6,
+ 586, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
+ 36, 37, 38, 583, 587, 593, 590, 597, 602, 591,
+ 594, 588, 598, 612, 589, 595, 596, 619, 599, 924,
+ 600, 601, 620, 613, 618, 621, 614, 995, 996, 629,
+ 631, 640, 663, 664, 668, 670, 688, 39, 40, 691,
+ 676, 637, 630, 679, 690, 638, 641, 636, 692, 695,
+ 639, 642, 693, 694, 41, 42, 43, 44, 649, 45,
+ 643, 46, 644, 650, 47, 48, 651, 687, 159, 707,
+ 698, 652, 653, 711, 712, 713, 714, 654, 699, 655,
+ 656, 657, 658, 661, 49, 610, 715, 50, 51, 52,
+ 675, 53, 54, 55, 56, 57, 58, 59, 60, 2,
+ 667, 669, 671, 716, 61, 62, 672, 63, 64, 673,
+ 674, 3, 4, 5, 677, 6, 678, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 680,
+ 681, 683, 682, 684, 685, 717, 686, 722, 689, 725,
+ 696, 736, 743, 744, 701, 745, 746, 735, 747, 702,
+ 703, 726, 758, 731, 752, 761, 753, 739, 759, 738,
+ 763, 740, 750, 39, 40, 742, 762, 764, 766, 767,
+ 741, 768, 769, 773, 774, 779, 782, 780, 783, 788,
+ 41, 42, 43, 44, 790, 45, 791, 46, 792, 793,
+ 47, 48, 800, 802, 794, 795, 796, 797, 798, 801,
+ 803, 804, 805, 806, 807, 813, 808, 810, 818, 811,
+ 49, 819, 820, 50, 51, 52, 822, 53, 54, 55,
+ 56, 57, 58, 59, 60, 823, 824, 827, 828, 831,
+ 61, 62, 837, 63, 64, 832, 838, 829, 830, 839,
+ 840, 833, 834, 845, 841, 842, 835, 843, 844, 846,
+ 848, 849, 858, 853, 850, 854, 855, 860, 859, 861,
+ 862, 863, 864, 872, 873, 877, 878, 880, 882, 883,
+ 885, 420, 884, 894, 902, 897, 898, 903, 912, 914,
+ 921, 922, 923, 886, 887, 888, 891, 925, 889, 890,
+ 892, 893, 926, 900, 899, 901, 904, 905, 935, 944,
+ 959, 915, 939, 973, 920, 960, 931, 933, 934, 936,
+ 937, 938, 945, 943, 946, 997, 999, 947, 998, 1007,
+ 948, 950, 952, 958, 974, 975, 1000, 1001, 994, 1002,
+ 1003, 1005, 1004, 1006, 1008, 1009, 1010, 1011, 1012, 1013,
+ 1018, 895, 992, 1014, 121, 1015, 1016, 0, 1017, 452,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 472
+};
+
+static const yytype_int16 yycheck[] =
+{
+ 27, 28, 0, 30, 31, 32, 211, 34, 35, 36,
+ 37, 42, 43, 44, 70, 71, 232, 215, 45, 36,
+ 37, 227, 0, 538, 157, 278, 279, 487, 486, 25,
+ 488, 540, 25, 89, 29, 30, 29, 30, 77, 29,
+ 30, 0, 83, 70, 69, 70, 262, 103, 62, 254,
+ 25, 256, 71, 27, 260, 69, 227, 25, 26, 86,
+ 87, 88, 89, 796, 91, 92, 162, 77, 77, 77,
+ 27, 939, 70, 278, 279, 97, 103, 77, 78, 79,
+ 83, 108, 25, 25, 90, 91, 92, 25, 25, 260,
+ 97, 97, 29, 30, 62, 49, 142, 83, 57, 157,
+ 83, 69, 906, 971, 162, 68, 63, 82, 841, 63,
+ 97, 70, 71, 56, 114, 102, 103, 97, 56, 165,
+ 120, 160, 375, 164, 87, 62, 15, 25, 26, 18,
+ 89, 20, 69, 22, 93, 35, 25, 162, 27, 25,
+ 29, 30, 157, 162, 103, 172, 35, 162, 162, 664,
+ 160, 160, 160, 167, 168, 148, 162, 124, 125, 157,
+ 620, 164, 62, 621, 62, 165, 162, 162, 97, 69,
+ 375, 69, 162, 62, 148, 142, 62, 25, 164, 157,
+ 69, 164, 97, 69, 184, 185, 186, 187, 188, 189,
+ 190, 191, 192, 193, 162, 25, 85, 86, 157, 167,
+ 168, 25, 161, 25, 1008, 1009, 165, 166, 167, 168,
+ 162, 170, 128, 129, 62, 162, 216, 217, 162, 3,
+ 4, 69, 138, 139, 8, 162, 162, 227, 25, 62,
+ 167, 168, 62, 25, 123, 19, 69, 29, 30, 69,
+ 62, 69, 70, 35, 125, 126, 127, 69, 25, 502,
+ 503, 25, 29, 30, 82, 83, 472, 163, 35, 163,
+ 260, 35, 162, 290, 162, 62, 293, 167, 168, 167,
+ 168, 298, 69, 162, 29, 30, 162, 162, 167, 168,
+ 35, 167, 168, 163, 25, 62, 313, 314, 315, 163,
+ 543, 157, 69, 62, 253, 161, 323, 502, 503, 76,
+ 69, 25, 163, 25, 25, 29, 30, 163, 85, 86,
+ 87, 35, 89, 35, 162, 371, 372, 450, 25, 167,
+ 168, 62, 25, 157, 351, 352, 353, 161, 69, 162,
+ 105, 106, 162, 162, 167, 168, 111, 167, 168, 157,
+ 162, 62, 25, 161, 25, 167, 168, 162, 69, 25,
+ 69, 70, 311, 29, 30, 62, 383, 384, 385, 62,
+ 820, 162, 69, 82, 83, 162, 69, 827, 157, 162,
+ 167, 168, 161, 400, 401, 402, 105, 106, 157, 62,
+ 159, 62, 111, 25, 411, 162, 69, 0, 69, 62,
+ 167, 168, 162, 162, 29, 30, 69, 25, 167, 168,
+ 427, 29, 30, 430, 157, 432, 433, 434, 161, 436,
+ 437, 438, 162, 922, 373, 924, 443, 376, 69, 70,
+ 162, 162, 97, 29, 30, 35, 167, 168, 387, 388,
+ 389, 82, 83, 460, 66, 134, 135, 97, 62, 71,
+ 72, 162, 102, 103, 157, 69, 167, 168, 161, 408,
+ 132, 133, 450, 69, 70, 162, 62, 455, 456, 162,
+ 167, 168, 162, 69, 167, 168, 82, 83, 25, 157,
+ 120, 121, 450, 161, 501, 125, 126, 127, 25, 162,
+ 172, 162, 509, 35, 167, 168, 167, 168, 25, 162,
+ 35, 450, 509, 35, 167, 168, 455, 456, 704, 35,
+ 706, 5, 6, 7, 25, 9, 10, 35, 12, 13,
+ 14, 15, 16, 17, 69, 70, 97, 25, 99, 100,
+ 101, 25, 25, 27, 28, 29, 30, 82, 83, 33,
+ 25, 35, 157, 25, 62, 157, 161, 735, 162, 161,
+ 738, 69, 519, 167, 168, 522, 523, 64, 25, 66,
+ 577, 25, 69, 70, 71, 72, 162, 27, 62, 157,
+ 157, 167, 168, 161, 161, 69, 25, 594, 595, 596,
+ 74, 75, 76, 90, 91, 157, 169, 170, 171, 161,
+ 84, 85, 86, 157, 35, 89, 25, 161, 64, 65,
+ 66, 67, 25, 69, 70, 71, 72, 624, 66, 797,
+ 627, 69, 70, 71, 72, 821, 25, 69, 70, 71,
+ 808, 25, 810, 811, 90, 91, 27, 157, 122, 123,
+ 836, 161, 649, 650, 583, 132, 133, 25, 90, 91,
+ 92, 590, 591, 157, 162, 97, 25, 161, 157, 167,
+ 168, 27, 161, 670, 82, 83, 64, 65, 66, 67,
+ 25, 69, 70, 71, 72, 71, 861, 25, 162, 163,
+ 162, 692, 25, 167, 168, 64, 65, 157, 67, 162,
+ 69, 70, 90, 91, 78, 79, 80, 81, 159, 78,
+ 79, 80, 81, 124, 125, 161, 140, 141, 25, 716,
+ 746, 90, 91, 92, 120, 121, 66, 656, 657, 69,
+ 70, 71, 72, 701, 69, 70, 64, 763, 66, 67,
+ 162, 69, 70, 71, 72, 97, 162, 99, 100, 101,
+ 90, 91, 104, 25, 683, 162, 107, 108, 109, 110,
+ 135, 136, 90, 91, 143, 144, 120, 121, 162, 698,
+ 699, 88, 701, 70, 25, 162, 93, 94, 25, 162,
+ 97, 98, 779, 25, 162, 102, 103, 163, 25, 162,
+ 162, 70, 163, 790, 25, 162, 162, 162, 162, 162,
+ 162, 162, 162, 97, 157, 35, 35, 97, 163, 70,
+ 70, 161, 161, 157, 157, 173, 813, 97, 157, 161,
+ 157, 157, 25, 157, 25, 157, 157, 157, 25, 35,
+ 125, 135, 161, 157, 157, 25, 158, 164, 164, 158,
+ 158, 25, 25, 25, 35, 25, 25, 25, 25, 25,
+ 25, 162, 25, 25, 162, 158, 162, 158, 158, 158,
+ 789, 25, 25, 34, 25, 70, 25, 131, 161, 157,
+ 25, 25, 25, 25, 137, 21, 158, 35, 25, 164,
+ 158, 157, 25, 25, 161, 25, 25, 884, 25, 818,
+ 887, 164, 0, 1, 891, 892, 893, 25, 164, 25,
+ 25, 97, 831, 11, 162, 161, 903, 904, 905, 164,
+ 164, 912, 97, 159, 35, 23, 24, 25, 35, 27,
+ 161, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 157, 161, 157, 97, 157, 25, 97,
+ 159, 135, 157, 161, 134, 159, 159, 35, 157, 898,
+ 157, 157, 35, 161, 142, 35, 157, 974, 975, 25,
+ 25, 25, 35, 35, 35, 91, 25, 95, 96, 25,
+ 97, 157, 161, 97, 97, 157, 161, 164, 97, 25,
+ 157, 161, 97, 97, 112, 113, 114, 115, 157, 117,
+ 161, 119, 162, 157, 122, 123, 161, 130, 97, 25,
+ 69, 157, 157, 25, 35, 25, 35, 161, 76, 162,
+ 162, 162, 162, 162, 142, 162, 25, 145, 146, 147,
+ 164, 149, 150, 151, 152, 153, 154, 155, 156, 11,
+ 161, 161, 161, 90, 162, 163, 161, 165, 166, 161,
+ 161, 23, 24, 25, 164, 27, 164, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 161,
+ 161, 157, 161, 161, 161, 25, 161, 25, 162, 25,
+ 160, 25, 25, 25, 157, 25, 97, 164, 135, 161,
+ 161, 161, 125, 161, 35, 25, 35, 161, 35, 164,
+ 97, 164, 162, 95, 96, 164, 164, 25, 97, 25,
+ 172, 97, 97, 161, 130, 159, 25, 163, 25, 157,
+ 112, 113, 114, 115, 159, 117, 157, 119, 157, 157,
+ 122, 123, 97, 97, 161, 161, 161, 161, 161, 161,
+ 161, 161, 97, 142, 125, 90, 164, 164, 97, 164,
+ 142, 161, 161, 145, 146, 147, 161, 149, 150, 151,
+ 152, 153, 154, 155, 156, 161, 161, 161, 161, 157,
+ 162, 163, 97, 165, 166, 157, 25, 161, 161, 35,
+ 25, 161, 161, 25, 161, 161, 164, 162, 162, 25,
+ 25, 25, 162, 25, 27, 25, 25, 25, 161, 25,
+ 31, 161, 161, 161, 161, 25, 71, 25, 25, 25,
+ 162, 83, 159, 132, 35, 70, 69, 91, 97, 125,
+ 25, 25, 32, 161, 159, 161, 159, 27, 162, 161,
+ 159, 159, 70, 157, 161, 161, 159, 159, 136, 21,
+ 25, 162, 162, 35, 161, 25, 161, 161, 161, 161,
+ 161, 161, 157, 161, 157, 136, 136, 161, 135, 71,
+ 162, 162, 162, 162, 159, 159, 136, 136, 161, 136,
+ 136, 161, 136, 161, 161, 161, 161, 161, 161, 161,
+ 35, 860, 969, 161, 37, 161, 161, -1, 161, 303,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, 322
+};
+
+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 1, 11, 23, 24, 25, 27, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 95,
+ 96, 112, 113, 114, 115, 117, 119, 122, 123, 142,
+ 145, 146, 147, 149, 150, 151, 152, 153, 154, 155,
+ 156, 162, 163, 165, 166, 175, 176, 177, 178, 197,
+ 205, 206, 207, 208, 209, 212, 162, 62, 69, 162,
+ 167, 168, 213, 218, 219, 220, 88, 93, 94, 97,
+ 98, 102, 103, 97, 99, 100, 101, 104, 211, 97,
+ 97, 97, 97, 97, 25, 25, 219, 219, 162, 219,
+ 168, 219, 168, 219, 162, 219, 219, 213, 217, 219,
+ 162, 217, 219, 162, 162, 163, 198, 163, 198, 163,
+ 198, 163, 198, 25, 219, 162, 163, 163, 97, 211,
+ 162, 162, 162, 162, 162, 162, 25, 178, 162, 162,
+ 27, 63, 25, 25, 82, 211, 0, 77, 160, 97,
+ 102, 103, 97, 25, 35, 69, 76, 85, 86, 87,
+ 89, 178, 205, 210, 219, 178, 210, 210, 162, 179,
+ 25, 220, 220, 220, 64, 65, 66, 67, 69, 70,
+ 71, 72, 90, 91, 25, 219, 25, 219, 25, 219,
+ 5, 6, 7, 9, 10, 12, 13, 14, 15, 16,
+ 17, 25, 27, 28, 33, 35, 62, 69, 74, 75,
+ 76, 84, 85, 86, 89, 122, 123, 162, 163, 178,
+ 194, 199, 210, 219, 25, 25, 219, 25, 219, 25,
+ 148, 178, 27, 148, 142, 165, 35, 35, 35, 35,
+ 15, 18, 20, 22, 25, 27, 35, 85, 86, 123,
+ 162, 178, 210, 219, 219, 25, 25, 26, 172, 25,
+ 26, 25, 25, 25, 25, 25, 25, 25, 25, 25,
+ 27, 25, 25, 25, 25, 25, 25, 35, 25, 25,
+ 56, 27, 157, 159, 69, 70, 82, 83, 201, 204,
+ 25, 27, 177, 178, 25, 162, 71, 178, 178, 178,
+ 178, 162, 178, 90, 91, 92, 162, 219, 162, 195,
+ 134, 135, 157, 159, 161, 220, 220, 220, 220, 220,
+ 220, 220, 220, 220, 220, 162, 162, 162, 162, 162,
+ 162, 162, 162, 64, 65, 67, 70, 78, 79, 80,
+ 81, 90, 91, 92, 200, 201, 162, 186, 70, 186,
+ 25, 25, 25, 25, 25, 25, 25, 163, 163, 25,
+ 178, 205, 206, 207, 209, 25, 70, 162, 162, 179,
+ 162, 187, 162, 105, 106, 111, 162, 105, 106, 111,
+ 162, 162, 162, 25, 25, 35, 178, 162, 201, 97,
+ 90, 91, 92, 97, 201, 35, 35, 163, 207, 209,
+ 179, 157, 97, 161, 70, 173, 161, 70, 157, 157,
+ 83, 164, 164, 164, 164, 161, 83, 201, 204, 83,
+ 201, 204, 157, 157, 157, 157, 157, 157, 157, 161,
+ 97, 219, 25, 56, 25, 219, 25, 219, 164, 164,
+ 77, 160, 195, 25, 35, 157, 157, 158, 158, 178,
+ 158, 219, 219, 219, 125, 135, 157, 161, 157, 161,
+ 25, 35, 208, 219, 25, 25, 25, 25, 35, 25,
+ 25, 25, 25, 25, 25, 162, 219, 219, 219, 25,
+ 25, 132, 133, 34, 162, 188, 162, 189, 158, 158,
+ 158, 158, 25, 25, 70, 103, 178, 161, 83, 201,
+ 204, 178, 25, 25, 157, 132, 133, 131, 25, 219,
+ 25, 219, 25, 219, 25, 178, 178, 178, 25, 25,
+ 25, 35, 137, 25, 68, 87, 219, 219, 219, 21,
+ 35, 158, 158, 25, 178, 161, 157, 219, 25, 25,
+ 25, 25, 25, 164, 219, 164, 25, 219, 164, 219,
+ 219, 219, 25, 219, 219, 219, 25, 162, 97, 219,
+ 161, 157, 161, 164, 164, 97, 177, 159, 178, 205,
+ 205, 35, 35, 157, 35, 219, 161, 161, 135, 134,
+ 97, 97, 179, 157, 159, 159, 159, 157, 157, 157,
+ 157, 157, 25, 188, 189, 188, 157, 162, 183, 157,
+ 162, 184, 161, 161, 157, 124, 125, 142, 142, 35,
+ 35, 35, 35, 219, 201, 204, 83, 201, 204, 25,
+ 161, 25, 213, 215, 216, 219, 164, 157, 157, 157,
+ 25, 161, 161, 161, 162, 196, 196, 196, 196, 157,
+ 157, 161, 157, 157, 161, 162, 162, 162, 162, 190,
+ 190, 162, 184, 35, 35, 83, 204, 161, 35, 161,
+ 91, 161, 161, 161, 161, 164, 97, 164, 164, 97,
+ 161, 161, 161, 157, 161, 161, 161, 130, 25, 162,
+ 97, 25, 97, 97, 97, 25, 160, 219, 69, 76,
+ 178, 157, 161, 161, 162, 178, 162, 25, 219, 219,
+ 219, 25, 35, 25, 35, 25, 90, 25, 125, 126,
+ 127, 181, 25, 124, 125, 25, 161, 157, 161, 157,
+ 161, 161, 189, 188, 219, 164, 25, 219, 164, 161,
+ 164, 172, 164, 25, 25, 25, 97, 135, 219, 219,
+ 162, 180, 35, 35, 140, 141, 178, 178, 125, 35,
+ 190, 25, 164, 97, 25, 219, 97, 25, 97, 97,
+ 25, 35, 178, 161, 130, 3, 4, 8, 19, 159,
+ 163, 198, 25, 25, 157, 161, 178, 178, 157, 205,
+ 159, 157, 157, 157, 161, 161, 161, 161, 161, 219,
+ 97, 161, 97, 161, 161, 97, 142, 125, 164, 186,
+ 164, 164, 186, 90, 169, 170, 171, 214, 97, 161,
+ 161, 210, 161, 161, 161, 120, 121, 161, 161, 161,
+ 161, 157, 157, 161, 161, 164, 210, 97, 25, 35,
+ 25, 161, 161, 162, 162, 25, 25, 219, 25, 25,
+ 27, 178, 219, 25, 25, 25, 180, 186, 162, 161,
+ 25, 25, 31, 161, 161, 186, 186, 186, 219, 178,
+ 189, 179, 161, 161, 189, 25, 178, 25, 71, 179,
+ 25, 180, 25, 25, 159, 162, 161, 159, 161, 162,
+ 161, 159, 159, 159, 132, 200, 201, 70, 69, 161,
+ 157, 161, 35, 91, 159, 159, 219, 107, 108, 109,
+ 110, 191, 97, 219, 125, 162, 192, 219, 219, 219,
+ 161, 25, 25, 32, 178, 27, 70, 219, 219, 219,
+ 192, 161, 198, 161, 161, 136, 161, 161, 161, 162,
+ 185, 184, 184, 161, 21, 157, 157, 161, 162, 193,
+ 162, 202, 162, 203, 120, 121, 181, 182, 162, 25,
+ 25, 135, 136, 128, 129, 138, 139, 143, 144, 157,
+ 161, 157, 161, 35, 159, 159, 157, 161, 157, 161,
+ 157, 161, 157, 161, 157, 161, 157, 161, 157, 161,
+ 157, 161, 182, 181, 161, 219, 219, 136, 135, 136,
+ 136, 136, 136, 136, 136, 161, 161, 71, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 35, 192,
+ 192
+};
+
+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 174, 175, 175, 176, 176, 176, 176, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 177, 177, 177,
+ 177, 177, 177, 177, 177, 177, 177, 178, 178, 179,
+ 179, 179, 179, 179, 180, 180, 181, 181, 181, 181,
+ 182, 182, 183, 183, 184, 184, 184, 185, 185, 185,
+ 185, 185, 186, 186, 186, 187, 187, 187, 188, 188,
+ 188, 188, 188, 188, 189, 189, 190, 190, 191, 191,
+ 191, 191, 192, 192, 193, 193, 193, 193, 194, 194,
+ 194, 195, 195, 196, 196, 197, 198, 199, 199, 200,
+ 200, 200, 200, 201, 201, 202, 202, 202, 202, 202,
+ 202, 202, 202, 203, 203, 203, 203, 204, 204, 204,
+ 205, 206, 207, 208, 208, 208, 208, 208, 209, 209,
+ 209, 210, 211, 211, 211, 211, 212, 212, 212, 212,
+ 213, 214, 214, 214, 215, 216, 216, 217, 218, 218,
+ 218, 218, 218, 219, 220, 220, 220, 220, 220, 220,
+ 220, 220, 220, 220, 220
+};
+
+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 0, 1, 2, 6, 4, 1, 1, 2,
+ 5, 1, 6, 6, 3, 3, 17, 17, 11, 11,
+ 11, 12, 12, 12, 5, 3, 3, 3, 8, 13,
+ 12, 13, 13, 8, 17, 6, 9, 3, 6, 3,
+ 5, 6, 8, 8, 2, 2, 4, 3, 2, 4,
+ 3, 6, 4, 7, 7, 3, 3, 6, 3, 4,
+ 3, 3, 3, 11, 11, 9, 5, 5, 9, 5,
+ 5, 6, 6, 5, 5, 5, 6, 6, 5, 1,
+ 3, 3, 3, 3, 4, 4, 9, 9, 5, 7,
+ 4, 6, 6, 7, 9, 8, 8, 11, 9, 4,
+ 5, 6, 7, 6, 4, 6, 5, 6, 6, 4,
+ 8, 10, 10, 12, 5, 6, 5, 6, 4, 4,
+ 4, 7, 9, 9, 9, 6, 6, 6, 8, 8,
+ 6, 5, 5, 8, 4, 7, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 2, 2, 4, 4,
+ 6, 6, 2, 2, 4, 2, 2, 2, 2, 2,
+ 2, 6, 6, 5, 4, 3, 3, 3, 3, 3,
+ 3, 4, 2, 4, 2, 4, 2, 4, 2, 7,
+ 8, 8, 7, 7, 7, 9, 7, 8, 9, 8,
+ 6, 7, 8, 9, 8, 7, 7, 6, 11, 7,
+ 11, 7, 3, 2, 1, 7, 9, 11, 3, 5,
+ 7, 2, 2, 2, 2, 1, 1, 2, 2, 4,
+ 1, 1, 6, 6, 6, 2, 2, 1, 1, 0,
+ 5, 5, 3, 3, 3, 3, 0, 1, 1, 1,
+ 1, 1, 0, 3, 0, 3, 3, 0, 3, 3,
+ 5, 5, 0, 3, 3, 0, 3, 3, 0, 3,
+ 3, 3, 5, 5, 0, 3, 0, 3, 1, 1,
+ 1, 1, 0, 3, 3, 3, 5, 5, 1, 1,
+ 1, 0, 3, 0, 3, 4, 4, 1, 1, 1,
+ 1, 1, 1, 1, 1, 3, 3, 3, 3, 5,
+ 5, 5, 5, 3, 3, 5, 5, 0, 1, 1,
+ 2, 2, 2, 3, 1, 5, 5, 3, 2, 2,
+ 2, 3, 1, 1, 1, 1, 3, 3, 3, 3,
+ 1, 1, 1, 1, 3, 1, 1, 3, 1, 1,
+ 3, 2, 2, 1, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 1
+};
+
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+/* Error token number */
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT. |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ YYFPRINTF (yyoutput, "%s %s (",
+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+ {
+ int yybot = *yybottom;
+ YYFPRINTF (stderr, " %d", yybot);
+ }
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr,
+ yystos[yyssp[yyi + 1 - yynrhs]],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ YYFPRINTF (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+ about the unexpected token YYTOKEN for the state stack whose top is
+ YYSSP.
+
+ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
+ not large enough to hold the message. In that case, also set
+ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
+ required number of bytes is too large to store. */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+{
+ YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+ const char *yyformat = YY_NULL;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+ "expected"). */
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+ tokens because there are none.
+ - The only way there can be no lookahead present (in yychar) is if
+ this state is a consistent state with a default action. Thus,
+ detecting the absence of a lookahead is sufficient to determine
+ that there is no unexpected or expected token to report. In that
+ case, just report a simple "syntax error".
+ - Don't assume there isn't a lookahead just because this state is a
+ consistent state with a default action. There might have been a
+ previous inconsistent state, consistent state with a non-default
+ action, or user semantic action that manipulated yychar.
+ - Of course, the expected token list depends on states to have
+ correct lookahead information, and it depends on the parser not
+ to perform extra reductions after fetching a lookahead from the
+ scanner and before detecting a syntax error. Thus, state merging
+ (from LALR or IELR) and default reductions corrupt the expected
+ token list. However, the list is correct for canonical LR with
+ one exception: it will still contain any token that will not be
+ accepted due to an error action in a later state.
+ */
+ if (yytoken != YYEMPTY)
+ {
+ int yyn = yypact[*yyssp];
+ yyarg[yycount++] = yytname[yytoken];
+ if (!yypact_value_is_default (yyn))
+ {
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. In other words, skip the first -YYN actions for
+ this state because they are default actions. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yyx;
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+ && !yytable_value_is_error (yytable[yyx + yyn]))
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+ }
+ }
+ }
+
+ switch (yycount)
+ {
+# define YYCASE_(N, S) \
+ case N: \
+ yyformat = S; \
+ break
+ YYCASE_(0, YY_("syntax error"));
+ YYCASE_(1, YY_("syntax error, unexpected %s"));
+ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+ }
+
+ {
+ YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+
+ if (*yymsg_alloc < yysize)
+ {
+ *yymsg_alloc = 2 * yysize;
+ if (! (yysize <= *yymsg_alloc
+ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+ return 1;
+ }
+
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ {
+ char *yyp = *yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyformat) != '\0')
+ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyformat += 2;
+ }
+ else
+ {
+ yyp++;
+ yyformat++;
+ }
+ }
+ return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+ YYUSE (yyvaluep);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol. */
+int yychar;
+
+/* The semantic value of the lookahead symbol. */
+YYSTYPE yylval;
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+int
+yyparse (void)
+{
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+ 'yyss': related to states.
+ 'yyvs': related to semantic values.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
+ YYSIZE_T yystacksize;
+
+ int yyn;
+ int yyresult;
+ /* Lookahead token as an internal (translated) token number. */
+ int yytoken = 0;
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss_alloc, yyss);
+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ if (yystate == YYFINAL)
+ YYACCEPT;
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ lookahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to lookahead token. */
+ yyn = yypact[yystate];
+ if (yypact_value_is_default (yyn))
+ goto yydefault;
+
+ /* Not known => get a lookahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yytable_value_is_error (yyn))
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the lookahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token. */
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 3:
+#line 647 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ insn = (yyvsp[0].instr);
+ if (insn == (INSTR_T) 0)
+ return NO_INSN_GENERATED;
+ else if (insn == (INSTR_T) - 1)
+ return SEMANTIC_ERROR;
+ else
+ return INSN_GENERATED;
+ }
+#line 2703 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 5:
+#line 661 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (((yyvsp[-5].instr)->value & 0xf800) == 0xc000)
+ {
+ if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-5].instr), (yyvsp[-3].instr), (yyvsp[-1].instr));
+ else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-5].instr), (yyvsp[-1].instr), (yyvsp[-3].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
+ }
+ else if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
+ {
+ if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-3].instr), (yyvsp[-5].instr), (yyvsp[-1].instr));
+ else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-3].instr), (yyvsp[-1].instr), (yyvsp[-5].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
+ }
+ else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
+ {
+ if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-3].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-1].instr), (yyvsp[-5].instr), (yyvsp[-3].instr));
+ else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-3].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-1].instr), (yyvsp[-3].instr), (yyvsp[-5].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
+ }
+ else
+ error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
+ }
+#line 2739 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 6:
+#line 694 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
+ {
+ if (is_group1 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-3].instr), (yyvsp[-1].instr), 0);
+ else if (is_group2 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-3].instr), 0, (yyvsp[-1].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
+ }
+ else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
+ {
+ if (is_group1 ((yyvsp[-3].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-1].instr), (yyvsp[-3].instr), 0);
+ else if (is_group2 ((yyvsp[-3].instr)))
+ (yyval.instr) = gen_multi_instr_1 ((yyvsp[-1].instr), 0, (yyvsp[-3].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
+ }
+ else if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 (0, (yyvsp[-3].instr), (yyvsp[-1].instr));
+ else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
+ (yyval.instr) = gen_multi_instr_1 (0, (yyvsp[-1].instr), (yyvsp[-3].instr));
+ else
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
+ }
+#line 2770 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 7:
+#line 721 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.instr) = 0;
+ yyerror ("");
+ yyerrok;
+ }
+#line 2780 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 8:
+#line 732 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.instr) = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
+ }
+#line 2788 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 9:
+#line 736 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ int op0, op1;
+ int w0 = 0, w1 = 0;
+ int h00, h10, h01, h11;
+
+ if (check_macfunc_option (&(yyvsp[-1].macfunc), &(yyvsp[0].mod)) < 0)
+ return yyerror ("bad option");
+
+ if ((yyvsp[-1].macfunc).n == 0)
+ {
+ if ((yyvsp[0].mod).MM)
+ return yyerror ("(m) not allowed with a0 unit");
+ op1 = 3;
+ op0 = (yyvsp[-1].macfunc).op;
+ w1 = 0;
+ w0 = (yyvsp[-1].macfunc).w;
+ h00 = IS_H ((yyvsp[-1].macfunc).s0);
+ h10 = IS_H ((yyvsp[-1].macfunc).s1);
+ h01 = h11 = 0;
+ }
+ else
+ {
+ op1 = (yyvsp[-1].macfunc).op;
+ op0 = 3;
+ w1 = (yyvsp[-1].macfunc).w;
+ w0 = 0;
+ h00 = h10 = 0;
+ h01 = IS_H ((yyvsp[-1].macfunc).s0);
+ h11 = IS_H ((yyvsp[-1].macfunc).s1);
+ }
+ (yyval.instr) = DSP32MAC (op1, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, w1, (yyvsp[-1].macfunc).P, h01, h11, h00, h10,
+ &(yyvsp[-1].macfunc).dst, op0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, w0);
+ }
+#line 2826 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 10:
+#line 774 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Register *dst;
+
+ if (check_macfuncs (&(yyvsp[-4].macfunc), &(yyvsp[-3].mod), &(yyvsp[-1].macfunc), &(yyvsp[0].mod)) < 0)
+ return -1;
+ notethat ("assign_macfunc (.), assign_macfunc (.)\n");
+
+ if ((yyvsp[-4].macfunc).w)
+ dst = &(yyvsp[-4].macfunc).dst;
+ else
+ dst = &(yyvsp[-1].macfunc).dst;
+
+ (yyval.instr) = DSP32MAC ((yyvsp[-4].macfunc).op, (yyvsp[-3].mod).MM, (yyvsp[0].mod).mod, (yyvsp[-4].macfunc).w, (yyvsp[-4].macfunc).P,
+ IS_H ((yyvsp[-4].macfunc).s0), IS_H ((yyvsp[-4].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+ dst, (yyvsp[-1].macfunc).op, &(yyvsp[-4].macfunc).s0, &(yyvsp[-4].macfunc).s1, (yyvsp[-1].macfunc).w);
+ }
+#line 2847 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 11:
+#line 794 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: DISALGNEXCPT\n");
+ (yyval.instr) = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
+ }
+#line 2856 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 12:
+#line 799 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && !IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
+ (yyval.instr) = DSP32ALU (11, 0, 0, &(yyvsp[-5].reg), &reg7, &reg7, 0, 0, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 2870 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 13:
+#line 809 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
+ (yyval.instr) = DSP32ALU (11, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &reg7, &reg7, 0, 0, 1);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 2884 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 14:
+#line 819 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+ (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
+ }
+#line 2893 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 15:
+#line 824 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+ (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
+ }
+#line 2902 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 16:
+#line 830 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG ((yyvsp[-13].reg)))
+ return yyerror ("Dregs expected");
+ else if (REG_SAME ((yyvsp[-15].reg), (yyvsp[-13].reg)))
+ return yyerror ("Illegal dest register combination");
+ else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
+ (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
+ }
+ }
+#line 2922 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 17:
+#line 848 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG ((yyvsp[-13].reg)))
+ return yyerror ("Dregs expected");
+ else if (REG_SAME ((yyvsp[-15].reg), (yyvsp[-13].reg)))
+ return yyerror ("Illegal dest register combination");
+ else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
+ (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 1);
+ }
+ }
+#line 2942 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 18:
+#line 865 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)))
+ return yyerror ("Dregs expected");
+ else if (REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg)))
+ return yyerror ("Illegal dest register combination");
+ else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
+ (yyval.instr) = DSP32ALU (24, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, (yyvsp[0].r0).r0, 0, 1);
+ }
+ }
+#line 2960 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 19:
+#line 879 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg)))
+ return yyerror ("Illegal dest register combination");
+
+ if (IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
+ (yyval.instr) = DSP32ALU (13, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0, (yyvsp[-1].r0).r0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 2977 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 20:
+#line 893 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-10].reg), (yyvsp[-4].reg)))
+ return yyerror ("Illegal dest register combination");
+
+ if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-4].reg)))
+ {
+ notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
+ (yyval.instr) = DSP32ALU (12, 0, &(yyvsp[-10].reg), &(yyvsp[-4].reg), &reg7, &reg7, 0, 0, 1);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 2994 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 21:
+#line 908 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-11].reg), (yyvsp[-5].reg)))
+ return yyerror ("Resource conflict in dest reg");
+
+ if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
+ && IS_A1 ((yyvsp[-3].reg)) && !IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
+ (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &reg7, &reg7, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 0);
+
+ }
+ else if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
+ && !IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
+ (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &reg7, &reg7, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 1);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3019 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 22:
+#line 930 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-8].r0).r0 == (yyvsp[-2].r0).r0)
+ return yyerror ("Operators must differ");
+
+ if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg))
+ && REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) && REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = dregs + dregs,"
+ "dregs = dregs - dregs (amod1)\n");
+ (yyval.instr) = DSP32ALU (4, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 2);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3038 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 23:
+#line 948 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) || !REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
+ return yyerror ("Differing source registers");
+
+ if (!IS_DREG ((yyvsp[-11].reg)) || !IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)) || !IS_DREG ((yyvsp[-5].reg)))
+ return yyerror ("Dregs expected");
+
+ if (REG_SAME ((yyvsp[-11].reg), (yyvsp[-5].reg)))
+ return yyerror ("Resource conflict in dest reg");
+
+ if ((yyvsp[-8].r0).r0 == 1 && (yyvsp[-2].r0).r0 == 2)
+ {
+ notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+ (yyval.instr) = DSP32ALU (1, 1, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
+ }
+ else if ((yyvsp[-8].r0).r0 == 0 && (yyvsp[-2].r0).r0 == 3)
+ {
+ notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+ (yyval.instr) = DSP32ALU (1, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
+ }
+ else
+ return yyerror ("Bar operand mismatch");
+ }
+#line 3066 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 24:
+#line 973 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ int op;
+
+ if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[0].r0).r0)
+ {
+ notethat ("dsp32alu: dregs = ABS dregs (v)\n");
+ op = 6;
+ }
+ else
+ {
+ /* Vector version of ABS. */
+ notethat ("dsp32alu: dregs = ABS dregs\n");
+ op = 7;
+ }
+ (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, 0, 0, 2);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3092 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 25:
+#line 995 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: Ax = ABS Ax\n");
+ (yyval.instr) = DSP32ALU (16, IS_A1 ((yyvsp[-2].reg)), 0, 0, &reg7, &reg7, 0, 0, IS_A1 ((yyvsp[0].reg)));
+ }
+#line 3101 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 26:
+#line 1000 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32alu: A0.l = reg_half\n");
+ (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
+ }
+ else
+ return yyerror ("A0.l = Rx.l expected");
+ }
+#line 3115 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 27:
+#line 1010 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32alu: A1.l = reg_half\n");
+ (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
+ }
+ else
+ return yyerror ("A1.l = Rx.l expected");
+ }
+#line 3129 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 28:
+#line 1021 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
+ (yyval.instr) = DSP32SHIFT (13, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[-5].r0).r0, 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3143 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 29:
+#line 1032 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-12].reg)))
+ return yyerror ("Dregs expected");
+ else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+ (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, (yyvsp[0].modcodes).r0);
+ }
+ }
+#line 3161 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 30:
+#line 1046 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-11].reg)))
+ return yyerror ("Dregs expected");
+ else if (!valid_dreg_pair (&(yyvsp[-7].reg), (yyvsp[-5].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+ (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-11].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0);
+ }
+ }
+#line 3179 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 31:
+#line 1062 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-12].reg)))
+ return yyerror ("Dregs expected");
+ else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
+ (yyval.instr) = DSP32ALU (22, (yyvsp[0].modcodes).r0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).aop);
+ }
+ }
+#line 3197 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 32:
+#line 1078 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-12].reg)))
+ return yyerror ("Dregs expected");
+ else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
+ (yyval.instr) = DSP32ALU (23, (yyvsp[0].modcodes).x0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, 0);
+ }
+ }
+#line 3215 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 33:
+#line 1093 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
+ (yyval.instr) = DSP32ALU (24, 0, 0, &(yyvsp[-7].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 0, 0, 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3229 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 34:
+#line 1105 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_HCOMPL ((yyvsp[-16].reg), (yyvsp[-14].reg)) && IS_HCOMPL ((yyvsp[-10].reg), (yyvsp[-3].reg)) && IS_HCOMPL ((yyvsp[-7].reg), (yyvsp[0].reg)))
+ {
+ notethat ("dsp32alu: dregs_hi = dregs_lo ="
+ "SIGN (dregs_hi) * dregs_hi + "
+ "SIGN (dregs_lo) * dregs_lo \n");
+
+ (yyval.instr) = DSP32ALU (12, 0, 0, &(yyvsp[-16].reg), &(yyvsp[-10].reg), &(yyvsp[-7].reg), 0, 0, 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3246 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 35:
+#line 1118 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[0].modcodes).aop == 0)
+ {
+ /* No saturation flag specified, generate the 16 bit variant. */
+ notethat ("COMP3op: dregs = dregs +- dregs\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[-2].r0).r0);
+ }
+ else
+ {
+ /* Saturation flag specified, generate the 32 bit variant. */
+ notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
+ (yyval.instr) = DSP32ALU (4, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
+ }
+ }
+ else
+ if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)) && (yyvsp[-2].r0).r0 == 0)
+ {
+ notethat ("COMP3op: pregs = pregs + pregs\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 5);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3276 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 36:
+#line 1144 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ int op;
+
+ if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
+ {
+ if ((yyvsp[0].r0).r0)
+ op = 6;
+ else
+ op = 7;
+
+ notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
+ (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), &(yyvsp[-2].reg), 0, 0, (yyvsp[-6].r0).r0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3297 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 37:
+#line 1162 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: Ax = - Ax\n");
+ (yyval.instr) = DSP32ALU (14, IS_A1 ((yyvsp[-2].reg)), 0, 0, &reg7, &reg7, 0, 0, IS_A1 ((yyvsp[0].reg)));
+ }
+#line 3306 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 38:
+#line 1167 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
+ (yyval.instr) = DSP32ALU (2 | (yyvsp[-2].r0).r0, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg),
+ (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)));
+ }
+#line 3316 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 39:
+#line 1173 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (EXPR_VALUE ((yyvsp[0].expr)) == 0 && !REG_SAME ((yyvsp[-2].reg), (yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: A1 = A0 = 0\n");
+ (yyval.instr) = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 0, 0, 2);
+ }
+ else
+ return yyerror ("Bad value, 0 expected");
+ }
+#line 3330 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 40:
+#line 1185 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)))
+ {
+ notethat ("dsp32alu: Ax = Ax (S)\n");
+ (yyval.instr) = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 1, 0, IS_A1 ((yyvsp[-4].reg)));
+ }
+ else
+ return yyerror ("Registers must be equal");
+ }
+#line 3344 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 41:
+#line 1196 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32alu: dregs_half = dregs (RND)\n");
+ (yyval.instr) = DSP32ALU (12, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, 0, 3);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3358 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 42:
+#line 1207 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
+ (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, (yyvsp[-4].r0).r0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3372 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 43:
+#line 1218 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
+ (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1, (yyvsp[-4].r0).r0 | 2);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3386 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 44:
+#line 1229 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!REG_SAME ((yyvsp[-1].reg), (yyvsp[0].reg)))
+ {
+ notethat ("dsp32alu: An = Am\n");
+ (yyval.instr) = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, IS_A1 ((yyvsp[-1].reg)), 0, 3);
+ }
+ else
+ return yyerror ("Accu reg arguments must differ");
+ }
+#line 3400 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 45:
+#line 1240 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32alu: An = dregs\n");
+ (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[0].reg), 0, 1, 0, IS_A1 ((yyvsp[-1].reg)) << 1);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3414 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 46:
+#line 1251 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_H ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[-3].reg).regno == REG_A0x && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: A0.x = dregs_lo\n");
+ (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 1);
+ }
+ else if ((yyvsp[-3].reg).regno == REG_A1x && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: A1.x = dregs_lo\n");
+ (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 3);
+ }
+ else if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ALU2op: dregs = dregs_lo\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 10 | ((yyvsp[0].r0).r0 ? 0: 1));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+ else
+ return yyerror ("Low reg expected");
+ }
+#line 3443 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 47:
+#line 1277 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("LDIMMhalf: pregs_half = imm16\n");
+
+ if (!IS_DREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)) && !IS_IREG ((yyvsp[-2].reg))
+ && !IS_MREG ((yyvsp[-2].reg)) && !IS_BREG ((yyvsp[-2].reg)) && !IS_LREG ((yyvsp[-2].reg)))
+ return yyerror ("Wrong register for load immediate");
+
+ if (!IS_IMM ((yyvsp[0].expr), 16) && !IS_UIMM ((yyvsp[0].expr), 16))
+ return yyerror ("Constant out of range");
+
+ (yyval.instr) = LDIMMHALF_R (&(yyvsp[-2].reg), IS_H ((yyvsp[-2].reg)), 0, 0, (yyvsp[0].expr));
+ }
+#line 3460 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 48:
+#line 1291 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32alu: An = 0\n");
+
+ if (imm7 ((yyvsp[0].expr)) != 0)
+ return yyerror ("0 expected");
+
+ (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[-1].reg)));
+ }
+#line 3473 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 49:
+#line 1301 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-3].reg)) && !IS_PREG ((yyvsp[-3].reg)) && !IS_IREG ((yyvsp[-3].reg))
+ && !IS_MREG ((yyvsp[-3].reg)) && !IS_BREG ((yyvsp[-3].reg)) && !IS_LREG ((yyvsp[-3].reg)))
+ return yyerror ("Wrong register for load immediate");
+
+ if ((yyvsp[0].r0).r0 == 0)
+ {
+ /* 7 bit immediate value if possible.
+ We will check for that constant value for efficiency
+ If it goes to reloc, it will be 16 bit. */
+ if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_DREG ((yyvsp[-3].reg)))
+ {
+ notethat ("COMPI2opD: dregs = imm7 (x) \n");
+ (yyval.instr) = COMPI2OPD (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
+ }
+ else if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ notethat ("COMPI2opP: pregs = imm7 (x)\n");
+ (yyval.instr) = COMPI2OPP (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
+ }
+ else
+ {
+ if (IS_CONST ((yyvsp[-1].expr)) && !IS_IMM ((yyvsp[-1].expr), 16))
+ return yyerror ("Immediate value out of range");
+
+ notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+ /* reg, H, S, Z. */
+ (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 1, 0, (yyvsp[-1].expr));
+ }
+ }
+ else
+ {
+ /* (z) There is no 7 bit zero extended instruction.
+ If the expr is a relocation, generate it. */
+
+ if (IS_CONST ((yyvsp[-1].expr)) && !IS_UIMM ((yyvsp[-1].expr), 16))
+ return yyerror ("Immediate value out of range");
+
+ notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+ /* reg, H, S, Z. */
+ (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 0, 1, (yyvsp[-1].expr));
+ }
+ }
+#line 3521 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 50:
+#line 1346 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_H ((yyvsp[-2].reg)))
+ return yyerror ("Low reg expected");
+
+ if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A0x)
+ {
+ notethat ("dsp32alu: dregs_lo = A0.x\n");
+ (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), &reg7, &reg7, 0, 0, 0);
+ }
+ else if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A1x)
+ {
+ notethat ("dsp32alu: dregs_lo = A1.x\n");
+ (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), &reg7, &reg7, 0, 0, 1);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3543 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 51:
+#line 1365 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
+ (yyval.instr) = DSP32ALU (0, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3557 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 52:
+#line 1376 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ALU2op: dregs = dregs_byte\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 12 | ((yyvsp[0].r0).r0 ? 0: 1));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3571 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 53:
+#line 1387 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
+ {
+ notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
+ (yyval.instr) = DSP32ALU (16, 0, 0, 0, &reg7, &reg7, 0, 0, 3);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3585 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 54:
+#line 1398 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
+ {
+ notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
+ (yyval.instr) = DSP32ALU (14, 0, 0, 0, &reg7, &reg7, 0, 0, 3);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3599 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 55:
+#line 1409 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: A0 -= A1\n");
+ (yyval.instr) = DSP32ALU (11, 0, 0, 0, &reg7, &reg7, (yyvsp[0].r0).r0, 0, 3);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3613 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 56:
+#line 1420 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 4)
+ {
+ notethat ("dagMODik: iregs -= 4\n");
+ (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 3);
+ }
+ else if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 2)
+ {
+ notethat ("dagMODik: iregs -= 2\n");
+ (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 1);
+ }
+ else
+ return yyerror ("Register or value mismatch");
+ }
+#line 3632 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 57:
+#line 1436 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dagMODim: iregs += mregs (opt_brev)\n");
+ /* i, m, op, br. */
+ (yyval.instr) = DAGMODIM (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1);
+ }
+ else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ notethat ("PTR2op: pregs += pregs (BREV )\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 5);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3652 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 58:
+#line 1453 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
+ {
+ notethat ("dagMODim: iregs -= mregs\n");
+ (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1, 0);
+ }
+ else if (IS_PREG ((yyvsp[-2].reg)) && IS_PREG ((yyvsp[0].reg)))
+ {
+ notethat ("PTR2op: pregs -= pregs\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3671 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 59:
+#line 1469 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32alu: A0 += A1 (W32)\n");
+ (yyval.instr) = DSP32ALU (11, 0, 0, 0, &reg7, &reg7, (yyvsp[0].r0).r0, 0, 2);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3685 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 60:
+#line 1480 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
+ {
+ notethat ("dagMODim: iregs += mregs\n");
+ (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0, 0);
+ }
+ else
+ return yyerror ("iregs += mregs expected");
+ }
+#line 3699 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 61:
+#line 1491 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IREG ((yyvsp[-2].reg)))
+ {
+ if (EXPR_VALUE ((yyvsp[0].expr)) == 4)
+ {
+ notethat ("dagMODik: iregs += 4\n");
+ (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 2);
+ }
+ else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+ {
+ notethat ("dagMODik: iregs += 2\n");
+ (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 0);
+ }
+ else
+ return yyerror ("iregs += [ 2 | 4 ");
+ }
+ else if (IS_PREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
+ {
+ notethat ("COMPI2opP: pregs += imm7\n");
+ (yyval.instr) = COMPI2OPP (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
+ }
+ else if (IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
+ {
+ notethat ("COMPI2opD: dregs += imm7\n");
+ (yyval.instr) = COMPI2OPD (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
+ }
+ else if ((IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg))) && IS_CONST ((yyvsp[0].expr)))
+ return yyerror ("Immediate value out of range");
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3735 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 62:
+#line 1524 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ALU2op: dregs *= dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3749 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 63:
+#line 1535 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+ return yyerror ("Bad dreg pair");
+ else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+ return yyerror ("Bad dreg pair");
+ else
+ {
+ notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
+ (yyval.instr) = DSP32ALU (18, 0, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
+ }
+ }
+#line 3765 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 64:
+#line 1548 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-10].reg), (yyvsp[-9].reg)) && REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)) && !REG_SAME ((yyvsp[-10].reg), (yyvsp[-4].reg)))
+ {
+ notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
+ (yyval.instr) = DSP32ALU (8, 0, 0, 0, &reg7, &reg7, 1, 0, 2);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3779 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 65:
+#line 1559 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg))
+ && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
+ {
+ if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
+ {
+ notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 4);
+ }
+ else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+ {
+ notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 5);
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+ else if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg))
+ && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
+ {
+ if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
+ {
+ notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 6);
+ }
+ else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+ {
+ notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 7);
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 3820 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 66:
+#line 1598 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("COMP3op: dregs = dregs | dregs\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3834 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 67:
+#line 1608 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("COMP3op: dregs = dregs ^ dregs\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 4);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3848 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 68:
+#line 1618 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+ {
+ notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 6);
+ }
+ else if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+ {
+ notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 7);
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 3872 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 69:
+#line 1638 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].reg).regno == REG_A0 && (yyvsp[0].reg).regno == REG_A1)
+ {
+ notethat ("CCflag: CC = A0 == A1\n");
+ (yyval.instr) = CCFLAG (0, 0, 5, 0, 0);
+ }
+ else
+ return yyerror ("AREGs are in bad order or same");
+ }
+#line 3886 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 70:
+#line 1648 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].reg).regno == REG_A0 && (yyvsp[0].reg).regno == REG_A1)
+ {
+ notethat ("CCflag: CC = A0 < A1\n");
+ (yyval.instr) = CCFLAG (0, 0, 6, 0, 0);
+ }
+ else
+ return yyerror ("AREGs are in bad order or same");
+ }
+#line 3900 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 71:
+#line 1658 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ || (IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg))))
+ {
+ notethat ("CCflag: CC = dpregs < dpregs\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad register in comparison");
+ }
+#line 3915 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 72:
+#line 1669 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-3].reg)) && !IS_PREG ((yyvsp[-3].reg)))
+ return yyerror ("Bad register in comparison");
+
+ if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
+ || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
+ {
+ notethat ("CCflag: CC = dpregs < (u)imm3\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), (yyvsp[0].r0).r0, 1, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad constant value");
+ }
+#line 3933 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 73:
+#line 1683 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ || (IS_PREG ((yyvsp[-2].reg)) && IS_PREG ((yyvsp[0].reg))))
+ {
+ notethat ("CCflag: CC = dpregs == dpregs\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), (yyvsp[0].reg).regno & CODE_MASK, 0, 0, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad register in comparison");
+ }
+#line 3948 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 74:
+#line 1694 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)))
+ return yyerror ("Bad register in comparison");
+
+ if (IS_IMM ((yyvsp[0].expr), 3))
+ {
+ notethat ("CCflag: CC = dpregs == imm3\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), imm3 ((yyvsp[0].expr)), 0, 1, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad constant range");
+ }
+#line 3965 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 75:
+#line 1707 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].reg).regno == REG_A0 && (yyvsp[0].reg).regno == REG_A1)
+ {
+ notethat ("CCflag: CC = A0 <= A1\n");
+ (yyval.instr) = CCFLAG (0, 0, 7, 0, 0);
+ }
+ else
+ return yyerror ("AREGs are in bad order or same");
+ }
+#line 3979 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 76:
+#line 1717 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ || (IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg))))
+ {
+ notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK,
+ 1 + (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad register in comparison");
+ }
+#line 3995 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 77:
+#line 1729 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-3].reg)) && !IS_PREG ((yyvsp[-3].reg)))
+ return yyerror ("Bad register in comparison");
+
+ if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
+ || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
+ {
+ notethat ("CCflag: CC = dpregs <= (u)imm3\n");
+ (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), 1 + (yyvsp[0].r0).r0, 1, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+ }
+ else
+ return yyerror ("Bad constant value");
+ }
+#line 4013 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 78:
+#line 1744 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("COMP3op: dregs = dregs & dregs\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 4027 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 79:
+#line 1755 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("CC2stat operation\n");
+ (yyval.instr) = bfin_gen_cc2stat ((yyvsp[0].modcodes).r0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).s0);
+ }
+#line 4036 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 80:
+#line 1761 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_GENREG ((yyvsp[-2].reg)) && IS_GENREG ((yyvsp[0].reg)))
+ || (IS_GENREG ((yyvsp[-2].reg)) && IS_DAGREG ((yyvsp[0].reg)))
+ || (IS_DAGREG ((yyvsp[-2].reg)) && IS_GENREG ((yyvsp[0].reg)))
+ || (IS_DAGREG ((yyvsp[-2].reg)) && IS_DAGREG ((yyvsp[0].reg)))
+ || (IS_GENREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_USP)
+ || ((yyvsp[-2].reg).regno == REG_USP && IS_GENREG ((yyvsp[0].reg)))
+ || ((yyvsp[-2].reg).regno == REG_USP && (yyvsp[0].reg).regno == REG_USP)
+ || (IS_DREG ((yyvsp[-2].reg)) && IS_SYSREG ((yyvsp[0].reg)))
+ || (IS_PREG ((yyvsp[-2].reg)) && IS_SYSREG ((yyvsp[0].reg)))
+ || (IS_SYSREG ((yyvsp[-2].reg)) && IS_GENREG ((yyvsp[0].reg)))
+ || (IS_ALLREG ((yyvsp[-2].reg)) && IS_EMUDAT ((yyvsp[0].reg)))
+ || (IS_EMUDAT ((yyvsp[-2].reg)) && IS_ALLREG ((yyvsp[0].reg)))
+ || (IS_SYSREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_USP))
+ {
+ (yyval.instr) = bfin_gen_regmv (&(yyvsp[0].reg), &(yyvsp[-2].reg));
+ }
+ else
+ return yyerror ("Unsupported register move");
+ }
+#line 4061 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 81:
+#line 1783 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("CC2dreg: CC = dregs\n");
+ (yyval.instr) = bfin_gen_cc2dreg (1, &(yyvsp[0].reg));
+ }
+ else
+ return yyerror ("Only 'CC = Dreg' supported");
+ }
+#line 4075 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 82:
+#line 1794 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)))
+ {
+ notethat ("CC2dreg: dregs = CC\n");
+ (yyval.instr) = bfin_gen_cc2dreg (0, &(yyvsp[-2].reg));
+ }
+ else
+ return yyerror ("Only 'Dreg = CC' supported");
+ }
+#line 4089 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 83:
+#line 1805 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("CC2dreg: CC =! CC\n");
+ (yyval.instr) = bfin_gen_cc2dreg (3, 0);
+ }
+#line 4098 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 84:
+#line 1813 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
+
+ if (!IS_H ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM)
+ return yyerror ("(M) not allowed with MAC0");
+
+ if ((yyvsp[0].mod).mod != 0 && (yyvsp[0].mod).mod != M_FU && (yyvsp[0].mod).mod != M_IS
+ && (yyvsp[0].mod).mod != M_IU && (yyvsp[0].mod).mod != M_T && (yyvsp[0].mod).mod != M_TFU
+ && (yyvsp[0].mod).mod != M_S2RND && (yyvsp[0].mod).mod != M_ISS2 && (yyvsp[0].mod).mod != M_IH)
+ return yyerror ("bad option.");
+
+ if (IS_H ((yyvsp[-3].reg)))
+ {
+ (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+ IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
+ &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
+ }
+ else
+ {
+ (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 0,
+ 0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+ &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
+ }
+ }
+#line 4127 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 85:
+#line 1839 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ /* Odd registers can use (M). */
+ if (!IS_DREG ((yyvsp[-3].reg)))
+ return yyerror ("Dreg expected");
+
+ if (IS_EVEN ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM)
+ return yyerror ("(M) not allowed with MAC0");
+
+ if ((yyvsp[0].mod).mod != 0 && (yyvsp[0].mod).mod != M_FU && (yyvsp[0].mod).mod != M_IS
+ && (yyvsp[0].mod).mod != M_S2RND && (yyvsp[0].mod).mod != M_ISS2)
+ return yyerror ("bad option");
+
+ if (!IS_EVEN ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
+
+ (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
+ IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
+ &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
+ }
+ else
+ {
+ notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
+ (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 1,
+ 0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+ &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
+ }
+ }
+#line 4160 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 86:
+#line 1870 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg)))
+ return yyerror ("Dregs expected");
+
+ if (!IS_HCOMPL((yyvsp[-8].reg), (yyvsp[-3].reg)))
+ return yyerror ("Dest registers mismatch");
+
+ if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
+ return -1;
+
+ if ((!IS_H ((yyvsp[-8].reg)) && (yyvsp[-5].mod).MM)
+ || (!IS_H ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM))
+ return yyerror ("(M) not allowed with MAC0");
+
+ notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
+ "dregs_lo = multiply_halfregs opt_mode\n");
+
+ if (IS_H ((yyvsp[-8].reg)))
+ (yyval.instr) = DSP32MULT (0, (yyvsp[-5].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+ IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+ &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+ else
+ (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+ IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
+ &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+ }
+#line 4191 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 87:
+#line 1898 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg)))
+ return yyerror ("Dregs expected");
+
+ if ((IS_EVEN ((yyvsp[-8].reg)) && (yyvsp[-3].reg).regno - (yyvsp[-8].reg).regno != 1)
+ || (IS_EVEN ((yyvsp[-3].reg)) && (yyvsp[-8].reg).regno - (yyvsp[-3].reg).regno != 1))
+ return yyerror ("Dest registers mismatch");
+
+ if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
+ return -1;
+
+ if ((IS_EVEN ((yyvsp[-8].reg)) && (yyvsp[-5].mod).MM)
+ || (IS_EVEN ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM))
+ return yyerror ("(M) not allowed with MAC0");
+
+ notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
+ "dregs = multiply_halfregs opt_mode\n");
+
+ if (IS_EVEN ((yyvsp[-8].reg)))
+ (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
+ IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
+ &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+ else
+ (yyval.instr) = DSP32MULT (0, (yyvsp[-5].mod).MM, (yyvsp[0].mod).mod, 1, 1,
+ IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+ &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+ }
+#line 4223 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 88:
+#line 1929 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)))
+ return yyerror ("Aregs must be same");
+
+ if (IS_DREG ((yyvsp[0].reg)) && !IS_H ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 0, IS_A1 ((yyvsp[-4].reg)));
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 4240 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 89:
+#line 1943 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-6].reg), (yyvsp[-3].reg)));
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 4254 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 90:
+#line 1954 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
+ return yyerror ("Aregs must be same");
+
+ if (IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
+ (yyval.instr) = DSP32SHIFTIMM (3, 0, imm5 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+#line 4271 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 91:
+#line 1968 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ if ((yyvsp[0].modcodes).r0)
+ {
+ /* Vector? */
+ notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
+ (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), imm4 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
+ }
+ else
+ {
+ notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
+ (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
+ }
+ }
+ else if ((yyvsp[0].modcodes).s0 == 0 && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+ {
+ notethat ("PTR2op: pregs = pregs << 2\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 1);
+ }
+ else if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+ {
+ notethat ("COMP3op: pregs = pregs << 1\n");
+ (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-3].reg), 5);
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+ else
+ return yyerror ("Bad shift value or register");
+ }
+#line 4309 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 92:
+#line 2002 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_UIMM ((yyvsp[-1].expr), 4))
+ {
+ if ((yyvsp[0].modcodes).s0)
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
+ (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
+ }
+ else
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+ (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
+ }
+ }
+ else
+ return yyerror ("Bad shift value");
+ }
+#line 4331 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 93:
+#line 2020 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ int op;
+
+ if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[0].modcodes).r0)
+ {
+ op = 1;
+ notethat ("dsp32shift: dregs = ASHIFT dregs BY "
+ "dregs_lo (V, .)\n");
+ }
+ else
+ {
+
+ op = 2;
+ notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
+ }
+ (yyval.instr) = DSP32SHIFT (op, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 4358 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 94:
+#line 2045 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-8].reg)) && IS_DREG_L ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
+ (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+ }
+ else
+ return yyerror ("Bad shift value or register");
+ }
+#line 4372 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 95:
+#line 2057 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
+ (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+ }
+ else if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_H ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
+ (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 3, 0);
+ }
+ else
+ return yyerror ("Bad shift value or register");
+ }
+#line 4391 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 96:
+#line 2075 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
+ (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4405 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 97:
+#line 2086 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)))
+ {
+ notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
+ (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-10].reg), &(yyvsp[-4].reg), &(yyvsp[-6].reg), 3, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4419 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 98:
+#line 2097 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
+ {
+ notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
+ (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4433 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 99:
+#line 2108 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
+ return yyerror ("Aregs must be same");
+
+ if (IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
+ (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
+ }
+ else
+ return yyerror ("Shift value range error");
+ }
+#line 4450 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 100:
+#line 2121 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 1, IS_A1 ((yyvsp[-4].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4464 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 101:
+#line 2132 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-2].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4478 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 102:
+#line 2143 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
+ (yyval.instr) = DSP32SHIFT ((yyvsp[0].r0).r0 ? 1: 2, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4492 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 103:
+#line 2154 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4506 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 104:
+#line 2165 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6) >= 0)
+ {
+ notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
+ (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
+ }
+ else
+ return yyerror ("Accu register expected");
+ }
+#line 4520 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 105:
+#line 2176 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[0].r0).r0 == 1)
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
+ (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+ else
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
+ (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
+ }
+ else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+ {
+ notethat ("PTR2op: pregs = pregs >> 2\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 3);
+ }
+ else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+ {
+ notethat ("PTR2op: pregs = pregs >> 1\n");
+ (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 4);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+ }
+#line 4557 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 106:
+#line 2209 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
+ (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-4].reg), -uimm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4571 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 107:
+#line 2219 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
+ (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg),
+ (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
+ }
+ else
+ return yyerror ("Register or modifier mismatch");
+ }
+#line 4586 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 108:
+#line 2232 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ if ((yyvsp[0].modcodes).r0)
+ {
+ /* Vector? */
+ notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
+ (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+ }
+ else
+ {
+ notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
+ (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+ }
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4609 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 109:
+#line 2252 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = ONES dregs\n");
+ (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 3, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4623 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 110:
+#line 2263 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
+ (yyval.instr) = DSP32SHIFT (4, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4637 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 111:
+#line 2274 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-9].reg))
+ && (yyvsp[-3].reg).regno == REG_A0
+ && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
+ (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 0, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4653 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 112:
+#line 2287 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-9].reg))
+ && (yyvsp[-3].reg).regno == REG_A0
+ && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
+ (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 1, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4669 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 113:
+#line 2300 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-11].reg)) && !IS_H ((yyvsp[-11].reg)) && !REG_SAME ((yyvsp[-5].reg), (yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
+ (yyval.instr) = DSP32SHIFT (12, &(yyvsp[-11].reg), 0, 0, 1, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4683 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 114:
+#line 2311 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 2, IS_A1 ((yyvsp[-4].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4697 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 115:
+#line 2322 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 3, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4711 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 116:
+#line 2333 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_IMM ((yyvsp[0].expr), 6))
+ {
+ notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
+ (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4725 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 117:
+#line 2344 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6))
+ {
+ (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4738 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 118:
+#line 2354 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
+ (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, 0, IS_A1 ((yyvsp[0].reg)), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4752 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 119:
+#line 2365 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
+ (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 0, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4766 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 120:
+#line 2376 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
+ (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 1 + IS_H ((yyvsp[0].reg)), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4780 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 121:
+#line 2388 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG_L ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-2].reg)))
+ {
+ notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
+ (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-6].reg), 0, &(yyvsp[-2].reg), ((yyvsp[0].r0).r0 ? 0 : 1), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4794 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 122:
+#line 2399 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
+ {
+ notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
+ (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), 2 | ((yyvsp[0].r0).r0 ? 0 : 1), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4808 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 123:
+#line 2410 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)))
+ return yyerror ("Illegal source register combination");
+
+ if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)) && !IS_A1 ((yyvsp[-2].reg)))
+ {
+ notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
+ (yyval.instr) = DSP32SHIFT (8, 0, &(yyvsp[-6].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4825 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 124:
+#line 2424 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_A1 ((yyvsp[-8].reg)) && !IS_A1 ((yyvsp[-5].reg)) && IS_A1 ((yyvsp[-3].reg)))
+ {
+ notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
+ (yyval.instr) = DSP32SHIFT (12, 0, 0, 0, 0, 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 4839 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 125:
+#line 2437 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 4);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4853 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 126:
+#line 2449 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 2);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4867 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 127:
+#line 2461 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 3);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4881 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 128:
+#line 2472 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 0);
+ }
+ else
+ return yyerror ("Register mismatch or value error");
+ }
+#line 4895 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 129:
+#line 2483 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+ {
+ notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 1);
+ }
+ else
+ return yyerror ("Register mismatch or value error");
+ }
+#line 4909 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 130:
+#line 2494 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg)))
+ && (IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg))))
+ {
+ notethat ("ccMV: IF ! CC gregs = gregs\n");
+ (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 0);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4924 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 131:
+#line 2506 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg)))
+ && (IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg))))
+ {
+ notethat ("ccMV: IF CC gregs = gregs\n");
+ (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 1);
+ }
+ else
+ return yyerror ("Register mismatch");
+ }
+#line 4939 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 132:
+#line 2518 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL10 ((yyvsp[0].expr)))
+ {
+ notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
+ (yyval.instr) = BRCC (0, 0, (yyvsp[0].expr));
+ }
+ else
+ return yyerror ("Bad jump offset");
+ }
+#line 4953 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 133:
+#line 2529 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL10 ((yyvsp[-3].expr)))
+ {
+ notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
+ (yyval.instr) = BRCC (0, 1, (yyvsp[-3].expr));
+ }
+ else
+ return yyerror ("Bad jump offset");
+ }
+#line 4967 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 134:
+#line 2540 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL10 ((yyvsp[0].expr)))
+ {
+ notethat ("BRCC: IF CC JUMP pcrel11m2\n");
+ (yyval.instr) = BRCC (1, 0, (yyvsp[0].expr));
+ }
+ else
+ return yyerror ("Bad jump offset");
+ }
+#line 4981 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 135:
+#line 2551 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL10 ((yyvsp[-3].expr)))
+ {
+ notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
+ (yyval.instr) = BRCC (1, 1, (yyvsp[-3].expr));
+ }
+ else
+ return yyerror ("Bad jump offset");
+ }
+#line 4995 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 136:
+#line 2561 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: NOP\n");
+ (yyval.instr) = PROGCTRL (0, 0);
+ }
+#line 5004 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 137:
+#line 2567 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: RTS\n");
+ (yyval.instr) = PROGCTRL (1, 0);
+ }
+#line 5013 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 138:
+#line 2573 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: RTI\n");
+ (yyval.instr) = PROGCTRL (1, 1);
+ }
+#line 5022 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 139:
+#line 2579 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: RTX\n");
+ (yyval.instr) = PROGCTRL (1, 2);
+ }
+#line 5031 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 140:
+#line 2585 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: RTN\n");
+ (yyval.instr) = PROGCTRL (1, 3);
+ }
+#line 5040 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 141:
+#line 2591 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: RTE\n");
+ (yyval.instr) = PROGCTRL (1, 4);
+ }
+#line 5049 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 142:
+#line 2597 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: IDLE\n");
+ (yyval.instr) = PROGCTRL (2, 0);
+ }
+#line 5058 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 143:
+#line 2603 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: CSYNC\n");
+ (yyval.instr) = PROGCTRL (2, 3);
+ }
+#line 5067 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 144:
+#line 2609 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: SSYNC\n");
+ (yyval.instr) = PROGCTRL (2, 4);
+ }
+#line 5076 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 145:
+#line 2615 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: EMUEXCPT\n");
+ (yyval.instr) = PROGCTRL (2, 5);
+ }
+#line 5085 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 146:
+#line 2621 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ProgCtrl: CLI dregs\n");
+ (yyval.instr) = PROGCTRL (3, (yyvsp[0].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Dreg expected for CLI");
+ }
+#line 5099 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 147:
+#line 2632 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ProgCtrl: STI dregs\n");
+ (yyval.instr) = PROGCTRL (4, (yyvsp[0].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Dreg expected for STI");
+ }
+#line 5113 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 148:
+#line 2643 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ProgCtrl: JUMP (pregs )\n");
+ (yyval.instr) = PROGCTRL (5, (yyvsp[-1].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Bad register for indirect jump");
+ }
+#line 5127 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 149:
+#line 2654 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ProgCtrl: CALL (pregs )\n");
+ (yyval.instr) = PROGCTRL (6, (yyvsp[-1].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Bad register for indirect call");
+ }
+#line 5141 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 150:
+#line 2665 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ProgCtrl: CALL (PC + pregs )\n");
+ (yyval.instr) = PROGCTRL (7, (yyvsp[-1].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Bad register for indirect call");
+ }
+#line 5155 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 151:
+#line 2676 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("ProgCtrl: JUMP (PC + pregs )\n");
+ (yyval.instr) = PROGCTRL (8, (yyvsp[-1].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Bad register for indirect jump");
+ }
+#line 5169 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 152:
+#line 2687 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_UIMM ((yyvsp[0].expr), 4))
+ {
+ notethat ("ProgCtrl: RAISE uimm4\n");
+ (yyval.instr) = PROGCTRL (9, uimm4 ((yyvsp[0].expr)));
+ }
+ else
+ return yyerror ("Bad value for RAISE");
+ }
+#line 5183 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 153:
+#line 2698 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("ProgCtrl: EMUEXCPT\n");
+ (yyval.instr) = PROGCTRL (10, uimm4 ((yyvsp[0].expr)));
+ }
+#line 5192 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 154:
+#line 2704 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[-1].reg).regno == REG_SP || (yyvsp[-1].reg).regno == REG_FP)
+ return yyerror ("Bad register for TESTSET");
+
+ notethat ("ProgCtrl: TESTSET (pregs )\n");
+ (yyval.instr) = PROGCTRL (11, (yyvsp[-1].reg).regno & CODE_MASK);
+ }
+ else
+ return yyerror ("Preg expected");
+ }
+#line 5209 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 155:
+#line 2718 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL12 ((yyvsp[0].expr)))
+ {
+ notethat ("UJUMP: JUMP pcrel12\n");
+ (yyval.instr) = UJUMP ((yyvsp[0].expr));
+ }
+ else
+ return yyerror ("Bad value for relative jump");
+ }
+#line 5223 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 156:
+#line 2729 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL12 ((yyvsp[0].expr)))
+ {
+ notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
+ (yyval.instr) = UJUMP((yyvsp[0].expr));
+ }
+ else
+ return yyerror ("Bad value for relative jump");
+ }
+#line 5237 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 157:
+#line 2740 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL24 ((yyvsp[0].expr)))
+ {
+ notethat ("CALLa: jump.l pcrel24\n");
+ (yyval.instr) = CALLA ((yyvsp[0].expr), 0);
+ }
+ else
+ return yyerror ("Bad value for long jump");
+ }
+#line 5251 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 158:
+#line 2751 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL24 ((yyvsp[0].expr)))
+ {
+ notethat ("CALLa: jump.l pcrel24\n");
+ (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
+ }
+ else
+ return yyerror ("Bad value for long jump");
+ }
+#line 5265 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 159:
+#line 2762 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL24 ((yyvsp[0].expr)))
+ {
+ notethat ("CALLa: CALL pcrel25m2\n");
+ (yyval.instr) = CALLA ((yyvsp[0].expr), 1);
+ }
+ else
+ return yyerror ("Bad call address");
+ }
+#line 5279 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 160:
+#line 2772 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL24 ((yyvsp[0].expr)))
+ {
+ notethat ("CALLa: CALL pcrel25m2\n");
+ (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
+ }
+ else
+ return yyerror ("Bad call address");
+ }
+#line 5293 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 161:
+#line 2785 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 8);
+ else
+ return yyerror ("Bad registers for DIVQ");
+ }
+#line 5304 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 162:
+#line 2793 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 9);
+ else
+ return yyerror ("Bad registers for DIVS");
+ }
+#line 5315 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 163:
+#line 2801 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
+ {
+ if ((yyvsp[0].modcodes).r0 == 0 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 0)
+ {
+ notethat ("ALU2op: dregs = - dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-4].reg), &(yyvsp[-1].reg), 14);
+ }
+ else if ((yyvsp[0].modcodes).r0 == 1 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 3)
+ {
+ notethat ("dsp32alu: dregs = - dregs (.)\n");
+ (yyval.instr) = DSP32ALU (15, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
+ }
+ else
+ {
+ notethat ("dsp32alu: dregs = - dregs (.)\n");
+ (yyval.instr) = DSP32ALU (7, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
+ }
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5342 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 164:
+#line 2825 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ALU2op: dregs = ~dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[0].reg), 15);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5356 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 165:
+#line 2836 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ALU2op: dregs >>= dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5370 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 166:
+#line 2847 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("LOGI2op: dregs >>= uimm5\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 6);
+ }
+ else
+ return yyerror ("Dregs expected or value error");
+ }
+#line 5384 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 167:
+#line 2858 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ALU2op: dregs >>>= dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5398 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 168:
+#line 2869 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("ALU2op: dregs <<= dregs\n");
+ (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5412 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 169:
+#line 2880 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("LOGI2op: dregs <<= uimm5\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 7);
+ }
+ else
+ return yyerror ("Dregs expected or const value error");
+ }
+#line 5426 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 170:
+#line 2892 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+ {
+ notethat ("LOGI2op: dregs >>>= uimm5\n");
+ (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 5);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 5440 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 171:
+#line 2905 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("CaCTRL: FLUSH [ pregs ]\n");
+ if (IS_PREG ((yyvsp[-1].reg)))
+ (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 2);
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5452 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 172:
+#line 2914 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[0].reg)))
+ {
+ notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 2);
+ }
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5466 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 173:
+#line 2925 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 1);
+ }
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5480 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 174:
+#line 2936 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[0].reg)))
+ {
+ notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 1);
+ }
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5494 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 175:
+#line 2948 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("CaCTRL: IFLUSH [ pregs ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 3);
+ }
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5508 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 176:
+#line 2959 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[0].reg)))
+ {
+ notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 3);
+ }
+ else
+ return yyerror ("Bad register(s) for FLUSH");
+ }
+#line 5522 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 177:
+#line 2970 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("CaCTRL: PREFETCH [ pregs ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 0);
+ }
+ else
+ return yyerror ("Bad register(s) for PREFETCH");
+ }
+#line 5536 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 178:
+#line 2981 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PREG ((yyvsp[0].reg)))
+ {
+ notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
+ (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 0);
+ }
+ else
+ return yyerror ("Bad register(s) for PREFETCH");
+ }
+#line 5550 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 179:
+#line 2995 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if (!IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
+ (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 2, 0, 1);
+ }
+#line 5564 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 180:
+#line 3007 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-3].expr);
+
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if (!IS_PREG ((yyvsp[-5].reg)))
+ return yyerror ("Preg expected in address");
+
+ if (IS_RELOC ((yyvsp[-3].expr)))
+ return yyerror ("Plain symbol used as offset");
+
+ if ((yyvsp[-4].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (in_range_p (tmp, -32768, 32767, 0))
+ {
+ notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 2, 0, (yyvsp[-3].expr));
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5591 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 181:
+#line 3033 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-3].expr);
+
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if (!IS_PREG ((yyvsp[-5].reg)))
+ return yyerror ("Preg expected in address");
+
+ if ((yyvsp[-4].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (IS_RELOC ((yyvsp[-3].expr)))
+ return yyerror ("Plain symbol used as offset");
+
+ if (in_range_p (tmp, 0, 30, 1))
+ {
+ notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
+ (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), tmp, 1, 1);
+ }
+ else if (in_range_p (tmp, -65536, 65535, 1))
+ {
+ notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 1, 0, tmp);
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5623 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 182:
+#line 3063 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if (!IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
+ (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1, 0, 1);
+ }
+#line 5637 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 183:
+#line 3074 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if ((yyvsp[-3].modcodes).x0 == 2)
+ {
+ if (!IS_IREG ((yyvsp[-4].reg)) && !IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Ireg or Preg expected in address");
+ }
+ else if (!IS_IREG ((yyvsp[-4].reg)))
+ return yyerror ("Ireg expected in address");
+
+ if (IS_IREG ((yyvsp[-4].reg)))
+ {
+ notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
+ (yyval.instr) = DSPLDST (&(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
+ }
+ else
+ {
+ notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[0].reg), &(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
+ }
+ }
+#line 5664 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 184:
+#line 3099 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-3].expr);
+ int ispreg = IS_PREG ((yyvsp[0].reg));
+
+ if (!IS_PREG ((yyvsp[-5].reg)))
+ return yyerror ("Preg expected in address");
+
+ if (!IS_DREG ((yyvsp[0].reg)) && !ispreg)
+ return yyerror ("Preg expected for source operand");
+
+ if ((yyvsp[-4].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (IS_RELOC ((yyvsp[-3].expr)))
+ return yyerror ("Plain symbol used as offset");
+
+ if (in_range_p (tmp, 0, 63, 3))
+ {
+ notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
+ (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), tmp, 1, ispreg ? 3 : 0);
+ }
+ else if ((yyvsp[-5].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+ {
+ notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+ (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[0].reg), 1);
+ }
+ else if (in_range_p (tmp, -131072, 131071, 3))
+ {
+ notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 0, ispreg ? 1 : 0, tmp);
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5704 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 185:
+#line 3136 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-2].expr);
+ if (!IS_DREG ((yyvsp[-8].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Preg expected in address");
+
+ if ((yyvsp[-3].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (IS_RELOC ((yyvsp[-2].expr)))
+ return yyerror ("Plain symbol used as offset");
+
+ if (in_range_p (tmp, 0, 30, 1))
+ {
+ notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
+ (yyval.instr) = LDSTII (&(yyvsp[-4].reg), &(yyvsp[-8].reg), tmp, 0, 1 << (yyvsp[0].r0).r0);
+ }
+ else if (in_range_p (tmp, -65536, 65535, 1))
+ {
+ notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 1, (yyvsp[0].r0).r0, tmp);
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5735 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 186:
+#line 3164 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-6].reg)))
+ return yyerror ("Dreg expected for source operand");
+ if ((yyvsp[-1].modcodes).x0 == 2)
+ {
+ if (!IS_IREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)))
+ return yyerror ("Ireg or Preg expected in address");
+ }
+ else if (!IS_IREG ((yyvsp[-2].reg)))
+ return yyerror ("Ireg expected in address");
+
+ if (IS_IREG ((yyvsp[-2].reg)))
+ {
+ notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
+ (yyval.instr) = DSPLDST(&(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), &(yyvsp[-6].reg), (yyvsp[-1].modcodes).x0, 0);
+ }
+ else
+ {
+ notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-2].reg), &(yyvsp[-6].reg), &(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), 0);
+ }
+ }
+#line 5762 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 187:
+#line 3189 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-7].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-3].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
+ (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 1, (yyvsp[0].r0).r0, 0);
+ }
+#line 5776 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 188:
+#line 3200 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-8].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-4].reg)) || !IS_PREG ((yyvsp[-2].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[-8].reg), &(yyvsp[-2].reg), 3, (yyvsp[0].r0).r0);
+ }
+#line 5790 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 189:
+#line 3211 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-7].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-3].reg)) || !IS_PREG ((yyvsp[-1].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-7].reg), &(yyvsp[-1].reg), 1 + IS_H ((yyvsp[-7].reg)), 0);
+ }
+#line 5804 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 190:
+#line 3222 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_IREG ((yyvsp[-4].reg)) && !IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Ireg or Preg expected in address");
+ else if (IS_IREG ((yyvsp[-4].reg)) && !IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+ else if (IS_PREG ((yyvsp[-4].reg)) && !IS_DREG ((yyvsp[0].reg)) && !IS_PREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg or Preg expected for source operand");
+
+ if (IS_IREG ((yyvsp[-4].reg)))
+ {
+ notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
+ (yyval.instr) = DSPLDST(&(yyvsp[-4].reg), 0, &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
+ }
+ else if (IS_DREG ((yyvsp[0].reg)))
+ {
+ notethat ("LDST: [ pregs <post_op> ] = dregs\n");
+ (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 0, 1);
+ }
+ else
+ {
+ notethat ("LDST: [ pregs <post_op> ] = pregs\n");
+ (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 1, 1);
+ }
+ }
+#line 5833 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 191:
+#line 3248 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+
+ if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
+ {
+ notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
+ (yyval.instr) = DSPLDST(&(yyvsp[-5].reg), (yyvsp[-3].reg).regno & CODE_MASK, &(yyvsp[0].reg), 3, 1);
+ }
+ else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 0, 1);
+ }
+ else
+ return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
+ }
+#line 5855 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 192:
+#line 3267 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dreg expected for source operand");
+
+ if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+ {
+ notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
+ }
+ else
+ return yyerror ("Preg ++ Preg expected in address");
+ }
+#line 5872 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 193:
+#line 3281 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-2].expr);
+ if (!IS_DREG ((yyvsp[-8].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-4].reg)))
+ return yyerror ("Preg expected in address");
+
+ if ((yyvsp[-3].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (IS_RELOC ((yyvsp[-2].expr)))
+ return yyerror ("Plain symbol used as offset");
+
+ if (in_range_p (tmp, -32768, 32767, 0))
+ {
+ notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
+ (yyvsp[0].r0).r0 ? 'X' : 'Z');
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 2, (yyvsp[0].r0).r0, tmp);
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5899 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 194:
+#line 3305 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-7].reg)))
+ return yyerror ("Dreg expected for destination operand");
+ if (!IS_PREG ((yyvsp[-3].reg)))
+ return yyerror ("Preg expected in address");
+
+ notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
+ (yyvsp[0].r0).r0 ? 'X' : 'Z');
+ (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 2, (yyvsp[0].r0).r0, 0);
+ }
+#line 5914 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 195:
+#line 3317 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-6].reg)))
+ return yyerror ("Dreg expected for destination operand");
+
+ if (IS_IREG ((yyvsp[-3].reg)) && IS_MREG ((yyvsp[-1].reg)))
+ {
+ notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
+ (yyval.instr) = DSPLDST(&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, &(yyvsp[-6].reg), 3, 0);
+ }
+ else if (IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)))
+ {
+ notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
+ (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-6].reg), &(yyvsp[-1].reg), 0, 0);
+ }
+ else
+ return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
+ }
+#line 5936 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 196:
+#line 3336 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node *tmp = (yyvsp[-1].expr);
+ int ispreg = IS_PREG ((yyvsp[-6].reg));
+ int isgot = IS_RELOC((yyvsp[-1].expr));
+
+ if (!IS_PREG ((yyvsp[-3].reg)))
+ return yyerror ("Preg expected in address");
+
+ if (!IS_DREG ((yyvsp[-6].reg)) && !ispreg)
+ return yyerror ("Dreg or Preg expected for destination operand");
+
+ if (tmp->type == Expr_Node_Reloc
+ && strcmp (tmp->value.s_value,
+ "_current_shared_library_p5_offset_") != 0)
+ return yyerror ("Plain symbol used as offset");
+
+ if ((yyvsp[-2].r0).r0)
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+
+ if (isgot)
+ {
+ notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1 : 0, tmp);
+ }
+ else if (in_range_p (tmp, 0, 63, 3))
+ {
+ notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
+ (yyval.instr) = LDSTII (&(yyvsp[-3].reg), &(yyvsp[-6].reg), tmp, 0, ispreg ? 3 : 0);
+ }
+ else if ((yyvsp[-3].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+ {
+ notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+ tmp = unary (Expr_Op_Type_NEG, tmp);
+ (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[-6].reg), 0);
+ }
+ else if (in_range_p (tmp, -131072, 131071, 3))
+ {
+ notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
+ (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1 : 0, tmp);
+
+ }
+ else
+ return yyerror ("Displacement out of range");
+ }
+#line 5985 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 197:
+#line 3382 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_IREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)))
+ return yyerror ("Ireg or Preg expected in address");
+ else if (IS_IREG ((yyvsp[-2].reg)) && !IS_DREG ((yyvsp[-5].reg)))
+ return yyerror ("Dreg expected in destination operand");
+ else if (IS_PREG ((yyvsp[-2].reg)) && !IS_DREG ((yyvsp[-5].reg)) && !IS_PREG ((yyvsp[-5].reg))
+ && ((yyvsp[-2].reg).regno != REG_SP || !IS_ALLREG ((yyvsp[-5].reg)) || (yyvsp[-1].modcodes).x0 != 0))
+ return yyerror ("Dreg or Preg expected in destination operand");
+
+ if (IS_IREG ((yyvsp[-2].reg)))
+ {
+ notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
+ (yyval.instr) = DSPLDST (&(yyvsp[-2].reg), 0, &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0);
+ }
+ else if (IS_DREG ((yyvsp[-5].reg)))
+ {
+ notethat ("LDST: dregs = [ pregs <post_op> ]\n");
+ (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 0, 0);
+ }
+ else if (IS_PREG ((yyvsp[-5].reg)))
+ {
+ if (REG_SAME ((yyvsp[-5].reg), (yyvsp[-2].reg)) && (yyvsp[-1].modcodes).x0 != 2)
+ return yyerror ("Pregs can't be same");
+
+ notethat ("LDST: pregs = [ pregs <post_op> ]\n");
+ (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 1, 0);
+ }
+ else
+ {
+ notethat ("PushPopReg: allregs = [ SP ++ ]\n");
+ (yyval.instr) = PUSHPOPREG (&(yyvsp[-5].reg), 0);
+ }
+ }
+#line 6023 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 198:
+#line 3419 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-10].reg).regno != REG_SP)
+ yyerror ("Stack Pointer expected");
+ if ((yyvsp[-7].reg).regno == REG_R7
+ && IN_RANGE ((yyvsp[-5].expr), 0, 7)
+ && (yyvsp[-3].reg).regno == REG_P5
+ && IN_RANGE ((yyvsp[-1].expr), 0, 5))
+ {
+ notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-5].expr)), imm5 ((yyvsp[-1].expr)), 1, 1, 1);
+ }
+ else
+ return yyerror ("Bad register for PushPopMultiple");
+ }
+#line 6042 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 199:
+#line 3435 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-6].reg).regno != REG_SP)
+ yyerror ("Stack Pointer expected");
+
+ if ((yyvsp[-3].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-1].expr), 0, 7))
+ {
+ notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-1].expr)), 0, 1, 0, 1);
+ }
+ else if ((yyvsp[-3].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-1].expr), 0, 6))
+ {
+ notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-1].expr)), 0, 1, 1);
+ }
+ else
+ return yyerror ("Bad register for PushPopMultiple");
+ }
+#line 6064 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 200:
+#line 3454 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[0].reg).regno != REG_SP)
+ yyerror ("Stack Pointer expected");
+ if ((yyvsp[-9].reg).regno == REG_R7 && (IN_RANGE ((yyvsp[-7].expr), 0, 7))
+ && (yyvsp[-5].reg).regno == REG_P5 && (IN_RANGE ((yyvsp[-3].expr), 0, 6)))
+ {
+ notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-7].expr)), imm5 ((yyvsp[-3].expr)), 1, 1, 0);
+ }
+ else
+ return yyerror ("Bad register range for PushPopMultiple");
+ }
+#line 6081 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 201:
+#line 3468 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[0].reg).regno != REG_SP)
+ yyerror ("Stack Pointer expected");
+
+ if ((yyvsp[-5].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-3].expr), 0, 7))
+ {
+ notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-3].expr)), 0, 1, 0, 0);
+ }
+ else if ((yyvsp[-5].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-3].expr), 0, 6))
+ {
+ notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
+ (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-3].expr)), 0, 1, 0);
+ }
+ else
+ return yyerror ("Bad register range for PushPopMultiple");
+ }
+#line 6103 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 202:
+#line 3487 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].reg).regno != REG_SP)
+ yyerror ("Stack Pointer expected");
+
+ if (IS_ALLREG ((yyvsp[0].reg)))
+ {
+ notethat ("PushPopReg: [ -- SP ] = allregs\n");
+ (yyval.instr) = PUSHPOPREG (&(yyvsp[0].reg), 1);
+ }
+ else
+ return yyerror ("Bad register for PushPopReg");
+ }
+#line 6120 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 203:
+#line 3503 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_URANGE (16, (yyvsp[0].expr), 0, 4))
+ (yyval.instr) = LINKAGE (0, uimm16s4 ((yyvsp[0].expr)));
+ else
+ return yyerror ("Bad constant for LINK");
+ }
+#line 6131 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 204:
+#line 3511 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("linkage: UNLINK\n");
+ (yyval.instr) = LINKAGE (1, 0);
+ }
+#line 6140 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 205:
+#line 3520 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL4 ((yyvsp[-4].expr)) && IS_LPPCREL10 ((yyvsp[-2].expr)) && IS_CREG ((yyvsp[0].reg)))
+ {
+ notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
+ (yyval.instr) = LOOPSETUP ((yyvsp[-4].expr), &(yyvsp[0].reg), 0, (yyvsp[-2].expr), 0);
+ }
+ else
+ return yyerror ("Bad register or values for LSETUP");
+
+ }
+#line 6155 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 206:
+#line 3531 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL4 ((yyvsp[-6].expr)) && IS_LPPCREL10 ((yyvsp[-4].expr))
+ && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
+ {
+ notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
+ (yyval.instr) = LOOPSETUP ((yyvsp[-6].expr), &(yyvsp[-2].reg), 1, (yyvsp[-4].expr), &(yyvsp[0].reg));
+ }
+ else
+ return yyerror ("Bad register or values for LSETUP");
+ }
+#line 6170 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 207:
+#line 3543 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_PCREL4 ((yyvsp[-8].expr)) && IS_LPPCREL10 ((yyvsp[-6].expr))
+ && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg))
+ && EXPR_VALUE ((yyvsp[0].expr)) == 1)
+ {
+ notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
+ (yyval.instr) = LOOPSETUP ((yyvsp[-8].expr), &(yyvsp[-4].reg), 3, (yyvsp[-6].expr), &(yyvsp[-2].reg));
+ }
+ else
+ return yyerror ("Bad register or values for LSETUP");
+ }
+#line 6186 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 208:
+#line 3557 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_RELOC ((yyvsp[-1].expr)))
+ return yyerror ("Invalid expression in loop statement");
+ if (!IS_CREG ((yyvsp[0].reg)))
+ return yyerror ("Invalid loop counter register");
+ (yyval.instr) = bfin_gen_loop ((yyvsp[-1].expr), &(yyvsp[0].reg), 0, 0);
+ }
+#line 6198 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 209:
+#line 3565 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_RELOC ((yyvsp[-3].expr)) && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
+ {
+ notethat ("Loop: LOOP expr counters = pregs\n");
+ (yyval.instr) = bfin_gen_loop ((yyvsp[-3].expr), &(yyvsp[-2].reg), 1, &(yyvsp[0].reg));
+ }
+ else
+ return yyerror ("Bad register or values for LOOP");
+ }
+#line 6212 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 210:
+#line 3575 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_RELOC ((yyvsp[-5].expr)) && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 1)
+ {
+ notethat ("Loop: LOOP expr counters = pregs >> 1\n");
+ (yyval.instr) = bfin_gen_loop ((yyvsp[-5].expr), &(yyvsp[-4].reg), 3, &(yyvsp[-2].reg));
+ }
+ else
+ return yyerror ("Bad register or values for LOOP");
+ }
+#line 6226 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 211:
+#line 3587 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node_Value val;
+ val.i_value = (yyvsp[0].value);
+ Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
+ bfin_loop_attempt_create_label (tmp, 1);
+ if (!IS_RELOC (tmp))
+ return yyerror ("Invalid expression in LOOP_BEGIN statement");
+ bfin_loop_beginend (tmp, 1);
+ (yyval.instr) = 0;
+ }
+#line 6241 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 212:
+#line 3598 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_RELOC ((yyvsp[0].expr)))
+ return yyerror ("Invalid expression in LOOP_BEGIN statement");
+
+ bfin_loop_beginend ((yyvsp[0].expr), 1);
+ (yyval.instr) = 0;
+ }
+#line 6253 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 213:
+#line 3608 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node_Value val;
+ val.i_value = (yyvsp[0].value);
+ Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
+ bfin_loop_attempt_create_label (tmp, 1);
+ if (!IS_RELOC (tmp))
+ return yyerror ("Invalid expression in LOOP_END statement");
+ bfin_loop_beginend (tmp, 0);
+ (yyval.instr) = 0;
+ }
+#line 6268 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 214:
+#line 3619 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_RELOC ((yyvsp[0].expr)))
+ return yyerror ("Invalid expression in LOOP_END statement");
+
+ bfin_loop_beginend ((yyvsp[0].expr), 0);
+ (yyval.instr) = 0;
+ }
+#line 6280 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 215:
+#line 3630 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("psedoDEBUG: ABORT\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, 3, 0);
+ }
+#line 6289 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 216:
+#line 3636 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("pseudoDEBUG: DBG\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, 7, 0);
+ }
+#line 6298 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 217:
+#line 3641 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("pseudoDEBUG: DBG REG_A\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, IS_A1 ((yyvsp[0].reg)), 0);
+ }
+#line 6307 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 218:
+#line 3646 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("pseudoDEBUG: DBG allregs\n");
+ (yyval.instr) = bfin_gen_pseudodbg (0, (yyvsp[0].reg).regno & CODE_MASK, ((yyvsp[0].reg).regno & CLASS_MASK) >> 4);
+ }
+#line 6316 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 219:
+#line 3652 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[-1].reg)))
+ return yyerror ("Dregs expected");
+ notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, 6, ((yyvsp[-1].reg).regno & CODE_MASK) >> 4);
+ }
+#line 6327 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 220:
+#line 3660 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("psedoDEBUG: DBGHALT\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, 5, 0);
+ }
+#line 6336 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 221:
+#line 3666 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("psedoDEBUG: HLT\n");
+ (yyval.instr) = bfin_gen_pseudodbg (3, 4, 0);
+ }
+#line 6345 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 222:
+#line 3672 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
+ (yyval.instr) = bfin_gen_pseudodbg_assert (IS_H ((yyvsp[-3].reg)), &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+ }
+#line 6354 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 223:
+#line 3678 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
+ (yyval.instr) = bfin_gen_pseudodbg_assert (3, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+ }
+#line 6363 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 224:
+#line 3684 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
+ (yyval.instr) = bfin_gen_pseudodbg_assert (2, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+ }
+#line 6372 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 225:
+#line 3690 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_UIMM ((yyvsp[0].expr), 8))
+ return yyerror ("Constant out of range");
+ notethat ("psedodbg_assert: OUTC uimm8\n");
+ (yyval.instr) = bfin_gen_pseudochr (uimm8 ((yyvsp[0].expr)));
+ }
+#line 6383 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 226:
+#line 3698 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (!IS_DREG ((yyvsp[0].reg)))
+ return yyerror ("Dregs expected");
+ notethat ("psedodbg_assert: OUTC dreg\n");
+ (yyval.instr) = bfin_gen_pseudodbg (2, (yyvsp[0].reg).regno & CODE_MASK, 0);
+ }
+#line 6394 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 227:
+#line 3712 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[0].reg);
+ }
+#line 6402 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 228:
+#line 3716 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[0].reg);
+ }
+#line 6410 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 229:
+#line 3725 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mod).MM = 0;
+ (yyval.mod).mod = 0;
+ }
+#line 6419 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 230:
+#line 3730 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mod).MM = 1;
+ (yyval.mod).mod = (yyvsp[-1].value);
+ }
+#line 6428 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 231:
+#line 3735 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mod).MM = 1;
+ (yyval.mod).mod = (yyvsp[-3].value);
+ }
+#line 6437 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 232:
+#line 3740 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mod).MM = 0;
+ (yyval.mod).mod = (yyvsp[-1].value);
+ }
+#line 6446 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 233:
+#line 3745 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mod).MM = 1;
+ (yyval.mod).mod = 0;
+ }
+#line 6455 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 234:
+#line 3752 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6463 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 235:
+#line 3756 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6471 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 236:
+#line 3762 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ }
+#line 6480 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 237:
+#line 3767 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1;
+ (yyval.modcodes).x0 = 0;
+ }
+#line 6489 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 238:
+#line 3772 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 1;
+ }
+#line 6498 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 239:
+#line 3777 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1;
+ (yyval.modcodes).x0 = 1;
+ }
+#line 6507 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 240:
+#line 3785 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6515 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 241:
+#line 3789 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6523 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 242:
+#line 3795 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ }
+#line 6532 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 243:
+#line 3800 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+ (yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+ }
+#line 6541 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 244:
+#line 3807 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ (yyval.modcodes).aop = 0;
+ }
+#line 6551 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 245:
+#line 3813 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ (yyval.modcodes).aop = 1;
+ }
+#line 6561 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 246:
+#line 3819 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1;
+ (yyval.modcodes).x0 = 0;
+ (yyval.modcodes).aop = 1;
+ }
+#line 6571 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 247:
+#line 3827 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ }
+#line 6581 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 248:
+#line 3833 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).x0 = 0;
+ }
+#line 6591 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 249:
+#line 3839 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+ (yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+ }
+#line 6601 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 250:
+#line 3845 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 2 + (yyvsp[-3].r0).r0;
+ (yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+ (yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+ }
+#line 6611 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 251:
+#line 3851 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = (yyvsp[-3].modcodes).s0;
+ (yyval.modcodes).x0 = (yyvsp[-3].modcodes).x0;
+ }
+#line 6621 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 252:
+#line 3859 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6629 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 253:
+#line 3863 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6637 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 254:
+#line 3867 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6645 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 255:
+#line 3873 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6653 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 256:
+#line 3877 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6661 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 257:
+#line 3881 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6669 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 258:
+#line 3887 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).aop = 0;
+ }
+#line 6679 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 259:
+#line 3893 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).aop = 3;
+ }
+#line 6689 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 260:
+#line 3899 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = 1;
+ (yyval.modcodes).aop = 3;
+ }
+#line 6699 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 261:
+#line 3905 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 0;
+ (yyval.modcodes).aop = 3;
+ }
+#line 6709 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 262:
+#line 3911 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6718 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 263:
+#line 3916 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6727 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 264:
+#line 3923 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6735 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 265:
+#line 3927 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6743 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 266:
+#line 3933 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0;
+ }
+#line 6751 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 267:
+#line 3937 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6759 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 268:
+#line 3944 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6767 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 269:
+#line 3948 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6775 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 270:
+#line 3952 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 3;
+ }
+#line 6783 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 271:
+#line 3956 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 2;
+ }
+#line 6791 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 272:
+#line 3962 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6799 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 273:
+#line 3966 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6807 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 274:
+#line 3973 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6816 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 275:
+#line 3978 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].value) != M_T)
+ return yyerror ("Bad modifier");
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 0;
+ }
+#line 6827 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 276:
+#line 3985 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-3].value) != M_T)
+ return yyerror ("Bad modifier");
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6838 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 277:
+#line 3992 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].value) != M_T)
+ return yyerror ("Bad modifier");
+ (yyval.modcodes).r0 = 1;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 6849 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 278:
+#line 4004 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6857 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 279:
+#line 4008 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6865 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 280:
+#line 4012 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 2;
+ }
+#line 6873 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 281:
+#line 4018 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6881 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 282:
+#line 4022 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].value) == M_W32)
+ (yyval.r0).r0 = 1;
+ else
+ return yyerror ("Only (W32) allowed");
+ }
+#line 6892 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 283:
+#line 4031 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6900 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 284:
+#line 4035 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].value) == M_IU)
+ (yyval.r0).r0 = 3;
+ else
+ return yyerror ("(IU) expected");
+ }
+#line 6911 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 285:
+#line 4044 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[-1].reg);
+ }
+#line 6919 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 286:
+#line 4050 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[-2].reg);
+ }
+#line 6927 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 287:
+#line 4059 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6935 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 288:
+#line 4063 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6943 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 289:
+#line 4070 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6951 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 290:
+#line 4074 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6959 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 291:
+#line 4078 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 2;
+ }
+#line 6967 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 292:
+#line 4082 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 3;
+ }
+#line 6975 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 293:
+#line 4089 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 6983 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 294:
+#line 4093 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 6991 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 295:
+#line 4100 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1; /* HL. */
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 0; /* aop. */
+ }
+#line 7002 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 296:
+#line 4108 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1; /* HL. */
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 1; /* aop. */
+ }
+#line 7013 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 297:
+#line 4116 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0; /* HL. */
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 0; /* aop. */
+ }
+#line 7024 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 298:
+#line 4124 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0; /* HL. */
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 1;
+ }
+#line 7035 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 299:
+#line 4132 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1; /* HL. */
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 0; /* aop. */
+ }
+#line 7046 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 300:
+#line 4139 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 1; /* HL. */
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 1; /* aop. */
+ }
+#line 7057 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 301:
+#line 4146 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0; /* HL. */
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 0; /* aop. */
+ }
+#line 7068 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 302:
+#line 4154 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0; /* HL. */
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 0; /* x. */
+ (yyval.modcodes).aop = 1; /* aop. */
+ }
+#line 7079 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 303:
+#line 4164 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 0; /* HL. */
+ }
+#line 7088 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 304:
+#line 4169 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 0; /* s. */
+ (yyval.modcodes).x0 = 1; /* HL. */
+ }
+#line 7097 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 305:
+#line 4174 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 0; /* HL. */
+ }
+#line 7106 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 306:
+#line 4179 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).s0 = 1; /* s. */
+ (yyval.modcodes).x0 = 1; /* HL. */
+ }
+#line 7115 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 307:
+#line 4186 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).x0 = 2;
+ }
+#line 7123 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 308:
+#line 4190 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).x0 = 0;
+ }
+#line 7131 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 309:
+#line 4194 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).x0 = 1;
+ }
+#line 7139 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 310:
+#line 4203 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[-1].reg);
+ }
+#line 7147 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 311:
+#line 4210 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[-1].reg);
+ }
+#line 7155 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 312:
+#line 4217 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[-1].reg);
+ }
+#line 7163 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 313:
+#line 4224 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_A1 ((yyvsp[0].reg)) && IS_EVEN ((yyvsp[-2].reg)))
+ return yyerror ("Cannot move A1 to even register");
+ else if (!IS_A1 ((yyvsp[0].reg)) && !IS_EVEN ((yyvsp[-2].reg)))
+ return yyerror ("Cannot move A0 to odd register");
+
+ (yyval.macfunc).w = 1;
+ (yyval.macfunc).P = 1;
+ (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
+ (yyval.macfunc).op = 3;
+ (yyval.macfunc).dst = (yyvsp[-2].reg);
+ (yyval.macfunc).s0.regno = 0;
+ (yyval.macfunc).s1.regno = 0;
+ }
+#line 7182 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 314:
+#line 4239 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.macfunc) = (yyvsp[0].macfunc);
+ (yyval.macfunc).w = 0; (yyval.macfunc).P = 0;
+ (yyval.macfunc).dst.regno = 0;
+ }
+#line 7192 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 315:
+#line 4245 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].macfunc).n && IS_EVEN ((yyvsp[-4].reg)))
+ return yyerror ("Cannot move A1 to even register");
+ else if (!(yyvsp[-1].macfunc).n && !IS_EVEN ((yyvsp[-4].reg)))
+ return yyerror ("Cannot move A0 to odd register");
+
+ (yyval.macfunc) = (yyvsp[-1].macfunc);
+ (yyval.macfunc).w = 1;
+ (yyval.macfunc).P = 1;
+ (yyval.macfunc).dst = (yyvsp[-4].reg);
+ }
+#line 7208 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 316:
+#line 4258 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-1].macfunc).n && !IS_H ((yyvsp[-4].reg)))
+ return yyerror ("Cannot move A1 to low half of register");
+ else if (!(yyvsp[-1].macfunc).n && IS_H ((yyvsp[-4].reg)))
+ return yyerror ("Cannot move A0 to high half of register");
+
+ (yyval.macfunc) = (yyvsp[-1].macfunc);
+ (yyval.macfunc).w = 1;
+ (yyval.macfunc).P = 0;
+ (yyval.macfunc).dst = (yyvsp[-4].reg);
+ }
+#line 7224 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 317:
+#line 4271 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_A1 ((yyvsp[0].reg)) && !IS_H ((yyvsp[-2].reg)))
+ return yyerror ("Cannot move A1 to low half of register");
+ else if (!IS_A1 ((yyvsp[0].reg)) && IS_H ((yyvsp[-2].reg)))
+ return yyerror ("Cannot move A0 to high half of register");
+
+ (yyval.macfunc).w = 1;
+ (yyval.macfunc).P = 0;
+ (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
+ (yyval.macfunc).op = 3;
+ (yyval.macfunc).dst = (yyvsp[-2].reg);
+ (yyval.macfunc).s0.regno = 0;
+ (yyval.macfunc).s1.regno = 0;
+ }
+#line 7243 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 318:
+#line 4289 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+ (yyval.macfunc).op = 0;
+ (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+ (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+ }
+#line 7254 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 319:
+#line 4296 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+ (yyval.macfunc).op = 1;
+ (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+ (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+ }
+#line 7265 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 320:
+#line 4303 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+ (yyval.macfunc).op = 2;
+ (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+ (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+ }
+#line 7276 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 321:
+#line 4313 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+ {
+ (yyval.macfunc).s0 = (yyvsp[-2].reg);
+ (yyval.macfunc).s1 = (yyvsp[0].reg);
+ }
+ else
+ return yyerror ("Dregs expected");
+ }
+#line 7290 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 322:
+#line 4326 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 0;
+ }
+#line 7298 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 323:
+#line 4330 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 1;
+ }
+#line 7306 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 324:
+#line 4334 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 2;
+ }
+#line 7314 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 325:
+#line 4338 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.r0).r0 = 3;
+ }
+#line 7322 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 326:
+#line 4345 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = (yyvsp[0].reg).regno;
+ (yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = 0;
+ }
+#line 7332 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 327:
+#line 4351 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0x18;
+ (yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = 0;
+ }
+#line 7342 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 328:
+#line 4357 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = (yyvsp[-2].reg).regno;
+ (yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 7352 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 329:
+#line 4363 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.modcodes).r0 = 0x18;
+ (yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+ (yyval.modcodes).s0 = 1;
+ }
+#line 7362 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 330:
+#line 4373 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node_Value val;
+ val.s_value = S_GET_NAME((yyvsp[0].symbol));
+ (yyval.expr) = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
+ }
+#line 7372 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 331:
+#line 4382 "./config/bfin-parse.y" /* yacc.c:1661 */
+ { (yyval.value) = BFD_RELOC_BFIN_GOT; }
+#line 7378 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 332:
+#line 4384 "./config/bfin-parse.y" /* yacc.c:1661 */
+ { (yyval.value) = BFD_RELOC_BFIN_GOT17M4; }
+#line 7384 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 333:
+#line 4386 "./config/bfin-parse.y" /* yacc.c:1661 */
+ { (yyval.value) = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
+#line 7390 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 334:
+#line 4390 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node_Value val;
+ val.i_value = (yyvsp[0].value);
+ (yyval.expr) = Expr_Node_Create (Expr_Node_GOT_Reloc, val, (yyvsp[-2].expr), NULL);
+ }
+#line 7400 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 335:
+#line 4398 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[0].expr);
+ }
+#line 7408 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 336:
+#line 4402 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[0].expr);
+ }
+#line 7416 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 337:
+#line 4409 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[-2].expr);
+ }
+#line 7424 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 338:
+#line 4415 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ Expr_Node_Value val;
+ val.i_value = (yyvsp[0].value);
+ (yyval.expr) = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
+ }
+#line 7434 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 339:
+#line 4421 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[0].expr);
+ }
+#line 7442 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 340:
+#line 4425 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[-1].expr);
+ }
+#line 7450 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 341:
+#line 4429 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = unary (Expr_Op_Type_COMP, (yyvsp[0].expr));
+ }
+#line 7458 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 342:
+#line 4433 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = unary (Expr_Op_Type_NEG, (yyvsp[0].expr));
+ }
+#line 7466 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 343:
+#line 4439 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[0].expr);
+ }
+#line 7474 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 344:
+#line 4445 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Mult, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7482 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 345:
+#line 4449 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Div, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7490 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 346:
+#line 4453 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Mod, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7498 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 347:
+#line 4457 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Add, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7506 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 348:
+#line 4461 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Sub, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7514 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 349:
+#line 4465 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Lshift, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7522 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 350:
+#line 4469 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_Rshift, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7530 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 351:
+#line 4473 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_BAND, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7538 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 352:
+#line 4477 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_LOR, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7546 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 353:
+#line 4481 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = binary (Expr_Op_Type_BOR, (yyvsp[-2].expr), (yyvsp[0].expr));
+ }
+#line 7554 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 354:
+#line 4485 "./config/bfin-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.expr) = (yyvsp[0].expr);
+ }
+#line 7562 "bfin-parse.c" /* yacc.c:1661 */
+ break;
+
+
+#line 7566 "bfin-parse.c" /* yacc.c:1661 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+ that yytoken be updated with the new translation. We take the
+ approach of translating immediately before every use of yytoken.
+ One alternative is translating here after every semantic action,
+ but that translation would be missed if the semantic action invokes
+ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
+ incorrect destructor might then be invoked immediately. In the
+ case of YYERROR or YYBACKUP, subsequent parser actions might lead
+ to an incorrect destructor call or verbose syntax error message
+ before the lookahead is translated. */
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error. |
+`--------------------------------------*/
+yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+ yyssp, yytoken)
+ {
+ char const *yymsgp = YY_("syntax error");
+ int yysyntax_error_status;
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ if (yysyntax_error_status == 0)
+ yymsgp = yymsg;
+ else if (yysyntax_error_status == 1)
+ {
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+ if (!yymsg)
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ yysyntax_error_status = 2;
+ }
+ else
+ {
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ yymsgp = yymsg;
+ }
+ }
+ yyerror (yymsgp);
+ if (yysyntax_error_status == 2)
+ goto yyexhaustedlab;
+ }
+# undef YYSYNTAX_ERROR
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEMPTY)
+ {
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ }
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ return yyresult;
+}
+#line 4491 "./config/bfin-parse.y" /* yacc.c:1906 */
+
+
+EXPR_T
+mkexpr (int x, SYMBOL_T s)
+{
+ EXPR_T e = XNEW (struct expression_cell);
+ e->value = x;
+ EXPR_SYMBOL(e) = s;
+ return e;
+}
+
+static int
+value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
+{
+ int umax = (1 << sz) - 1;
+ int min = -(1 << (sz - 1));
+ int max = (1 << (sz - 1)) - 1;
+
+ int v = (EXPR_VALUE (exp)) & 0xffffffff;
+
+ if ((v % mul) != 0)
+ {
+ error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
+ return 0;
+ }
+
+ v /= mul;
+
+ if (sign)
+ v = -v;
+
+ if (issigned)
+ {
+ if (v >= min && v <= max) return 1;
+
+#ifdef DEBUG
+ fprintf(stderr, "signed value %lx out of range\n", v * mul);
+#endif
+ return 0;
+ }
+ if (v <= umax && v >= 0)
+ return 1;
+#ifdef DEBUG
+ fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
+#endif
+ return 0;
+}
+
+/* Return the expression structure that allows symbol operations.
+ If the left and right children are constants, do the operation. */
+static Expr_Node *
+binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
+{
+ Expr_Node_Value val;
+
+ if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
+ {
+ switch (op)
+ {
+ case Expr_Op_Type_Add:
+ x->value.i_value += y->value.i_value;
+ break;
+ case Expr_Op_Type_Sub:
+ x->value.i_value -= y->value.i_value;
+ break;
+ case Expr_Op_Type_Mult:
+ x->value.i_value *= y->value.i_value;
+ break;
+ case Expr_Op_Type_Div:
+ if (y->value.i_value == 0)
+ error ("Illegal Expression: Division by zero.");
+ else
+ x->value.i_value /= y->value.i_value;
+ break;
+ case Expr_Op_Type_Mod:
+ x->value.i_value %= y->value.i_value;
+ break;
+ case Expr_Op_Type_Lshift:
+ x->value.i_value <<= y->value.i_value;
+ break;
+ case Expr_Op_Type_Rshift:
+ x->value.i_value >>= y->value.i_value;
+ break;
+ case Expr_Op_Type_BAND:
+ x->value.i_value &= y->value.i_value;
+ break;
+ case Expr_Op_Type_BOR:
+ x->value.i_value |= y->value.i_value;
+ break;
+ case Expr_Op_Type_BXOR:
+ x->value.i_value ^= y->value.i_value;
+ break;
+ case Expr_Op_Type_LAND:
+ x->value.i_value = x->value.i_value && y->value.i_value;
+ break;
+ case Expr_Op_Type_LOR:
+ x->value.i_value = x->value.i_value || y->value.i_value;
+ break;
+
+ default:
+ error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
+ }
+ return x;
+ }
+ /* Canonicalize order to EXPR OP CONSTANT. */
+ if (x->type == Expr_Node_Constant)
+ {
+ Expr_Node *t = x;
+ x = y;
+ y = t;
+ }
+ /* Canonicalize subtraction of const to addition of negated const. */
+ if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
+ {
+ op = Expr_Op_Type_Add;
+ y->value.i_value = -y->value.i_value;
+ }
+ if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
+ && x->Right_Child->type == Expr_Node_Constant)
+ {
+ if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
+ {
+ x->Right_Child->value.i_value += y->value.i_value;
+ return x;
+ }
+ }
+
+ /* Create a new expression structure. */
+ val.op_value = op;
+ return Expr_Node_Create (Expr_Node_Binop, val, x, y);
+}
+
+static Expr_Node *
+unary (Expr_Op_Type op, Expr_Node *x)
+{
+ if (x->type == Expr_Node_Constant)
+ {
+ switch (op)
+ {
+ case Expr_Op_Type_NEG:
+ x->value.i_value = -x->value.i_value;
+ break;
+ case Expr_Op_Type_COMP:
+ x->value.i_value = ~x->value.i_value;
+ break;
+ default:
+ error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
+ }
+ return x;
+ }
+ else
+ {
+ /* Create a new expression structure. */
+ Expr_Node_Value val;
+ val.op_value = op;
+ return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
+ }
+}
+
+int debug_codeselection = 0;
+static void
+notethat (const char *format, ...)
+{
+ va_list ap;
+ va_start (ap, format);
+ if (debug_codeselection)
+ {
+ vfprintf (errorf, format, ap);
+ }
+ va_end (ap);
+}
+
+#ifdef TEST
+main (int argc, char **argv)
+{
+ yyparse();
+}
+#endif
+
diff --git a/gas/bfin-parse.h b/gas/bfin-parse.h
new file mode 100644
index 0000000..ba649fe
--- /dev/null
+++ b/gas/bfin-parse.h
@@ -0,0 +1,422 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison interface for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+#ifndef YY_YY_BFIN_PARSE_H_INCLUDED
+# define YY_YY_BFIN_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ BYTEOP16P = 258,
+ BYTEOP16M = 259,
+ BYTEOP1P = 260,
+ BYTEOP2P = 261,
+ BYTEOP3P = 262,
+ BYTEUNPACK = 263,
+ BYTEPACK = 264,
+ PACK = 265,
+ SAA = 266,
+ ALIGN8 = 267,
+ ALIGN16 = 268,
+ ALIGN24 = 269,
+ VIT_MAX = 270,
+ EXTRACT = 271,
+ DEPOSIT = 272,
+ EXPADJ = 273,
+ SEARCH = 274,
+ ONES = 275,
+ SIGN = 276,
+ SIGNBITS = 277,
+ LINK = 278,
+ UNLINK = 279,
+ REG = 280,
+ PC = 281,
+ CCREG = 282,
+ BYTE_DREG = 283,
+ REG_A_DOUBLE_ZERO = 284,
+ REG_A_DOUBLE_ONE = 285,
+ A_ZERO_DOT_L = 286,
+ A_ZERO_DOT_H = 287,
+ A_ONE_DOT_L = 288,
+ A_ONE_DOT_H = 289,
+ HALF_REG = 290,
+ NOP = 291,
+ RTI = 292,
+ RTS = 293,
+ RTX = 294,
+ RTN = 295,
+ RTE = 296,
+ HLT = 297,
+ IDLE = 298,
+ STI = 299,
+ CLI = 300,
+ CSYNC = 301,
+ SSYNC = 302,
+ EMUEXCPT = 303,
+ RAISE = 304,
+ EXCPT = 305,
+ LSETUP = 306,
+ LOOP = 307,
+ LOOP_BEGIN = 308,
+ LOOP_END = 309,
+ DISALGNEXCPT = 310,
+ JUMP = 311,
+ JUMP_DOT_S = 312,
+ JUMP_DOT_L = 313,
+ CALL = 314,
+ ABORT = 315,
+ NOT = 316,
+ TILDA = 317,
+ BANG = 318,
+ AMPERSAND = 319,
+ BAR = 320,
+ PERCENT = 321,
+ CARET = 322,
+ BXOR = 323,
+ MINUS = 324,
+ PLUS = 325,
+ STAR = 326,
+ SLASH = 327,
+ NEG = 328,
+ MIN = 329,
+ MAX = 330,
+ ABS = 331,
+ DOUBLE_BAR = 332,
+ _PLUS_BAR_PLUS = 333,
+ _PLUS_BAR_MINUS = 334,
+ _MINUS_BAR_PLUS = 335,
+ _MINUS_BAR_MINUS = 336,
+ _MINUS_MINUS = 337,
+ _PLUS_PLUS = 338,
+ SHIFT = 339,
+ LSHIFT = 340,
+ ASHIFT = 341,
+ BXORSHIFT = 342,
+ _GREATER_GREATER_GREATER_THAN_ASSIGN = 343,
+ ROT = 344,
+ LESS_LESS = 345,
+ GREATER_GREATER = 346,
+ _GREATER_GREATER_GREATER = 347,
+ _LESS_LESS_ASSIGN = 348,
+ _GREATER_GREATER_ASSIGN = 349,
+ DIVS = 350,
+ DIVQ = 351,
+ ASSIGN = 352,
+ _STAR_ASSIGN = 353,
+ _BAR_ASSIGN = 354,
+ _CARET_ASSIGN = 355,
+ _AMPERSAND_ASSIGN = 356,
+ _MINUS_ASSIGN = 357,
+ _PLUS_ASSIGN = 358,
+ _ASSIGN_BANG = 359,
+ _LESS_THAN_ASSIGN = 360,
+ _ASSIGN_ASSIGN = 361,
+ GE = 362,
+ LT = 363,
+ LE = 364,
+ GT = 365,
+ LESS_THAN = 366,
+ FLUSHINV = 367,
+ FLUSH = 368,
+ IFLUSH = 369,
+ PREFETCH = 370,
+ PRNT = 371,
+ OUTC = 372,
+ WHATREG = 373,
+ TESTSET = 374,
+ ASL = 375,
+ ASR = 376,
+ B = 377,
+ W = 378,
+ NS = 379,
+ S = 380,
+ CO = 381,
+ SCO = 382,
+ TH = 383,
+ TL = 384,
+ BP = 385,
+ BREV = 386,
+ X = 387,
+ Z = 388,
+ M = 389,
+ MMOD = 390,
+ R = 391,
+ RND = 392,
+ RNDL = 393,
+ RNDH = 394,
+ RND12 = 395,
+ RND20 = 396,
+ V = 397,
+ LO = 398,
+ HI = 399,
+ BITTGL = 400,
+ BITCLR = 401,
+ BITSET = 402,
+ BITTST = 403,
+ BITMUX = 404,
+ DBGAL = 405,
+ DBGAH = 406,
+ DBGHALT = 407,
+ DBG = 408,
+ DBGA = 409,
+ DBGCMPLX = 410,
+ IF = 411,
+ COMMA = 412,
+ BY = 413,
+ COLON = 414,
+ SEMICOLON = 415,
+ RPAREN = 416,
+ LPAREN = 417,
+ LBRACK = 418,
+ RBRACK = 419,
+ STATUS_REG = 420,
+ MNOP = 421,
+ SYMBOL = 422,
+ NUMBER = 423,
+ GOT = 424,
+ GOT17M4 = 425,
+ FUNCDESC_GOT17M4 = 426,
+ AT = 427,
+ PLTPC = 428
+ };
+#endif
+/* Tokens. */
+#define BYTEOP16P 258
+#define BYTEOP16M 259
+#define BYTEOP1P 260
+#define BYTEOP2P 261
+#define BYTEOP3P 262
+#define BYTEUNPACK 263
+#define BYTEPACK 264
+#define PACK 265
+#define SAA 266
+#define ALIGN8 267
+#define ALIGN16 268
+#define ALIGN24 269
+#define VIT_MAX 270
+#define EXTRACT 271
+#define DEPOSIT 272
+#define EXPADJ 273
+#define SEARCH 274
+#define ONES 275
+#define SIGN 276
+#define SIGNBITS 277
+#define LINK 278
+#define UNLINK 279
+#define REG 280
+#define PC 281
+#define CCREG 282
+#define BYTE_DREG 283
+#define REG_A_DOUBLE_ZERO 284
+#define REG_A_DOUBLE_ONE 285
+#define A_ZERO_DOT_L 286
+#define A_ZERO_DOT_H 287
+#define A_ONE_DOT_L 288
+#define A_ONE_DOT_H 289
+#define HALF_REG 290
+#define NOP 291
+#define RTI 292
+#define RTS 293
+#define RTX 294
+#define RTN 295
+#define RTE 296
+#define HLT 297
+#define IDLE 298
+#define STI 299
+#define CLI 300
+#define CSYNC 301
+#define SSYNC 302
+#define EMUEXCPT 303
+#define RAISE 304
+#define EXCPT 305
+#define LSETUP 306
+#define LOOP 307
+#define LOOP_BEGIN 308
+#define LOOP_END 309
+#define DISALGNEXCPT 310
+#define JUMP 311
+#define JUMP_DOT_S 312
+#define JUMP_DOT_L 313
+#define CALL 314
+#define ABORT 315
+#define NOT 316
+#define TILDA 317
+#define BANG 318
+#define AMPERSAND 319
+#define BAR 320
+#define PERCENT 321
+#define CARET 322
+#define BXOR 323
+#define MINUS 324
+#define PLUS 325
+#define STAR 326
+#define SLASH 327
+#define NEG 328
+#define MIN 329
+#define MAX 330
+#define ABS 331
+#define DOUBLE_BAR 332
+#define _PLUS_BAR_PLUS 333
+#define _PLUS_BAR_MINUS 334
+#define _MINUS_BAR_PLUS 335
+#define _MINUS_BAR_MINUS 336
+#define _MINUS_MINUS 337
+#define _PLUS_PLUS 338
+#define SHIFT 339
+#define LSHIFT 340
+#define ASHIFT 341
+#define BXORSHIFT 342
+#define _GREATER_GREATER_GREATER_THAN_ASSIGN 343
+#define ROT 344
+#define LESS_LESS 345
+#define GREATER_GREATER 346
+#define _GREATER_GREATER_GREATER 347
+#define _LESS_LESS_ASSIGN 348
+#define _GREATER_GREATER_ASSIGN 349
+#define DIVS 350
+#define DIVQ 351
+#define ASSIGN 352
+#define _STAR_ASSIGN 353
+#define _BAR_ASSIGN 354
+#define _CARET_ASSIGN 355
+#define _AMPERSAND_ASSIGN 356
+#define _MINUS_ASSIGN 357
+#define _PLUS_ASSIGN 358
+#define _ASSIGN_BANG 359
+#define _LESS_THAN_ASSIGN 360
+#define _ASSIGN_ASSIGN 361
+#define GE 362
+#define LT 363
+#define LE 364
+#define GT 365
+#define LESS_THAN 366
+#define FLUSHINV 367
+#define FLUSH 368
+#define IFLUSH 369
+#define PREFETCH 370
+#define PRNT 371
+#define OUTC 372
+#define WHATREG 373
+#define TESTSET 374
+#define ASL 375
+#define ASR 376
+#define B 377
+#define W 378
+#define NS 379
+#define S 380
+#define CO 381
+#define SCO 382
+#define TH 383
+#define TL 384
+#define BP 385
+#define BREV 386
+#define X 387
+#define Z 388
+#define M 389
+#define MMOD 390
+#define R 391
+#define RND 392
+#define RNDL 393
+#define RNDH 394
+#define RND12 395
+#define RND20 396
+#define V 397
+#define LO 398
+#define HI 399
+#define BITTGL 400
+#define BITCLR 401
+#define BITSET 402
+#define BITTST 403
+#define BITMUX 404
+#define DBGAL 405
+#define DBGAH 406
+#define DBGHALT 407
+#define DBG 408
+#define DBGA 409
+#define DBGCMPLX 410
+#define IF 411
+#define COMMA 412
+#define BY 413
+#define COLON 414
+#define SEMICOLON 415
+#define RPAREN 416
+#define LPAREN 417
+#define LBRACK 418
+#define RBRACK 419
+#define STATUS_REG 420
+#define MNOP 421
+#define SYMBOL 422
+#define NUMBER 423
+#define GOT 424
+#define GOT17M4 425
+#define FUNCDESC_GOT17M4 426
+#define AT 427
+#define PLTPC 428
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 444 "./config/bfin-parse.y" /* yacc.c:1915 */
+
+ INSTR_T instr;
+ Expr_Node *expr;
+ SYMBOL_T symbol;
+ long value;
+ Register reg;
+ Macfunc macfunc;
+ struct { int r0; int s0; int x0; int aop; } modcodes;
+ struct { int r0; } r0;
+ Opt_mode mod;
+
+#line 412 "bfin-parse.h" /* yacc.c:1915 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_BFIN_PARSE_H_INCLUDED */
diff --git a/gas/configure b/gas/configure
index db24db5..ce7091e 100755
--- a/gas/configure
+++ b/gas/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.64 for gas 2.27.90.
+# Generated by GNU Autoconf 2.64 for gas 2.28.
#
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software
@@ -556,8 +556,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='gas'
PACKAGE_TARNAME='gas'
-PACKAGE_VERSION='2.27.90'
-PACKAGE_STRING='gas 2.27.90'
+PACKAGE_VERSION='2.28'
+PACKAGE_STRING='gas 2.28'
PACKAGE_BUGREPORT=''
PACKAGE_URL=''
@@ -1330,7 +1330,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures gas 2.27.90 to adapt to many kinds of systems.
+\`configure' configures gas 2.28 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1401,7 +1401,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of gas 2.27.90:";;
+ short | recursive ) echo "Configuration of gas 2.28:";;
esac
cat <<\_ACEOF
@@ -1523,7 +1523,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-gas configure 2.27.90
+gas configure 2.28
generated by GNU Autoconf 2.64
Copyright (C) 2009 Free Software Foundation, Inc.
@@ -1933,7 +1933,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by gas $as_me 2.27.90, which was
+It was created by gas $as_me 2.28, which was
generated by GNU Autoconf 2.64. Invocation command line was
$ $0 $@
@@ -3742,7 +3742,7 @@ fi
# Define the identity of the package.
PACKAGE='gas'
- VERSION='2.27.90'
+ VERSION='2.28'
cat >>confdefs.h <<_ACEOF
@@ -15212,7 +15212,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by gas $as_me 2.27.90, which was
+This file was extended by gas $as_me 2.28, which was
generated by GNU Autoconf 2.64. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -15276,7 +15276,7 @@ Report bugs to the package provider."
_ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_version="\\
-gas config.status 2.27.90
+gas config.status 2.28
configured by $0, generated by GNU Autoconf 2.64,
with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
diff --git a/gas/doc/as.1 b/gas/doc/as.1
new file mode 100644
index 0000000..132e8e3
--- /dev/null
+++ b/gas/doc/as.1
@@ -0,0 +1,2073 @@
+.\" Automatically generated by Pod::Man 2.27 (Pod::Simple 3.28)
+.\"
+.\" Standard preamble:
+.\" ========================================================================
+.de Sp \" Vertical space (when we can't use .PP)
+.if t .sp .5v
+.if n .sp
+..
+.de Vb \" Begin verbatim text
+.ft CW
+.nf
+.ne \\$1
+..
+.de Ve \" End verbatim text
+.ft R
+.fi
+..
+.\" Set up some character translations and predefined strings. \*(-- will
+.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
+.\" double quote, and \*(R" will give a right double quote. \*(C+ will
+.\" give a nicer C++. Capital omega is used to do unbreakable dashes and
+.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff,
+.\" nothing in troff, for use with C<>.
+.tr \(*W-
+.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
+.ie n \{\
+. ds -- \(*W-
+. ds PI pi
+. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
+. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
+. ds L" ""
+. ds R" ""
+. ds C` ""
+. ds C' ""
+'br\}
+.el\{\
+. ds -- \|\(em\|
+. ds PI \(*p
+. ds L" ``
+. ds R" ''
+. ds C`
+. ds C'
+'br\}
+.\"
+.\" Escape single quotes in literal strings from groff's Unicode transform.
+.ie \n(.g .ds Aq \(aq
+.el .ds Aq '
+.\"
+.\" If the F register is turned on, we'll generate index entries on stderr for
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
+.\" entries marked with X<> in POD. Of course, you'll have to process the
+.\" output yourself in some meaningful fashion.
+.\"
+.\" Avoid warning from groff about undefined register 'F'.
+.de IX
+..
+.nr rF 0
+.if \n(.g .if rF .nr rF 1
+.if (\n(rF:(\n(.g==0)) \{
+. if \nF \{
+. de IX
+. tm Index:\\$1\t\\n%\t"\\$2"
+..
+. if !\nF==2 \{
+. nr % 0
+. nr F 2
+. \}
+. \}
+.\}
+.rr rF
+.\"
+.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
+.\" Fear. Run. Save yourself. No user-serviceable parts.
+. \" fudge factors for nroff and troff
+.if n \{\
+. ds #H 0
+. ds #V .8m
+. ds #F .3m
+. ds #[ \f1
+. ds #] \fP
+.\}
+.if t \{\
+. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
+. ds #V .6m
+. ds #F 0
+. ds #[ \&
+. ds #] \&
+.\}
+. \" simple accents for nroff and troff
+.if n \{\
+. ds ' \&
+. ds ` \&
+. ds ^ \&
+. ds , \&
+. ds ~ ~
+. ds /
+.\}
+.if t \{\
+. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
+. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
+. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
+. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
+. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
+. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
+.\}
+. \" troff and (daisy-wheel) nroff accents
+.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
+.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
+.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
+.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
+.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
+.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
+.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
+.ds ae a\h'-(\w'a'u*4/10)'e
+.ds Ae A\h'-(\w'A'u*4/10)'E
+. \" corrections for vroff
+.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
+.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
+. \" for low resolution devices (crt and lpr)
+.if \n(.H>23 .if \n(.V>19 \
+\{\
+. ds : e
+. ds 8 ss
+. ds o a
+. ds d- d\h'-1'\(ga
+. ds D- D\h'-1'\(hy
+. ds th \o'bp'
+. ds Th \o'LP'
+. ds ae ae
+. ds Ae AE
+.\}
+.rm #[ #] #H #V #F C
+.\" ========================================================================
+.\"
+.IX Title "AS 1"
+.TH AS 1 "2017-03-02" "binutils-2.28" "GNU Development Tools"
+.\" For nroff, turn off justification. Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.if n .ad l
+.nh
+.SH "NAME"
+AS \- the portable GNU assembler.
+.SH "SYNOPSIS"
+.IX Header "SYNOPSIS"
+as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
+ [\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR]
+ [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
+ [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
+ [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-gdwarf\-sections\fR]
+ [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
+ [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
+ [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
+ [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR]
+ [\fB\-\-no\-pad\-sections\fR]
+ [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR]
+ [\fB\-\-hash\-size\fR=\fI\s-1NUM\s0\fR] [\fB\-\-reduce\-memory\-overheads\fR]
+ [\fB\-\-statistics\fR]
+ [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR]
+ [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR]
+ [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
+ [\fB\-\-sectname\-subst\fR] [\fB\-\-size\-check=[error|warning]\fR]
+ [\fB\-\-elf\-stt\-common=[no|yes]\fR]
+ [\fB\-\-target\-help\fR] [\fItarget-options\fR]
+ [\fB\-\-\fR|\fIfiles\fR ...]
+.SH "TARGET"
+.IX Header "TARGET"
+\&\fITarget AArch64 options:\fR
+ [\fB\-EB\fR|\fB\-EL\fR]
+ [\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
+.PP
+\&\fITarget Alpha options:\fR
+ [\fB\-m\fR\fIcpu\fR]
+ [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
+ [\fB\-replace\fR | \fB\-noreplace\fR]
+ [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
+ [\fB\-F\fR] [\fB\-32addr\fR]
+.PP
+\&\fITarget \s-1ARC\s0 options:\fR
+ [\fB\-mcpu=\fR\fIcpu\fR]
+ [\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
+ [\fB\-mcode\-density\fR]
+ [\fB\-mrelax\fR]
+ [\fB\-EB\fR|\fB\-EL\fR]
+.PP
+\&\fITarget \s-1ARM\s0 options:\fR
+ [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
+ [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
+ [\fB\-mfpu\fR=\fIfloating-point-format\fR]
+ [\fB\-mfloat\-abi\fR=\fIabi\fR]
+ [\fB\-meabi\fR=\fIver\fR]
+ [\fB\-mthumb\fR]
+ [\fB\-EB\fR|\fB\-EL\fR]
+ [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
+ \fB\-mapcs\-reentrant\fR]
+ [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
+.PP
+\&\fITarget Blackfin options:\fR
+ [\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]]
+ [\fB\-mfdpic\fR]
+ [\fB\-mno\-fdpic\fR]
+ [\fB\-mnopic\fR]
+.PP
+\&\fITarget \s-1CRIS\s0 options:\fR
+ [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
+ [\fB\-\-pic\fR] [\fB\-N\fR]
+ [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
+ [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
+.PP
+\&\fITarget D10V options:\fR
+ [\fB\-O\fR]
+.PP
+\&\fITarget D30V options:\fR
+ [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
+.PP
+\&\fITarget \s-1EPIPHANY\s0 options:\fR
+ [\fB\-mepiphany\fR|\fB\-mepiphany16\fR]
+.PP
+\&\fITarget H8/300 options:\fR
+ [\-h\-tick\-hex]
+.PP
+\&\fITarget i386 options:\fR
+ [\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR]
+ [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
+.PP
+\&\fITarget i960 options:\fR
+ [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
+ \fB\-AKC\fR|\fB\-AMC\fR]
+ [\fB\-b\fR] [\fB\-no\-relax\fR]
+.PP
+\&\fITarget \s-1IA\-64\s0 options:\fR
+ [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
+ [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
+ [\fB\-mle\fR|\fBmbe\fR]
+ [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
+ [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
+ [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
+ [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
+.PP
+\&\fITarget \s-1IP2K\s0 options:\fR
+ [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
+.PP
+\&\fITarget M32C options:\fR
+ [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex]
+.PP
+\&\fITarget M32R options:\fR
+ [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
+ \fB\-\-W[n]p\fR]
+.PP
+\&\fITarget M680X0 options:\fR
+ [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
+.PP
+\&\fITarget M68HC11 options:\fR
+ [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
+ [\fB\-mshort\fR|\fB\-mlong\fR]
+ [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
+ [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]
+ [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
+ [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
+.PP
+\&\fITarget \s-1MCORE\s0 options:\fR
+ [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
+ [\fB\-mcpu=[210|340]\fR]
+.PP
+\&\fITarget Meta options:\fR
+ [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR]
+\&\fITarget \s-1MICROBLAZE\s0 options:\fR
+.PP
+\&\fITarget \s-1MIPS\s0 options:\fR
+ [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
+ [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
+ [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]
+ [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
+ [\fB\-mfp64\fR] [\fB\-mgp64\fR] [\fB\-mfpxx\fR]
+ [\fB\-modd\-spreg\fR] [\fB\-mno\-odd\-spreg\fR]
+ [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
+ [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
+ [\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR]
+ [\fB\-mips64r3\fR] [\fB\-mips64r5\fR] [\fB\-mips64r6\fR]
+ [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
+ [\fB\-mignore\-branch\-isa\fR] [\fB\-mno\-ignore\-branch\-isa\fR]
+ [\fB\-mnan=\fR\fIencoding\fR]
+ [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
+ [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
+ [\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR]
+ [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]
+ [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
+ [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
+ [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
+ [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]
+ [\fB\-mdspr3\fR] [\fB\-mno\-dspr3\fR]
+ [\fB\-mmsa\fR] [\fB\-mno\-msa\fR]
+ [\fB\-mxpa\fR] [\fB\-mno\-xpa\fR]
+ [\fB\-mmt\fR] [\fB\-mno\-mt\fR]
+ [\fB\-mmcu\fR] [\fB\-mno\-mcu\fR]
+ [\fB\-minsn32\fR] [\fB\-mno\-insn32\fR]
+ [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
+ [\fB\-mfix\-rm7000\fR] [\fB\-mno\-fix\-rm7000\fR]
+ [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR]
+ [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR]
+ [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
+ [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
+.PP
+\&\fITarget \s-1MMIX\s0 options:\fR
+ [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
+ [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
+ [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
+ [\fB\-\-linker\-allocated\-gregs\fR]
+.PP
+\&\fITarget Nios \s-1II\s0 options:\fR
+ [\fB\-relax\-all\fR] [\fB\-relax\-section\fR] [\fB\-no\-relax\fR]
+ [\fB\-EB\fR] [\fB\-EL\fR]
+.PP
+\&\fITarget \s-1NDS32\s0 options:\fR
+ [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR] [\fB\-mcpu=\fR\fIcpu\fR]
+ [\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR]
+ [\fB\-m[no\-]16\-bit\fR] [\fB\-m[no\-]perf\-ext\fR] [\fB\-m[no\-]perf2\-ext\fR]
+ [\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR] [\fB\-m[no\-]div\fR]
+ [\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR] [\fB\-m[no\-]fpu\-dp\-ext\fR]
+ [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fI\s-1FREG\s0\fR] [\fB\-mreduced\-regs\fR]
+ [\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR] [\fB\-mno\-relax\fR]
+ [\fB\-mb2bb\fR]
+.PP
+\&\fITarget \s-1PDP11\s0 options:\fR
+ [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
+ [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
+ [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
+.PP
+\&\fITarget picoJava options:\fR
+ [\fB\-mb\fR|\fB\-me\fR]
+.PP
+\&\fITarget PowerPC options:\fR
+ [\fB\-a32\fR|\fB\-a64\fR]
+ [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
+ \fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mppc64\fR|
+ \fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|\fB\-me6500\fR|\fB\-mppc64bridge\fR|
+ \fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|\fB\-mpower6\fR|\fB\-mpwr6\fR|
+ \fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
+ \fB\-mcell\fR|\fB\-mspe\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
+ [\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR|\fB\-mhtm\fR|\fB\-mvle\fR]
+ [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
+ [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR]
+ [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
+ [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
+ [\fB\-nops=\fR\fIcount\fR]
+.PP
+\&\fITarget \s-1RL78\s0 options:\fR
+ [\fB\-mg10\fR]
+ [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
+.PP
+\&\fITarget \s-1RX\s0 options:\fR
+ [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR]
+ [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
+ [\fB\-muse\-conventional\-section\-names\fR]
+ [\fB\-msmall\-data\-limit\fR]
+ [\fB\-mpid\fR]
+ [\fB\-mrelax\fR]
+ [\fB\-mint\-register=\fR\fInumber\fR]
+ [\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR]
+.PP
+\&\fITarget RISC-V options:\fR
+ [\fB\-march\fR=\fI\s-1ISA\s0\fR]
+ [\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
+.PP
+\&\fITarget s390 options:\fR
+ [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR]
+ [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
+ [\fB\-mwarn\-areg\-zero\fR]
+.PP
+\&\fITarget \s-1SCORE\s0 options:\fR
+ [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR]
+ [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
+ [\fB\-march=score7\fR][\fB\-march=score3\fR]
+ [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR]
+.PP
+\&\fITarget \s-1SPARC\s0 options:\fR
+ [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
+ \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
+ \fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
+ \fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
+ \fB\-Asparcvis2\fR|\fB\-Asparcfmaf\fR|\fB\-Asparcima\fR|\fB\-Asparcvis3\fR
+ \fB\-Asparcvisr\fR|\fB\-Asparc5\fR]
+ [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
+ \fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
+ \fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
+ \fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
+ \fB\-xarch=sparcvis2\fR|\fB\-xarch=sparcfmaf\fR|\fB\-xarch=sparcima\fR
+ \fB\-xarch=sparcvis3\fR|\fB\-xarch=sparcvisr\fR|\fB\-xarch=sparc5\fR
+ \fB\-bump\fR]
+ [\fB\-32\fR|\fB\-64\fR]
+ [\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR]
+.PP
+\&\fITarget \s-1TIC54X\s0 options:\fR
+ [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]
+ [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
+.PP
+\&\fITarget \s-1TIC6X\s0 options:\fR
+ [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR]
+ [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR]
+ [\fB\-mpic\fR|\fB\-mno\-pic\fR]
+.PP
+\&\fITarget TILE-Gx options:\fR
+ [\fB\-m32\fR|\fB\-m64\fR][\fB\-EB\fR][\fB\-EL\fR]
+.PP
+\&\fITarget Visium options:\fR
+ [\fB\-mtune=\fR\fIarch\fR]
+.PP
+\&\fITarget Xtensa options:\fR
+ [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]auto\-litpools\fR]
+ [\fB\-\-[no\-]absolute\-literals\fR]
+ [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
+ [\fB\-\-[no\-]transform\fR]
+ [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
+ [\fB\-\-[no\-]trampolines\fR]
+.PP
+\&\fITarget Z80 options:\fR
+ [\fB\-z80\fR] [\fB\-r800\fR]
+ [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
+ [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
+ [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
+ [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
+ [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
+ [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
+.SH "DESCRIPTION"
+.IX Header "DESCRIPTION"
+\&\s-1GNU \s0\fBas\fR is really a family of assemblers.
+If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
+should find a fairly similar environment when you use it on another
+architecture. Each version has much in common with the others,
+including object file formats, most assembler directives (often called
+\&\fIpseudo-ops\fR) and assembler syntax.
+.PP
+\&\fBas\fR is primarily intended to assemble the output of the
+\&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
+\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
+assemble correctly everything that other assemblers for the same
+machine would assemble.
+Any exceptions are documented explicitly.
+This doesn't mean \fBas\fR always uses the same syntax as another
+assembler for the same architecture; for example, we know of several
+incompatible versions of 680x0 assembly language syntax.
+.PP
+Each time you run \fBas\fR it assembles exactly one source
+program. The source program is made up of one or more files.
+(The standard input is also a file.)
+.PP
+You give \fBas\fR a command line that has zero or more input file
+names. The input files are read (from left file name to right). A
+command line argument (in any position) that has no special meaning
+is taken to be an input file name.
+.PP
+If you give \fBas\fR no file names it attempts to read one input file
+from the \fBas\fR standard input, which is normally your terminal. You
+may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
+to assemble.
+.PP
+Use \fB\-\-\fR if you need to explicitly name the standard input file
+in your command line.
+.PP
+If the source is empty, \fBas\fR produces a small, empty object
+file.
+.PP
+\&\fBas\fR may write warnings and error messages to the standard error
+file (usually your terminal). This should not happen when a compiler
+runs \fBas\fR automatically. Warnings report an assumption made so
+that \fBas\fR could keep assembling a flawed program; errors report a
+grave problem that stops the assembly.
+.PP
+If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler,
+you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
+The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
+by commas. For example:
+.PP
+.Vb 1
+\& gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
+.Ve
+.PP
+This passes two options to the assembler: \fB\-alh\fR (emit a listing to
+standard output with high-level and assembly source) and \fB\-L\fR (retain
+local symbols in the symbol table).
+.PP
+Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
+command-line options are automatically passed to the assembler by the compiler.
+(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
+precisely what options it passes to each compilation pass, including the
+assembler.)
+.SH "OPTIONS"
+.IX Header "OPTIONS"
+.IP "\fB@\fR\fIfile\fR" 4
+.IX Item "@file"
+Read command-line options from \fIfile\fR. The options read are
+inserted in place of the original @\fIfile\fR option. If \fIfile\fR
+does not exist, or cannot be read, then the option will be treated
+literally, and not removed.
+.Sp
+Options in \fIfile\fR are separated by whitespace. A whitespace
+character may be included in an option by surrounding the entire
+option in either single or double quotes. Any character (including a
+backslash) may be included by prefixing the character to be included
+with a backslash. The \fIfile\fR may itself contain additional
+@\fIfile\fR options; any such options will be processed recursively.
+.IP "\fB\-a[cdghlmns]\fR" 4
+.IX Item "-a[cdghlmns]"
+Turn on listings, in any of a variety of ways:
+.RS 4
+.IP "\fB\-ac\fR" 4
+.IX Item "-ac"
+omit false conditionals
+.IP "\fB\-ad\fR" 4
+.IX Item "-ad"
+omit debugging directives
+.IP "\fB\-ag\fR" 4
+.IX Item "-ag"
+include general information, like as version and options passed
+.IP "\fB\-ah\fR" 4
+.IX Item "-ah"
+include high-level source
+.IP "\fB\-al\fR" 4
+.IX Item "-al"
+include assembly
+.IP "\fB\-am\fR" 4
+.IX Item "-am"
+include macro expansions
+.IP "\fB\-an\fR" 4
+.IX Item "-an"
+omit forms processing
+.IP "\fB\-as\fR" 4
+.IX Item "-as"
+include symbols
+.IP "\fB=file\fR" 4
+.IX Item "=file"
+set the name of the listing file
+.RE
+.RS 4
+.Sp
+You may combine these options; for example, use \fB\-aln\fR for assembly
+listing without forms processing. The \fB=file\fR option, if used, must be
+the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
+.RE
+.IP "\fB\-\-alternate\fR" 4
+.IX Item "--alternate"
+Begin in alternate macro mode.
+.IP "\fB\-\-compress\-debug\-sections\fR" 4
+.IX Item "--compress-debug-sections"
+Compress \s-1DWARF\s0 debug sections using zlib with \s-1SHF_COMPRESSED\s0 from the
+\&\s-1ELF ABI. \s0 The resulting object file may not be compatible with older
+linkers and object file utilities. Note if compression would make a
+given section \fIlarger\fR then it is not compressed.
+.IP "\fB\-\-compress\-debug\-sections=none\fR" 4
+.IX Item "--compress-debug-sections=none"
+.PD 0
+.IP "\fB\-\-compress\-debug\-sections=zlib\fR" 4
+.IX Item "--compress-debug-sections=zlib"
+.IP "\fB\-\-compress\-debug\-sections=zlib\-gnu\fR" 4
+.IX Item "--compress-debug-sections=zlib-gnu"
+.IP "\fB\-\-compress\-debug\-sections=zlib\-gabi\fR" 4
+.IX Item "--compress-debug-sections=zlib-gabi"
+.PD
+These options control how \s-1DWARF\s0 debug sections are compressed.
+\&\fB\-\-compress\-debug\-sections=none\fR is equivalent to
+\&\fB\-\-nocompress\-debug\-sections\fR.
+\&\fB\-\-compress\-debug\-sections=zlib\fR and
+\&\fB\-\-compress\-debug\-sections=zlib\-gabi\fR are equivalent to
+\&\fB\-\-compress\-debug\-sections\fR.
+\&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses \s-1DWARF\s0 debug
+sections using zlib. The debug sections are renamed to begin with
+\&\fB.zdebug\fR. Note if compression would make a given section
+\&\fIlarger\fR then it is not compressed nor renamed.
+.IP "\fB\-\-nocompress\-debug\-sections\fR" 4
+.IX Item "--nocompress-debug-sections"
+Do not compress \s-1DWARF\s0 debug sections. This is usually the default for all
+targets except the x86/x86_64, but a configure time option can be used to
+override this.
+.IP "\fB\-D\fR" 4
+.IX Item "-D"
+Ignored. This option is accepted for script compatibility with calls to
+other assemblers.
+.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4
+.IX Item "--debug-prefix-map old=new"
+When assembling files in directory \fI\fIold\fI\fR, record debugging
+information describing them as in \fI\fInew\fI\fR instead.
+.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
+.IX Item "--defsym sym=value"
+Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
+\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
+indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
+value. The value of the symbol can be overridden inside a source file via the
+use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
+.IP "\fB\-f\fR" 4
+.IX Item "-f"
+\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
+compiler output).
+.IP "\fB\-g\fR" 4
+.IX Item "-g"
+.PD 0
+.IP "\fB\-\-gen\-debug\fR" 4
+.IX Item "--gen-debug"
+.PD
+Generate debugging information for each assembler source line using whichever
+debug format is preferred by the target. This currently means either \s-1STABS,
+ECOFF\s0 or \s-1DWARF2.\s0
+.IP "\fB\-\-gstabs\fR" 4
+.IX Item "--gstabs"
+Generate stabs debugging information for each assembler line. This
+may help debugging assembler code, if the debugger can handle it.
+.IP "\fB\-\-gstabs+\fR" 4
+.IX Item "--gstabs+"
+Generate stabs debugging information for each assembler line, with \s-1GNU\s0
+extensions that probably only gdb can handle, and that could make other
+debuggers crash or refuse to read your program. This
+may help debugging assembler code. Currently the only \s-1GNU\s0 extension is
+the location of the current working directory at assembling time.
+.IP "\fB\-\-gdwarf\-2\fR" 4
+.IX Item "--gdwarf-2"
+Generate \s-1DWARF2\s0 debugging information for each assembler line. This
+may help debugging assembler code, if the debugger can handle it. Note\-\-\-this
+option is only supported by some targets, not all of them.
+.IP "\fB\-\-gdwarf\-sections\fR" 4
+.IX Item "--gdwarf-sections"
+Instead of creating a .debug_line section, create a series of
+\&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the
+corresponding code section. For example a code section called \fI.text.func\fR
+will have its dwarf line number information placed into a section called
+\&\fI.debug_line.text.func\fR. If the code section is just called \fI.text\fR
+then debug line section will still be called just \fI.debug_line\fR without any
+suffix.
+.IP "\fB\-\-size\-check=error\fR" 4
+.IX Item "--size-check=error"
+.PD 0
+.IP "\fB\-\-size\-check=warning\fR" 4
+.IX Item "--size-check=warning"
+.PD
+Issue an error or warning for invalid \s-1ELF \s0.size directive.
+.IP "\fB\-\-elf\-stt\-common=no\fR" 4
+.IX Item "--elf-stt-common=no"
+.PD 0
+.IP "\fB\-\-elf\-stt\-common=yes\fR" 4
+.IX Item "--elf-stt-common=yes"
+.PD
+These options control whether the \s-1ELF\s0 assembler should generate common
+symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be controlled
+by a configure option \fB\-\-enable\-elf\-stt\-common\fR.
+.IP "\fB\-\-help\fR" 4
+.IX Item "--help"
+Print a summary of the command line options and exit.
+.IP "\fB\-\-target\-help\fR" 4
+.IX Item "--target-help"
+Print a summary of all target specific options and exit.
+.IP "\fB\-I\fR \fIdir\fR" 4
+.IX Item "-I dir"
+Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
+.IP "\fB\-J\fR" 4
+.IX Item "-J"
+Don't warn about signed overflow.
+.IP "\fB\-K\fR" 4
+.IX Item "-K"
+Issue warnings when difference tables altered for long displacements.
+.IP "\fB\-L\fR" 4
+.IX Item "-L"
+.PD 0
+.IP "\fB\-\-keep\-locals\fR" 4
+.IX Item "--keep-locals"
+.PD
+Keep (in the symbol table) local symbols. These symbols start with
+system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems
+or \fBL\fR for traditional a.out systems.
+.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
+.IX Item "--listing-lhs-width=number"
+Set the maximum width, in words, of the output data column for an assembler
+listing to \fInumber\fR.
+.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
+.IX Item "--listing-lhs-width2=number"
+Set the maximum width, in words, of the output data column for continuation
+lines in an assembler listing to \fInumber\fR.
+.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
+.IX Item "--listing-rhs-width=number"
+Set the maximum width of an input source line, as displayed in a listing, to
+\&\fInumber\fR bytes.
+.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
+.IX Item "--listing-cont-lines=number"
+Set the maximum number of lines printed in a listing for a single line of input
+to \fInumber\fR + 1.
+.IP "\fB\-\-no\-pad\-sections\fR" 4
+.IX Item "--no-pad-sections"
+Stop the assembler for padding the ends of output sections to the alignment
+of that section. The default is to pad the sections, but this can waste space
+which might be needed on targets which have tight memory constraints.
+.IP "\fB\-o\fR \fIobjfile\fR" 4
+.IX Item "-o objfile"
+Name the object-file output from \fBas\fR \fIobjfile\fR.
+.IP "\fB\-R\fR" 4
+.IX Item "-R"
+Fold the data section into the text section.
+.IP "\fB\-\-hash\-size=\fR\fInumber\fR" 4
+.IX Item "--hash-size=number"
+Set the default size of \s-1GAS\s0's hash tables to a prime number close to
+\&\fInumber\fR. Increasing this value can reduce the length of time it takes the
+assembler to perform its tasks, at the expense of increasing the assembler's
+memory requirements. Similarly reducing this value can reduce the memory
+requirements at the expense of speed.
+.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
+.IX Item "--reduce-memory-overheads"
+This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
+assembly processes slower. Currently this switch is a synonym for
+\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
+.IP "\fB\-\-sectname\-subst\fR" 4
+.IX Item "--sectname-subst"
+Honor substitution sequences in section names.
+.IP "\fB\-\-statistics\fR" 4
+.IX Item "--statistics"
+Print the maximum space (in bytes) and total time (in seconds) used by
+assembly.
+.IP "\fB\-\-strip\-local\-absolute\fR" 4
+.IX Item "--strip-local-absolute"
+Remove local absolute symbols from the outgoing symbol table.
+.IP "\fB\-v\fR" 4
+.IX Item "-v"
+.PD 0
+.IP "\fB\-version\fR" 4
+.IX Item "-version"
+.PD
+Print the \fBas\fR version.
+.IP "\fB\-\-version\fR" 4
+.IX Item "--version"
+Print the \fBas\fR version and exit.
+.IP "\fB\-W\fR" 4
+.IX Item "-W"
+.PD 0
+.IP "\fB\-\-no\-warn\fR" 4
+.IX Item "--no-warn"
+.PD
+Suppress warning messages.
+.IP "\fB\-\-fatal\-warnings\fR" 4
+.IX Item "--fatal-warnings"
+Treat warnings as errors.
+.IP "\fB\-\-warn\fR" 4
+.IX Item "--warn"
+Don't suppress warning messages or treat them as errors.
+.IP "\fB\-w\fR" 4
+.IX Item "-w"
+Ignored.
+.IP "\fB\-x\fR" 4
+.IX Item "-x"
+Ignored.
+.IP "\fB\-Z\fR" 4
+.IX Item "-Z"
+Generate an object file even after errors.
+.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
+.IX Item "-- | files ..."
+Standard input, or source files to assemble.
+.PP
+The following options are available when as is configured for the
+64\-bit mode of the \s-1ARM\s0 Architecture (AArch64).
+.IP "\fB\-EB\fR" 4
+.IX Item "-EB"
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a big-endian processor.
+.IP "\fB\-EL\fR" 4
+.IX Item "-EL"
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a little-endian processor.
+.IP "\fB\-mabi=\fR\fIabi\fR" 4
+.IX Item "-mabi=abi"
+Specify which \s-1ABI\s0 the source code uses. The recognized arguments
+are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object
+file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR.
+.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
+.IX Item "-mcpu=processor[+extension...]"
+This option specifies the target processor. The assembler will issue an error
+message if an attempt is made to assemble an instruction which will not execute
+on the target processor. The following processor names are recognized:
+\&\f(CW\*(C`cortex\-a35\*(C'\fR,
+\&\f(CW\*(C`cortex\-a53\*(C'\fR,
+\&\f(CW\*(C`cortex\-a57\*(C'\fR,
+\&\f(CW\*(C`cortex\-a72\*(C'\fR,
+\&\f(CW\*(C`cortex\-a73\*(C'\fR,
+\&\f(CW\*(C`exynos\-m1\*(C'\fR,
+\&\f(CW\*(C`falkor\*(C'\fR,
+\&\f(CW\*(C`qdf24xx\*(C'\fR,
+\&\f(CW\*(C`thunderx\*(C'\fR,
+\&\f(CW\*(C`vulcan\*(C'\fR,
+\&\f(CW\*(C`xgene1\*(C'\fR
+and
+\&\f(CW\*(C`xgene2\*(C'\fR.
+The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
+instructions valid for any supported processor, including all optional
+extensions.
+.Sp
+In addition to the basic instruction set, the assembler can be told to
+accept, or restrict, various extension mnemonics that extend the
+processor.
+.Sp
+If some implementations of a particular processor can have an
+extension, then then those extensions are automatically enabled.
+Consequently, you will not normally have to specify any additional
+extensions.
+.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
+.IX Item "-march=architecture[+extension...]"
+This option specifies the target architecture. The assembler will
+issue an error message if an attempt is made to assemble an
+instruction which will not execute on the target architecture. The
+following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR,
+\&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR and \f(CW\*(C`armv8.3\-a\*(C'\fR.
+.Sp
+If both \fB\-mcpu\fR and \fB\-march\fR are specified, the
+assembler will use the setting for \fB\-mcpu\fR. If neither are
+specified, the assembler will default to \fB\-mcpu=all\fR.
+.Sp
+The architecture option can be extended with the same instruction set
+extension options as the \fB\-mcpu\fR option. Unlike
+\&\fB\-mcpu\fR, extensions are not always enabled by default,
+.IP "\fB\-mverbose\-error\fR" 4
+.IX Item "-mverbose-error"
+This option enables verbose error messages for AArch64 gas. This option
+is enabled by default.
+.IP "\fB\-mno\-verbose\-error\fR" 4
+.IX Item "-mno-verbose-error"
+This option disables verbose error messages in AArch64 gas.
+.PP
+The following options are available when as is configured for an Alpha
+processor.
+.IP "\fB\-m\fR\fIcpu\fR" 4
+.IX Item "-mcpu"
+This option specifies the target processor. If an attempt is made to
+assemble an instruction which will not execute on the target processor,
+the assembler may either expand the instruction as a macro or issue an
+error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive.
+.Sp
+The following processor names are recognized:
+\&\f(CW21064\fR,
+\&\f(CW\*(C`21064a\*(C'\fR,
+\&\f(CW21066\fR,
+\&\f(CW21068\fR,
+\&\f(CW21164\fR,
+\&\f(CW\*(C`21164a\*(C'\fR,
+\&\f(CW\*(C`21164pc\*(C'\fR,
+\&\f(CW21264\fR,
+\&\f(CW\*(C`21264a\*(C'\fR,
+\&\f(CW\*(C`21264b\*(C'\fR,
+\&\f(CW\*(C`ev4\*(C'\fR,
+\&\f(CW\*(C`ev5\*(C'\fR,
+\&\f(CW\*(C`lca45\*(C'\fR,
+\&\f(CW\*(C`ev5\*(C'\fR,
+\&\f(CW\*(C`ev56\*(C'\fR,
+\&\f(CW\*(C`pca56\*(C'\fR,
+\&\f(CW\*(C`ev6\*(C'\fR,
+\&\f(CW\*(C`ev67\*(C'\fR,
+\&\f(CW\*(C`ev68\*(C'\fR.
+The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
+instructions valid for any Alpha processor.
+.Sp
+In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR,
+and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the
+numbered processor names (e.g. 21064) enable the processor-specific PALcode
+instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not.
+.IP "\fB\-mdebug\fR" 4
+.IX Item "-mdebug"
+.PD 0
+.IP "\fB\-no\-mdebug\fR" 4
+.IX Item "-no-mdebug"
+.PD
+Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for
+stabs directives and procedure descriptors. The default is to automatically
+enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
+.IP "\fB\-relax\fR" 4
+.IX Item "-relax"
+This option forces all relocations to be put into the object file, instead
+of saving space and resolving some relocations at assembly time. Note that
+this option does not propagate all symbol arithmetic into the object file,
+because not all symbol arithmetic can be represented. However, the option
+can still be useful in specific applications.
+.IP "\fB\-replace\fR" 4
+.IX Item "-replace"
+.PD 0
+.IP "\fB\-noreplace\fR" 4
+.IX Item "-noreplace"
+.PD
+Enables or disables the optimization of procedure calls, both at assemblage
+and at link time. These options are only available for \s-1VMS\s0 targets and
+\&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker
+Utility Manual.
+.IP "\fB\-g\fR" 4
+.IX Item "-g"
+This option is used when the compiler generates debug information. When
+\&\fBgcc\fR is using \fBmips-tfile\fR to generate debug
+information for \s-1ECOFF,\s0 local labels must be passed through to the object
+file. Otherwise this option has no effect.
+.IP "\fB\-G\fR\fIsize\fR" 4
+.IX Item "-Gsize"
+A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR,
+while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.
+.IP "\fB\-F\fR" 4
+.IX Item "-F"
+.PD 0
+.IP "\fB\-32addr\fR" 4
+.IX Item "-32addr"
+.PD
+These options are ignored for backward compatibility.
+.PP
+The following options are available when as is configured for an \s-1ARC\s0
+processor.
+.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
+.IX Item "-mcpu=cpu"
+This option selects the core processor variant.
+.IP "\fB\-EB | \-EL\fR" 4
+.IX Item "-EB | -EL"
+Select either big-endian (\-EB) or little-endian (\-EL) output.
+.IP "\fB\-mcode\-density\fR" 4
+.IX Item "-mcode-density"
+Enable Code Density extenssion instructions.
+.PP
+The following options are available when as is configured for the \s-1ARM\s0
+processor family.
+.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
+.IX Item "-mcpu=processor[+extension...]"
+Specify which \s-1ARM\s0 processor variant is the target.
+.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
+.IX Item "-march=architecture[+extension...]"
+Specify which \s-1ARM\s0 architecture variant is used by the target.
+.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
+.IX Item "-mfpu=floating-point-format"
+Select which Floating Point architecture is the target.
+.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
+.IX Item "-mfloat-abi=abi"
+Select which floating point \s-1ABI\s0 is in use.
+.IP "\fB\-mthumb\fR" 4
+.IX Item "-mthumb"
+Enable Thumb only instruction decoding.
+.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
+.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
+Select which procedure calling convention is in use.
+.IP "\fB\-EB | \-EL\fR" 4
+.IX Item "-EB | -EL"
+Select either big-endian (\-EB) or little-endian (\-EL) output.
+.IP "\fB\-mthumb\-interwork\fR" 4
+.IX Item "-mthumb-interwork"
+Specify that the code has been generated with interworking between Thumb and
+\&\s-1ARM\s0 code in mind.
+.IP "\fB\-mccs\fR" 4
+.IX Item "-mccs"
+Turns on CodeComposer Studio assembly syntax compatibility mode.
+.IP "\fB\-k\fR" 4
+.IX Item "-k"
+Specify that \s-1PIC\s0 code has been generated.
+.PP
+The following options are available when as is configured for
+the Blackfin processor family.
+.IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4
+.IX Item "-mcpu=processor[-sirevision]"
+This option specifies the target processor. The optional \fIsirevision\fR
+is not used in assembler. It's here such that \s-1GCC\s0 can easily pass down its
+\&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an
+error message if an attempt is made to assemble an instruction which
+will not execute on the target processor. The following processor names are
+recognized:
+\&\f(CW\*(C`bf504\*(C'\fR,
+\&\f(CW\*(C`bf506\*(C'\fR,
+\&\f(CW\*(C`bf512\*(C'\fR,
+\&\f(CW\*(C`bf514\*(C'\fR,
+\&\f(CW\*(C`bf516\*(C'\fR,
+\&\f(CW\*(C`bf518\*(C'\fR,
+\&\f(CW\*(C`bf522\*(C'\fR,
+\&\f(CW\*(C`bf523\*(C'\fR,
+\&\f(CW\*(C`bf524\*(C'\fR,
+\&\f(CW\*(C`bf525\*(C'\fR,
+\&\f(CW\*(C`bf526\*(C'\fR,
+\&\f(CW\*(C`bf527\*(C'\fR,
+\&\f(CW\*(C`bf531\*(C'\fR,
+\&\f(CW\*(C`bf532\*(C'\fR,
+\&\f(CW\*(C`bf533\*(C'\fR,
+\&\f(CW\*(C`bf534\*(C'\fR,
+\&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),
+\&\f(CW\*(C`bf536\*(C'\fR,
+\&\f(CW\*(C`bf537\*(C'\fR,
+\&\f(CW\*(C`bf538\*(C'\fR,
+\&\f(CW\*(C`bf539\*(C'\fR,
+\&\f(CW\*(C`bf542\*(C'\fR,
+\&\f(CW\*(C`bf542m\*(C'\fR,
+\&\f(CW\*(C`bf544\*(C'\fR,
+\&\f(CW\*(C`bf544m\*(C'\fR,
+\&\f(CW\*(C`bf547\*(C'\fR,
+\&\f(CW\*(C`bf547m\*(C'\fR,
+\&\f(CW\*(C`bf548\*(C'\fR,
+\&\f(CW\*(C`bf548m\*(C'\fR,
+\&\f(CW\*(C`bf549\*(C'\fR,
+\&\f(CW\*(C`bf549m\*(C'\fR,
+\&\f(CW\*(C`bf561\*(C'\fR,
+and
+\&\f(CW\*(C`bf592\*(C'\fR.
+.IP "\fB\-mfdpic\fR" 4
+.IX Item "-mfdpic"
+Assemble for the \s-1FDPIC ABI.\s0
+.IP "\fB\-mno\-fdpic\fR" 4
+.IX Item "-mno-fdpic"
+.PD 0
+.IP "\fB\-mnopic\fR" 4
+.IX Item "-mnopic"
+.PD
+Disable \-mfdpic.
+.PP
+See the info pages for documentation of the CRIS-specific options.
+.PP
+The following options are available when as is configured for
+a D10V processor.
+.IP "\fB\-O\fR" 4
+.IX Item "-O"
+Optimize output by parallelizing instructions.
+.PP
+The following options are available when as is configured for a D30V
+processor.
+.IP "\fB\-O\fR" 4
+.IX Item "-O"
+Optimize output by parallelizing instructions.
+.IP "\fB\-n\fR" 4
+.IX Item "-n"
+Warn when nops are generated.
+.IP "\fB\-N\fR" 4
+.IX Item "-N"
+Warn when a nop after a 32\-bit multiply instruction is generated.
+.PP
+The following options are available when as is configured for
+an Epiphany processor.
+.IP "\fB\-mepiphany\fR" 4
+.IX Item "-mepiphany"
+Specifies that the both 32 and 16 bit instructions are allowed. This is the
+default behavior.
+.IP "\fB\-mepiphany16\fR" 4
+.IX Item "-mepiphany16"
+Restricts the permitted instructions to just the 16 bit set.
+.PP
+The following options are available when as is configured for an H8/300
+processor.
+\&\f(CW@chapter\fR H8/300 Dependent Features
+.SS "Options"
+.IX Subsection "Options"
+The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one
+machine-dependent option:
+.IP "\fB\-h\-tick\-hex\fR" 4
+.IX Item "-h-tick-hex"
+Support H'00 style hex constants in addition to 0x00 style.
+.IP "\fB\-mach=\fR\fIname\fR" 4
+.IX Item "-mach=name"
+Sets the H8300 machine variant. The following machine names
+are recognised:
+\&\f(CW\*(C`h8300h\*(C'\fR,
+\&\f(CW\*(C`h8300hn\*(C'\fR,
+\&\f(CW\*(C`h8300s\*(C'\fR,
+\&\f(CW\*(C`h8300sn\*(C'\fR,
+\&\f(CW\*(C`h8300sx\*(C'\fR and
+\&\f(CW\*(C`h8300sxn\*(C'\fR.
+.PP
+The following options are available when as is configured for
+an i386 processor.
+.IP "\fB\-\-32 | \-\-x32 | \-\-64\fR" 4
+.IX Item "--32 | --x32 | --64"
+Select the word size, either 32 bits or 64 bits. \fB\-\-32\fR
+implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR
+imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size
+respectively.
+.Sp
+These options are only available with the \s-1ELF\s0 object file format, and
+require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit
+platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit
+usage and use x86\-64 as target platform).
+.IP "\fB\-n\fR" 4
+.IX Item "-n"
+By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for
+alignment within code sections with multi-byte nop instructions such
+as leal 0(%esi,1),%esi. This switch disables the optimization.
+.IP "\fB\-\-divide\fR" 4
+.IX Item "--divide"
+On SVR4\-derived platforms, the character \fB/\fR is treated as a comment
+character, which means that it cannot be used in expressions. The
+\&\fB\-\-divide\fR option turns \fB/\fR into a normal character. This does
+not disable \fB/\fR at the beginning of a line starting a comment, or
+affect using \fB#\fR for starting a comment.
+.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4
+.IX Item "-march=CPU[+EXTENSION...]"
+This option specifies the target processor. The assembler will
+issue an error message if an attempt is made to assemble an instruction
+which will not execute on the target processor. The following
+processor names are recognized:
+\&\f(CW\*(C`i8086\*(C'\fR,
+\&\f(CW\*(C`i186\*(C'\fR,
+\&\f(CW\*(C`i286\*(C'\fR,
+\&\f(CW\*(C`i386\*(C'\fR,
+\&\f(CW\*(C`i486\*(C'\fR,
+\&\f(CW\*(C`i586\*(C'\fR,
+\&\f(CW\*(C`i686\*(C'\fR,
+\&\f(CW\*(C`pentium\*(C'\fR,
+\&\f(CW\*(C`pentiumpro\*(C'\fR,
+\&\f(CW\*(C`pentiumii\*(C'\fR,
+\&\f(CW\*(C`pentiumiii\*(C'\fR,
+\&\f(CW\*(C`pentium4\*(C'\fR,
+\&\f(CW\*(C`prescott\*(C'\fR,
+\&\f(CW\*(C`nocona\*(C'\fR,
+\&\f(CW\*(C`core\*(C'\fR,
+\&\f(CW\*(C`core2\*(C'\fR,
+\&\f(CW\*(C`corei7\*(C'\fR,
+\&\f(CW\*(C`l1om\*(C'\fR,
+\&\f(CW\*(C`k1om\*(C'\fR,
+\&\f(CW\*(C`iamcu\*(C'\fR,
+\&\f(CW\*(C`k6\*(C'\fR,
+\&\f(CW\*(C`k6_2\*(C'\fR,
+\&\f(CW\*(C`athlon\*(C'\fR,
+\&\f(CW\*(C`opteron\*(C'\fR,
+\&\f(CW\*(C`k8\*(C'\fR,
+\&\f(CW\*(C`amdfam10\*(C'\fR,
+\&\f(CW\*(C`bdver1\*(C'\fR,
+\&\f(CW\*(C`bdver2\*(C'\fR,
+\&\f(CW\*(C`bdver3\*(C'\fR,
+\&\f(CW\*(C`bdver4\*(C'\fR,
+\&\f(CW\*(C`znver1\*(C'\fR,
+\&\f(CW\*(C`btver1\*(C'\fR,
+\&\f(CW\*(C`btver2\*(C'\fR,
+\&\f(CW\*(C`generic32\*(C'\fR and
+\&\f(CW\*(C`generic64\*(C'\fR.
+.Sp
+In addition to the basic instruction set, the assembler can be told to
+accept various extension mnemonics. For example,
+\&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and
+\&\fIvmx\fR. The following extensions are currently supported:
+\&\f(CW8087\fR,
+\&\f(CW287\fR,
+\&\f(CW387\fR,
+\&\f(CW687\fR,
+\&\f(CW\*(C`no87\*(C'\fR,
+\&\f(CW\*(C`no287\*(C'\fR,
+\&\f(CW\*(C`no387\*(C'\fR,
+\&\f(CW\*(C`no687\*(C'\fR,
+\&\f(CW\*(C`mmx\*(C'\fR,
+\&\f(CW\*(C`nommx\*(C'\fR,
+\&\f(CW\*(C`sse\*(C'\fR,
+\&\f(CW\*(C`sse2\*(C'\fR,
+\&\f(CW\*(C`sse3\*(C'\fR,
+\&\f(CW\*(C`ssse3\*(C'\fR,
+\&\f(CW\*(C`sse4.1\*(C'\fR,
+\&\f(CW\*(C`sse4.2\*(C'\fR,
+\&\f(CW\*(C`sse4\*(C'\fR,
+\&\f(CW\*(C`nosse\*(C'\fR,
+\&\f(CW\*(C`nosse2\*(C'\fR,
+\&\f(CW\*(C`nosse3\*(C'\fR,
+\&\f(CW\*(C`nossse3\*(C'\fR,
+\&\f(CW\*(C`nosse4.1\*(C'\fR,
+\&\f(CW\*(C`nosse4.2\*(C'\fR,
+\&\f(CW\*(C`nosse4\*(C'\fR,
+\&\f(CW\*(C`avx\*(C'\fR,
+\&\f(CW\*(C`avx2\*(C'\fR,
+\&\f(CW\*(C`noavx\*(C'\fR,
+\&\f(CW\*(C`noavx2\*(C'\fR,
+\&\f(CW\*(C`adx\*(C'\fR,
+\&\f(CW\*(C`rdseed\*(C'\fR,
+\&\f(CW\*(C`prfchw\*(C'\fR,
+\&\f(CW\*(C`smap\*(C'\fR,
+\&\f(CW\*(C`mpx\*(C'\fR,
+\&\f(CW\*(C`sha\*(C'\fR,
+\&\f(CW\*(C`rdpid\*(C'\fR,
+\&\f(CW\*(C`ptwrite\*(C'\fR,
+\&\f(CW\*(C`prefetchwt1\*(C'\fR,
+\&\f(CW\*(C`clflushopt\*(C'\fR,
+\&\f(CW\*(C`se1\*(C'\fR,
+\&\f(CW\*(C`clwb\*(C'\fR,
+\&\f(CW\*(C`avx512f\*(C'\fR,
+\&\f(CW\*(C`avx512cd\*(C'\fR,
+\&\f(CW\*(C`avx512er\*(C'\fR,
+\&\f(CW\*(C`avx512pf\*(C'\fR,
+\&\f(CW\*(C`avx512vl\*(C'\fR,
+\&\f(CW\*(C`avx512bw\*(C'\fR,
+\&\f(CW\*(C`avx512dq\*(C'\fR,
+\&\f(CW\*(C`avx512ifma\*(C'\fR,
+\&\f(CW\*(C`avx512vbmi\*(C'\fR,
+\&\f(CW\*(C`avx512_4fmaps\*(C'\fR,
+\&\f(CW\*(C`avx512_4vnniw\*(C'\fR,
+\&\f(CW\*(C`avx512_vpopcntdq\*(C'\fR,
+\&\f(CW\*(C`noavx512f\*(C'\fR,
+\&\f(CW\*(C`noavx512cd\*(C'\fR,
+\&\f(CW\*(C`noavx512er\*(C'\fR,
+\&\f(CW\*(C`noavx512pf\*(C'\fR,
+\&\f(CW\*(C`noavx512vl\*(C'\fR,
+\&\f(CW\*(C`noavx512bw\*(C'\fR,
+\&\f(CW\*(C`noavx512dq\*(C'\fR,
+\&\f(CW\*(C`noavx512ifma\*(C'\fR,
+\&\f(CW\*(C`noavx512vbmi\*(C'\fR,
+\&\f(CW\*(C`noavx512_4fmaps\*(C'\fR,
+\&\f(CW\*(C`noavx512_4vnniw\*(C'\fR,
+\&\f(CW\*(C`noavx512_vpopcntdq\*(C'\fR,
+\&\f(CW\*(C`vmx\*(C'\fR,
+\&\f(CW\*(C`vmfunc\*(C'\fR,
+\&\f(CW\*(C`smx\*(C'\fR,
+\&\f(CW\*(C`xsave\*(C'\fR,
+\&\f(CW\*(C`xsaveopt\*(C'\fR,
+\&\f(CW\*(C`xsavec\*(C'\fR,
+\&\f(CW\*(C`xsaves\*(C'\fR,
+\&\f(CW\*(C`aes\*(C'\fR,
+\&\f(CW\*(C`pclmul\*(C'\fR,
+\&\f(CW\*(C`fsgsbase\*(C'\fR,
+\&\f(CW\*(C`rdrnd\*(C'\fR,
+\&\f(CW\*(C`f16c\*(C'\fR,
+\&\f(CW\*(C`bmi2\*(C'\fR,
+\&\f(CW\*(C`fma\*(C'\fR,
+\&\f(CW\*(C`movbe\*(C'\fR,
+\&\f(CW\*(C`ept\*(C'\fR,
+\&\f(CW\*(C`lzcnt\*(C'\fR,
+\&\f(CW\*(C`hle\*(C'\fR,
+\&\f(CW\*(C`rtm\*(C'\fR,
+\&\f(CW\*(C`invpcid\*(C'\fR,
+\&\f(CW\*(C`clflush\*(C'\fR,
+\&\f(CW\*(C`mwaitx\*(C'\fR,
+\&\f(CW\*(C`clzero\*(C'\fR,
+\&\f(CW\*(C`lwp\*(C'\fR,
+\&\f(CW\*(C`fma4\*(C'\fR,
+\&\f(CW\*(C`xop\*(C'\fR,
+\&\f(CW\*(C`cx16\*(C'\fR,
+\&\f(CW\*(C`syscall\*(C'\fR,
+\&\f(CW\*(C`rdtscp\*(C'\fR,
+\&\f(CW\*(C`3dnow\*(C'\fR,
+\&\f(CW\*(C`3dnowa\*(C'\fR,
+\&\f(CW\*(C`sse4a\*(C'\fR,
+\&\f(CW\*(C`sse5\*(C'\fR,
+\&\f(CW\*(C`svme\*(C'\fR,
+\&\f(CW\*(C`abm\*(C'\fR and
+\&\f(CW\*(C`padlock\*(C'\fR.
+Note that rather than extending a basic instruction set, the extension
+mnemonics starting with \f(CW\*(C`no\*(C'\fR revoke the respective functionality.
+.Sp
+When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
+\&\f(CW\*(C`.arch\*(C'\fR directive will take precedent.
+.IP "\fB\-mtune=\fR\fI\s-1CPU\s0\fR" 4
+.IX Item "-mtune=CPU"
+This option specifies a processor to optimize for. When used in
+conjunction with the \fB\-march\fR option, only instructions
+of the processor specified by the \fB\-march\fR option will be
+generated.
+.Sp
+Valid \fI\s-1CPU\s0\fR values are identical to the processor list of
+\&\fB\-march=\fR\fI\s-1CPU\s0\fR.
+.IP "\fB\-msse2avx\fR" 4
+.IX Item "-msse2avx"
+This option specifies that the assembler should encode \s-1SSE\s0 instructions
+with \s-1VEX\s0 prefix.
+.IP "\fB\-msse\-check=\fR\fInone\fR" 4
+.IX Item "-msse-check=none"
+.PD 0
+.IP "\fB\-msse\-check=\fR\fIwarning\fR" 4
+.IX Item "-msse-check=warning"
+.IP "\fB\-msse\-check=\fR\fIerror\fR" 4
+.IX Item "-msse-check=error"
+.PD
+These options control if the assembler should check \s-1SSE\s0 instructions.
+\&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0
+instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR
+will make the assembler issue a warning for any \s-1SSE\s0 instruction.
+\&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error
+for any \s-1SSE\s0 instruction.
+.IP "\fB\-mavxscalar=\fR\fI128\fR" 4
+.IX Item "-mavxscalar=128"
+.PD 0
+.IP "\fB\-mavxscalar=\fR\fI256\fR" 4
+.IX Item "-mavxscalar=256"
+.PD
+These options control how the assembler should encode scalar \s-1AVX\s0
+instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar
+\&\s-1AVX\s0 instructions with 128bit vector length, which is the default.
+\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions
+with 256bit vector length.
+.IP "\fB\-mevexlig=\fR\fI128\fR" 4
+.IX Item "-mevexlig=128"
+.PD 0
+.IP "\fB\-mevexlig=\fR\fI256\fR" 4
+.IX Item "-mevexlig=256"
+.IP "\fB\-mevexlig=\fR\fI512\fR" 4
+.IX Item "-mevexlig=512"
+.PD
+These options control how the assembler should encode length-ignored
+(\s-1LIG\s0) \s-1EVEX\s0 instructions. \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG
+EVEX\s0 instructions with 128bit vector length, which is the default.
+\&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will
+encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length,
+respectively.
+.IP "\fB\-mevexwig=\fR\fI0\fR" 4
+.IX Item "-mevexwig=0"
+.PD 0
+.IP "\fB\-mevexwig=\fR\fI1\fR" 4
+.IX Item "-mevexwig=1"
+.PD
+These options control how the assembler should encode w\-ignored (\s-1WIG\s0)
+\&\s-1EVEX\s0 instructions. \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG
+EVEX\s0 instructions with evex.w = 0, which is the default.
+\&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with
+evex.w = 1.
+.IP "\fB\-mmnemonic=\fR\fIatt\fR" 4
+.IX Item "-mmnemonic=att"
+.PD 0
+.IP "\fB\-mmnemonic=\fR\fIintel\fR" 4
+.IX Item "-mmnemonic=intel"
+.PD
+This option specifies instruction mnemonic for matching instructions.
+The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will
+take precedent.
+.IP "\fB\-msyntax=\fR\fIatt\fR" 4
+.IX Item "-msyntax=att"
+.PD 0
+.IP "\fB\-msyntax=\fR\fIintel\fR" 4
+.IX Item "-msyntax=intel"
+.PD
+This option specifies instruction syntax when processing instructions.
+The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will
+take precedent.
+.IP "\fB\-mnaked\-reg\fR" 4
+.IX Item "-mnaked-reg"
+This opetion specifies that registers don't require a \fB%\fR prefix.
+The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent.
+.IP "\fB\-madd\-bnd\-prefix\fR" 4
+.IX Item "-madd-bnd-prefix"
+This option forces the assembler to add \s-1BND\s0 prefix to all branches, even
+if such prefix was not explicitly specified in the source code.
+.IP "\fB\-mno\-shared\fR" 4
+.IX Item "-mno-shared"
+On \s-1ELF\s0 target, the assembler normally optimizes out non-PLT relocations
+against defined non-weak global branch targets with default visibility.
+The \fB\-mshared\fR option tells the assembler to generate code which
+may go into a shared library where all non-weak global branch targets
+with default visibility can be preempted. The resulting code is
+slightly bigger. This option only affects the handling of branch
+instructions.
+.IP "\fB\-mbig\-obj\fR" 4
+.IX Item "-mbig-obj"
+On x86\-64 \s-1PE/COFF\s0 target this option forces the use of big object file
+format, which allows more than 32768 sections.
+.IP "\fB\-momit\-lock\-prefix=\fR\fIno\fR" 4
+.IX Item "-momit-lock-prefix=no"
+.PD 0
+.IP "\fB\-momit\-lock\-prefix=\fR\fIyes\fR" 4
+.IX Item "-momit-lock-prefix=yes"
+.PD
+These options control how the assembler should encode lock prefix.
+This option is intended as a workaround for processors, that fail on
+lock prefix. This option can only be safely used with single-core,
+single-thread computers
+\&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes.
+\&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual,
+which is the default.
+.IP "\fB\-mfence\-as\-lock\-add=\fR\fIno\fR" 4
+.IX Item "-mfence-as-lock-add=no"
+.PD 0
+.IP "\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR" 4
+.IX Item "-mfence-as-lock-add=yes"
+.PD
+These options control how the assembler should encode lfence, mfence and
+sfence.
+\&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and
+sfence as \fBlock addl \f(CB$0x0\fB, (%rsp)\fR in 64\-bit mode and
+\&\fBlock addl \f(CB$0x0\fB, (%esp)\fR in 32\-bit mode.
+\&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and
+sfence as usual, which is the default.
+.IP "\fB\-mrelax\-relocations=\fR\fIno\fR" 4
+.IX Item "-mrelax-relocations=no"
+.PD 0
+.IP "\fB\-mrelax\-relocations=\fR\fIyes\fR" 4
+.IX Item "-mrelax-relocations=yes"
+.PD
+These options control whether the assembler should generate relax
+relocations, R_386_GOT32X, in 32\-bit mode, or R_X86_64_GOTPCRELX and
+R_X86_64_REX_GOTPCRELX, in 64\-bit mode.
+\&\fB\-mrelax\-relocations=\fR\fIyes\fR will generate relax relocations.
+\&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax
+relocations. The default can be controlled by a configure option
+\&\fB\-\-enable\-x86\-relax\-relocations\fR.
+.IP "\fB\-mevexrcig=\fR\fIrne\fR" 4
+.IX Item "-mevexrcig=rne"
+.PD 0
+.IP "\fB\-mevexrcig=\fR\fIrd\fR" 4
+.IX Item "-mevexrcig=rd"
+.IP "\fB\-mevexrcig=\fR\fIru\fR" 4
+.IX Item "-mevexrcig=ru"
+.IP "\fB\-mevexrcig=\fR\fIrz\fR" 4
+.IX Item "-mevexrcig=rz"
+.PD
+These options control how the assembler should encode SAE-only
+\&\s-1EVEX\s0 instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode \s-1RC\s0 bits
+of \s-1EVEX\s0 instruction with 00, which is the default.
+\&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR
+and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only \s-1EVEX\s0 instructions
+with 01, 10 and 11 \s-1RC\s0 bits, respectively.
+.IP "\fB\-mamd64\fR" 4
+.IX Item "-mamd64"
+.PD 0
+.IP "\fB\-mintel64\fR" 4
+.IX Item "-mintel64"
+.PD
+This option specifies that the assembler should accept only \s-1AMD64\s0 or
+Intel64 \s-1ISA\s0 in 64\-bit mode. The default is to accept both.
+.PP
+The following options are available when as is configured for the
+Intel 80960 processor.
+.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
+.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
+Specify which variant of the 960 architecture is the target.
+.IP "\fB\-b\fR" 4
+.IX Item "-b"
+Add code to collect statistics about branches taken.
+.IP "\fB\-no\-relax\fR" 4
+.IX Item "-no-relax"
+Do not alter compare-and-branch instructions for long displacements;
+error if necessary.
+.PP
+The following options are available when as is configured for the
+Ubicom \s-1IP2K\s0 series.
+.IP "\fB\-mip2022ext\fR" 4
+.IX Item "-mip2022ext"
+Specifies that the extended \s-1IP2022\s0 instructions are allowed.
+.IP "\fB\-mip2022\fR" 4
+.IX Item "-mip2022"
+Restores the default behaviour, which restricts the permitted instructions to
+just the basic \s-1IP2022\s0 ones.
+.PP
+The following options are available when as is configured for the
+Renesas M32C and M16C processors.
+.IP "\fB\-m32c\fR" 4
+.IX Item "-m32c"
+Assemble M32C instructions.
+.IP "\fB\-m16c\fR" 4
+.IX Item "-m16c"
+Assemble M16C instructions (the default).
+.IP "\fB\-relax\fR" 4
+.IX Item "-relax"
+Enable support for link-time relaxations.
+.IP "\fB\-h\-tick\-hex\fR" 4
+.IX Item "-h-tick-hex"
+Support H'00 style hex constants in addition to 0x00 style.
+.PP
+The following options are available when as is configured for the
+Renesas M32R (formerly Mitsubishi M32R) series.
+.IP "\fB\-\-m32rx\fR" 4
+.IX Item "--m32rx"
+Specify which processor in the M32R family is the target. The default
+is normally the M32R, but this option changes it to the M32RX.
+.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
+.IX Item "--warn-explicit-parallel-conflicts or --Wp"
+Produce warning messages when questionable parallel constructs are
+encountered.
+.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
+.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
+Do not produce warning messages when questionable parallel constructs are
+encountered.
+.PP
+The following options are available when as is configured for the
+Motorola 68000 series.
+.IP "\fB\-l\fR" 4
+.IX Item "-l"
+Shorten references to undefined symbols, to one word instead of two.
+.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
+.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
+.PD 0
+.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
+.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
+.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
+.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
+.PD
+Specify what processor in the 68000 family is the target. The default
+is normally the 68020, but this can be changed at configuration time.
+.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
+.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
+The target machine does (or does not) have a floating-point coprocessor.
+The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
+the basic 68000 is not compatible with the 68881, a combination of the
+two can be specified, since it's possible to do emulation of the
+coprocessor instructions with the main processor.
+.IP "\fB\-m68851 | \-mno\-68851\fR" 4
+.IX Item "-m68851 | -mno-68851"
+The target machine does (or does not) have a memory-management
+unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
+.PP
+The following options are available when as is configured for an
+Altera Nios \s-1II\s0 processor.
+.IP "\fB\-relax\-section\fR" 4
+.IX Item "-relax-section"
+Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR
+sequences when possible. The generated code sequences are suitable
+for use in position-independent code, but there is a practical limit
+on the extended branch range because of the length of the sequences.
+This option is the default.
+.IP "\fB\-relax\-all\fR" 4
+.IX Item "-relax-all"
+Replace branch instructions not determinable to be in range
+and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences
+(respectively). This option generates absolute relocations against the
+target symbols and is not appropriate for position-independent code.
+.IP "\fB\-no\-relax\fR" 4
+.IX Item "-no-relax"
+Do not replace any branches or calls.
+.IP "\fB\-EB\fR" 4
+.IX Item "-EB"
+Generate big-endian output.
+.IP "\fB\-EL\fR" 4
+.IX Item "-EL"
+Generate little-endian output. This is the default.
+.IP "\fB\-march=\fR\fIarchitecture\fR" 4
+.IX Item "-march=architecture"
+This option specifies the target architecture. The assembler issues
+an error message if an attempt is made to assemble an instruction which
+will not execute on the target architecture. The following architecture
+names are recognized:
+\&\f(CW\*(C`r1\*(C'\fR,
+\&\f(CW\*(C`r2\*(C'\fR.
+The default is \f(CW\*(C`r1\*(C'\fR.
+.PP
+The following options are available when as is configured for a
+Meta processor.
+.ie n .IP """\-mcpu=metac11""" 4
+.el .IP "\f(CW\-mcpu=metac11\fR" 4
+.IX Item "-mcpu=metac11"
+Generate code for Meta 1.1.
+.ie n .IP """\-mcpu=metac12""" 4
+.el .IP "\f(CW\-mcpu=metac12\fR" 4
+.IX Item "-mcpu=metac12"
+Generate code for Meta 1.2.
+.ie n .IP """\-mcpu=metac21""" 4
+.el .IP "\f(CW\-mcpu=metac21\fR" 4
+.IX Item "-mcpu=metac21"
+Generate code for Meta 2.1.
+.ie n .IP """\-mfpu=metac21""" 4
+.el .IP "\f(CW\-mfpu=metac21\fR" 4
+.IX Item "-mfpu=metac21"
+Allow code to use \s-1FPU\s0 hardware of Meta 2.1.
+.PP
+See the info pages for documentation of the MMIX-specific options.
+.PP
+The following options are available when as is configured for a
+\&\s-1NDS32\s0 processor.
+.ie n .IP """\-O1""" 4
+.el .IP "\f(CW\-O1\fR" 4
+.IX Item "-O1"
+Optimize for performance.
+.ie n .IP """\-Os""" 4
+.el .IP "\f(CW\-Os\fR" 4
+.IX Item "-Os"
+Optimize for space.
+.ie n .IP """\-EL""" 4
+.el .IP "\f(CW\-EL\fR" 4
+.IX Item "-EL"
+Produce little endian data output.
+.ie n .IP """\-EB""" 4
+.el .IP "\f(CW\-EB\fR" 4
+.IX Item "-EB"
+Produce little endian data output.
+.ie n .IP """\-mpic""" 4
+.el .IP "\f(CW\-mpic\fR" 4
+.IX Item "-mpic"
+Generate \s-1PIC.\s0
+.ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4
+.el .IP "\f(CW\-mno\-fp\-as\-gp\-relax\fR" 4
+.IX Item "-mno-fp-as-gp-relax"
+Suppress fp-as-gp relaxation for this file.
+.ie n .IP """\-mb2bb\-relax""" 4
+.el .IP "\f(CW\-mb2bb\-relax\fR" 4
+.IX Item "-mb2bb-relax"
+Back-to-back branch optimization.
+.ie n .IP """\-mno\-all\-relax""" 4
+.el .IP "\f(CW\-mno\-all\-relax\fR" 4
+.IX Item "-mno-all-relax"
+Suppress all relaxation for this file.
+.ie n .IP """\-march=<arch name>""" 4
+.el .IP "\f(CW\-march=<arch name>\fR" 4
+.IX Item "-march=<arch name>"
+Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
+v3s, v2, v2j, v2f, v2s.
+.ie n .IP """\-mbaseline=<baseline>""" 4
+.el .IP "\f(CW\-mbaseline=<baseline>\fR" 4
+.IX Item "-mbaseline=<baseline>"
+Assemble for baseline <baseline> which could be v2, v3, v3m.
+.ie n .IP """\-mfpu\-freg=\f(CIFREG\f(CW""" 4
+.el .IP "\f(CW\-mfpu\-freg=\f(CIFREG\f(CW\fR" 4
+.IX Item "-mfpu-freg=FREG"
+Specify a \s-1FPU\s0 configuration.
+.RS 4
+.ie n .IP """0 8 SP / 4 DP registers""" 4
+.el .IP "\f(CW0 8 SP / 4 DP registers\fR" 4
+.IX Item "0 8 SP / 4 DP registers"
+.PD 0
+.ie n .IP """1 16 SP / 8 DP registers""" 4
+.el .IP "\f(CW1 16 SP / 8 DP registers\fR" 4
+.IX Item "1 16 SP / 8 DP registers"
+.ie n .IP """2 32 SP / 16 DP registers""" 4
+.el .IP "\f(CW2 32 SP / 16 DP registers\fR" 4
+.IX Item "2 32 SP / 16 DP registers"
+.ie n .IP """3 32 SP / 32 DP registers""" 4
+.el .IP "\f(CW3 32 SP / 32 DP registers\fR" 4
+.IX Item "3 32 SP / 32 DP registers"
+.RE
+.RS 4
+.RE
+.ie n .IP """\-mabi=\f(CIabi\f(CW""" 4
+.el .IP "\f(CW\-mabi=\f(CIabi\f(CW\fR" 4
+.IX Item "-mabi=abi"
+.PD
+Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
+.ie n .IP """\-m[no\-]mac""" 4
+.el .IP "\f(CW\-m[no\-]mac\fR" 4
+.IX Item "-m[no-]mac"
+Enable/Disable Multiply instructions support.
+.ie n .IP """\-m[no\-]div""" 4
+.el .IP "\f(CW\-m[no\-]div\fR" 4
+.IX Item "-m[no-]div"
+Enable/Disable Divide instructions support.
+.ie n .IP """\-m[no\-]16bit\-ext""" 4
+.el .IP "\f(CW\-m[no\-]16bit\-ext\fR" 4
+.IX Item "-m[no-]16bit-ext"
+Enable/Disable 16\-bit extension
+.ie n .IP """\-m[no\-]dx\-regs""" 4
+.el .IP "\f(CW\-m[no\-]dx\-regs\fR" 4
+.IX Item "-m[no-]dx-regs"
+Enable/Disable d0/d1 registers
+.ie n .IP """\-m[no\-]perf\-ext""" 4
+.el .IP "\f(CW\-m[no\-]perf\-ext\fR" 4
+.IX Item "-m[no-]perf-ext"
+Enable/Disable Performance extension
+.ie n .IP """\-m[no\-]perf2\-ext""" 4
+.el .IP "\f(CW\-m[no\-]perf2\-ext\fR" 4
+.IX Item "-m[no-]perf2-ext"
+Enable/Disable Performance extension 2
+.ie n .IP """\-m[no\-]string\-ext""" 4
+.el .IP "\f(CW\-m[no\-]string\-ext\fR" 4
+.IX Item "-m[no-]string-ext"
+Enable/Disable String extension
+.ie n .IP """\-m[no\-]reduced\-regs""" 4
+.el .IP "\f(CW\-m[no\-]reduced\-regs\fR" 4
+.IX Item "-m[no-]reduced-regs"
+Enable/Disable Reduced Register configuration (\s-1GPR16\s0) option
+.ie n .IP """\-m[no\-]audio\-isa\-ext""" 4
+.el .IP "\f(CW\-m[no\-]audio\-isa\-ext\fR" 4
+.IX Item "-m[no-]audio-isa-ext"
+Enable/Disable \s-1AUDIO ISA\s0 extension
+.ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4
+.el .IP "\f(CW\-m[no\-]fpu\-sp\-ext\fR" 4
+.IX Item "-m[no-]fpu-sp-ext"
+Enable/Disable \s-1FPU SP\s0 extension
+.ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4
+.el .IP "\f(CW\-m[no\-]fpu\-dp\-ext\fR" 4
+.IX Item "-m[no-]fpu-dp-ext"
+Enable/Disable \s-1FPU DP\s0 extension
+.ie n .IP """\-m[no\-]fpu\-fma""" 4
+.el .IP "\f(CW\-m[no\-]fpu\-fma\fR" 4
+.IX Item "-m[no-]fpu-fma"
+Enable/Disable \s-1FPU\s0 fused-multiply-add instructions
+.ie n .IP """\-mall\-ext""" 4
+.el .IP "\f(CW\-mall\-ext\fR" 4
+.IX Item "-mall-ext"
+Turn on all extensions and instructions support
+.PP
+The following options are available when as is configured for a
+PowerPC processor.
+.IP "\fB\-a32\fR" 4
+.IX Item "-a32"
+Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0
+.IP "\fB\-a64\fR" 4
+.IX Item "-a64"
+Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0
+.IP "\fB\-K \s-1PIC\s0\fR" 4
+.IX Item "-K PIC"
+Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags.
+.IP "\fB\-mpwrx | \-mpwr2\fR" 4
+.IX Item "-mpwrx | -mpwr2"
+Generate code for \s-1POWER/2 \s0(\s-1RIOS2\s0).
+.IP "\fB\-mpwr\fR" 4
+.IX Item "-mpwr"
+Generate code for \s-1POWER \s0(\s-1RIOS1\s0)
+.IP "\fB\-m601\fR" 4
+.IX Item "-m601"
+Generate code for PowerPC 601.
+.IP "\fB\-mppc, \-mppc32, \-m603, \-m604\fR" 4
+.IX Item "-mppc, -mppc32, -m603, -m604"
+Generate code for PowerPC 603/604.
+.IP "\fB\-m403, \-m405\fR" 4
+.IX Item "-m403, -m405"
+Generate code for PowerPC 403/405.
+.IP "\fB\-m440\fR" 4
+.IX Item "-m440"
+Generate code for PowerPC 440. BookE and some 405 instructions.
+.IP "\fB\-m464\fR" 4
+.IX Item "-m464"
+Generate code for PowerPC 464.
+.IP "\fB\-m476\fR" 4
+.IX Item "-m476"
+Generate code for PowerPC 476.
+.IP "\fB\-m7400, \-m7410, \-m7450, \-m7455\fR" 4
+.IX Item "-m7400, -m7410, -m7450, -m7455"
+Generate code for PowerPC 7400/7410/7450/7455.
+.IP "\fB\-m750cl\fR" 4
+.IX Item "-m750cl"
+Generate code for PowerPC 750CL.
+.IP "\fB\-m821, \-m850, \-m860\fR" 4
+.IX Item "-m821, -m850, -m860"
+Generate code for PowerPC 821/850/860.
+.IP "\fB\-mppc64, \-m620\fR" 4
+.IX Item "-mppc64, -m620"
+Generate code for PowerPC 620/625/630.
+.IP "\fB\-me500, \-me500x2\fR" 4
+.IX Item "-me500, -me500x2"
+Generate code for Motorola e500 core complex.
+.IP "\fB\-me500mc\fR" 4
+.IX Item "-me500mc"
+Generate code for Freescale e500mc core complex.
+.IP "\fB\-me500mc64\fR" 4
+.IX Item "-me500mc64"
+Generate code for Freescale e500mc64 core complex.
+.IP "\fB\-me5500\fR" 4
+.IX Item "-me5500"
+Generate code for Freescale e5500 core complex.
+.IP "\fB\-me6500\fR" 4
+.IX Item "-me6500"
+Generate code for Freescale e6500 core complex.
+.IP "\fB\-mspe\fR" 4
+.IX Item "-mspe"
+Generate code for Motorola \s-1SPE\s0 instructions.
+.IP "\fB\-mtitan\fR" 4
+.IX Item "-mtitan"
+Generate code for AppliedMicro Titan core complex.
+.IP "\fB\-mppc64bridge\fR" 4
+.IX Item "-mppc64bridge"
+Generate code for PowerPC 64, including bridge insns.
+.IP "\fB\-mbooke\fR" 4
+.IX Item "-mbooke"
+Generate code for 32\-bit BookE.
+.IP "\fB\-ma2\fR" 4
+.IX Item "-ma2"
+Generate code for A2 architecture.
+.IP "\fB\-me300\fR" 4
+.IX Item "-me300"
+Generate code for PowerPC e300 family.
+.IP "\fB\-maltivec\fR" 4
+.IX Item "-maltivec"
+Generate code for processors with AltiVec instructions.
+.IP "\fB\-mvle\fR" 4
+.IX Item "-mvle"
+Generate code for Freescale PowerPC \s-1VLE\s0 instructions.
+.IP "\fB\-mvsx\fR" 4
+.IX Item "-mvsx"
+Generate code for processors with Vector-Scalar (\s-1VSX\s0) instructions.
+.IP "\fB\-mhtm\fR" 4
+.IX Item "-mhtm"
+Generate code for processors with Hardware Transactional Memory instructions.
+.IP "\fB\-mpower4, \-mpwr4\fR" 4
+.IX Item "-mpower4, -mpwr4"
+Generate code for Power4 architecture.
+.IP "\fB\-mpower5, \-mpwr5, \-mpwr5x\fR" 4
+.IX Item "-mpower5, -mpwr5, -mpwr5x"
+Generate code for Power5 architecture.
+.IP "\fB\-mpower6, \-mpwr6\fR" 4
+.IX Item "-mpower6, -mpwr6"
+Generate code for Power6 architecture.
+.IP "\fB\-mpower7, \-mpwr7\fR" 4
+.IX Item "-mpower7, -mpwr7"
+Generate code for Power7 architecture.
+.IP "\fB\-mpower8, \-mpwr8\fR" 4
+.IX Item "-mpower8, -mpwr8"
+Generate code for Power8 architecture.
+.IP "\fB\-mpower9, \-mpwr9\fR" 4
+.IX Item "-mpower9, -mpwr9"
+Generate code for Power9 architecture.
+.IP "\fB\-mcell\fR" 4
+.IX Item "-mcell"
+.PD 0
+.IP "\fB\-mcell\fR" 4
+.IX Item "-mcell"
+.PD
+Generate code for Cell Broadband Engine architecture.
+.IP "\fB\-mcom\fR" 4
+.IX Item "-mcom"
+Generate code Power/PowerPC common instructions.
+.IP "\fB\-many\fR" 4
+.IX Item "-many"
+Generate code for any architecture (\s-1PWR/PWRX/PPC\s0).
+.IP "\fB\-mregnames\fR" 4
+.IX Item "-mregnames"
+Allow symbolic names for registers.
+.IP "\fB\-mno\-regnames\fR" 4
+.IX Item "-mno-regnames"
+Do not allow symbolic names for registers.
+.IP "\fB\-mrelocatable\fR" 4
+.IX Item "-mrelocatable"
+Support for \s-1GCC\s0's \-mrelocatable option.
+.IP "\fB\-mrelocatable\-lib\fR" 4
+.IX Item "-mrelocatable-lib"
+Support for \s-1GCC\s0's \-mrelocatable\-lib option.
+.IP "\fB\-memb\fR" 4
+.IX Item "-memb"
+Set \s-1PPC_EMB\s0 bit in \s-1ELF\s0 flags.
+.IP "\fB\-mlittle, \-mlittle\-endian, \-le\fR" 4
+.IX Item "-mlittle, -mlittle-endian, -le"
+Generate code for a little endian machine.
+.IP "\fB\-mbig, \-mbig\-endian, \-be\fR" 4
+.IX Item "-mbig, -mbig-endian, -be"
+Generate code for a big endian machine.
+.IP "\fB\-msolaris\fR" 4
+.IX Item "-msolaris"
+Generate code for Solaris.
+.IP "\fB\-mno\-solaris\fR" 4
+.IX Item "-mno-solaris"
+Do not generate code for Solaris.
+.IP "\fB\-nops=\fR\fIcount\fR" 4
+.IX Item "-nops=count"
+If an alignment directive inserts more than \fIcount\fR nops, put a
+branch at the beginning to skip execution of the nops.
+.PP
+The following options are available when as is configured for a
+RISC-V processor.
+.IP "\fB\-march=ISA\fR" 4
+.IX Item "-march=ISA"
+Select the base isa, as specified by \s-1ISA. \s0 For example \-march=rv32ima.
+.IP "\fB\-mabi=ABI\fR" 4
+.IX Item "-mabi=ABI"
+Selects the \s-1ABI,\s0 which is either \*(L"ilp32\*(R" or \*(L"lp64\*(R", optionally followed
+by \*(L"f\*(R", \*(L"d\*(R", or \*(L"q\*(R" to indicate single-precision, double-precision, or
+quad-precision floating-point calling convention, or none to indicate
+the soft-float calling convention.
+.PP
+See the info pages for documentation of the RX-specific options.
+.PP
+The following options are available when as is configured for the s390
+processor family.
+.IP "\fB\-m31\fR" 4
+.IX Item "-m31"
+.PD 0
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
+.PD
+Select the word size, either 31/32 bits or 64 bits.
+.IP "\fB\-mesa\fR" 4
+.IX Item "-mesa"
+.PD 0
+.IP "\fB\-mzarch\fR" 4
+.IX Item "-mzarch"
+.PD
+Select the architecture mode, either the Enterprise System
+Architecture (esa) or the z/Architecture mode (zarch).
+.IP "\fB\-march=\fR\fIprocessor\fR" 4
+.IX Item "-march=processor"
+Specify which s390 processor variant is the target, \fBg5\fR (or
+\&\fBarch3\fR), \fBg6\fR, \fBz900\fR (or \fBarch5\fR), \fBz990\fR (or
+\&\fBarch6\fR), \fBz9\-109\fR, \fBz9\-ec\fR (or \fBarch7\fR), \fBz10\fR (or
+\&\fBarch8\fR), \fBz196\fR (or \fBarch9\fR), \fBzEC12\fR (or \fBarch10\fR),
+\&\fBz13\fR (or \fBarch11\fR), or \fBarch12\fR.
+.IP "\fB\-mregnames\fR" 4
+.IX Item "-mregnames"
+.PD 0
+.IP "\fB\-mno\-regnames\fR" 4
+.IX Item "-mno-regnames"
+.PD
+Allow or disallow symbolic names for registers.
+.IP "\fB\-mwarn\-areg\-zero\fR" 4
+.IX Item "-mwarn-areg-zero"
+Warn whenever the operand for a base or index register has been specified
+but evaluates to zero.
+.PP
+The following options are available when as is configured for a
+\&\s-1TMS320C6000\s0 processor.
+.IP "\fB\-march=\fR\fIarch\fR" 4
+.IX Item "-march=arch"
+Enable (only) instructions from architecture \fIarch\fR. By default,
+all instructions are permitted.
+.Sp
+The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR,
+\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
+.IP "\fB\-mdsbt\fR" 4
+.IX Item "-mdsbt"
+.PD 0
+.IP "\fB\-mno\-dsbt\fR" 4
+.IX Item "-mno-dsbt"
+.PD
+The \fB\-mdsbt\fR option causes the assembler to generate the
+\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the
+code is using \s-1DSBT\s0 addressing. The \fB\-mno\-dsbt\fR option, the
+default, causes the tag to have a value of 0, indicating that the code
+does not use \s-1DSBT\s0 addressing. The linker will emit a warning if
+objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together.
+.IP "\fB\-mpid=no\fR" 4
+.IX Item "-mpid=no"
+.PD 0
+.IP "\fB\-mpid=near\fR" 4
+.IX Item "-mpid=near"
+.IP "\fB\-mpid=far\fR" 4
+.IX Item "-mpid=far"
+.PD
+The \fB\-mpid=\fR option causes the assembler to generate the
+\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data
+addressing used by the code. \fB\-mpid=no\fR, the default,
+indicates position-dependent data addressing, \fB\-mpid=near\fR
+indicates position-independent addressing with \s-1GOT\s0 accesses using near
+\&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent
+addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing. The linker will
+emit a warning if objects built with different settings of this option
+are linked together.
+.IP "\fB\-mpic\fR" 4
+.IX Item "-mpic"
+.PD 0
+.IP "\fB\-mno\-pic\fR" 4
+.IX Item "-mno-pic"
+.PD
+The \fB\-mpic\fR option causes the assembler to generate the
+\&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the
+code is using position-independent code addressing, The
+\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of
+0, indicating position-dependent code addressing. The linker will
+emit a warning if objects of different type (position-dependent and
+position-independent) are linked together.
+.IP "\fB\-mbig\-endian\fR" 4
+.IX Item "-mbig-endian"
+.PD 0
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+.PD
+Generate code for the specified endianness. The default is
+little-endian.
+.PP
+The following options are available when as is configured for a TILE-Gx
+processor.
+.IP "\fB\-m32 | \-m64\fR" 4
+.IX Item "-m32 | -m64"
+Select the word size, either 32 bits or 64 bits.
+.IP "\fB\-EB | \-EL\fR" 4
+.IX Item "-EB | -EL"
+Select the endianness, either big-endian (\-EB) or little-endian (\-EL).
+.PP
+The following option is available when as is configured for a Visium
+processor.
+.IP "\fB\-mtune=\fR\fIarch\fR" 4
+.IX Item "-mtune=arch"
+This option specifies the target architecture. If an attempt is made to
+assemble an instruction that will not execute on the target architecture,
+the assembler will issue an error message.
+.Sp
+The following names are recognized:
+\&\f(CW\*(C`mcm24\*(C'\fR
+\&\f(CW\*(C`mcm\*(C'\fR
+\&\f(CW\*(C`gr5\*(C'\fR
+\&\f(CW\*(C`gr6\*(C'\fR
+.PP
+The following options are available when as is configured for an
+Xtensa processor.
+.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
+.IX Item "--text-section-literals | --no-text-section-literals"
+Control the treatment of literal pools. The default is
+\&\fB\-\-no\-text\-section\-literals\fR, which places literals in
+separate sections in the output file. This allows the literal pool to be
+placed in a data \s-1RAM/ROM. \s0 With \fB\-\-text\-section\-literals\fR, the
+literals are interspersed in the text section in order to keep them as
+close as possible to their references. This may be necessary for large
+assembly files, where the literals would otherwise be out of range of the
+\&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into
+pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding
+\&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced
+via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode
+\&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
+.IP "\fB\-\-auto\-litpools | \-\-no\-auto\-litpools\fR" 4
+.IX Item "--auto-litpools | --no-auto-litpools"
+Control the treatment of literal pools. The default is
+\&\fB\-\-no\-auto\-litpools\fR, which in the absence of
+\&\fB\-\-text\-section\-literals\fR places literals in separate sections
+in the output file. This allows the literal pool to be placed in a data
+\&\s-1RAM/ROM. \s0 With \fB\-\-auto\-litpools\fR, the literals are interspersed
+in the text section in order to keep them as close as possible to their
+references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not
+required. This may be necessary for very large functions, where single
+literal pool at the beginning of the function may not be reachable by
+\&\f(CW\*(C`L32R\*(C'\fR instructions at the end. These options only affect
+literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals
+for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
+When used together with \fB\-\-text\-section\-literals\fR,
+\&\fB\-\-auto\-litpools\fR takes precedence.
+.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
+.IX Item "--absolute-literals | --no-absolute-literals"
+Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
+or PC-relative addressing. If the processor includes the absolute
+addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR
+relocations. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR relocations
+can be used.
+.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
+.IX Item "--target-align | --no-target-align"
+Enable or disable automatic alignment to reduce branch penalties at some
+expense in code size. This optimization is enabled by default. Note
+that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR that
+have fixed alignment requirements.
+.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
+.IX Item "--longcalls | --no-longcalls"
+Enable or disable transformation of call instructions to allow calls
+across a greater range of addresses. This option should be used when call
+targets can potentially be out of range. It may degrade both code size
+and performance, but the linker can generally optimize away the
+unnecessary overhead when a call ends up within range. The default is
+\&\fB\-\-no\-longcalls\fR.
+.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
+.IX Item "--transform | --no-transform"
+Enable or disable all assembler transformations of Xtensa instructions,
+including both relaxation and optimization. The default is
+\&\fB\-\-transform\fR; \fB\-\-no\-transform\fR should only be used in the
+rare cases when the instructions must be exactly as specified in the
+assembly source. Using \fB\-\-no\-transform\fR causes out of range
+instruction operands to be errors.
+.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
+.IX Item "--rename-section oldname=newname"
+Rename the \fIoldname\fR section to \fInewname\fR. This option can be used
+multiple times to rename multiple sections.
+.IP "\fB\-\-trampolines | \-\-no\-trampolines\fR" 4
+.IX Item "--trampolines | --no-trampolines"
+Enable or disable transformation of jump instructions to allow jumps
+across a greater range of addresses. This option should be used when jump targets can
+potentially be out of range. In the absence of such jumps this option
+does not affect code size or performance. The default is
+\&\fB\-\-trampolines\fR.
+.PP
+The following options are available when as is configured for
+a Z80 family processor.
+.IP "\fB\-z80\fR" 4
+.IX Item "-z80"
+Assemble for Z80 processor.
+.IP "\fB\-r800\fR" 4
+.IX Item "-r800"
+Assemble for R800 processor.
+.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
+.IX Item "-ignore-undocumented-instructions"
+.PD 0
+.IP "\fB\-Wnud\fR" 4
+.IX Item "-Wnud"
+.PD
+Assemble undocumented Z80 instructions that also work on R800 without warning.
+.IP "\fB\-ignore\-unportable\-instructions\fR" 4
+.IX Item "-ignore-unportable-instructions"
+.PD 0
+.IP "\fB\-Wnup\fR" 4
+.IX Item "-Wnup"
+.PD
+Assemble all undocumented Z80 instructions without warning.
+.IP "\fB\-warn\-undocumented\-instructions\fR" 4
+.IX Item "-warn-undocumented-instructions"
+.PD 0
+.IP "\fB\-Wud\fR" 4
+.IX Item "-Wud"
+.PD
+Issue a warning for undocumented Z80 instructions that also work on R800.
+.IP "\fB\-warn\-unportable\-instructions\fR" 4
+.IX Item "-warn-unportable-instructions"
+.PD 0
+.IP "\fB\-Wup\fR" 4
+.IX Item "-Wup"
+.PD
+Issue a warning for undocumented Z80 instructions that do not work on R800.
+.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
+.IX Item "-forbid-undocumented-instructions"
+.PD 0
+.IP "\fB\-Fud\fR" 4
+.IX Item "-Fud"
+.PD
+Treat all undocumented instructions as errors.
+.IP "\fB\-forbid\-unportable\-instructions\fR" 4
+.IX Item "-forbid-unportable-instructions"
+.PD 0
+.IP "\fB\-Fup\fR" 4
+.IX Item "-Fup"
+.PD
+Treat undocumented Z80 instructions that do not work on R800 as errors.
+.SH "SEE ALSO"
+.IX Header "SEE ALSO"
+\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
+.SH "COPYRIGHT"
+.IX Header "COPYRIGHT"
+Copyright (c) 1991\-2017 Free Software Foundation, Inc.
+.PP
+Permission is granted to copy, distribute and/or modify this document
+under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3
+or any later version published by the Free Software Foundation;
+with no Invariant Sections, with no Front-Cover Texts, and with no
+Back-Cover Texts. A copy of the license is included in the
+section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
diff --git a/gas/doc/as.info b/gas/doc/as.info
new file mode 100644
index 0000000..ca4fa5b
--- /dev/null
+++ b/gas/doc/as.info
@@ -0,0 +1,28078 @@
+This is as.info, produced by makeinfo version 4.8 from as.texinfo.
+
+INFO-DIR-SECTION Software development
+START-INFO-DIR-ENTRY
+* As: (as). The GNU assembler.
+* Gas: (as). The GNU assembler.
+END-INFO-DIR-ENTRY
+
+ This file documents the GNU Assembler "as".
+
+ Copyright (C) 1991-2017 Free Software Foundation, Inc.
+
+ Permission is granted to copy, distribute and/or modify this document
+under the terms of the GNU Free Documentation License, Version 1.3 or
+any later version published by the Free Software Foundation; with no
+Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
+Texts. A copy of the license is included in the section entitled "GNU
+Free Documentation License".
+
+
+File: as.info, Node: Top, Next: Overview, Up: (dir)
+
+Using as
+********
+
+This file is a user guide to the GNU assembler `as' (GNU Binutils)
+version 2.28.
+
+ This document is distributed under the terms of the GNU Free
+Documentation License. A copy of the license is included in the
+section entitled "GNU Free Documentation License".
+
+* Menu:
+
+* Overview:: Overview
+* Invoking:: Command-Line Options
+* Syntax:: Syntax
+* Sections:: Sections and Relocation
+* Symbols:: Symbols
+* Expressions:: Expressions
+* Pseudo Ops:: Assembler Directives
+
+* Object Attributes:: Object Attributes
+* Machine Dependencies:: Machine Dependent Features
+* Reporting Bugs:: Reporting Bugs
+* Acknowledgements:: Who Did What
+* GNU Free Documentation License:: GNU Free Documentation License
+* AS Index:: AS Index
+
+
+File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top
+
+1 Overview
+**********
+
+Here is a brief summary of how to invoke `as'. For details, see *Note
+Command-Line Options: Invoking.
+
+ as [-a[cdghlns][=FILE]] [-alternate] [-D]
+ [-compress-debug-sections] [-nocompress-debug-sections]
+ [-debug-prefix-map OLD=NEW]
+ [-defsym SYM=VAL] [-f] [-g] [-gstabs]
+ [-gstabs+] [-gdwarf-2] [-gdwarf-sections]
+ [-help] [-I DIR] [-J]
+ [-K] [-L] [-listing-lhs-width=NUM]
+ [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
+ [-listing-cont-lines=NUM] [-keep-locals]
+ [-no-pad-sections]
+ [-o OBJFILE] [-R]
+ [-hash-size=NUM] [-reduce-memory-overheads]
+ [-statistics]
+ [-v] [-version] [-version]
+ [-W] [-warn] [-fatal-warnings] [-w] [-x]
+ [-Z] [@FILE]
+ [-sectname-subst] [-size-check=[error|warning]]
+ [-elf-stt-common=[no|yes]]
+ [-target-help] [TARGET-OPTIONS]
+ [-|FILES ...]
+
+ _Target AArch64 options:_
+ [-EB|-EL]
+ [-mabi=ABI]
+
+ _Target Alpha options:_
+ [-mCPU]
+ [-mdebug | -no-mdebug]
+ [-replace | -noreplace]
+ [-relax] [-g] [-GSIZE]
+ [-F] [-32addr]
+
+ _Target ARC options:_
+ [-mcpu=CPU]
+ [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
+ [-mcode-density]
+ [-mrelax]
+ [-EB|-EL]
+
+ _Target ARM options:_
+ [-mcpu=PROCESSOR[+EXTENSION...]]
+ [-march=ARCHITECTURE[+EXTENSION...]]
+ [-mfpu=FLOATING-POINT-FORMAT]
+ [-mfloat-abi=ABI]
+ [-meabi=VER]
+ [-mthumb]
+ [-EB|-EL]
+ [-mapcs-32|-mapcs-26|-mapcs-float|
+ -mapcs-reentrant]
+ [-mthumb-interwork] [-k]
+
+ _Target Blackfin options:_
+ [-mcpu=PROCESSOR[-SIREVISION]]
+ [-mfdpic]
+ [-mno-fdpic]
+ [-mnopic]
+
+ _Target CRIS options:_
+ [-underscore | -no-underscore]
+ [-pic] [-N]
+ [-emulation=criself | -emulation=crisaout]
+ [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
+
+ _Target D10V options:_
+ [-O]
+
+ _Target D30V options:_
+ [-O|-n|-N]
+
+ _Target EPIPHANY options:_
+ [-mepiphany|-mepiphany16]
+
+ _Target H8/300 options:_
+ [-h-tick-hex]
+
+ _Target i386 options:_
+ [-32|-x32|-64] [-n]
+ [-march=CPU[+EXTENSION...]] [-mtune=CPU]
+
+ _Target i960 options:_
+ [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
+ -AKC|-AMC]
+ [-b] [-no-relax]
+
+ _Target IA-64 options:_
+ [-mconstant-gp|-mauto-pic]
+ [-milp32|-milp64|-mlp64|-mp64]
+ [-mle|mbe]
+ [-mtune=itanium1|-mtune=itanium2]
+ [-munwind-check=warning|-munwind-check=error]
+ [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
+ [-x|-xexplicit] [-xauto] [-xdebug]
+
+ _Target IP2K options:_
+ [-mip2022|-mip2022ext]
+
+ _Target M32C options:_
+ [-m32c|-m16c] [-relax] [-h-tick-hex]
+
+ _Target M32R options:_
+ [-m32rx|-[no-]warn-explicit-parallel-conflicts|
+ -W[n]p]
+
+ _Target M680X0 options:_
+ [-l] [-m68000|-m68010|-m68020|...]
+
+ _Target M68HC11 options:_
+ [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
+ [-mshort|-mlong]
+ [-mshort-double|-mlong-double]
+ [-force-long-branches] [-short-branches]
+ [-strict-direct-mode] [-print-insn-syntax]
+ [-print-opcodes] [-generate-example]
+
+ _Target MCORE options:_
+ [-jsri2bsr] [-sifilter] [-relax]
+ [-mcpu=[210|340]]
+
+ _Target Meta options:_
+ [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU]
+ _Target MICROBLAZE options:_
+
+ _Target MIPS options:_
+ [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
+ [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
+ [-non_shared] [-xgot [-mvxworks-pic]
+ [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
+ [-mfp64] [-mgp64] [-mfpxx]
+ [-modd-spreg] [-mno-odd-spreg]
+ [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
+ [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
+ [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
+ [-mips64r3] [-mips64r5] [-mips64r6]
+ [-construct-floats] [-no-construct-floats]
+ [-mignore-branch-isa] [-mno-ignore-branch-isa]
+ [-mnan=ENCODING]
+ [-trap] [-no-break] [-break] [-no-trap]
+ [-mips16] [-no-mips16]
+ [-mmicromips] [-mno-micromips]
+ [-msmartmips] [-mno-smartmips]
+ [-mips3d] [-no-mips3d]
+ [-mdmx] [-no-mdmx]
+ [-mdsp] [-mno-dsp]
+ [-mdspr2] [-mno-dspr2]
+ [-mdspr3] [-mno-dspr3]
+ [-mmsa] [-mno-msa]
+ [-mxpa] [-mno-xpa]
+ [-mmt] [-mno-mt]
+ [-mmcu] [-mno-mcu]
+ [-minsn32] [-mno-insn32]
+ [-mfix7000] [-mno-fix7000]
+ [-mfix-rm7000] [-mno-fix-rm7000]
+ [-mfix-vr4120] [-mno-fix-vr4120]
+ [-mfix-vr4130] [-mno-fix-vr4130]
+ [-mdebug] [-no-mdebug]
+ [-mpdr] [-mno-pdr]
+
+ _Target MMIX options:_
+ [-fixed-special-register-names] [-globalize-symbols]
+ [-gnu-syntax] [-relax] [-no-predefined-symbols]
+ [-no-expand] [-no-merge-gregs] [-x]
+ [-linker-allocated-gregs]
+
+ _Target Nios II options:_
+ [-relax-all] [-relax-section] [-no-relax]
+ [-EB] [-EL]
+
+ _Target NDS32 options:_
+ [-EL] [-EB] [-O] [-Os] [-mcpu=CPU]
+ [-misa=ISA] [-mabi=ABI] [-mall-ext]
+ [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
+ [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
+ [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
+ [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
+ [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
+ [-mb2bb]
+
+ _Target PDP11 options:_
+ [-mpic|-mno-pic] [-mall] [-mno-extensions]
+ [-mEXTENSION|-mno-EXTENSION]
+ [-mCPU] [-mMACHINE]
+
+ _Target picoJava options:_
+ [-mb|-me]
+
+ _Target PowerPC options:_
+ [-a32|-a64]
+ [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
+ -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
+ -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
+ -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
+ -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
+ -mcell|-mspe|-mtitan|-me300|-mcom]
+ [-many] [-maltivec|-mvsx|-mhtm|-mvle]
+ [-mregnames|-mno-regnames]
+ [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
+ [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
+ [-msolaris|-mno-solaris]
+ [-nops=COUNT]
+
+ _Target RL78 options:_
+ [-mg10]
+ [-m32bit-doubles|-m64bit-doubles]
+
+ _Target RX options:_
+ [-mlittle-endian|-mbig-endian]
+ [-m32bit-doubles|-m64bit-doubles]
+ [-muse-conventional-section-names]
+ [-msmall-data-limit]
+ [-mpid]
+ [-mrelax]
+ [-mint-register=NUMBER]
+ [-mgcc-abi|-mrx-abi]
+
+ _Target RISC-V options:_
+ [-march=ISA]
+ [-mabi=ABI]
+
+ _Target s390 options:_
+ [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
+ [-mregnames|-mno-regnames]
+ [-mwarn-areg-zero]
+
+ _Target SCORE options:_
+ [-EB][-EL][-FIXDD][-NWARN]
+ [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
+ [-march=score7][-march=score3]
+ [-USE_R1][-KPIC][-O0][-G NUM][-V]
+
+ _Target SPARC options:_
+ [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
+ -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
+ -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
+ -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
+ -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
+ -Asparcvisr|-Asparc5]
+ [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
+ -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
+ -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
+ -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
+ -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
+ -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
+ -bump]
+ [-32|-64]
+ [-enforce-aligned-data][-dcti-couples-detect]
+
+ _Target TIC54X options:_
+ [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
+ [-merrors-to-file <FILENAME>|-me <FILENAME>]
+
+ _Target TIC6X options:_
+ [-march=ARCH] [-mbig-endian|-mlittle-endian]
+ [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
+ [-mpic|-mno-pic]
+
+ _Target TILE-Gx options:_
+ [-m32|-m64][-EB][-EL]
+
+ _Target Visium options:_
+ [-mtune=ARCH]
+
+ _Target Xtensa options:_
+ [-[no-]text-section-literals] [-[no-]auto-litpools]
+ [-[no-]absolute-literals]
+ [-[no-]target-align] [-[no-]longcalls]
+ [-[no-]transform]
+ [-rename-section OLDNAME=NEWNAME]
+ [-[no-]trampolines]
+
+ _Target Z80 options:_
+ [-z80] [-r800]
+ [ -ignore-undocumented-instructions] [-Wnud]
+ [ -ignore-unportable-instructions] [-Wnup]
+ [ -warn-undocumented-instructions] [-Wud]
+ [ -warn-unportable-instructions] [-Wup]
+ [ -forbid-undocumented-instructions] [-Fud]
+ [ -forbid-unportable-instructions] [-Fup]
+
+`@FILE'
+ Read command-line options from FILE. The options read are
+ inserted in place of the original @FILE option. If FILE does not
+ exist, or cannot be read, then the option will be treated
+ literally, and not removed.
+
+ Options in FILE are separated by whitespace. A whitespace
+ character may be included in an option by surrounding the entire
+ option in either single or double quotes. Any character
+ (including a backslash) may be included by prefixing the character
+ to be included with a backslash. The FILE may itself contain
+ additional @FILE options; any such options will be processed
+ recursively.
+
+`-a[cdghlmns]'
+ Turn on listings, in any of a variety of ways:
+
+ `-ac'
+ omit false conditionals
+
+ `-ad'
+ omit debugging directives
+
+ `-ag'
+ include general information, like as version and options
+ passed
+
+ `-ah'
+ include high-level source
+
+ `-al'
+ include assembly
+
+ `-am'
+ include macro expansions
+
+ `-an'
+ omit forms processing
+
+ `-as'
+ include symbols
+
+ `=file'
+ set the name of the listing file
+
+ You may combine these options; for example, use `-aln' for assembly
+ listing without forms processing. The `=file' option, if used,
+ must be the last one. By itself, `-a' defaults to `-ahls'.
+
+`--alternate'
+ Begin in alternate macro mode. *Note `.altmacro': Altmacro.
+
+`--compress-debug-sections'
+ Compress DWARF debug sections using zlib with SHF_COMPRESSED from
+ the ELF ABI. The resulting object file may not be compatible with
+ older linkers and object file utilities. Note if compression
+ would make a given section _larger_ then it is not compressed.
+
+`--compress-debug-sections=none'
+`--compress-debug-sections=zlib'
+`--compress-debug-sections=zlib-gnu'
+`--compress-debug-sections=zlib-gabi'
+ These options control how DWARF debug sections are compressed.
+ `--compress-debug-sections=none' is equivalent to
+ `--nocompress-debug-sections'. `--compress-debug-sections=zlib'
+ and `--compress-debug-sections=zlib-gabi' are equivalent to
+ `--compress-debug-sections'. `--compress-debug-sections=zlib-gnu'
+ compresses DWARF debug sections using zlib. The debug sections
+ are renamed to begin with `.zdebug'. Note if compression would
+ make a given section _larger_ then it is not compressed nor
+ renamed.
+
+`--nocompress-debug-sections'
+ Do not compress DWARF debug sections. This is usually the default
+ for all targets except the x86/x86_64, but a configure time option
+ can be used to override this.
+
+`-D'
+ Ignored. This option is accepted for script compatibility with
+ calls to other assemblers.
+
+`--debug-prefix-map OLD=NEW'
+ When assembling files in directory `OLD', record debugging
+ information describing them as in `NEW' instead.
+
+`--defsym SYM=VALUE'
+ Define the symbol SYM to be VALUE before assembling the input file.
+ VALUE must be an integer constant. As in C, a leading `0x'
+ indicates a hexadecimal value, and a leading `0' indicates an octal
+ value. The value of the symbol can be overridden inside a source
+ file via the use of a `.set' pseudo-op.
+
+`-f'
+ "fast"--skip whitespace and comment preprocessing (assume source is
+ compiler output).
+
+`-g'
+`--gen-debug'
+ Generate debugging information for each assembler source line
+ using whichever debug format is preferred by the target. This
+ currently means either STABS, ECOFF or DWARF2.
+
+`--gstabs'
+ Generate stabs debugging information for each assembler line. This
+ may help debugging assembler code, if the debugger can handle it.
+
+`--gstabs+'
+ Generate stabs debugging information for each assembler line, with
+ GNU extensions that probably only gdb can handle, and that could
+ make other debuggers crash or refuse to read your program. This
+ may help debugging assembler code. Currently the only GNU
+ extension is the location of the current working directory at
+ assembling time.
+
+`--gdwarf-2'
+ Generate DWARF2 debugging information for each assembler line.
+ This may help debugging assembler code, if the debugger can handle
+ it. Note--this option is only supported by some targets, not all
+ of them.
+
+`--gdwarf-sections'
+ Instead of creating a .debug_line section, create a series of
+ .debug_line.FOO sections where FOO is the name of the
+ corresponding code section. For example a code section called
+ .TEXT.FUNC will have its dwarf line number information placed into
+ a section called .DEBUG_LINE.TEXT.FUNC. If the code section is
+ just called .TEXT then debug line section will still be called
+ just .DEBUG_LINE without any suffix.
+
+`--size-check=error'
+`--size-check=warning'
+ Issue an error or warning for invalid ELF .size directive.
+
+`--elf-stt-common=no'
+`--elf-stt-common=yes'
+ These options control whether the ELF assembler should generate
+ common symbols with the `STT_COMMON' type. The default can be
+ controlled by a configure option `--enable-elf-stt-common'.
+
+`--help'
+ Print a summary of the command line options and exit.
+
+`--target-help'
+ Print a summary of all target specific options and exit.
+
+`-I DIR'
+ Add directory DIR to the search list for `.include' directives.
+
+`-J'
+ Don't warn about signed overflow.
+
+`-K'
+ Issue warnings when difference tables altered for long
+ displacements.
+
+`-L'
+`--keep-locals'
+ Keep (in the symbol table) local symbols. These symbols start with
+ system-specific local label prefixes, typically `.L' for ELF
+ systems or `L' for traditional a.out systems. *Note Symbol
+ Names::.
+
+`--listing-lhs-width=NUMBER'
+ Set the maximum width, in words, of the output data column for an
+ assembler listing to NUMBER.
+
+`--listing-lhs-width2=NUMBER'
+ Set the maximum width, in words, of the output data column for
+ continuation lines in an assembler listing to NUMBER.
+
+`--listing-rhs-width=NUMBER'
+ Set the maximum width of an input source line, as displayed in a
+ listing, to NUMBER bytes.
+
+`--listing-cont-lines=NUMBER'
+ Set the maximum number of lines printed in a listing for a single
+ line of input to NUMBER + 1.
+
+`--no-pad-sections'
+ Stop the assembler for padding the ends of output sections to the
+ alignment of that section. The default is to pad the sections,
+ but this can waste space which might be needed on targets which
+ have tight memory constraints.
+
+`-o OBJFILE'
+ Name the object-file output from `as' OBJFILE.
+
+`-R'
+ Fold the data section into the text section.
+
+`--hash-size=NUMBER'
+ Set the default size of GAS's hash tables to a prime number close
+ to NUMBER. Increasing this value can reduce the length of time it
+ takes the assembler to perform its tasks, at the expense of
+ increasing the assembler's memory requirements. Similarly
+ reducing this value can reduce the memory requirements at the
+ expense of speed.
+
+`--reduce-memory-overheads'
+ This option reduces GAS's memory requirements, at the expense of
+ making the assembly processes slower. Currently this switch is a
+ synonym for `--hash-size=4051', but in the future it may have
+ other effects as well.
+
+`--sectname-subst'
+ Honor substitution sequences in section names. *Note `.section
+ NAME': Section Name Substitutions.
+
+`--statistics'
+ Print the maximum space (in bytes) and total time (in seconds)
+ used by assembly.
+
+`--strip-local-absolute'
+ Remove local absolute symbols from the outgoing symbol table.
+
+`-v'
+`-version'
+ Print the `as' version.
+
+`--version'
+ Print the `as' version and exit.
+
+`-W'
+`--no-warn'
+ Suppress warning messages.
+
+`--fatal-warnings'
+ Treat warnings as errors.
+
+`--warn'
+ Don't suppress warning messages or treat them as errors.
+
+`-w'
+ Ignored.
+
+`-x'
+ Ignored.
+
+`-Z'
+ Generate an object file even after errors.
+
+`-- | FILES ...'
+ Standard input, or source files to assemble.
+
+
+ *Note AArch64 Options::, for the options available when as is
+configured for the 64-bit mode of the ARM Architecture (AArch64).
+
+ *Note Alpha Options::, for the options available when as is
+configured for an Alpha processor.
+
+ The following options are available when as is configured for an ARC
+processor.
+
+`-mcpu=CPU'
+ This option selects the core processor variant.
+
+`-EB | -EL'
+ Select either big-endian (-EB) or little-endian (-EL) output.
+
+`-mcode-density'
+ Enable Code Density extenssion instructions.
+
+ The following options are available when as is configured for the ARM
+processor family.
+
+`-mcpu=PROCESSOR[+EXTENSION...]'
+ Specify which ARM processor variant is the target.
+
+`-march=ARCHITECTURE[+EXTENSION...]'
+ Specify which ARM architecture variant is used by the target.
+
+`-mfpu=FLOATING-POINT-FORMAT'
+ Select which Floating Point architecture is the target.
+
+`-mfloat-abi=ABI'
+ Select which floating point ABI is in use.
+
+`-mthumb'
+ Enable Thumb only instruction decoding.
+
+`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
+ Select which procedure calling convention is in use.
+
+`-EB | -EL'
+ Select either big-endian (-EB) or little-endian (-EL) output.
+
+`-mthumb-interwork'
+ Specify that the code has been generated with interworking between
+ Thumb and ARM code in mind.
+
+`-mccs'
+ Turns on CodeComposer Studio assembly syntax compatibility mode.
+
+`-k'
+ Specify that PIC code has been generated.
+
+ *Note Blackfin Options::, for the options available when as is
+configured for the Blackfin processor family.
+
+ See the info pages for documentation of the CRIS-specific options.
+
+ The following options are available when as is configured for a D10V
+processor.
+`-O'
+ Optimize output by parallelizing instructions.
+
+ The following options are available when as is configured for a D30V
+processor.
+`-O'
+ Optimize output by parallelizing instructions.
+
+`-n'
+ Warn when nops are generated.
+
+`-N'
+ Warn when a nop after a 32-bit multiply instruction is generated.
+
+ The following options are available when as is configured for the
+Adapteva EPIPHANY series.
+
+ *Note Epiphany Options::, for the options available when as is
+configured for an Epiphany processor.
+
+ *Note i386-Options::, for the options available when as is
+configured for an i386 processor.
+
+ The following options are available when as is configured for the
+Intel 80960 processor.
+
+`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
+ Specify which variant of the 960 architecture is the target.
+
+`-b'
+ Add code to collect statistics about branches taken.
+
+`-no-relax'
+ Do not alter compare-and-branch instructions for long
+ displacements; error if necessary.
+
+
+ The following options are available when as is configured for the
+Ubicom IP2K series.
+
+`-mip2022ext'
+ Specifies that the extended IP2022 instructions are allowed.
+
+`-mip2022'
+ Restores the default behaviour, which restricts the permitted
+ instructions to just the basic IP2022 ones.
+
+
+ The following options are available when as is configured for the
+Renesas M32C and M16C processors.
+
+`-m32c'
+ Assemble M32C instructions.
+
+`-m16c'
+ Assemble M16C instructions (the default).
+
+`-relax'
+ Enable support for link-time relaxations.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
+
+ The following options are available when as is configured for the
+Renesas M32R (formerly Mitsubishi M32R) series.
+
+`--m32rx'
+ Specify which processor in the M32R family is the target. The
+ default is normally the M32R, but this option changes it to the
+ M32RX.
+
+`--warn-explicit-parallel-conflicts or --Wp'
+ Produce warning messages when questionable parallel constructs are
+ encountered.
+
+`--no-warn-explicit-parallel-conflicts or --Wnp'
+ Do not produce warning messages when questionable parallel
+ constructs are encountered.
+
+
+ The following options are available when as is configured for the
+Motorola 68000 series.
+
+`-l'
+ Shorten references to undefined symbols, to one word instead of
+ two.
+
+`-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
+`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
+`| -m68333 | -m68340 | -mcpu32 | -m5200'
+ Specify what processor in the 68000 family is the target. The
+ default is normally the 68020, but this can be changed at
+ configuration time.
+
+`-m68881 | -m68882 | -mno-68881 | -mno-68882'
+ The target machine does (or does not) have a floating-point
+ coprocessor. The default is to assume a coprocessor for 68020,
+ 68030, and cpu32. Although the basic 68000 is not compatible with
+ the 68881, a combination of the two can be specified, since it's
+ possible to do emulation of the coprocessor instructions with the
+ main processor.
+
+`-m68851 | -mno-68851'
+ The target machine does (or does not) have a memory-management
+ unit coprocessor. The default is to assume an MMU for 68020 and
+ up.
+
+
+ *Note Nios II Options::, for the options available when as is
+configured for an Altera Nios II processor.
+
+ For details about the PDP-11 machine dependent features options, see
+*Note PDP-11-Options::.
+
+`-mpic | -mno-pic'
+ Generate position-independent (or position-dependent) code. The
+ default is `-mpic'.
+
+`-mall'
+`-mall-extensions'
+ Enable all instruction set extensions. This is the default.
+
+`-mno-extensions'
+ Disable all instruction set extensions.
+
+`-mEXTENSION | -mno-EXTENSION'
+ Enable (or disable) a particular instruction set extension.
+
+`-mCPU'
+ Enable the instruction set extensions supported by a particular
+ CPU, and disable all other extensions.
+
+`-mMACHINE'
+ Enable the instruction set extensions supported by a particular
+ machine model, and disable all other extensions.
+
+ The following options are available when as is configured for a
+picoJava processor.
+
+`-mb'
+ Generate "big endian" format output.
+
+`-ml'
+ Generate "little endian" format output.
+
+
+ The following options are available when as is configured for the
+Motorola 68HC11 or 68HC12 series.
+
+`-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg'
+ Specify what processor is the target. The default is defined by
+ the configuration option when building the assembler.
+
+`--xgate-ramoffset'
+ Instruct the linker to offset RAM addresses from S12X address
+ space into XGATE address space.
+
+`-mshort'
+ Specify to use the 16-bit integer ABI.
+
+`-mlong'
+ Specify to use the 32-bit integer ABI.
+
+`-mshort-double'
+ Specify to use the 32-bit double ABI.
+
+`-mlong-double'
+ Specify to use the 64-bit double ABI.
+
+`--force-long-branches'
+ Relative branches are turned into absolute ones. This concerns
+ conditional branches, unconditional branches and branches to a sub
+ routine.
+
+`-S | --short-branches'
+ Do not turn relative branches into absolute ones when the offset
+ is out of range.
+
+`--strict-direct-mode'
+ Do not turn the direct addressing mode into extended addressing
+ mode when the instruction does not support direct addressing mode.
+
+`--print-insn-syntax'
+ Print the syntax of instruction in case of error.
+
+`--print-opcodes'
+ Print the list of instructions with syntax and then exit.
+
+`--generate-example'
+ Print an example of instruction for each possible instruction and
+ then exit. This option is only useful for testing `as'.
+
+
+ The following options are available when `as' is configured for the
+SPARC architecture:
+
+`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
+`-Av8plus | -Av8plusa | -Av9 | -Av9a'
+ Explicitly select a variant of the SPARC architecture.
+
+ `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9'
+ and `-Av9a' select a 64 bit environment.
+
+ `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
+ UltraSPARC extensions.
+
+`-xarch=v8plus | -xarch=v8plusa'
+ For compatibility with the Solaris v9 assembler. These options are
+ equivalent to -Av8plus and -Av8plusa, respectively.
+
+`-bump'
+ Warn when the assembler switches to another architecture.
+
+ The following options are available when as is configured for the
+'c54x architecture.
+
+`-mfar-mode'
+ Enable extended addressing mode. All addresses and relocations
+ will assume extended addressing (usually 23 bits).
+
+`-mcpu=CPU_VERSION'
+ Sets the CPU version being compiled for.
+
+`-merrors-to-file FILENAME'
+ Redirect error output to a file, for broken systems which don't
+ support such behaviour in the shell.
+
+ The following options are available when as is configured for a MIPS
+processor.
+
+`-G NUM'
+ This option sets the largest size of an object that can be
+ referenced implicitly with the `gp' register. It is only accepted
+ for targets that use ECOFF format, such as a DECstation running
+ Ultrix. The default value is 8.
+
+`-EB'
+ Generate "big endian" format output.
+
+`-EL'
+ Generate "little endian" format output.
+
+`-mips1'
+`-mips2'
+`-mips3'
+`-mips4'
+`-mips5'
+`-mips32'
+`-mips32r2'
+`-mips32r3'
+`-mips32r5'
+`-mips32r6'
+`-mips64'
+`-mips64r2'
+`-mips64r3'
+`-mips64r5'
+`-mips64r6'
+ Generate code for a particular MIPS Instruction Set Architecture
+ level. `-mips1' is an alias for `-march=r3000', `-mips2' is an
+ alias for `-march=r6000', `-mips3' is an alias for `-march=r4000'
+ and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32',
+ `-mips32r2', `-mips32r3', `-mips32r5', `-mips32r6', `-mips64',
+ `-mips64r2', `-mips64r3', `-mips64r5', and `-mips64r6' correspond
+ to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3,
+ MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2,
+ MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA
+ processors, respectively.
+
+`-march=CPU'
+ Generate code for a particular MIPS CPU.
+
+`-mtune=CPU'
+ Schedule and tune for a particular MIPS CPU.
+
+`-mfix7000'
+`-mno-fix7000'
+ Cause nops to be inserted if the read of the destination register
+ of an mfhi or mflo instruction occurs in the following two
+ instructions.
+
+`-mfix-rm7000'
+`-mno-fix-rm7000'
+ Cause nops to be inserted if a dmult or dmultu instruction is
+ followed by a load instruction.
+
+`-mdebug'
+`-no-mdebug'
+ Cause stabs-style debugging output to go into an ECOFF-style
+ .mdebug section instead of the standard ELF .stabs sections.
+
+`-mpdr'
+`-mno-pdr'
+ Control generation of `.pdr' sections.
+
+`-mgp32'
+`-mfp32'
+ The register sizes are normally inferred from the ISA and ABI, but
+ these flags force a certain group of registers to be treated as 32
+ bits wide at all times. `-mgp32' controls the size of
+ general-purpose registers and `-mfp32' controls the size of
+ floating-point registers.
+
+`-mgp64'
+`-mfp64'
+ The register sizes are normally inferred from the ISA and ABI, but
+ these flags force a certain group of registers to be treated as 64
+ bits wide at all times. `-mgp64' controls the size of
+ general-purpose registers and `-mfp64' controls the size of
+ floating-point registers.
+
+`-mfpxx'
+ The register sizes are normally inferred from the ISA and ABI, but
+ using this flag in combination with `-mabi=32' enables an ABI
+ variant which will operate correctly with floating-point registers
+ which are 32 or 64 bits wide.
+
+`-modd-spreg'
+`-mno-odd-spreg'
+ Enable use of floating-point operations on odd-numbered
+ single-precision registers when supported by the ISA. `-mfpxx'
+ implies `-mno-odd-spreg', otherwise the default is `-modd-spreg'.
+
+`-mips16'
+`-no-mips16'
+ Generate code for the MIPS 16 processor. This is equivalent to
+ putting `.set mips16' at the start of the assembly file.
+ `-no-mips16' turns off this option.
+
+`-mmicromips'
+`-mno-micromips'
+ Generate code for the microMIPS processor. This is equivalent to
+ putting `.set micromips' at the start of the assembly file.
+ `-mno-micromips' turns off this option. This is equivalent to
+ putting `.set nomicromips' at the start of the assembly file.
+
+`-msmartmips'
+`-mno-smartmips'
+ Enables the SmartMIPS extension to the MIPS32 instruction set.
+ This is equivalent to putting `.set smartmips' at the start of the
+ assembly file. `-mno-smartmips' turns off this option.
+
+`-mips3d'
+`-no-mips3d'
+ Generate code for the MIPS-3D Application Specific Extension.
+ This tells the assembler to accept MIPS-3D instructions.
+ `-no-mips3d' turns off this option.
+
+`-mdmx'
+`-no-mdmx'
+ Generate code for the MDMX Application Specific Extension. This
+ tells the assembler to accept MDMX instructions. `-no-mdmx' turns
+ off this option.
+
+`-mdsp'
+`-mno-dsp'
+ Generate code for the DSP Release 1 Application Specific Extension.
+ This tells the assembler to accept DSP Release 1 instructions.
+ `-mno-dsp' turns off this option.
+
+`-mdspr2'
+`-mno-dspr2'
+ Generate code for the DSP Release 2 Application Specific Extension.
+ This option implies `-mdsp'. This tells the assembler to accept
+ DSP Release 2 instructions. `-mno-dspr2' turns off this option.
+
+`-mdspr3'
+`-mno-dspr3'
+ Generate code for the DSP Release 3 Application Specific Extension.
+ This option implies `-mdsp' and `-mdspr2'. This tells the
+ assembler to accept DSP Release 3 instructions. `-mno-dspr3'
+ turns off this option.
+
+`-mmsa'
+`-mno-msa'
+ Generate code for the MIPS SIMD Architecture Extension. This
+ tells the assembler to accept MSA instructions. `-mno-msa' turns
+ off this option.
+
+`-mxpa'
+`-mno-xpa'
+ Generate code for the MIPS eXtended Physical Address (XPA)
+ Extension. This tells the assembler to accept XPA instructions.
+ `-mno-xpa' turns off this option.
+
+`-mmt'
+`-mno-mt'
+ Generate code for the MT Application Specific Extension. This
+ tells the assembler to accept MT instructions. `-mno-mt' turns
+ off this option.
+
+`-mmcu'
+`-mno-mcu'
+ Generate code for the MCU Application Specific Extension. This
+ tells the assembler to accept MCU instructions. `-mno-mcu' turns
+ off this option.
+
+`-minsn32'
+`-mno-insn32'
+ Only use 32-bit instruction encodings when generating code for the
+ microMIPS processor. This option inhibits the use of any 16-bit
+ instructions. This is equivalent to putting `.set insn32' at the
+ start of the assembly file. `-mno-insn32' turns off this option.
+ This is equivalent to putting `.set noinsn32' at the start of the
+ assembly file. By default `-mno-insn32' is selected, allowing all
+ instructions to be used.
+
+`--construct-floats'
+`--no-construct-floats'
+ The `--no-construct-floats' option disables the construction of
+ double width floating point constants by loading the two halves of
+ the value into the two single width floating point registers that
+ make up the double width register. By default
+ `--construct-floats' is selected, allowing construction of these
+ floating point constants.
+
+`--relax-branch'
+`--no-relax-branch'
+ The `--relax-branch' option enables the relaxation of out-of-range
+ branches. By default `--no-relax-branch' is selected, causing any
+ out-of-range branches to produce an error.
+
+`-mignore-branch-isa'
+`-mno-ignore-branch-isa'
+ Ignore branch checks for invalid transitions between ISA modes.
+ The semantics of branches does not provide for an ISA mode switch,
+ so in most cases the ISA mode a branch has been encoded for has to
+ be the same as the ISA mode of the branch's target label.
+ Therefore GAS has checks implemented that verify in branch
+ assembly that the two ISA modes match. `-mignore-branch-isa'
+ disables these checks. By default `-mno-ignore-branch-isa' is
+ selected, causing any invalid branch requiring a transition
+ between ISA modes to produce an error.
+
+`-mnan=ENCODING'
+ Select between the IEEE 754-2008 (`-mnan=2008') or the legacy
+ (`-mnan=legacy') NaN encoding format. The latter is the default.
+
+`--emulation=NAME'
+ This option was formerly used to switch between ELF and ECOFF
+ output on targets like IRIX 5 that supported both. MIPS ECOFF
+ support was removed in GAS 2.24, so the option now serves little
+ purpose. It is retained for backwards compatibility.
+
+ The available configuration names are: `mipself', `mipslelf' and
+ `mipsbelf'. Choosing `mipself' now has no effect, since the output
+ is always ELF. `mipslelf' and `mipsbelf' select little- and
+ big-endian output respectively, but `-EL' and `-EB' are now the
+ preferred options instead.
+
+`-nocpp'
+ `as' ignores this option. It is accepted for compatibility with
+ the native tools.
+
+`--trap'
+`--no-trap'
+`--break'
+`--no-break'
+ Control how to deal with multiplication overflow and division by
+ zero. `--trap' or `--no-break' (which are synonyms) take a trap
+ exception (and only work for Instruction Set Architecture level 2
+ and higher); `--break' or `--no-trap' (also synonyms, and the
+ default) take a break exception.
+
+`-n'
+ When this option is used, `as' will issue a warning every time it
+ generates a nop instruction from a macro.
+
+ The following options are available when as is configured for an
+MCore processor.
+
+`-jsri2bsr'
+`-nojsri2bsr'
+ Enable or disable the JSRI to BSR transformation. By default this
+ is enabled. The command line option `-nojsri2bsr' can be used to
+ disable it.
+
+`-sifilter'
+`-nosifilter'
+ Enable or disable the silicon filter behaviour. By default this
+ is disabled. The default can be overridden by the `-sifilter'
+ command line option.
+
+`-relax'
+ Alter jump instructions for long displacements.
+
+`-mcpu=[210|340]'
+ Select the cpu type on the target hardware. This controls which
+ instructions can be assembled.
+
+`-EB'
+ Assemble for a big endian target.
+
+`-EL'
+ Assemble for a little endian target.
+
+
+ *Note Meta Options::, for the options available when as is configured
+for a Meta processor.
+
+ See the info pages for documentation of the MMIX-specific options.
+
+ *Note NDS32 Options::, for the options available when as is
+configured for a NDS32 processor.
+
+ *Note PowerPC-Opts::, for the options available when as is configured
+for a PowerPC processor.
+
+ *Note RISC-V-Opts::, for the options available when as is configured
+for a RISC-V processor.
+
+ See the info pages for documentation of the RX-specific options.
+
+ The following options are available when as is configured for the
+s390 processor family.
+
+`-m31'
+`-m64'
+ Select the word size, either 31/32 bits or 64 bits.
+
+`-mesa'
+
+`-mzarch'
+ Select the architecture mode, either the Enterprise System
+ Architecture (esa) or the z/Architecture mode (zarch).
+
+`-march=PROCESSOR'
+ Specify which s390 processor variant is the target, `g5' (or
+ `arch3'), `g6', `z900' (or `arch5'), `z990' (or `arch6'),
+ `z9-109', `z9-ec' (or `arch7'), `z10' (or `arch8'), `z196' (or
+ `arch9'), `zEC12' (or `arch10'), `z13' (or `arch11'), or `arch12'.
+
+`-mregnames'
+`-mno-regnames'
+ Allow or disallow symbolic names for registers.
+
+`-mwarn-areg-zero'
+ Warn whenever the operand for a base or index register has been
+ specified but evaluates to zero.
+
+ *Note TIC6X Options::, for the options available when as is
+configured for a TMS320C6000 processor.
+
+ *Note TILE-Gx Options::, for the options available when as is
+configured for a TILE-Gx processor.
+
+ *Note Visium Options::, for the options available when as is
+configured for a Visium processor.
+
+ *Note Xtensa Options::, for the options available when as is
+configured for an Xtensa processor.
+
+ The following options are available when as is configured for a Z80
+family processor.
+`-z80'
+ Assemble for Z80 processor.
+
+`-r800'
+ Assemble for R800 processor.
+
+`-ignore-undocumented-instructions'
+`-Wnud'
+ Assemble undocumented Z80 instructions that also work on R800
+ without warning.
+
+`-ignore-unportable-instructions'
+`-Wnup'
+ Assemble all undocumented Z80 instructions without warning.
+
+`-warn-undocumented-instructions'
+`-Wud'
+ Issue a warning for undocumented Z80 instructions that also work
+ on R800.
+
+`-warn-unportable-instructions'
+`-Wup'
+ Issue a warning for undocumented Z80 instructions that do not work
+ on R800.
+
+`-forbid-undocumented-instructions'
+`-Fud'
+ Treat all undocumented instructions as errors.
+
+`-forbid-unportable-instructions'
+`-Fup'
+ Treat undocumented Z80 instructions that do not work on R800 as
+ errors.
+
+* Menu:
+
+* Manual:: Structure of this Manual
+* GNU Assembler:: The GNU Assembler
+* Object Formats:: Object File Formats
+* Command Line:: Command Line
+* Input Files:: Input Files
+* Object:: Output (Object) File
+* Errors:: Error and Warning Messages
+
+
+File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview
+
+1.1 Structure of this Manual
+============================
+
+This manual is intended to describe what you need to know to use GNU
+`as'. We cover the syntax expected in source files, including notation
+for symbols, constants, and expressions; the directives that `as'
+understands; and of course how to invoke `as'.
+
+ This manual also describes some of the machine-dependent features of
+various flavors of the assembler.
+
+ On the other hand, this manual is _not_ intended as an introduction
+to programming in assembly language--let alone programming in general!
+In a similar vein, we make no attempt to introduce the machine
+architecture; we do _not_ describe the instruction set, standard
+mnemonics, registers or addressing modes that are standard to a
+particular architecture. You may want to consult the manufacturer's
+machine architecture manual for this information.
+
+
+File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview
+
+1.2 The GNU Assembler
+=====================
+
+GNU `as' is really a family of assemblers. If you use (or have used)
+the GNU assembler on one architecture, you should find a fairly similar
+environment when you use it on another architecture. Each version has
+much in common with the others, including object file formats, most
+assembler directives (often called "pseudo-ops") and assembler syntax.
+
+ `as' is primarily intended to assemble the output of the GNU C
+compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried
+to make `as' assemble correctly everything that other assemblers for
+the same machine would assemble. Any exceptions are documented
+explicitly (*note Machine Dependencies::). This doesn't mean `as'
+always uses the same syntax as another assembler for the same
+architecture; for example, we know of several incompatible versions of
+680x0 assembly language syntax.
+
+ Unlike older assemblers, `as' is designed to assemble a source
+program in one pass of the source file. This has a subtle impact on the
+`.org' directive (*note `.org': Org.).
+
+
+File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview
+
+1.3 Object File Formats
+=======================
+
+The GNU assembler can be configured to produce several alternative
+object file formats. For the most part, this does not affect how you
+write assembly language programs; but directives for debugging symbols
+are typically different in different file formats. *Note Symbol
+Attributes: Symbol Attributes.
+
+
+File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview
+
+1.4 Command Line
+================
+
+After the program name `as', the command line may contain options and
+file names. Options may appear in any order, and may be before, after,
+or between file names. The order of file names is significant.
+
+ `--' (two hyphens) by itself names the standard input file
+explicitly, as one of the files for `as' to assemble.
+
+ Except for `--' any command line argument that begins with a hyphen
+(`-') is an option. Each option changes the behavior of `as'. No
+option changes the way another option works. An option is a `-'
+followed by one or more letters; the case of the letter is important.
+All options are optional.
+
+ Some options expect exactly one file name to follow them. The file
+name may either immediately follow the option's letter (compatible with
+older assemblers) or it may be the next command argument (GNU
+standard). These two command lines are equivalent:
+
+ as -o my-object-file.o mumble.s
+ as -omy-object-file.o mumble.s
+
+
+File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview
+
+1.5 Input Files
+===============
+
+We use the phrase "source program", abbreviated "source", to describe
+the program input to one run of `as'. The program may be in one or
+more files; how the source is partitioned into files doesn't change the
+meaning of the source.
+
+ The source program is a concatenation of the text in all the files,
+in the order specified.
+
+ Each time you run `as' it assembles exactly one source program. The
+source program is made up of one or more files. (The standard input is
+also a file.)
+
+ You give `as' a command line that has zero or more input file names.
+The input files are read (from left file name to right). A command
+line argument (in any position) that has no special meaning is taken to
+be an input file name.
+
+ If you give `as' no file names it attempts to read one input file
+from the `as' standard input, which is normally your terminal. You may
+have to type <ctl-D> to tell `as' there is no more program to assemble.
+
+ Use `--' if you need to explicitly name the standard input file in
+your command line.
+
+ If the source is empty, `as' produces a small, empty object file.
+
+Filenames and Line-numbers
+--------------------------
+
+There are two ways of locating a line in the input file (or files) and
+either may be used in reporting error messages. One way refers to a
+line number in a physical file; the other refers to a line number in a
+"logical" file. *Note Error and Warning Messages: Errors.
+
+ "Physical files" are those files named in the command line given to
+`as'.
+
+ "Logical files" are simply names declared explicitly by assembler
+directives; they bear no relation to physical files. Logical file
+names help error messages reflect the original source file, when `as'
+source is itself synthesized from other files. `as' understands the
+`#' directives emitted by the `gcc' preprocessor. See also *Note
+`.file': File.
+
+
+File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview
+
+1.6 Output (Object) File
+========================
+
+Every time you run `as' it produces an output file, which is your
+assembly language program translated into numbers. This file is the
+object file. Its default name is `a.out'. You can give it another
+name by using the `-o' option. Conventionally, object file names end
+with `.o'. The default name is used for historical reasons: older
+assemblers were capable of assembling self-contained programs directly
+into a runnable program. (For some formats, this isn't currently
+possible, but it can be done for the `a.out' format.)
+
+ The object file is meant for input to the linker `ld'. It contains
+assembled program code, information to help `ld' integrate the
+assembled program into a runnable file, and (optionally) symbolic
+information for the debugger.
+
+
+File: as.info, Node: Errors, Prev: Object, Up: Overview
+
+1.7 Error and Warning Messages
+==============================
+
+`as' may write warnings and error messages to the standard error file
+(usually your terminal). This should not happen when a compiler runs
+`as' automatically. Warnings report an assumption made so that `as'
+could keep assembling a flawed program; errors report a grave problem
+that stops the assembly.
+
+ Warning messages have the format
+
+ file_name:NNN:Warning Message Text
+
+(where NNN is a line number). If both a logical file name (*note
+`.file': File.) and a logical line number (*note `.line': Line.) have
+been given then they will be used, otherwise the file name and line
+number in the current assembler source file will be used. The message
+text is intended to be self explanatory (in the grand Unix tradition).
+
+ Note the file name must be set via the logical version of the `.file'
+directive, not the DWARF2 version of the `.file' directive. For
+example:
+
+ .file 2 "bar.c"
+ error_assembler_source
+ .file "foo.c"
+ .line 30
+ error_c_source
+
+ produces this output:
+
+ Assembler messages:
+ asm.s:2: Error: no such instruction: `error_assembler_source'
+ foo.c:31: Error: no such instruction: `error_c_source'
+
+ Error messages have the format
+
+ file_name:NNN:FATAL:Error Message Text
+
+ The file name and line number are derived as for warning messages.
+The actual message text may be rather less explanatory because many of
+them aren't supposed to happen.
+
+
+File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top
+
+2 Command-Line Options
+**********************
+
+This chapter describes command-line options available in _all_ versions
+of the GNU assembler; see *Note Machine Dependencies::, for options
+specific to particular machine architectures.
+
+ If you are invoking `as' via the GNU C compiler, you can use the
+`-Wa' option to pass arguments through to the assembler. The assembler
+arguments must be separated from each other (and the `-Wa') by commas.
+For example:
+
+ gcc -c -g -O -Wa,-alh,-L file.c
+
+This passes two options to the assembler: `-alh' (emit a listing to
+standard output with high-level and assembly source) and `-L' (retain
+local symbols in the symbol table).
+
+ Usually you do not need to use this `-Wa' mechanism, since many
+compiler command-line options are automatically passed to the assembler
+by the compiler. (You can call the GNU compiler driver with the `-v'
+option to see precisely what options it passes to each compilation
+pass, including the assembler.)
+
+* Menu:
+
+* a:: -a[cdghlns] enable listings
+* alternate:: --alternate enable alternate macro syntax
+* D:: -D for compatibility
+* f:: -f to work faster
+* I:: -I for .include search path
+
+* K:: -K for difference tables
+
+* L:: -L to retain local symbols
+* listing:: --listing-XXX to configure listing output
+* M:: -M or --mri to assemble in MRI compatibility mode
+* MD:: --MD for dependency tracking
+* no-pad-sections:: --no-pad-sections to stop section padding
+* o:: -o to name the object file
+* R:: -R to join data and text sections
+* statistics:: --statistics to see statistics about assembly
+* traditional-format:: --traditional-format for compatible output
+* v:: -v to announce version
+* W:: -W, --no-warn, --warn, --fatal-warnings to control warnings
+* Z:: -Z to make object file even after errors
+
+
+File: as.info, Node: a, Next: alternate, Up: Invoking
+
+2.1 Enable Listings: `-a[cdghlns]'
+==================================
+
+These options enable listing output from the assembler. By itself,
+`-a' requests high-level, assembly, and symbols listing. You can use
+other letters to select specific options for the list: `-ah' requests a
+high-level language listing, `-al' requests an output-program assembly
+listing, and `-as' requests a symbol table listing. High-level
+listings require that a compiler debugging option like `-g' be used,
+and that assembly listings (`-al') be requested also.
+
+ Use the `-ag' option to print a first section with general assembly
+information, like as version, switches passed, or time stamp.
+
+ Use the `-ac' option to omit false conditionals from a listing. Any
+lines which are not assembled because of a false `.if' (or `.ifdef', or
+any other conditional), or a true `.if' followed by an `.else', will be
+omitted from the listing.
+
+ Use the `-ad' option to omit debugging directives from the listing.
+
+ Once you have specified one of these options, you can further control
+listing output and its appearance using the directives `.list',
+`.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an'
+option turns off all forms processing. If you do not request listing
+output with one of the `-a' options, the listing-control directives
+have no effect.
+
+ The letters after `-a' may be combined into one option, _e.g._,
+`-aln'.
+
+ Note if the assembler source is coming from the standard input (e.g.,
+because it is being created by `gcc' and the `-pipe' command line switch
+is being used) then the listing will not contain any comments or
+preprocessor directives. This is because the listing code buffers
+input source lines from stdin only after they have been preprocessed by
+the assembler. This reduces memory usage and makes the code more
+efficient.
+
+
+File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking
+
+2.2 `--alternate'
+=================
+
+Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
+
+
+File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking
+
+2.3 `-D'
+========
+
+This option has no effect whatsoever, but it is accepted to make it more
+likely that scripts written for other assemblers also work with `as'.
+
+
+File: as.info, Node: f, Next: I, Prev: D, Up: Invoking
+
+2.4 Work Faster: `-f'
+=====================
+
+`-f' should only be used when assembling programs written by a
+(trusted) compiler. `-f' stops the assembler from doing whitespace and
+comment preprocessing on the input file(s) before assembling them.
+*Note Preprocessing: Preprocessing.
+
+ _Warning:_ if you use `-f' when the files actually need to be
+ preprocessed (if they contain comments, for example), `as' does
+ not work correctly.
+
+
+File: as.info, Node: I, Next: K, Prev: f, Up: Invoking
+
+2.5 `.include' Search Path: `-I' PATH
+=====================================
+
+Use this option to add a PATH to the list of directories `as' searches
+for files specified in `.include' directives (*note `.include':
+Include.). You may use `-I' as many times as necessary to include a
+variety of paths. The current working directory is always searched
+first; after that, `as' searches any `-I' directories in the same order
+as they were specified (left to right) on the command line.
+
+
+File: as.info, Node: K, Next: L, Prev: I, Up: Invoking
+
+2.6 Difference Tables: `-K'
+===========================
+
+`as' sometimes alters the code emitted for directives of the form
+`.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option
+if you want a warning issued when this is done.
+
+
+File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking
+
+2.7 Include Local Symbols: `-L'
+===============================
+
+Symbols beginning with system-specific local label prefixes, typically
+`.L' for ELF systems or `L' for traditional a.out systems, are called
+"local symbols". *Note Symbol Names::. Normally you do not see such
+symbols when debugging, because they are intended for the use of
+programs (like compilers) that compose assembler programs, not for your
+notice. Normally both `as' and `ld' discard such symbols, so you do
+not normally debug with them.
+
+ This option tells `as' to retain those local symbols in the object
+file. Usually if you do this you also tell the linker `ld' to preserve
+those symbols.
+
+
+File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking
+
+2.8 Configuring listing output: `--listing'
+===========================================
+
+The listing feature of the assembler can be enabled via the command
+line switch `-a' (*note a::). This feature combines the input source
+file(s) with a hex dump of the corresponding locations in the output
+object file, and displays them as a listing file. The format of this
+listing can be controlled by directives inside the assembler source
+(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl'
+(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::)
+and also by the following switches:
+
+`--listing-lhs-width=`number''
+ Sets the maximum width, in words, of the first line of the hex
+ byte dump. This dump appears on the left hand side of the listing
+ output.
+
+`--listing-lhs-width2=`number''
+ Sets the maximum width, in words, of any further lines of the hex
+ byte dump for a given input source line. If this value is not
+ specified, it defaults to being the same as the value specified
+ for `--listing-lhs-width'. If neither switch is used the default
+ is to one.
+
+`--listing-rhs-width=`number''
+ Sets the maximum width, in characters, of the source line that is
+ displayed alongside the hex dump. The default value for this
+ parameter is 100. The source line is displayed on the right hand
+ side of the listing output.
+
+`--listing-cont-lines=`number''
+ Sets the maximum number of continuation lines of hex dump that
+ will be displayed for a given single line of source input. The
+ default value is 4.
+
+
+File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking
+
+2.9 Assemble in MRI Compatibility Mode: `-M'
+============================================
+
+The `-M' or `--mri' option selects MRI compatibility mode. This
+changes the syntax and pseudo-op handling of `as' to make it compatible
+with the `ASM68K' or the `ASM960' (depending upon the configured
+target) assembler from Microtec Research. The exact nature of the MRI
+syntax will not be documented here; see the MRI manuals for more
+information. Note in particular that the handling of macros and macro
+arguments is somewhat different. The purpose of this option is to
+permit assembling existing MRI assembler code using `as'.
+
+ The MRI compatibility is not complete. Certain operations of the
+MRI assembler depend upon its object file format, and can not be
+supported using other object file formats. Supporting these would
+require enhancing each object file format individually. These are:
+
+ * global symbols in common section
+
+ The m68k MRI assembler supports common sections which are merged
+ by the linker. Other object file formats do not support this.
+ `as' handles common sections by treating them as a single common
+ symbol. It permits local symbols to be defined within a common
+ section, but it can not support global symbols, since it has no
+ way to describe them.
+
+ * complex relocations
+
+ The MRI assemblers support relocations against a negated section
+ address, and relocations which combine the start addresses of two
+ or more sections. These are not support by other object file
+ formats.
+
+ * `END' pseudo-op specifying start address
+
+ The MRI `END' pseudo-op permits the specification of a start
+ address. This is not supported by other object file formats. The
+ start address may instead be specified using the `-e' option to
+ the linker, or in a linker script.
+
+ * `IDNT', `.ident' and `NAME' pseudo-ops
+
+ The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module
+ name to the output file. This is not supported by other object
+ file formats.
+
+ * `ORG' pseudo-op
+
+ The m68k MRI `ORG' pseudo-op begins an absolute section at a given
+ address. This differs from the usual `as' `.org' pseudo-op, which
+ changes the location within the current section. Absolute
+ sections are not supported by other object file formats. The
+ address of a section may be assigned within a linker script.
+
+ There are some other features of the MRI assembler which are not
+supported by `as', typically either because they are difficult or
+because they seem of little consequence. Some of these may be
+supported in future releases.
+
+ * EBCDIC strings
+
+ EBCDIC strings are not supported.
+
+ * packed binary coded decimal
+
+ Packed binary coded decimal is not supported. This means that the
+ `DC.P' and `DCB.P' pseudo-ops are not supported.
+
+ * `FEQU' pseudo-op
+
+ The m68k `FEQU' pseudo-op is not supported.
+
+ * `NOOBJ' pseudo-op
+
+ The m68k `NOOBJ' pseudo-op is not supported.
+
+ * `OPT' branch control options
+
+ The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL',
+ and `BRW'--are ignored. `as' automatically relaxes all branches,
+ whether forward or backward, to an appropriate size, so these
+ options serve no purpose.
+
+ * `OPT' list control options
+
+ The following m68k `OPT' list control options are ignored: `C',
+ `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'.
+
+ * other `OPT' options
+
+ The following m68k `OPT' options are ignored: `NEST', `O', `OLD',
+ `OP', `P', `PCO', `PCR', `PCS', `R'.
+
+ * `OPT' `D' option is default
+
+ The m68k `OPT' `D' option is the default, unlike the MRI assembler.
+ `OPT NOD' may be used to turn it off.
+
+ * `XREF' pseudo-op.
+
+ The m68k `XREF' pseudo-op is ignored.
+
+ * `.debug' pseudo-op
+
+ The i960 `.debug' pseudo-op is not supported.
+
+ * `.extended' pseudo-op
+
+ The i960 `.extended' pseudo-op is not supported.
+
+ * `.list' pseudo-op.
+
+ The various options of the i960 `.list' pseudo-op are not
+ supported.
+
+ * `.optimize' pseudo-op
+
+ The i960 `.optimize' pseudo-op is not supported.
+
+ * `.output' pseudo-op
+
+ The i960 `.output' pseudo-op is not supported.
+
+ * `.setreal' pseudo-op
+
+ The i960 `.setreal' pseudo-op is not supported.
+
+
+
+File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking
+
+2.10 Dependency Tracking: `--MD'
+================================
+
+`as' can generate a dependency file for the file it creates. This file
+consists of a single rule suitable for `make' describing the
+dependencies of the main source file.
+
+ The rule is written to the file named in its argument.
+
+ This feature is used in the automatic updating of makefiles.
+
+
+File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking
+
+2.11 Output Section Padding
+===========================
+
+Normally the assembler will pad the end of each output section up to its
+alignment boundary. But this can waste space, which can be significant
+on memory constrained targets. So the `--no-pad-sections' option will
+disable this behaviour.
+
+
+File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking
+
+2.12 Name the Object File: `-o'
+===============================
+
+There is always one object file output when you run `as'. By default
+it has the name `a.out' (or `b.out', for Intel 960 targets only). You
+use this option (which takes exactly one filename) to give the object
+file a different name.
+
+ Whatever the object file is called, `as' overwrites any existing
+file of the same name.
+
+
+File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking
+
+2.13 Join Data and Text Sections: `-R'
+======================================
+
+`-R' tells `as' to write the object file as if all data-section data
+lives in the text section. This is only done at the very last moment:
+your binary data are the same, but data section parts are relocated
+differently. The data section part of your object file is zero bytes
+long because all its bytes are appended to the text section. (*Note
+Sections and Relocation: Sections.)
+
+ When you specify `-R' it would be possible to generate shorter
+address displacements (because we do not have to cross between text and
+data section). We refrain from doing this simply for compatibility with
+older versions of `as'. In future, `-R' may work this way.
+
+ When `as' is configured for COFF or ELF output, this option is only
+useful if you use sections named `.text' and `.data'.
+
+ `-R' is not supported for any of the HPPA targets. Using `-R'
+generates a warning from `as'.
+
+
+File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking
+
+2.14 Display Assembly Statistics: `--statistics'
+================================================
+
+Use `--statistics' to display two statistics about the resources used by
+`as': the maximum amount of space allocated during the assembly (in
+bytes), and the total execution time taken for the assembly (in CPU
+seconds).
+
+
+File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking
+
+2.15 Compatible Output: `--traditional-format'
+==============================================
+
+For some targets, the output of `as' is different in some ways from the
+output of some existing assembler. This switch requests `as' to use
+the traditional format instead.
+
+ For example, it disables the exception frame optimizations which
+`as' normally does by default on `gcc' output.
+
+
+File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking
+
+2.16 Announce Version: `-v'
+===========================
+
+You can find out what version of as is running by including the option
+`-v' (which you can also spell as `-version') on the command line.
+
+
+File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking
+
+2.17 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings'
+======================================================================
+
+`as' should never give a warning or error message when assembling
+compiler output. But programs written by people often cause `as' to
+give a warning that a particular assumption was made. All such
+warnings are directed to the standard error file.
+
+ If you use the `-W' and `--no-warn' options, no warnings are issued.
+This only affects the warning messages: it does not change any
+particular of how `as' assembles your file. Errors, which stop the
+assembly, are still reported.
+
+ If you use the `--fatal-warnings' option, `as' considers files that
+generate warnings to be in error.
+
+ You can switch these options off again by specifying `--warn', which
+causes warnings to be output as usual.
+
+
+File: as.info, Node: Z, Prev: W, Up: Invoking
+
+2.18 Generate Object File in Spite of Errors: `-Z'
+==================================================
+
+After an error message, `as' normally produces no output. If for some
+reason you are interested in object file output even after `as' gives
+an error message on your program, use the `-Z' option. If there are
+any errors, `as' continues anyways, and writes an object file after a
+final warning message of the form `N errors, M warnings, generating bad
+object file.'
+
+
+File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top
+
+3 Syntax
+********
+
+This chapter describes the machine-independent syntax allowed in a
+source file. `as' syntax is similar to what many other assemblers use;
+it is inspired by the BSD 4.2 assembler, except that `as' does not
+assemble Vax bit-fields.
+
+* Menu:
+
+* Preprocessing:: Preprocessing
+* Whitespace:: Whitespace
+* Comments:: Comments
+* Symbol Intro:: Symbols
+* Statements:: Statements
+* Constants:: Constants
+
+
+File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax
+
+3.1 Preprocessing
+=================
+
+The `as' internal preprocessor:
+ * adjusts and removes extra whitespace. It leaves one space or tab
+ before the keywords on a line, and turns any other whitespace on
+ the line into a single space.
+
+ * removes all comments, replacing them with a single space, or an
+ appropriate number of newlines.
+
+ * converts character constants into the appropriate numeric values.
+
+ It does not do macro processing, include file handling, or anything
+else you may get from your C compiler's preprocessor. You can do
+include file processing with the `.include' directive (*note
+`.include': Include.). You can use the GNU C compiler driver to get
+other "CPP" style preprocessing by giving the input file a `.S' suffix.
+*Note Options Controlling the Kind of Output: (gcc info)Overall
+Options.
+
+ Excess whitespace, comments, and character constants cannot be used
+in the portions of the input text that are not preprocessed.
+
+ If the first line of an input file is `#NO_APP' or if you use the
+`-f' option, whitespace and comments are not removed from the input
+file. Within an input file, you can ask for whitespace and comment
+removal in specific portions of the by putting a line that says `#APP'
+before the text that may contain whitespace or comments, and putting a
+line that says `#NO_APP' after this text. This feature is mainly
+intend to support `asm' statements in compilers whose output is
+otherwise free of comments and whitespace.
+
+
+File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax
+
+3.2 Whitespace
+==============
+
+"Whitespace" is one or more blanks or tabs, in any order. Whitespace
+is used to separate symbols, and to make programs neater for people to
+read. Unless within character constants (*note Character Constants:
+Characters.), any whitespace means the same as exactly one space.
+
+
+File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax
+
+3.3 Comments
+============
+
+There are two ways of rendering comments to `as'. In both cases the
+comment is equivalent to one space.
+
+ Anything from `/*' through the next `*/' is a comment. This means
+you may not nest these comments.
+
+ /*
+ The only way to include a newline ('\n') in a comment
+ is to use this sort of comment.
+ */
+
+ /* This sort of comment does not nest. */
+
+ Anything from a "line comment" character up to the next newline is
+considered a comment and is ignored. The line comment character is
+target specific, and some targets multiple comment characters. Some
+targets also have line comment characters that only work if they are
+the first character on a line. Some targets use a sequence of two
+characters to introduce a line comment. Some targets can also change
+their line comment characters depending upon command line options that
+have been used. For more details see the _Syntax_ section in the
+documentation for individual targets.
+
+ If the line comment character is the hash sign (`#') then it still
+has the special ability to enable and disable preprocessing (*note
+Preprocessing::) and to specify logical line numbers:
+
+ To be compatible with past assemblers, lines that begin with `#'
+have a special interpretation. Following the `#' should be an absolute
+expression (*note Expressions::): the logical line number of the _next_
+line. Then a string (*note Strings: Strings.) is allowed: if present
+it is a new logical file name. The rest of the line, if any, should be
+whitespace.
+
+ If the first non-whitespace characters on the line are not numeric,
+the line is ignored. (Just like a comment.)
+
+ # This is an ordinary comment.
+ # 42-6 "new_file_name" # New logical file name
+ # This is logical line # 36.
+ This feature is deprecated, and may disappear from future versions
+of `as'.
+
+
+File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax
+
+3.4 Symbols
+===========
+
+A "symbol" is one or more characters chosen from the set of all letters
+(both upper and lower case), digits and the three characters `_.$'. On
+most machines, you can also use `$' in symbol names; exceptions are
+noted in *Note Machine Dependencies::. No symbol may begin with a
+digit. Case is significant. There is no length limit; all characters
+are significant. Multibyte characters are supported. Symbols are
+delimited by characters not in that set, or by the beginning of a file
+(since the source program must end with a newline, the end of a file is
+not a possible symbol delimiter). *Note Symbols::.
+
+Symbol names may also be enclosed in double quote `"' characters. In
+such cases any characters are allowed, except for the NUL character.
+If a double quote character is to be included in the symbol name it
+must be preceeded by a backslash `\' character.
+
+
+File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax
+
+3.5 Statements
+==============
+
+A "statement" ends at a newline character (`\n') or a "line separator
+character". The line separator character is target specific and
+described in the _Syntax_ section of each target's documentation. Not
+all targets support a line separator character. The newline or line
+separator character is considered to be part of the preceding
+statement. Newlines and separators within character constants are an
+exception: they do not end statements.
+
+ It is an error to end any statement with end-of-file: the last
+character of any input file should be a newline.
+
+ An empty statement is allowed, and may include whitespace. It is
+ignored.
+
+ A statement begins with zero or more labels, optionally followed by a
+key symbol which determines what kind of statement it is. The key
+symbol determines the syntax of the rest of the statement. If the
+symbol begins with a dot `.' then the statement is an assembler
+directive: typically valid for any computer. If the symbol begins with
+a letter the statement is an assembly language "instruction": it
+assembles into a machine language instruction. Different versions of
+`as' for different computers recognize different instructions. In
+fact, the same symbol may represent a different instruction in a
+different computer's assembly language.
+
+ A label is a symbol immediately followed by a colon (`:').
+Whitespace before a label or after a colon is permitted, but you may not
+have whitespace between a label's symbol and its colon. *Note Labels::.
+
+ For HPPA targets, labels need not be immediately followed by a
+colon, but the definition of a label must begin in column zero. This
+also implies that only one label may be defined on each line.
+
+ label: .directive followed by something
+ another_label: # This is an empty statement.
+ instruction operand_1, operand_2, ...
+
+
+File: as.info, Node: Constants, Prev: Statements, Up: Syntax
+
+3.6 Constants
+=============
+
+A constant is a number, written so that its value is known by
+inspection, without knowing any context. Like this:
+ .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
+ .ascii "Ring the bell\7" # A string constant.
+ .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum.
+ .float 0f-314159265358979323846264338327\
+ 95028841971.693993751E-40 # - pi, a flonum.
+
+* Menu:
+
+* Characters:: Character Constants
+* Numbers:: Number Constants
+
+
+File: as.info, Node: Characters, Next: Numbers, Up: Constants
+
+3.6.1 Character Constants
+-------------------------
+
+There are two kinds of character constants. A "character" stands for
+one character in one byte and its value may be used in numeric
+expressions. String constants (properly called string _literals_) are
+potentially many bytes and their values may not be used in arithmetic
+expressions.
+
+* Menu:
+
+* Strings:: Strings
+* Chars:: Characters
+
+
+File: as.info, Node: Strings, Next: Chars, Up: Characters
+
+3.6.1.1 Strings
+...............
+
+A "string" is written between double-quotes. It may contain
+double-quotes or null characters. The way to get special characters
+into a string is to "escape" these characters: precede them with a
+backslash `\' character. For example `\\' represents one backslash:
+the first `\' is an escape which tells `as' to interpret the second
+character literally as a backslash (which prevents `as' from
+recognizing the second `\' as an escape character). The complete list
+of escapes follows.
+
+`\b'
+ Mnemonic for backspace; for ASCII this is octal code 010.
+
+`backslash-f'
+ Mnemonic for FormFeed; for ASCII this is octal code 014.
+
+`\n'
+ Mnemonic for newline; for ASCII this is octal code 012.
+
+`\r'
+ Mnemonic for carriage-Return; for ASCII this is octal code 015.
+
+`\t'
+ Mnemonic for horizontal Tab; for ASCII this is octal code 011.
+
+`\ DIGIT DIGIT DIGIT'
+ An octal character code. The numeric code is 3 octal digits. For
+ compatibility with other Unix systems, 8 and 9 are accepted as
+ digits: for example, `\008' has the value 010, and `\009' the
+ value 011.
+
+`\`x' HEX-DIGITS...'
+ A hex character code. All trailing hex digits are combined.
+ Either upper or lower case `x' works.
+
+`\\'
+ Represents one `\' character.
+
+`\"'
+ Represents one `"' character. Needed in strings to represent this
+ character, because an unescaped `"' would end the string.
+
+`\ ANYTHING-ELSE'
+ Any other character when escaped by `\' gives a warning, but
+ assembles as if the `\' was not present. The idea is that if you
+ used an escape sequence you clearly didn't want the literal
+ interpretation of the following character. However `as' has no
+ other interpretation, so `as' knows it is giving you the wrong
+ code and warns you of the fact.
+
+ Which characters are escapable, and what those escapes represent,
+varies widely among assemblers. The current set is what we think the
+BSD 4.2 assembler recognizes, and is a subset of what most C compilers
+recognize. If you are in doubt, do not use an escape sequence.
+
+
+File: as.info, Node: Chars, Prev: Strings, Up: Characters
+
+3.6.1.2 Characters
+..................
+
+A single character may be written as a single quote immediately
+followed by that character. Some backslash escapes apply to
+characters, `\b', `\f', `\n', `\r', `\t', and `\"' with the same meaning
+as for strings, plus `\'' for a single quote. So if you want to write
+the character backslash, you must write `'\\' where the first `\'
+escapes the second `\'. As you can see, the quote is an acute accent,
+not a grave accent. A newline immediately following an acute accent is
+taken as a literal character and does not count as the end of a
+statement. The value of a character constant in a numeric expression
+is the machine's byte-wide code for that character. `as' assumes your
+character code is ASCII: `'A' means 65, `'B' means 66, and so on.
+
+
+File: as.info, Node: Numbers, Prev: Characters, Up: Constants
+
+3.6.2 Number Constants
+----------------------
+
+`as' distinguishes three kinds of numbers according to how they are
+stored in the target machine. _Integers_ are numbers that would fit
+into an `int' in the C language. _Bignums_ are integers, but they are
+stored in more than 32 bits. _Flonums_ are floating point numbers,
+described below.
+
+* Menu:
+
+* Integers:: Integers
+* Bignums:: Bignums
+* Flonums:: Flonums
+
+
+File: as.info, Node: Integers, Next: Bignums, Up: Numbers
+
+3.6.2.1 Integers
+................
+
+A binary integer is `0b' or `0B' followed by zero or more of the binary
+digits `01'.
+
+ An octal integer is `0' followed by zero or more of the octal digits
+(`01234567').
+
+ A decimal integer starts with a non-zero digit followed by zero or
+more digits (`0123456789').
+
+ A hexadecimal integer is `0x' or `0X' followed by one or more
+hexadecimal digits chosen from `0123456789abcdefABCDEF'.
+
+ Integers have the usual values. To denote a negative integer, use
+the prefix operator `-' discussed under expressions (*note Prefix
+Operators: Prefix Ops.).
+
+
+File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers
+
+3.6.2.2 Bignums
+...............
+
+A "bignum" has the same syntax and semantics as an integer except that
+the number (or its negative) takes more than 32 bits to represent in
+binary. The distinction is made because in some places integers are
+permitted while bignums are not.
+
+
+File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers
+
+3.6.2.3 Flonums
+...............
+
+A "flonum" represents a floating point number. The translation is
+indirect: a decimal floating point number from the text is converted by
+`as' to a generic binary floating point number of more than sufficient
+precision. This generic floating point number is converted to a
+particular computer's floating point format (or formats) by a portion
+of `as' specialized to that computer.
+
+ A flonum is written by writing (in order)
+ * The digit `0'. (`0' is optional on the HPPA.)
+
+ * A letter, to tell `as' the rest of the number is a flonum. `e' is
+ recommended. Case is not important.
+
+ On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
+ letter must be one of the letters `DFPRSX' (in upper or lower
+ case).
+
+ On the ARC, the letter must be one of the letters `DFRS' (in upper
+ or lower case).
+
+ On the Intel 960 architecture, the letter must be one of the
+ letters `DFT' (in upper or lower case).
+
+ On the HPPA architecture, the letter must be `E' (upper case only).
+
+ * An optional sign: either `+' or `-'.
+
+ * An optional "integer part": zero or more decimal digits.
+
+ * An optional "fractional part": `.' followed by zero or more
+ decimal digits.
+
+ * An optional exponent, consisting of:
+
+ * An `E' or `e'.
+
+ * Optional sign: either `+' or `-'.
+
+ * One or more decimal digits.
+
+
+ At least one of the integer part or the fractional part must be
+present. The floating point number has the usual base-10 value.
+
+ `as' does all processing using integers. Flonums are computed
+independently of any floating point hardware in the computer running
+`as'.
+
+
+File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top
+
+4 Sections and Relocation
+*************************
+
+* Menu:
+
+* Secs Background:: Background
+* Ld Sections:: Linker Sections
+* As Sections:: Assembler Internal Sections
+* Sub-Sections:: Sub-Sections
+* bss:: bss Section
+
+
+File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections
+
+4.1 Background
+==============
+
+Roughly, a section is a range of addresses, with no gaps; all data "in"
+those addresses is treated the same for some particular purpose. For
+example there may be a "read only" section.
+
+ The linker `ld' reads many object files (partial programs) and
+combines their contents to form a runnable program. When `as' emits an
+object file, the partial program is assumed to start at address 0.
+`ld' assigns the final addresses for the partial program, so that
+different partial programs do not overlap. This is actually an
+oversimplification, but it suffices to explain how `as' uses sections.
+
+ `ld' moves blocks of bytes of your program to their run-time
+addresses. These blocks slide to their run-time addresses as rigid
+units; their length does not change and neither does the order of bytes
+within them. Such a rigid unit is called a _section_. Assigning
+run-time addresses to sections is called "relocation". It includes the
+task of adjusting mentions of object-file addresses so they refer to
+the proper run-time addresses. For the H8/300, and for the Renesas /
+SuperH SH, `as' pads sections if needed to ensure they end on a word
+(sixteen bit) boundary.
+
+ An object file written by `as' has at least three sections, any of
+which may be empty. These are named "text", "data" and "bss" sections.
+
+ When it generates COFF or ELF output, `as' can also generate
+whatever other named sections you specify using the `.section'
+directive (*note `.section': Section.). If you do not use any
+directives that place output in the `.text' or `.data' sections, these
+sections still exist, but are empty.
+
+ When `as' generates SOM or ELF output for the HPPA, `as' can also
+generate whatever other named sections you specify using the `.space'
+and `.subspace' directives. See `HP9000 Series 800 Assembly Language
+Reference Manual' (HP 92432-90001) for details on the `.space' and
+`.subspace' assembler directives.
+
+ Additionally, `as' uses different names for the standard text, data,
+and bss sections when generating SOM output. Program text is placed
+into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'.
+
+ Within the object file, the text section starts at address `0', the
+data section follows, and the bss section follows the data section.
+
+ When generating either SOM or ELF output files on the HPPA, the text
+section starts at address `0', the data section at address `0x4000000',
+and the bss section follows the data section.
+
+ To let `ld' know which data changes when the sections are relocated,
+and how to change that data, `as' also writes to the object file
+details of the relocation needed. To perform relocation `ld' must
+know, each time an address in the object file is mentioned:
+ * Where in the object file is the beginning of this reference to an
+ address?
+
+ * How long (in bytes) is this reference?
+
+ * Which section does the address refer to? What is the numeric
+ value of
+ (ADDRESS) - (START-ADDRESS OF SECTION)?
+
+ * Is the reference to an address "Program-Counter relative"?
+
+ In fact, every address `as' ever uses is expressed as
+ (SECTION) + (OFFSET INTO SECTION)
+ Further, most expressions `as' computes have this section-relative
+nature. (For some object formats, such as SOM for the HPPA, some
+expressions are symbol-relative instead.)
+
+ In this manual we use the notation {SECNAME N} to mean "offset N
+into section SECNAME."
+
+ Apart from text, data and bss sections you need to know about the
+"absolute" section. When `ld' mixes partial programs, addresses in the
+absolute section remain unchanged. For example, address `{absolute 0}'
+is "relocated" to run-time address 0 by `ld'. Although the linker
+never arranges two partial programs' data sections with overlapping
+addresses after linking, _by definition_ their absolute sections must
+overlap. Address `{absolute 239}' in one part of a program is always
+the same address when the program is running as address `{absolute
+239}' in any other part of the program.
+
+ The idea of sections is extended to the "undefined" section. Any
+address whose section is unknown at assembly time is by definition
+rendered {undefined U}--where U is filled in later. Since numbers are
+always defined, the only way to generate an undefined address is to
+mention an undefined symbol. A reference to a named common block would
+be such a symbol: its value is unknown at assembly time so it has
+section _undefined_.
+
+ By analogy the word _section_ is used to describe groups of sections
+in the linked program. `ld' puts all partial programs' text sections
+in contiguous addresses in the linked program. It is customary to
+refer to the _text section_ of a program, meaning all the addresses of
+all partial programs' text sections. Likewise for data and bss
+sections.
+
+ Some sections are manipulated by `ld'; others are invented for use
+of `as' and have no meaning except during assembly.
+
+
+File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections
+
+4.2 Linker Sections
+===================
+
+`ld' deals with just four kinds of sections, summarized below.
+
+*named sections*
+*text section*
+*data section*
+ These sections hold your program. `as' and `ld' treat them as
+ separate but equal sections. Anything you can say of one section
+ is true of another. When the program is running, however, it is
+ customary for the text section to be unalterable. The text
+ section is often shared among processes: it contains instructions,
+ constants and the like. The data section of a running program is
+ usually alterable: for example, C variables would be stored in the
+ data section.
+
+*bss section*
+ This section contains zeroed bytes when your program begins
+ running. It is used to hold uninitialized variables or common
+ storage. The length of each partial program's bss section is
+ important, but because it starts out containing zeroed bytes there
+ is no need to store explicit zero bytes in the object file. The
+ bss section was invented to eliminate those explicit zeros from
+ object files.
+
+*absolute section*
+ Address 0 of this section is always "relocated" to runtime address
+ 0. This is useful if you want to refer to an address that `ld'
+ must not change when relocating. In this sense we speak of
+ absolute addresses being "unrelocatable": they do not change
+ during relocation.
+
+*undefined section*
+ This "section" is a catch-all for address references to objects
+ not in the preceding sections.
+
+ An idealized example of three relocatable sections follows. The
+example uses the traditional section names `.text' and `.data'. Memory
+addresses are on the horizontal axis.
+
+ +-----+----+--+
+ partial program # 1: |ttttt|dddd|00|
+ +-----+----+--+
+
+ text data bss
+ seg. seg. seg.
+
+ +---+---+---+
+ partial program # 2: |TTT|DDD|000|
+ +---+---+---+
+
+ +--+---+-----+--+----+---+-----+~~
+ linked program: | |TTT|ttttt| |dddd|DDD|00000|
+ +--+---+-----+--+----+---+-----+~~
+
+ addresses: 0 ...
+
+
+File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections
+
+4.3 Assembler Internal Sections
+===============================
+
+These sections are meant only for the internal use of `as'. They have
+no meaning at run-time. You do not really need to know about these
+sections for most purposes; but they can be mentioned in `as' warning
+messages, so it might be helpful to have an idea of their meanings to
+`as'. These sections are used to permit the value of every expression
+in your assembly language program to be a section-relative address.
+
+ASSEMBLER-INTERNAL-LOGIC-ERROR!
+ An internal assembler logic error has been found. This means
+ there is a bug in the assembler.
+
+expr section
+ The assembler stores complex expression internally as combinations
+ of symbols. When it needs to represent an expression as a symbol,
+ it puts it in the expr section.
+
+
+File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections
+
+4.4 Sub-Sections
+================
+
+Assembled bytes conventionally fall into two sections: text and data.
+You may have separate groups of data in named sections that you want to
+end up near to each other in the object file, even though they are not
+contiguous in the assembler source. `as' allows you to use
+"subsections" for this purpose. Within each section, there can be
+numbered subsections with values from 0 to 8192. Objects assembled
+into the same subsection go into the object file together with other
+objects in the same subsection. For example, a compiler might want to
+store constants in the text section, but might not want to have them
+interspersed with the program being assembled. In this case, the
+compiler could issue a `.text 0' before each section of code being
+output, and a `.text 1' before each group of constants being output.
+
+Subsections are optional. If you do not use subsections, everything
+goes in subsection number zero.
+
+ Each subsection is zero-padded up to a multiple of four bytes.
+(Subsections may be padded a different amount on different flavors of
+`as'.)
+
+ Subsections appear in your object file in numeric order, lowest
+numbered to highest. (All this to be compatible with other people's
+assemblers.) The object file contains no representation of
+subsections; `ld' and other programs that manipulate object files see
+no trace of them. They just see all your text subsections as a text
+section, and all your data subsections as a data section.
+
+ To specify which subsection you want subsequent statements assembled
+into, use a numeric argument to specify it, in a `.text EXPRESSION' or
+a `.data EXPRESSION' statement. When generating COFF output, you can
+also use an extra subsection argument with arbitrary named sections:
+`.section NAME, EXPRESSION'. When generating ELF output, you can also
+use the `.subsection' directive (*note SubSection::) to specify a
+subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute
+expression (*note Expressions::). If you just say `.text' then `.text
+0' is assumed. Likewise `.data' means `.data 0'. Assembly begins in
+`text 0'. For instance:
+ .text 0 # The default subsection is text 0 anyway.
+ .ascii "This lives in the first text subsection. *"
+ .text 1
+ .ascii "But this lives in the second text subsection."
+ .data 0
+ .ascii "This lives in the data section,"
+ .ascii "in the first data subsection."
+ .text 0
+ .ascii "This lives in the first text section,"
+ .ascii "immediately following the asterisk (*)."
+
+ Each section has a "location counter" incremented by one for every
+byte assembled into that section. Because subsections are merely a
+convenience restricted to `as' there is no concept of a subsection
+location counter. There is no way to directly manipulate a location
+counter--but the `.align' directive changes it, and any label
+definition captures its current value. The location counter of the
+section where statements are being assembled is said to be the "active"
+location counter.
+
+
+File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections
+
+4.5 bss Section
+===============
+
+The bss section is used for local common variable storage. You may
+allocate address space in the bss section, but you may not dictate data
+to load into it before your program executes. When your program starts
+running, all the contents of the bss section are zeroed bytes.
+
+ The `.lcomm' pseudo-op defines a symbol in the bss section; see
+*Note `.lcomm': Lcomm.
+
+ The `.comm' pseudo-op may be used to declare a common symbol, which
+is another form of uninitialized symbol; see *Note `.comm': Comm.
+
+ When assembling for a target which supports multiple sections, such
+as ELF or COFF, you may switch into the `.bss' section and define
+symbols as usual; see *Note `.section': Section. You may only assemble
+zero values into the section. Typically the section will only contain
+symbol definitions and `.skip' directives (*note `.skip': Skip.).
+
+
+File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top
+
+5 Symbols
+*********
+
+Symbols are a central concept: the programmer uses symbols to name
+things, the linker uses symbols to link, and the debugger uses symbols
+to debug.
+
+ _Warning:_ `as' does not place symbols in the object file in the
+ same order they were declared. This may break some debuggers.
+
+* Menu:
+
+* Labels:: Labels
+* Setting Symbols:: Giving Symbols Other Values
+* Symbol Names:: Symbol Names
+* Dot:: The Special Dot Symbol
+* Symbol Attributes:: Symbol Attributes
+
+
+File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols
+
+5.1 Labels
+==========
+
+A "label" is written as a symbol immediately followed by a colon `:'.
+The symbol then represents the current value of the active location
+counter, and is, for example, a suitable instruction operand. You are
+warned if you use the same symbol to represent two different locations:
+the first definition overrides any other definitions.
+
+ On the HPPA, the usual form for a label need not be immediately
+followed by a colon, but instead must start in column zero. Only one
+label may be defined on a single line. To work around this, the HPPA
+version of `as' also provides a special directive `.label' for defining
+labels more flexibly.
+
+
+File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols
+
+5.2 Giving Symbols Other Values
+===============================
+
+A symbol can be given an arbitrary value by writing a symbol, followed
+by an equals sign `=', followed by an expression (*note Expressions::).
+This is equivalent to using the `.set' directive. *Note `.set': Set.
+In the same way, using a double equals sign `='`=' here represents an
+equivalent of the `.eqv' directive. *Note `.eqv': Eqv.
+
+ Blackfin does not support symbol assignment with `='.
+
+
+File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols
+
+5.3 Symbol Names
+================
+
+Symbol names begin with a letter or with one of `._'. On most
+machines, you can also use `$' in symbol names; exceptions are noted in
+*Note Machine Dependencies::. That character may be followed by any
+string of digits, letters, dollar signs (unless otherwise noted for a
+particular target machine), and underscores.
+
+Case of letters is significant: `foo' is a different symbol name than
+`Foo'.
+
+ Symbol names do not start with a digit. An exception to this rule
+is made for Local Labels. See below.
+
+ Multibyte characters are supported. To generate a symbol name
+containing multibyte characters enclose it within double quotes and use
+escape codes. cf *Note Strings::. Generating a multibyte symbol name
+from a label is not currently supported.
+
+ Each symbol has exactly one name. Each name in an assembly language
+program refers to exactly one symbol. You may use that symbol name any
+number of times in a program.
+
+Local Symbol Names
+------------------
+
+A local symbol is any symbol beginning with certain local label
+prefixes. By default, the local label prefix is `.L' for ELF systems or
+`L' for traditional a.out systems, but each target may have its own set
+of local label prefixes. On the HPPA local symbols begin with `L$'.
+
+ Local symbols are defined and used within the assembler, but they are
+normally not saved in object files. Thus, they are not visible when
+debugging. You may use the `-L' option (*note Include Local Symbols:
+L.) to retain the local symbols in the object files.
+
+Local Labels
+------------
+
+Local labels are different from local symbols. Local labels help
+compilers and programmers use names temporarily. They create symbols
+which are guaranteed to be unique over the entire scope of the input
+source code and which can be referred to by a simple notation. To
+define a local label, write a label of the form `N:' (where N
+represents any non-negative integer). To refer to the most recent
+previous definition of that label write `Nb', using the same number as
+when you defined the label. To refer to the next definition of a local
+label, write `Nf'. The `b' stands for "backwards" and the `f' stands
+for "forwards".
+
+ There is no restriction on how you can use these labels, and you can
+reuse them too. So that it is possible to repeatedly define the same
+local label (using the same number `N'), although you can only refer to
+the most recently defined local label of that number (for a backwards
+reference) or the next definition of a specific local label for a
+forward reference. It is also worth noting that the first 10 local
+labels (`0:'...`9:') are implemented in a slightly more efficient
+manner than the others.
+
+ Here is an example:
+
+ 1: branch 1f
+ 2: branch 1b
+ 1: branch 2f
+ 2: branch 1b
+
+ Which is the equivalent of:
+
+ label_1: branch label_3
+ label_2: branch label_1
+ label_3: branch label_4
+ label_4: branch label_3
+
+ Local label names are only a notational device. They are immediately
+transformed into more conventional symbol names before the assembler
+uses them. The symbol names are stored in the symbol table, appear in
+error messages, and are optionally emitted to the object file. The
+names are constructed using these parts:
+
+`_local label prefix_'
+ All local symbols begin with the system-specific local label
+ prefix. Normally both `as' and `ld' forget symbols that start
+ with the local label prefix. These labels are used for symbols
+ you are never intended to see. If you use the `-L' option then
+ `as' retains these symbols in the object file. If you also
+ instruct `ld' to retain these symbols, you may use them in
+ debugging.
+
+`NUMBER'
+ This is the number that was used in the local label definition.
+ So if the label is written `55:' then the number is `55'.
+
+`C-B'
+ This unusual character is included so you do not accidentally
+ invent a symbol of the same name. The character has ASCII value
+ of `\002' (control-B).
+
+`_ordinal number_'
+ This is a serial number to keep the labels distinct. The first
+ definition of `0:' gets the number `1'. The 15th definition of
+ `0:' gets the number `15', and so on. Likewise the first
+ definition of `1:' gets the number `1' and its 15th definition
+ gets `15' as well.
+
+ So for example, the first `1:' may be named `.L1C-B1', and the 44th
+`3:' may be named `.L3C-B44'.
+
+Dollar Local Labels
+-------------------
+
+On some targets `as' also supports an even more local form of local
+labels called dollar labels. These labels go out of scope (i.e., they
+become undefined) as soon as a non-local label is defined. Thus they
+remain valid for only a small region of the input source code. Normal
+local labels, by contrast, remain in scope for the entire file, or
+until they are redefined by another occurrence of the same local label.
+
+ Dollar labels are defined in exactly the same way as ordinary local
+labels, except that they have a dollar sign suffix to their numeric
+value, e.g., `55$:'.
+
+ They can also be distinguished from ordinary local labels by their
+transformed names which use ASCII character `\001' (control-A) as the
+magic character to distinguish them from ordinary labels. For example,
+the fifth definition of `6$' may be named `.L6C-A5'.
+
+
+File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols
+
+5.4 The Special Dot Symbol
+==========================
+
+The special symbol `.' refers to the current address that `as' is
+assembling into. Thus, the expression `melvin: .long .' defines
+`melvin' to contain its own address. Assigning a value to `.' is
+treated the same as a `.org' directive. Thus, the expression `.=.+4'
+is the same as saying `.space 4'.
+
+
+File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols
+
+5.5 Symbol Attributes
+=====================
+
+Every symbol has, as well as its name, the attributes "Value" and
+"Type". Depending on output format, symbols can also have auxiliary
+attributes.
+
+ If you use a symbol without defining it, `as' assumes zero for all
+these attributes, and probably won't warn you. This makes the symbol
+an externally defined symbol, which is generally what you would want.
+
+* Menu:
+
+* Symbol Value:: Value
+* Symbol Type:: Type
+
+
+* a.out Symbols:: Symbol Attributes: `a.out'
+
+* COFF Symbols:: Symbol Attributes for COFF
+
+* SOM Symbols:: Symbol Attributes for SOM
+
+
+File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes
+
+5.5.1 Value
+-----------
+
+The value of a symbol is (usually) 32 bits. For a symbol which labels a
+location in the text, data, bss or absolute sections the value is the
+number of addresses from the start of that section to the label.
+Naturally for text, data and bss sections the value of a symbol changes
+as `ld' changes section base addresses during linking. Absolute
+symbols' values do not change during linking: that is why they are
+called absolute.
+
+ The value of an undefined symbol is treated in a special way. If it
+is 0 then the symbol is not defined in this assembler source file, and
+`ld' tries to determine its value from other files linked into the same
+program. You make this kind of symbol simply by mentioning a symbol
+name without defining it. A non-zero value represents a `.comm' common
+declaration. The value is how much common storage to reserve, in bytes
+(addresses). The symbol refers to the first address of the allocated
+storage.
+
+
+File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes
+
+5.5.2 Type
+----------
+
+The type attribute of a symbol contains relocation (section)
+information, any flag settings indicating that a symbol is external, and
+(optionally), other information for linkers and debuggers. The exact
+format depends on the object-code output format in use.
+
+
+File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes
+
+5.5.3 Symbol Attributes: `a.out'
+--------------------------------
+
+* Menu:
+
+* Symbol Desc:: Descriptor
+* Symbol Other:: Other
+
+
+File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols
+
+5.5.3.1 Descriptor
+..................
+
+This is an arbitrary 16-bit value. You may establish a symbol's
+descriptor value by using a `.desc' statement (*note `.desc': Desc.).
+A descriptor value means nothing to `as'.
+
+
+File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols
+
+5.5.3.2 Other
+.............
+
+This is an arbitrary 8-bit value. It means nothing to `as'.
+
+
+File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes
+
+5.5.4 Symbol Attributes for COFF
+--------------------------------
+
+The COFF format supports a multitude of auxiliary symbol attributes;
+like the primary symbol attributes, they are set between `.def' and
+`.endef' directives.
+
+5.5.4.1 Primary Attributes
+..........................
+
+The symbol name is set with `.def'; the value and type, respectively,
+with `.val' and `.type'.
+
+5.5.4.2 Auxiliary Attributes
+............................
+
+The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and
+`.weak' can generate auxiliary symbol table information for COFF.
+
+
+File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes
+
+5.5.5 Symbol Attributes for SOM
+-------------------------------
+
+The SOM format for the HPPA supports a multitude of symbol attributes
+set with the `.EXPORT' and `.IMPORT' directives.
+
+ The attributes are described in `HP9000 Series 800 Assembly Language
+Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT'
+assembler directive documentation.
+
+
+File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top
+
+6 Expressions
+*************
+
+An "expression" specifies an address or numeric value. Whitespace may
+precede and/or follow an expression.
+
+ The result of an expression must be an absolute number, or else an
+offset into a particular section. If an expression is not absolute,
+and there is not enough information when `as' sees the expression to
+know its section, a second pass over the source program might be
+necessary to interpret the expression--but the second pass is currently
+not implemented. `as' aborts with an error message in this situation.
+
+* Menu:
+
+* Empty Exprs:: Empty Expressions
+* Integer Exprs:: Integer Expressions
+
+
+File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions
+
+6.1 Empty Expressions
+=====================
+
+An empty expression has no value: it is just whitespace or null.
+Wherever an absolute expression is required, you may omit the
+expression, and `as' assumes a value of (absolute) 0. This is
+compatible with other assemblers.
+
+
+File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions
+
+6.2 Integer Expressions
+=======================
+
+An "integer expression" is one or more _arguments_ delimited by
+_operators_.
+
+* Menu:
+
+* Arguments:: Arguments
+* Operators:: Operators
+* Prefix Ops:: Prefix Operators
+* Infix Ops:: Infix Operators
+
+
+File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs
+
+6.2.1 Arguments
+---------------
+
+"Arguments" are symbols, numbers or subexpressions. In other contexts
+arguments are sometimes called "arithmetic operands". In this manual,
+to avoid confusing them with the "instruction operands" of the machine
+language, we use the term "argument" to refer to parts of expressions
+only, reserving the word "operand" to refer only to machine instruction
+operands.
+
+ Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
+text, data, bss, absolute, or undefined. NNN is a signed, 2's
+complement 32 bit integer.
+
+ Numbers are usually integers.
+
+ A number can be a flonum or bignum. In this case, you are warned
+that only the low order 32 bits are used, and `as' pretends these 32
+bits are an integer. You may write integer-manipulating instructions
+that act on exotic constants, compatible with other assemblers.
+
+ Subexpressions are a left parenthesis `(' followed by an integer
+expression, followed by a right parenthesis `)'; or a prefix operator
+followed by an argument.
+
+
+File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs
+
+6.2.2 Operators
+---------------
+
+"Operators" are arithmetic functions, like `+' or `%'. Prefix
+operators are followed by an argument. Infix operators appear between
+their arguments. Operators may be preceded and/or followed by
+whitespace.
+
+
+File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs
+
+6.2.3 Prefix Operator
+---------------------
+
+`as' has the following "prefix operators". They each take one
+argument, which must be absolute.
+
+`-'
+ "Negation". Two's complement negation.
+
+`~'
+ "Complementation". Bitwise not.
+
+
+File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs
+
+6.2.4 Infix Operators
+---------------------
+
+"Infix operators" take two arguments, one on either side. Operators
+have precedence, but operations with equal precedence are performed left
+to right. Apart from `+' or `-', both arguments must be absolute, and
+the result is absolute.
+
+ 1. Highest Precedence
+
+ `*'
+ "Multiplication".
+
+ `/'
+ "Division". Truncation is the same as the C operator `/'
+
+ `%'
+ "Remainder".
+
+ `<<'
+ "Shift Left". Same as the C operator `<<'.
+
+ `>>'
+ "Shift Right". Same as the C operator `>>'.
+
+ 2. Intermediate precedence
+
+ `|'
+ "Bitwise Inclusive Or".
+
+ `&'
+ "Bitwise And".
+
+ `^'
+ "Bitwise Exclusive Or".
+
+ `!'
+ "Bitwise Or Not".
+
+ 3. Low Precedence
+
+ `+'
+ "Addition". If either argument is absolute, the result has
+ the section of the other argument. You may not add together
+ arguments from different sections.
+
+ `-'
+ "Subtraction". If the right argument is absolute, the result
+ has the section of the left argument. If both arguments are
+ in the same section, the result is absolute. You may not
+ subtract arguments from different sections.
+
+ `=='
+ "Is Equal To"
+
+ `<>'
+ `!='
+ "Is Not Equal To"
+
+ `<'
+ "Is Less Than"
+
+ `>'
+ "Is Greater Than"
+
+ `>='
+ "Is Greater Than Or Equal To"
+
+ `<='
+ "Is Less Than Or Equal To"
+
+ The comparison operators can be used as infix operators. A
+ true results has a value of -1 whereas a false result has a
+ value of 0. Note, these operators perform signed
+ comparisons.
+
+ 4. Lowest Precedence
+
+ `&&'
+ "Logical And".
+
+ `||'
+ "Logical Or".
+
+ These two logical operations can be used to combine the
+ results of sub expressions. Note, unlike the comparison
+ operators a true result returns a value of 1 but a false
+ results does still return 0. Also note that the logical or
+ operator has a slightly lower precedence than logical and.
+
+
+ In short, it's only meaningful to add or subtract the _offsets_ in an
+address; you can only have a defined section in one of the two
+arguments.
+
+
+File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top
+
+7 Assembler Directives
+**********************
+
+All assembler directives have names that begin with a period (`.').
+The names are case insensitive for most targets, and usually written in
+lower case.
+
+ This chapter discusses directives that are available regardless of
+the target machine configuration for the GNU assembler. Some machine
+configurations provide additional directives. *Note Machine
+Dependencies::.
+
+* Menu:
+
+* Abort:: `.abort'
+
+* ABORT (COFF):: `.ABORT'
+
+* Align:: `.align ABS-EXPR , ABS-EXPR'
+* Altmacro:: `.altmacro'
+* Ascii:: `.ascii "STRING"'...
+* Asciz:: `.asciz "STRING"'...
+* Balign:: `.balign ABS-EXPR , ABS-EXPR'
+* Bundle directives:: `.bundle_align_mode ABS-EXPR', etc
+* Byte:: `.byte EXPRESSIONS'
+* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc.
+* Comm:: `.comm SYMBOL , LENGTH '
+* Data:: `.data SUBSECTION'
+
+* Def:: `.def NAME'
+
+* Desc:: `.desc SYMBOL, ABS-EXPRESSION'
+
+* Dim:: `.dim'
+
+* Double:: `.double FLONUMS'
+* Eject:: `.eject'
+* Else:: `.else'
+* Elseif:: `.elseif'
+* End:: `.end'
+
+* Endef:: `.endef'
+
+* Endfunc:: `.endfunc'
+* Endif:: `.endif'
+* Equ:: `.equ SYMBOL, EXPRESSION'
+* Equiv:: `.equiv SYMBOL, EXPRESSION'
+* Eqv:: `.eqv SYMBOL, EXPRESSION'
+* Err:: `.err'
+* Error:: `.error STRING'
+* Exitm:: `.exitm'
+* Extern:: `.extern'
+* Fail:: `.fail'
+* File:: `.file'
+* Fill:: `.fill REPEAT , SIZE , VALUE'
+* Float:: `.float FLONUMS'
+* Func:: `.func'
+* Global:: `.global SYMBOL', `.globl SYMBOL'
+
+* Gnu_attribute:: `.gnu_attribute TAG,VALUE'
+* Hidden:: `.hidden NAMES'
+
+* hword:: `.hword EXPRESSIONS'
+* Ident:: `.ident'
+* If:: `.if ABSOLUTE EXPRESSION'
+* Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]'
+* Include:: `.include "FILE"'
+* Int:: `.int EXPRESSIONS'
+
+* Internal:: `.internal NAMES'
+
+* Irp:: `.irp SYMBOL,VALUES'...
+* Irpc:: `.irpc SYMBOL,VALUES'...
+* Lcomm:: `.lcomm SYMBOL , LENGTH'
+* Lflags:: `.lflags'
+
+* Line:: `.line LINE-NUMBER'
+
+* Linkonce:: `.linkonce [TYPE]'
+* List:: `.list'
+* Ln:: `.ln LINE-NUMBER'
+* Loc:: `.loc FILENO LINENO'
+* Loc_mark_labels:: `.loc_mark_labels ENABLE'
+
+* Local:: `.local NAMES'
+
+* Long:: `.long EXPRESSIONS'
+
+* Macro:: `.macro NAME ARGS'...
+* MRI:: `.mri VAL'
+* Noaltmacro:: `.noaltmacro'
+* Nolist:: `.nolist'
+* Octa:: `.octa BIGNUMS'
+* Offset:: `.offset LOC'
+* Org:: `.org NEW-LC, FILL'
+* P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR'
+
+* PopSection:: `.popsection'
+* Previous:: `.previous'
+
+* Print:: `.print STRING'
+
+* Protected:: `.protected NAMES'
+
+* Psize:: `.psize LINES, COLUMNS'
+* Purgem:: `.purgem NAME'
+
+* PushSection:: `.pushsection NAME'
+
+* Quad:: `.quad BIGNUMS'
+* Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
+* Rept:: `.rept COUNT'
+* Sbttl:: `.sbttl "SUBHEADING"'
+
+* Scl:: `.scl CLASS'
+
+* Section:: `.section NAME[, FLAGS]'
+
+* Set:: `.set SYMBOL, EXPRESSION'
+* Short:: `.short EXPRESSIONS'
+* Single:: `.single FLONUMS'
+
+* Size:: `.size [NAME , EXPRESSION]'
+
+* Skip:: `.skip SIZE , FILL'
+
+* Sleb128:: `.sleb128 EXPRESSIONS'
+
+* Space:: `.space SIZE , FILL'
+
+* Stab:: `.stabd, .stabn, .stabs'
+
+* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"'
+* Struct:: `.struct EXPRESSION'
+
+* SubSection:: `.subsection'
+* Symver:: `.symver NAME,NAME2@NODENAME'
+
+
+* Tag:: `.tag STRUCTNAME'
+
+* Text:: `.text SUBSECTION'
+* Title:: `.title "HEADING"'
+
+* Type:: `.type <INT | NAME , TYPE DESCRIPTION>'
+
+* Uleb128:: `.uleb128 EXPRESSIONS'
+
+* Val:: `.val ADDR'
+
+
+* Version:: `.version "STRING"'
+* VTableEntry:: `.vtable_entry TABLE, OFFSET'
+* VTableInherit:: `.vtable_inherit CHILD, PARENT'
+
+* Warning:: `.warning STRING'
+* Weak:: `.weak NAMES'
+* Weakref:: `.weakref ALIAS, SYMBOL'
+* Word:: `.word EXPRESSIONS'
+
+* Zero:: `.zero SIZE'
+* Deprecated:: Deprecated Directives
+
+
+File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops
+
+7.1 `.abort'
+============
+
+This directive stops the assembly immediately. It is for compatibility
+with other assemblers. The original idea was that the assembly
+language source would be piped into the assembler. If the sender of
+the source quit, it could use this directive tells `as' to quit also.
+One day `.abort' will not be supported.
+
+
+File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops
+
+7.2 `.ABORT' (COFF)
+===================
+
+When producing COFF output, `as' accepts this directive as a synonym
+for `.abort'.
+
+
+File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops
+
+7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
+=========================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary. The first expression (which must be absolute) is the
+alignment required, as described below.
+
+ The second expression (also absolute) gives the fill value to be
+stored in the padding bytes. It (and the comma) may be omitted. If it
+is omitted, the padding bytes are normally zero. However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+ The third expression is also absolute, and is also optional. If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive. If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all. You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+ The way the required alignment is specified varies from system to
+system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
+s390, sparc, tic4x, tic80 and xtensa, the first expression is the
+alignment request in bytes. For example `.align 8' advances the
+location counter until it is a multiple of 8. If the location counter
+is already a multiple of 8, no change is needed. For the tic54x, the
+first expression is the alignment request in words.
+
+ For other systems, including ppc, i386 using a.out format, arm and
+strongarm, it is the number of low-order zero bits the location counter
+must have after advancement. For example `.align 3' advances the
+location counter until it a multiple of 8. If the location counter is
+already a multiple of 8, no change is needed.
+
+ This inconsistency is due to the different behaviors of the various
+native assemblers for these systems which GAS must emulate. GAS also
+provides `.balign' and `.p2align' directives, described later, which
+have a consistent behavior across all architectures (but are specific
+to GAS).
+
+
+File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops
+
+7.4 `.altmacro'
+===============
+
+Enable alternate macro mode, enabling:
+
+`LOCAL NAME [ , ... ]'
+ One additional directive, `LOCAL', is available. It is used to
+ generate a string replacement for each of the NAME arguments, and
+ replace any instances of NAME in each macro expansion. The
+ replacement string is unique in the assembly, and different for
+ each separate macro expansion. `LOCAL' allows you to write macros
+ that define symbols, without fear of conflict between separate
+ macro expansions.
+
+`String delimiters'
+ You can write strings delimited in these other ways besides
+ `"STRING"':
+
+ `'STRING''
+ You can delimit strings with single-quote characters.
+
+ `<STRING>'
+ You can delimit strings with matching angle brackets.
+
+`single-character string escape'
+ To include any single character literally in a string (even if the
+ character would otherwise have some special meaning), you can
+ prefix the character with `!' (an exclamation mark). For example,
+ you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
+ 5.4!'.
+
+`Expression results as strings'
+ You can write `%EXPR' to evaluate the expression EXPR and use the
+ result as a string.
+
+
+File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops
+
+7.5 `.ascii "STRING"'...
+========================
+
+`.ascii' expects zero or more string literals (*note Strings::)
+separated by commas. It assembles each string (with no automatic
+trailing zero byte) into consecutive addresses.
+
+
+File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops
+
+7.6 `.asciz "STRING"'...
+========================
+
+`.asciz' is just like `.ascii', but each string is followed by a zero
+byte. The "z" in `.asciz' stands for "zero".
+
+
+File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops
+
+7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+==============================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary. The first expression (which must be absolute) is the
+alignment request in bytes. For example `.balign 8' advances the
+location counter until it is a multiple of 8. If the location counter
+is already a multiple of 8, no change is needed.
+
+ The second expression (also absolute) gives the fill value to be
+stored in the padding bytes. It (and the comma) may be omitted. If it
+is omitted, the padding bytes are normally zero. However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+ The third expression is also absolute, and is also optional. If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive. If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all. You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+ The `.balignw' and `.balignl' directives are variants of the
+`.balign' directive. The `.balignw' directive treats the fill pattern
+as a two byte word value. The `.balignl' directives treats the fill
+pattern as a four byte longword value. For example, `.balignw
+4,0x368d' will align to a multiple of 4. If it skips two bytes, they
+will be filled in with the value 0x368d (the exact placement of the
+bytes depends upon the endianness of the processor). If it skips 1 or
+3 bytes, the fill value is undefined.
+
+
+File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops
+
+7.8 Bundle directives
+=====================
+
+7.8.1 `.bundle_align_mode ABS-EXPR'
+-----------------------------------
+
+`.bundle_align_mode' enables or disables "aligned instruction bundle"
+mode. In this mode, sequences of adjacent instructions are grouped
+into fixed-sized "bundles". If the argument is zero, this mode is
+disabled (which is the default state). If the argument it not zero, it
+gives the size of an instruction bundle as a power of two (as for the
+`.p2align' directive, *note P2align::).
+
+ For some targets, it's an ABI requirement that no instruction may
+span a certain aligned boundary. A "bundle" is simply a sequence of
+instructions that starts on an aligned boundary. For example, if
+ABS-EXPR is `5' then the bundle size is 32, so each aligned chunk of 32
+bytes is a bundle. When aligned instruction bundle mode is in effect,
+no single instruction may span a boundary between bundles. If an
+instruction would start too close to the end of a bundle for the length
+of that particular instruction to fit within the bundle, then the space
+at the end of that bundle is filled with no-op instructions so the
+instruction starts in the next bundle. As a corollary, it's an error
+if any single instruction's encoding is longer than the bundle size.
+
+7.8.2 `.bundle_lock' and `.bundle_unlock'
+-----------------------------------------
+
+The `.bundle_lock' and directive `.bundle_unlock' directives allow
+explicit control over instruction bundle padding. These directives are
+only valid when `.bundle_align_mode' has been used to enable aligned
+instruction bundle mode. It's an error if they appear when
+`.bundle_align_mode' has not been used at all, or when the last
+directive was `.bundle_align_mode 0'.
+
+ For some targets, it's an ABI requirement that certain instructions
+may appear only as part of specified permissible sequences of multiple
+instructions, all within the same bundle. A pair of `.bundle_lock' and
+`.bundle_unlock' directives define a "bundle-locked" instruction
+sequence. For purposes of aligned instruction bundle mode, a sequence
+starting with `.bundle_lock' and ending with `.bundle_unlock' is
+treated as a single instruction. That is, the entire sequence must fit
+into a single bundle and may not span a bundle boundary. If necessary,
+no-op instructions will be inserted before the first instruction of the
+sequence so that the whole sequence starts on an aligned bundle
+boundary. It's an error if the sequence is longer than the bundle size.
+
+ For convenience when using `.bundle_lock' and `.bundle_unlock'
+inside assembler macros (*note Macro::), bundle-locked sequences may be
+nested. That is, a second `.bundle_lock' directive before the next
+`.bundle_unlock' directive has no effect except that it must be matched
+by another closing `.bundle_unlock' so that there is the same number of
+`.bundle_lock' and `.bundle_unlock' directives.
+
+
+File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops
+
+7.9 `.byte EXPRESSIONS'
+=======================
+
+`.byte' expects zero or more expressions, separated by commas. Each
+expression is assembled into the next byte.
+
+
+File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops
+
+7.10 CFI directives
+===================
+
+7.10.1 `.cfi_sections SECTION_LIST'
+-----------------------------------
+
+`.cfi_sections' may be used to specify whether CFI directives should
+emit `.eh_frame' section and/or `.debug_frame' section. If
+SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is
+`.debug_frame', `.debug_frame' is emitted. To emit both use
+`.eh_frame, .debug_frame'. The default if this directive is not used
+is `.cfi_sections .eh_frame'.
+
+ On targets that support compact unwinding tables these can be
+generated by specifying `.eh_frame_entry' instead of `.eh_frame'.
+
+ Some targets may support an additional name, such as `.c6xabi.exidx'
+which is used by the target.
+
+ The `.cfi_sections' directive can be repeated, with the same or
+different arguments, provided that CFI generation has not yet started.
+Once CFI generation has started however the section list is fixed and
+any attempts to redefine it will result in an error.
+
+7.10.2 `.cfi_startproc [simple]'
+--------------------------------
+
+`.cfi_startproc' is used at the beginning of each function that should
+have an entry in `.eh_frame'. It initializes some internal data
+structures. Don't forget to close the function by `.cfi_endproc'.
+
+ Unless `.cfi_startproc' is used along with parameter `simple' it
+also emits some architecture dependent initial CFI instructions.
+
+7.10.3 `.cfi_endproc'
+---------------------
+
+`.cfi_endproc' is used at the end of a function where it closes its
+unwind entry previously opened by `.cfi_startproc', and emits it to
+`.eh_frame'.
+
+7.10.4 `.cfi_personality ENCODING [, EXP]'
+------------------------------------------
+
+`.cfi_personality' defines personality routine and its encoding.
+ENCODING must be a constant determining how the personality should be
+encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not
+present, otherwise second argument should be a constant or a symbol
+name. When using indirect encodings, the symbol provided should be the
+location where personality can be loaded from, not the personality
+routine itself. The default after `.cfi_startproc' is
+`.cfi_personality 0xff', no personality routine.
+
+7.10.5 `.cfi_personality_id ID'
+-------------------------------
+
+`cfi_personality_id' defines a personality routine by its index as
+defined in a compact unwinding format. Only valid when generating
+compact EH frames (i.e. with `.cfi_sections eh_frame_entry'.
+
+7.10.6 `.cfi_fde_data [OPCODE1 [, ...]]'
+----------------------------------------
+
+`cfi_fde_data' is used to describe the compact unwind opcodes to be
+used for the current function. These are emitted inline in the
+`.eh_frame_entry' section if small enough and there is no LSDA, or in
+the `.gnu.extab' section otherwise. Only valid when generating compact
+EH frames (i.e. with `.cfi_sections eh_frame_entry'.
+
+7.10.7 `.cfi_lsda ENCODING [, EXP]'
+-----------------------------------
+
+`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant
+determining how the LSDA should be encoded. If it is 255
+(`DW_EH_PE_omit'), the second argument is not present, otherwise the
+second argument should be a constant or a symbol name. The default
+after `.cfi_startproc' is `.cfi_lsda 0xff', meaning that no LSDA is
+present.
+
+7.10.8 `.cfi_inline_lsda' [ALIGN]
+---------------------------------
+
+`.cfi_inline_lsda' marks the start of a LSDA data section and switches
+to the corresponding `.gnu.extab' section. Must be preceded by a CFI
+block containing a `.cfi_lsda' directive. Only valid when generating
+compact EH frames (i.e. with `.cfi_sections eh_frame_entry'.
+
+ The table header and unwinding opcodes will be generated at this
+point, so that they are immediately followed by the LSDA data. The
+symbol referenced by the `.cfi_lsda' directive should still be defined
+in case a fallback FDE based encoding is used. The LSDA data is
+terminated by a section directive.
+
+ The optional ALIGN argument specifies the alignment required. The
+alignment is specified as a power of two, as with the `.p2align'
+directive.
+
+7.10.9 `.cfi_def_cfa REGISTER, OFFSET'
+--------------------------------------
+
+`.cfi_def_cfa' defines a rule for computing CFA as: take address from
+REGISTER and add OFFSET to it.
+
+7.10.10 `.cfi_def_cfa_register REGISTER'
+----------------------------------------
+
+`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
+REGISTER will be used instead of the old one. Offset remains the same.
+
+7.10.11 `.cfi_def_cfa_offset OFFSET'
+------------------------------------
+
+`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
+remains the same, but OFFSET is new. Note that it is the absolute
+offset that will be added to a defined register to compute CFA address.
+
+7.10.12 `.cfi_adjust_cfa_offset OFFSET'
+---------------------------------------
+
+Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
+added/substracted from the previous offset.
+
+7.10.13 `.cfi_offset REGISTER, OFFSET'
+--------------------------------------
+
+Previous value of REGISTER is saved at offset OFFSET from CFA.
+
+7.10.14 `.cfi_val_offset REGISTER, OFFSET'
+------------------------------------------
+
+Previous value of REGISTER is CFA + OFFSET.
+
+7.10.15 `.cfi_rel_offset REGISTER, OFFSET'
+------------------------------------------
+
+Previous value of REGISTER is saved at offset OFFSET from the current
+CFA register. This is transformed to `.cfi_offset' using the known
+displacement of the CFA register from the CFA. This is often easier to
+use, because the number will match the code it's annotating.
+
+7.10.16 `.cfi_register REGISTER1, REGISTER2'
+--------------------------------------------
+
+Previous value of REGISTER1 is saved in register REGISTER2.
+
+7.10.17 `.cfi_restore REGISTER'
+-------------------------------
+
+`.cfi_restore' says that the rule for REGISTER is now the same as it
+was at the beginning of the function, after all initial instruction
+added by `.cfi_startproc' were executed.
+
+7.10.18 `.cfi_undefined REGISTER'
+---------------------------------
+
+From now on the previous value of REGISTER can't be restored anymore.
+
+7.10.19 `.cfi_same_value REGISTER'
+----------------------------------
+
+Current value of REGISTER is the same like in the previous frame, i.e.
+no restoration needed.
+
+7.10.20 `.cfi_remember_state' and `.cfi_restore_state'
+------------------------------------------------------
+
+`.cfi_remember_state' pushes the set of rules for every register onto an
+implicit stack, while `.cfi_restore_state' pops them off the stack and
+places them in the current row. This is useful for situations where
+you have multiple `.cfi_*' directives that need to be undone due to the
+control flow of the program. For example, we could have something like
+this (assuming the CFA is the value of `rbp'):
+
+ je label
+ popq %rbx
+ .cfi_restore %rbx
+ popq %r12
+ .cfi_restore %r12
+ popq %rbp
+ .cfi_restore %rbp
+ .cfi_def_cfa %rsp, 8
+ ret
+ label:
+ /* Do something else */
+
+ Here, we want the `.cfi' directives to affect only the rows
+corresponding to the instructions before `label'. This means we'd have
+to add multiple `.cfi' directives after `label' to recreate the
+original save locations of the registers, as well as setting the CFA
+back to the value of `rbp'. This would be clumsy, and result in a
+larger binary size. Instead, we can write:
+
+ je label
+ popq %rbx
+ .cfi_remember_state
+ .cfi_restore %rbx
+ popq %r12
+ .cfi_restore %r12
+ popq %rbp
+ .cfi_restore %rbp
+ .cfi_def_cfa %rsp, 8
+ ret
+ label:
+ .cfi_restore_state
+ /* Do something else */
+
+ That way, the rules for the instructions after `label' will be the
+same as before the first `.cfi_restore' without having to use multiple
+`.cfi' directives.
+
+7.10.21 `.cfi_return_column REGISTER'
+-------------------------------------
+
+Change return column REGISTER, i.e. the return address is either
+directly in REGISTER or can be accessed by rules for REGISTER.
+
+7.10.22 `.cfi_signal_frame'
+---------------------------
+
+Mark current function as signal trampoline.
+
+7.10.23 `.cfi_window_save'
+--------------------------
+
+SPARC register window has been saved.
+
+7.10.24 `.cfi_escape' EXPRESSION[, ...]
+---------------------------------------
+
+Allows the user to add arbitrary bytes to the unwind info. One might
+use this to add OS-specific CFI opcodes, or generic CFI opcodes that
+GAS does not yet support.
+
+7.10.25 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL'
+---------------------------------------------------------
+
+The current value of REGISTER is LABEL. The value of LABEL will be
+encoded in the output file according to ENCODING; see the description
+of `.cfi_personality' for details on this encoding.
+
+ The usefulness of equating a register to a fixed label is probably
+limited to the return address register. Here, it can be useful to mark
+a code segment that has only one return address which is reached by a
+direct branch and no copy of the return address exists in memory or
+another register.
+
+
+File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops
+
+7.11 `.comm SYMBOL , LENGTH '
+=============================
+
+`.comm' declares a common symbol named SYMBOL. When linking, a common
+symbol in one object file may be merged with a defined or common symbol
+of the same name in another object file. If `ld' does not see a
+definition for the symbol-just one or more common symbols-then it will
+allocate LENGTH bytes of uninitialized memory. LENGTH must be an
+absolute expression. If `ld' sees multiple common symbols with the
+same name, and they do not all have the same size, it will allocate
+space using the largest size.
+
+ When using ELF or (as a GNU extension) PE, the `.comm' directive
+takes an optional third argument. This is the desired alignment of the
+symbol, specified for ELF as a byte boundary (for example, an alignment
+of 16 means that the least significant 4 bits of the address should be
+zero), and for PE as a power of two (for example, an alignment of 5
+means aligned to a 32-byte boundary). The alignment must be an
+absolute expression, and it must be a power of two. If `ld' allocates
+uninitialized memory for the common symbol, it will use the alignment
+when placing the symbol. If no alignment is specified, `as' will set
+the alignment to the largest power of two less than or equal to the
+size of the symbol, up to a maximum of 16 on ELF, or the default
+section alignment of 4 on PE(1).
+
+ The syntax for `.comm' differs slightly on the HPPA. The syntax is
+`SYMBOL .comm, LENGTH'; SYMBOL is optional.
+
+ ---------- Footnotes ----------
+
+ (1) This is not the same as the executable image file alignment
+controlled by `ld''s `--section-alignment' option; image file sections
+in PE are aligned to multiples of 4096, which is far too large an
+alignment for ordinary variables. It is rather the default alignment
+for (non-debug) sections within object (`*.o') files, which are less
+strictly aligned.
+
+
+File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops
+
+7.12 `.data SUBSECTION'
+=======================
+
+`.data' tells `as' to assemble the following statements onto the end of
+the data subsection numbered SUBSECTION (which is an absolute
+expression). If SUBSECTION is omitted, it defaults to zero.
+
+
+File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops
+
+7.13 `.def NAME'
+================
+
+Begin defining debugging information for a symbol NAME; the definition
+extends until the `.endef' directive is encountered.
+
+
+File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops
+
+7.14 `.desc SYMBOL, ABS-EXPRESSION'
+===================================
+
+This directive sets the descriptor of the symbol (*note Symbol
+Attributes::) to the low 16 bits of an absolute expression.
+
+ The `.desc' directive is not available when `as' is configured for
+COFF output; it is only for `a.out' or `b.out' object format. For the
+sake of compatibility, `as' accepts it, but produces no output, when
+configured for COFF.
+
+
+File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops
+
+7.15 `.dim'
+===========
+
+This directive is generated by compilers to include auxiliary debugging
+information in the symbol table. It is only permitted inside
+`.def'/`.endef' pairs.
+
+
+File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops
+
+7.16 `.double FLONUMS'
+======================
+
+`.double' expects zero or more flonums, separated by commas. It
+assembles floating point numbers. The exact kind of floating point
+numbers emitted depends on how `as' is configured. *Note Machine
+Dependencies::.
+
+
+File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops
+
+7.17 `.eject'
+=============
+
+Force a page break at this point, when generating assembly listings.
+
+
+File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops
+
+7.18 `.else'
+============
+
+`.else' is part of the `as' support for conditional assembly; see *Note
+`.if': If. It marks the beginning of a section of code to be assembled
+if the condition for the preceding `.if' was false.
+
+
+File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops
+
+7.19 `.elseif'
+==============
+
+`.elseif' is part of the `as' support for conditional assembly; see
+*Note `.if': If. It is shorthand for beginning a new `.if' block that
+would otherwise fill the entire `.else' section.
+
+
+File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops
+
+7.20 `.end'
+===========
+
+`.end' marks the end of the assembly file. `as' does not process
+anything in the file past the `.end' directive.
+
+
+File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops
+
+7.21 `.endef'
+=============
+
+This directive flags the end of a symbol definition begun with `.def'.
+
+
+File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops
+
+7.22 `.endfunc'
+===============
+
+`.endfunc' marks the end of a function specified with `.func'.
+
+
+File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops
+
+7.23 `.endif'
+=============
+
+`.endif' is part of the `as' support for conditional assembly; it marks
+the end of a block of code that is only assembled conditionally. *Note
+`.if': If.
+
+
+File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops
+
+7.24 `.equ SYMBOL, EXPRESSION'
+==============================
+
+This directive sets the value of SYMBOL to EXPRESSION. It is
+synonymous with `.set'; see *Note `.set': Set.
+
+ The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.
+
+ The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the
+Z80 it is an eror if SYMBOL is already defined, but the symbol is not
+protected from later redefinition. Compare *Note Equiv::.
+
+
+File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops
+
+7.25 `.equiv SYMBOL, EXPRESSION'
+================================
+
+The `.equiv' directive is like `.equ' and `.set', except that the
+assembler will signal an error if SYMBOL is already defined. Note a
+symbol which has been referenced but not actually defined is considered
+to be undefined.
+
+ Except for the contents of the error message, this is roughly
+equivalent to
+ .ifdef SYM
+ .err
+ .endif
+ .equ SYM,VAL
+ plus it protects the symbol from later redefinition.
+
+
+File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops
+
+7.26 `.eqv SYMBOL, EXPRESSION'
+==============================
+
+The `.eqv' directive is like `.equiv', but no attempt is made to
+evaluate the expression or any part of it immediately. Instead each
+time the resulting symbol is used in an expression, a snapshot of its
+current value is taken.
+
+
+File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops
+
+7.27 `.err'
+===========
+
+If `as' assembles a `.err' directive, it will print an error message
+and, unless the `-Z' option was used, it will not generate an object
+file. This can be used to signal an error in conditionally compiled
+code.
+
+
+File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops
+
+7.28 `.error "STRING"'
+======================
+
+Similarly to `.err', this directive emits an error, but you can specify
+a string that will be emitted as the error message. If you don't
+specify the message, it defaults to `".error directive invoked in
+source file"'. *Note Error and Warning Messages: Errors.
+
+ .error "This code has not been assembled and tested."
+
+
+File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops
+
+7.29 `.exitm'
+=============
+
+Exit early from the current macro definition. *Note Macro::.
+
+
+File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops
+
+7.30 `.extern'
+==============
+
+`.extern' is accepted in the source program--for compatibility with
+other assemblers--but it is ignored. `as' treats all undefined symbols
+as external.
+
+
+File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops
+
+7.31 `.fail EXPRESSION'
+=======================
+
+Generates an error or a warning. If the value of the EXPRESSION is 500
+or more, `as' will print a warning message. If the value is less than
+500, `as' will print an error message. The message will include the
+value of EXPRESSION. This can occasionally be useful inside complex
+nested macros or conditional assembly.
+
+
+File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops
+
+7.32 `.file'
+============
+
+There are two different versions of the `.file' directive. Targets
+that support DWARF2 line number information use the DWARF2 version of
+`.file'. Other targets use the default version.
+
+Default Version
+---------------
+
+This version of the `.file' directive tells `as' that we are about to
+start a new logical file. The syntax is:
+
+ .file STRING
+
+ STRING is the new file name. In general, the filename is recognized
+whether or not it is surrounded by quotes `"'; but if you wish to
+specify an empty file name, you must give the quotes-`""'. This
+statement may go away in future: it is only recognized to be compatible
+with old `as' programs.
+
+DWARF2 Version
+--------------
+
+When emitting DWARF2 line number information, `.file' assigns filenames
+to the `.debug_line' file name table. The syntax is:
+
+ .file FILENO FILENAME
+
+ The FILENO operand should be a unique positive integer to use as the
+index of the entry in the table. The FILENAME operand is a C string
+literal.
+
+ The detail of filename indices is exposed to the user because the
+filename table is shared with the `.debug_info' section of the DWARF2
+debugging information, and thus the user must know the exact indices
+that table entries will have.
+
+
+File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops
+
+7.33 `.fill REPEAT , SIZE , VALUE'
+==================================
+
+REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT
+copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or
+more, but if it is more than 8, then it is deemed to have the value 8,
+compatible with other people's assemblers. The contents of each REPEAT
+bytes is taken from an 8-byte number. The highest order 4 bytes are
+zero. The lowest order 4 bytes are VALUE rendered in the byte-order of
+an integer on the computer `as' is assembling for. Each SIZE bytes in
+a repetition is taken from the lowest order SIZE bytes of this number.
+Again, this bizarre behavior is compatible with other people's
+assemblers.
+
+ SIZE and VALUE are optional. If the second comma and VALUE are
+absent, VALUE is assumed zero. If the first comma and following tokens
+are absent, SIZE is assumed to be 1.
+
+
+File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops
+
+7.34 `.float FLONUMS'
+=====================
+
+This directive assembles zero or more flonums, separated by commas. It
+has the same effect as `.single'. The exact kind of floating point
+numbers emitted depends on how `as' is configured. *Note Machine
+Dependencies::.
+
+
+File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops
+
+7.35 `.func NAME[,LABEL]'
+=========================
+
+`.func' emits debugging information to denote function NAME, and is
+ignored unless the file is assembled with debugging enabled. Only
+`--gstabs[+]' is currently supported. LABEL is the entry point of the
+function and if omitted NAME prepended with the `leading char' is used.
+`leading char' is usually `_' or nothing, depending on the target. All
+functions are currently defined to have `void' return type. The
+function must be terminated with `.endfunc'.
+
+
+File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops
+
+7.36 `.global SYMBOL', `.globl SYMBOL'
+======================================
+
+`.global' makes the symbol visible to `ld'. If you define SYMBOL in
+your partial program, its value is made available to other partial
+programs that are linked with it. Otherwise, SYMBOL takes its
+attributes from a symbol of the same name from another file linked into
+the same program.
+
+ Both spellings (`.globl' and `.global') are accepted, for
+compatibility with other assemblers.
+
+ On the HPPA, `.global' is not always enough to make it accessible to
+other partial programs. You may need the HPPA-only `.EXPORT' directive
+as well. *Note HPPA Assembler Directives: HPPA Directives.
+
+
+File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops
+
+7.37 `.gnu_attribute TAG,VALUE'
+===============================
+
+Record a GNU object attribute for this file. *Note Object Attributes::.
+
+
+File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops
+
+7.38 `.hidden NAMES'
+====================
+
+This is one of the ELF visibility directives. The other two are
+`.internal' (*note `.internal': Internal.) and `.protected' (*note
+`.protected': Protected.).
+
+ This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak). The directive sets
+the visibility to `hidden' which means that the symbols are not visible
+to other components. Such symbols are always considered to be
+`protected' as well.
+
+
+File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops
+
+7.39 `.hword EXPRESSIONS'
+=========================
+
+This expects zero or more EXPRESSIONS, and emits a 16 bit number for
+each.
+
+ This directive is a synonym for `.short'; depending on the target
+architecture, it may also be a synonym for `.word'.
+
+
+File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops
+
+7.40 `.ident'
+=============
+
+This directive is used by some assemblers to place tags in object
+files. The behavior of this directive varies depending on the target.
+When using the a.out object file format, `as' simply accepts the
+directive for source-file compatibility with existing assemblers, but
+does not emit anything for it. When using COFF, comments are emitted
+to the `.comment' or `.rdata' section, depending on the target. When
+using ELF, comments are emitted to the `.comment' section.
+
+
+File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops
+
+7.41 `.if ABSOLUTE EXPRESSION'
+==============================
+
+`.if' marks the beginning of a section of code which is only considered
+part of the source program being assembled if the argument (which must
+be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional
+section of code must be marked by `.endif' (*note `.endif': Endif.);
+optionally, you may include code for the alternative condition, flagged
+by `.else' (*note `.else': Else.). If you have several conditions to
+check, `.elseif' may be used to avoid nesting blocks if/else within
+each subsequent `.else' block.
+
+ The following variants of `.if' are also supported:
+`.ifdef SYMBOL'
+ Assembles the following section of code if the specified SYMBOL
+ has been defined. Note a symbol which has been referenced but not
+ yet defined is considered to be undefined.
+
+`.ifb TEXT'
+ Assembles the following section of code if the operand is blank
+ (empty).
+
+`.ifc STRING1,STRING2'
+ Assembles the following section of code if the two strings are the
+ same. The strings may be optionally quoted with single quotes.
+ If they are not quoted, the first string stops at the first comma,
+ and the second string stops at the end of the line. Strings which
+ contain whitespace should be quoted. The string comparison is
+ case sensitive.
+
+`.ifeq ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is zero.
+
+`.ifeqs STRING1,STRING2'
+ Another form of `.ifc'. The strings must be quoted using double
+ quotes.
+
+`.ifge ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is greater
+ than or equal to zero.
+
+`.ifgt ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is greater
+ than zero.
+
+`.ifle ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is less
+ than or equal to zero.
+
+`.iflt ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is less
+ than zero.
+
+`.ifnb TEXT'
+ Like `.ifb', but the sense of the test is reversed: this assembles
+ the following section of code if the operand is non-blank
+ (non-empty).
+
+`.ifnc STRING1,STRING2.'
+ Like `.ifc', but the sense of the test is reversed: this assembles
+ the following section of code if the two strings are not the same.
+
+`.ifndef SYMBOL'
+`.ifnotdef SYMBOL'
+ Assembles the following section of code if the specified SYMBOL
+ has not been defined. Both spelling variants are equivalent.
+ Note a symbol which has been referenced but not yet defined is
+ considered to be undefined.
+
+`.ifne ABSOLUTE EXPRESSION'
+ Assembles the following section of code if the argument is not
+ equal to zero (in other words, this is equivalent to `.if').
+
+`.ifnes STRING1,STRING2'
+ Like `.ifeqs', but the sense of the test is reversed: this
+ assembles the following section of code if the two strings are not
+ the same.
+
+
+File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops
+
+7.42 `.incbin "FILE"[,SKIP[,COUNT]]'
+====================================
+
+The `incbin' directive includes FILE verbatim at the current location.
+You can control the search paths used with the `-I' command-line option
+(*note Command-Line Options: Invoking.). Quotation marks are required
+around FILE.
+
+ The SKIP argument skips a number of bytes from the start of the
+FILE. The COUNT argument indicates the maximum number of bytes to
+read. Note that the data is not aligned in any way, so it is the user's
+responsibility to make sure that proper alignment is provided both
+before and after the `incbin' directive.
+
+
+File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops
+
+7.43 `.include "FILE"'
+======================
+
+This directive provides a way to include supporting files at specified
+points in your source program. The code from FILE is assembled as if
+it followed the point of the `.include'; when the end of the included
+file is reached, assembly of the original file continues. You can
+control the search paths used with the `-I' command-line option (*note
+Command-Line Options: Invoking.). Quotation marks are required around
+FILE.
+
+
+File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops
+
+7.44 `.int EXPRESSIONS'
+=======================
+
+Expect zero or more EXPRESSIONS, of any section, separated by commas.
+For each expression, emit a number that, at run time, is the value of
+that expression. The byte order and bit size of the number depends on
+what kind of target the assembly is for.
+
+
+File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops
+
+7.45 `.internal NAMES'
+======================
+
+This is one of the ELF visibility directives. The other two are
+`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note
+`.protected': Protected.).
+
+ This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak). The directive sets
+the visibility to `internal' which means that the symbols are
+considered to be `hidden' (i.e., not visible to other components), and
+that some extra, processor specific processing must also be performed
+upon the symbols as well.
+
+
+File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops
+
+7.46 `.irp SYMBOL,VALUES'...
+============================
+
+Evaluate a sequence of statements assigning different values to SYMBOL.
+The sequence of statements starts at the `.irp' directive, and is
+terminated by an `.endr' directive. For each VALUE, SYMBOL is set to
+VALUE, and the sequence of statements is assembled. If no VALUE is
+listed, the sequence of statements is assembled once, with SYMBOL set
+to the null string. To refer to SYMBOL within the sequence of
+statements, use \SYMBOL.
+
+ For example, assembling
+
+ .irp param,1,2,3
+ move d\param,sp@-
+ .endr
+
+ is equivalent to assembling
+
+ move d1,sp@-
+ move d2,sp@-
+ move d3,sp@-
+
+ For some caveats with the spelling of SYMBOL, see also *Note Macro::.
+
+
+File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops
+
+7.47 `.irpc SYMBOL,VALUES'...
+=============================
+
+Evaluate a sequence of statements assigning different values to SYMBOL.
+The sequence of statements starts at the `.irpc' directive, and is
+terminated by an `.endr' directive. For each character in VALUE,
+SYMBOL is set to the character, and the sequence of statements is
+assembled. If no VALUE is listed, the sequence of statements is
+assembled once, with SYMBOL set to the null string. To refer to SYMBOL
+within the sequence of statements, use \SYMBOL.
+
+ For example, assembling
+
+ .irpc param,123
+ move d\param,sp@-
+ .endr
+
+ is equivalent to assembling
+
+ move d1,sp@-
+ move d2,sp@-
+ move d3,sp@-
+
+ For some caveats with the spelling of SYMBOL, see also the discussion
+at *Note Macro::.
+
+
+File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops
+
+7.48 `.lcomm SYMBOL , LENGTH'
+=============================
+
+Reserve LENGTH (an absolute expression) bytes for a local common
+denoted by SYMBOL. The section and value of SYMBOL are those of the
+new local common. The addresses are allocated in the bss section, so
+that at run-time the bytes start off zeroed. SYMBOL is not declared
+global (*note `.global': Global.), so is normally not visible to `ld'.
+
+ Some targets permit a third argument to be used with `.lcomm'. This
+argument specifies the desired alignment of the symbol in the bss
+section.
+
+ The syntax for `.lcomm' differs slightly on the HPPA. The syntax is
+`SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
+
+
+File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops
+
+7.49 `.lflags'
+==============
+
+`as' accepts this directive, for compatibility with other assemblers,
+but ignores it.
+
+
+File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops
+
+7.50 `.line LINE-NUMBER'
+========================
+
+Change the logical line number. LINE-NUMBER must be an absolute
+expression. The next line has that logical line number. Therefore any
+other statements on the current line (after a statement separator
+character) are reported as on logical line number LINE-NUMBER - 1. One
+day `as' will no longer support this directive: it is recognized only
+for compatibility with existing assembler programs.
+
+Even though this is a directive associated with the `a.out' or `b.out'
+object-code formats, `as' still recognizes it when producing COFF
+output, and treats `.line' as though it were the COFF `.ln' _if_ it is
+found outside a `.def'/`.endef' pair.
+
+ Inside a `.def', `.line' is, instead, one of the directives used by
+compilers to generate auxiliary symbol information for debugging.
+
+
+File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops
+
+7.51 `.linkonce [TYPE]'
+=======================
+
+Mark the current section so that the linker only includes a single copy
+of it. This may be used to include the same section in several
+different object files, but ensure that the linker will only include it
+once in the final output file. The `.linkonce' pseudo-op must be used
+for each instance of the section. Duplicate sections are detected
+based on the section name, so it should be unique.
+
+ This directive is only supported by a few object file formats; as of
+this writing, the only object file format which supports it is the
+Portable Executable format used on Windows NT.
+
+ The TYPE argument is optional. If specified, it must be one of the
+following strings. For example:
+ .linkonce same_size
+ Not all types may be supported on all object file formats.
+
+`discard'
+ Silently discard duplicate sections. This is the default.
+
+`one_only'
+ Warn if there are duplicate sections, but still keep only one copy.
+
+`same_size'
+ Warn if any of the duplicates have different sizes.
+
+`same_contents'
+ Warn if any of the duplicates do not have exactly the same
+ contents.
+
+
+File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops
+
+7.52 `.list'
+============
+
+Control (in conjunction with the `.nolist' directive) whether or not
+assembly listings are generated. These two directives maintain an
+internal counter (which is zero initially). `.list' increments the
+counter, and `.nolist' decrements it. Assembly listings are generated
+whenever the counter is greater than zero.
+
+ By default, listings are disabled. When you enable them (with the
+`-a' command line option; *note Command-Line Options: Invoking.), the
+initial value of the listing counter is one.
+
+
+File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops
+
+7.53 `.ln LINE-NUMBER'
+======================
+
+`.ln' is a synonym for `.line'.
+
+
+File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops
+
+7.54 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
+============================================
+
+When emitting DWARF2 line number information, the `.loc' directive will
+add a row to the `.debug_line' line number matrix corresponding to the
+immediately following assembly instruction. The FILENO, LINENO, and
+optional COLUMN arguments will be applied to the `.debug_line' state
+machine before the row is added.
+
+ The OPTIONS are a sequence of the following tokens in any order:
+
+`basic_block'
+ This option will set the `basic_block' register in the
+ `.debug_line' state machine to `true'.
+
+`prologue_end'
+ This option will set the `prologue_end' register in the
+ `.debug_line' state machine to `true'.
+
+`epilogue_begin'
+ This option will set the `epilogue_begin' register in the
+ `.debug_line' state machine to `true'.
+
+`is_stmt VALUE'
+ This option will set the `is_stmt' register in the `.debug_line'
+ state machine to `value', which must be either 0 or 1.
+
+`isa VALUE'
+ This directive will set the `isa' register in the `.debug_line'
+ state machine to VALUE, which must be an unsigned integer.
+
+`discriminator VALUE'
+ This directive will set the `discriminator' register in the
+ `.debug_line' state machine to VALUE, which must be an unsigned
+ integer.
+
+
+
+File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops
+
+7.55 `.loc_mark_labels ENABLE'
+==============================
+
+When emitting DWARF2 line number information, the `.loc_mark_labels'
+directive makes the assembler emit an entry to the `.debug_line' line
+number matrix with the `basic_block' register in the state machine set
+whenever a code label is seen. The ENABLE argument should be either 1
+or 0, to enable or disable this function respectively.
+
+
+File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops
+
+7.56 `.local NAMES'
+===================
+
+This directive, which is available for ELF targets, marks each symbol in
+the comma-separated list of `names' as a local symbol so that it will
+not be externally visible. If the symbols do not already exist, they
+will be created.
+
+ For targets where the `.lcomm' directive (*note Lcomm::) does not
+accept an alignment argument, which is the case for most ELF targets,
+the `.local' directive can be used in combination with `.comm' (*note
+Comm::) to define aligned local common data.
+
+
+File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops
+
+7.57 `.long EXPRESSIONS'
+========================
+
+`.long' is the same as `.int'. *Note `.int': Int.
+
+
+File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops
+
+7.58 `.macro'
+=============
+
+The commands `.macro' and `.endm' allow you to define macros that
+generate assembly output. For example, this definition specifies a
+macro `sum' that puts a sequence of numbers into memory:
+
+ .macro sum from=0, to=5
+ .long \from
+ .if \to-\from
+ sum "(\from+1)",\to
+ .endif
+ .endm
+
+With that definition, `SUM 0,5' is equivalent to this assembly input:
+
+ .long 0
+ .long 1
+ .long 2
+ .long 3
+ .long 4
+ .long 5
+
+`.macro MACNAME'
+`.macro MACNAME MACARGS ...'
+ Begin the definition of a macro called MACNAME. If your macro
+ definition requires arguments, specify their names after the macro
+ name, separated by commas or spaces. You can qualify the macro
+ argument to indicate whether all invocations must specify a
+ non-blank value (through `:`req''), or whether it takes all of the
+ remaining arguments (through `:`vararg''). You can supply a
+ default value for any macro argument by following the name with
+ `=DEFLT'. You cannot define two macros with the same MACNAME
+ unless it has been subject to the `.purgem' directive (*note
+ Purgem::) between the two definitions. For example, these are all
+ valid `.macro' statements:
+
+ `.macro comm'
+ Begin the definition of a macro called `comm', which takes no
+ arguments.
+
+ `.macro plus1 p, p1'
+ `.macro plus1 p p1'
+ Either statement begins the definition of a macro called
+ `plus1', which takes two arguments; within the macro
+ definition, write `\p' or `\p1' to evaluate the arguments.
+
+ `.macro reserve_str p1=0 p2'
+ Begin the definition of a macro called `reserve_str', with two
+ arguments. The first argument has a default value, but not
+ the second. After the definition is complete, you can call
+ the macro either as `reserve_str A,B' (with `\p1' evaluating
+ to A and `\p2' evaluating to B), or as `reserve_str ,B' (with
+ `\p1' evaluating as the default, in this case `0', and `\p2'
+ evaluating to B).
+
+ `.macro m p1:req, p2=0, p3:vararg'
+ Begin the definition of a macro called `m', with at least
+ three arguments. The first argument must always have a value
+ specified, but not the second, which instead has a default
+ value. The third formal will get assigned all remaining
+ arguments specified at invocation time.
+
+ When you call a macro, you can specify the argument values
+ either by position, or by keyword. For example, `sum 9,17'
+ is equivalent to `sum to=17, from=9'.
+
+
+ Note that since each of the MACARGS can be an identifier exactly
+ as any other one permitted by the target architecture, there may be
+ occasional problems if the target hand-crafts special meanings to
+ certain characters when they occur in a special position. For
+ example, if the colon (`:') is generally permitted to be part of a
+ symbol name, but the architecture specific code special-cases it
+ when occurring as the final character of a symbol (to denote a
+ label), then the macro parameter replacement code will have no way
+ of knowing that and consider the whole construct (including the
+ colon) an identifier, and check only this identifier for being the
+ subject to parameter substitution. So for example this macro
+ definition:
+
+ .macro label l
+ \l:
+ .endm
+
+ might not work as expected. Invoking `label foo' might not create
+ a label called `foo' but instead just insert the text `\l:' into
+ the assembler source, probably generating an error about an
+ unrecognised identifier.
+
+ Similarly problems might occur with the period character (`.')
+ which is often allowed inside opcode names (and hence identifier
+ names). So for example constructing a macro to build an opcode
+ from a base name and a length specifier like this:
+
+ .macro opcode base length
+ \base.\length
+ .endm
+
+ and invoking it as `opcode store l' will not create a `store.l'
+ instruction but instead generate some kind of error as the
+ assembler tries to interpret the text `\base.\length'.
+
+ There are several possible ways around this problem:
+
+ `Insert white space'
+ If it is possible to use white space characters then this is
+ the simplest solution. eg:
+
+ .macro label l
+ \l :
+ .endm
+
+ `Use `\()''
+ The string `\()' can be used to separate the end of a macro
+ argument from the following text. eg:
+
+ .macro opcode base length
+ \base\().\length
+ .endm
+
+ `Use the alternate macro syntax mode'
+ In the alternative macro syntax mode the ampersand character
+ (`&') can be used as a separator. eg:
+
+ .altmacro
+ .macro label l
+ l&:
+ .endm
+
+ Note: this problem of correctly identifying string parameters to
+ pseudo ops also applies to the identifiers used in `.irp' (*note
+ Irp::) and `.irpc' (*note Irpc::) as well.
+
+`.endm'
+ Mark the end of a macro definition.
+
+`.exitm'
+ Exit early from the current macro definition.
+
+`\@'
+ `as' maintains a counter of how many macros it has executed in
+ this pseudo-variable; you can copy that number to your output with
+ `\@', but _only within a macro definition_.
+
+`LOCAL NAME [ , ... ]'
+ _Warning: `LOCAL' is only available if you select "alternate macro
+ syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro':
+ Altmacro.
+
+
+File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops
+
+7.59 `.mri VAL'
+===============
+
+If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero,
+this tells `as' to exit MRI mode. This change affects code assembled
+until the next `.mri' directive, or until the end of the file. *Note
+MRI mode: M.
+
+
+File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops
+
+7.60 `.noaltmacro'
+==================
+
+Disable alternate macro mode. *Note Altmacro::.
+
+
+File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops
+
+7.61 `.nolist'
+==============
+
+Control (in conjunction with the `.list' directive) whether or not
+assembly listings are generated. These two directives maintain an
+internal counter (which is zero initially). `.list' increments the
+counter, and `.nolist' decrements it. Assembly listings are generated
+whenever the counter is greater than zero.
+
+
+File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops
+
+7.62 `.octa BIGNUMS'
+====================
+
+This directive expects zero or more bignums, separated by commas. For
+each bignum, it emits a 16-byte integer.
+
+ The term "octa" comes from contexts in which a "word" is two bytes;
+hence _octa_-word for 16 bytes.
+
+
+File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops
+
+7.63 `.offset LOC'
+==================
+
+Set the location counter to LOC in the absolute section. LOC must be
+an absolute expression. This directive may be useful for defining
+symbols with absolute values. Do not confuse it with the `.org'
+directive.
+
+
+File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops
+
+7.64 `.org NEW-LC , FILL'
+=========================
+
+Advance the location counter of the current section to NEW-LC. NEW-LC
+is either an absolute expression or an expression with the same section
+as the current subsection. That is, you can't use `.org' to cross
+sections: if NEW-LC has the wrong section, the `.org' directive is
+ignored. To be compatible with former assemblers, if the section of
+NEW-LC is absolute, `as' issues a warning, then pretends the section of
+NEW-LC is the same as the current subsection.
+
+ `.org' may only increase the location counter, or leave it
+unchanged; you cannot use `.org' to move the location counter backwards.
+
+ Because `as' tries to assemble programs in one pass, NEW-LC may not
+be undefined. If you really detest this restriction we eagerly await a
+chance to share your improved assembler.
+
+ Beware that the origin is relative to the start of the section, not
+to the start of the subsection. This is compatible with other people's
+assemblers.
+
+ When the location counter (of the current subsection) is advanced,
+the intervening bytes are filled with FILL which should be an absolute
+expression. If the comma and FILL are omitted, FILL defaults to zero.
+
+
+File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops
+
+7.65 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+================================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary. The first expression (which must be absolute) is the
+number of low-order zero bits the location counter must have after
+advancement. For example `.p2align 3' advances the location counter
+until it a multiple of 8. If the location counter is already a
+multiple of 8, no change is needed.
+
+ The second expression (also absolute) gives the fill value to be
+stored in the padding bytes. It (and the comma) may be omitted. If it
+is omitted, the padding bytes are normally zero. However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+ The third expression is also absolute, and is also optional. If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive. If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all. You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+ The `.p2alignw' and `.p2alignl' directives are variants of the
+`.p2align' directive. The `.p2alignw' directive treats the fill
+pattern as a two byte word value. The `.p2alignl' directives treats the
+fill pattern as a four byte longword value. For example, `.p2alignw
+2,0x368d' will align to a multiple of 4. If it skips two bytes, they
+will be filled in with the value 0x368d (the exact placement of the
+bytes depends upon the endianness of the processor). If it skips 1 or
+3 bytes, the fill value is undefined.
+
+
+File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops
+
+7.66 `.popsection'
+==================
+
+This is one of the ELF section stack manipulation directives. The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.pushsection' (*note PushSection::), and `.previous'
+(*note Previous::).
+
+ This directive replaces the current section (and subsection) with
+the top section (and subsection) on the section stack. This section is
+popped off the stack.
+
+
+File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops
+
+7.67 `.previous'
+================
+
+This is one of the ELF section stack manipulation directives. The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
+(*note PopSection::).
+
+ This directive swaps the current section (and subsection) with most
+recently referenced section/subsection pair prior to this one. Multiple
+`.previous' directives in a row will flip between two sections (and
+their subsections). For example:
+
+ .section A
+ .subsection 1
+ .word 0x1234
+ .subsection 2
+ .word 0x5678
+ .previous
+ .word 0x9abc
+
+ Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into
+subsection 2 of section A. Whilst:
+
+ .section A
+ .subsection 1
+ # Now in section A subsection 1
+ .word 0x1234
+ .section B
+ .subsection 0
+ # Now in section B subsection 0
+ .word 0x5678
+ .subsection 1
+ # Now in section B subsection 1
+ .word 0x9abc
+ .previous
+ # Now in section B subsection 0
+ .word 0xdef0
+
+ Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection
+0 of section B and 0x9abc into subsection 1 of section B.
+
+ In terms of the section stack, this directive swaps the current
+section with the top section on the section stack.
+
+
+File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops
+
+7.68 `.print STRING'
+====================
+
+`as' will print STRING on the standard output during assembly. You
+must put STRING in double quotes.
+
+
+File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops
+
+7.69 `.protected NAMES'
+=======================
+
+This is one of the ELF visibility directives. The other two are
+`.hidden' (*note Hidden::) and `.internal' (*note Internal::).
+
+ This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak). The directive sets
+the visibility to `protected' which means that any references to the
+symbols from within the components that defines them must be resolved
+to the definition in that component, even if a definition in another
+component would normally preempt this.
+
+
+File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops
+
+7.70 `.psize LINES , COLUMNS'
+=============================
+
+Use this directive to declare the number of lines--and, optionally, the
+number of columns--to use for each page, when generating listings.
+
+ If you do not use `.psize', listings use a default line-count of 60.
+You may omit the comma and COLUMNS specification; the default width is
+200 columns.
+
+ `as' generates formfeeds whenever the specified number of lines is
+exceeded (or whenever you explicitly request one, using `.eject').
+
+ If you specify LINES as `0', no formfeeds are generated save those
+explicitly specified with `.eject'.
+
+
+File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops
+
+7.71 `.purgem NAME'
+===================
+
+Undefine the macro NAME, so that later uses of the string will not be
+expanded. *Note Macro::.
+
+
+File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops
+
+7.72 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]'
+========================================================================
+
+This is one of the ELF section stack manipulation directives. The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+ This directive pushes the current section (and subsection) onto the
+top of the section stack, and then replaces the current section and
+subsection with `name' and `subsection'. The optional `flags', `type'
+and `arguments' are treated the same as in the `.section' (*note
+Section::) directive.
+
+
+File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops
+
+7.73 `.quad BIGNUMS'
+====================
+
+`.quad' expects zero or more bignums, separated by commas. For each
+bignum, it emits an 8-byte integer. If the bignum won't fit in 8
+bytes, it prints a warning message; and just takes the lowest order 8
+bytes of the bignum.
+
+ The term "quad" comes from contexts in which a "word" is two bytes;
+hence _quad_-word for 8 bytes.
+
+
+File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops
+
+7.74 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
+==============================================
+
+Generate a relocation at OFFSET of type RELOC_NAME with value
+EXPRESSION. If OFFSET is a number, the relocation is generated in the
+current section. If OFFSET is an expression that resolves to a symbol
+plus offset, the relocation is generated in the given symbol's section.
+EXPRESSION, if present, must resolve to a symbol plus addend or to an
+absolute value, but note that not all targets support an addend. e.g.
+ELF REL targets such as i386 store an addend in the section contents
+rather than in the relocation. This low level interface does not
+support addends stored in the section.
+
+
+File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops
+
+7.75 `.rept COUNT'
+==================
+
+Repeat the sequence of lines between the `.rept' directive and the next
+`.endr' directive COUNT times.
+
+ For example, assembling
+
+ .rept 3
+ .long 0
+ .endr
+
+ is equivalent to assembling
+
+ .long 0
+ .long 0
+ .long 0
+
+
+File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops
+
+7.76 `.sbttl "SUBHEADING"'
+==========================
+
+Use SUBHEADING as the title (third line, immediately after the title
+line) when generating assembly listings.
+
+ This directive affects subsequent pages, as well as the current page
+if it appears within ten lines of the top of a page.
+
+
+File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops
+
+7.77 `.scl CLASS'
+=================
+
+Set the storage-class value for a symbol. This directive may only be
+used inside a `.def'/`.endef' pair. Storage class may flag whether a
+symbol is static or external, or it may record further symbolic
+debugging information.
+
+
+File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops
+
+7.78 `.section NAME'
+====================
+
+Use the `.section' directive to assemble the following code into a
+section named NAME.
+
+ This directive is only supported for targets that actually support
+arbitrarily named sections; on `a.out' targets, for example, it is not
+accepted, even with a standard `a.out' section name.
+
+COFF Version
+------------
+
+ For COFF targets, the `.section' directive is used in one of the
+following ways:
+
+ .section NAME[, "FLAGS"]
+ .section NAME[, SUBSECTION]
+
+ If the optional argument is quoted, it is taken as flags to use for
+the section. Each flag is a single character. The following flags are
+recognized:
+
+`b'
+ bss section (uninitialized data)
+
+`n'
+ section is not loaded
+
+`w'
+ writable section
+
+`d'
+ data section
+
+`e'
+ exclude section from linking
+
+`r'
+ read-only section
+
+`x'
+ executable section
+
+`s'
+ shared section (meaningful for PE targets)
+
+`a'
+ ignored. (For compatibility with the ELF version)
+
+`y'
+ section is not readable (meaningful for PE targets)
+
+`0-9'
+ single-digit power-of-two section alignment (GNU extension)
+
+ If no flags are specified, the default flags depend upon the section
+name. If the section name is not recognized, the default will be for
+the section to be loaded and writable. Note the `n' and `w' flags
+remove attributes from the section, rather than adding them, so if they
+are used on their own it will be as if no flags had been specified at
+all.
+
+ If the optional argument to the `.section' directive is not quoted,
+it is taken as a subsection number (*note Sub-Sections::).
+
+ELF Version
+-----------
+
+ This is one of the ELF section stack manipulation directives. The
+others are `.subsection' (*note SubSection::), `.pushsection' (*note
+PushSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+ For ELF targets, the `.section' directive is used like this:
+
+ .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
+
+ If the `--sectname-subst' command-line option is provided, the NAME
+argument may contain a substitution sequence. Only `%S' is supported at
+the moment, and substitutes the current section name. For example:
+
+ .macro exception_code
+ .section %S.exception
+ [exception code here]
+ .previous
+ .endm
+
+ .text
+ [code]
+ exception_code
+ [...]
+
+ .section .init
+ [init code]
+ exception_code
+ [...]
+
+ The two `exception_code' invocations above would create the
+`.text.exception' and `.init.exception' sections respectively. This is
+useful e.g. to discriminate between anciliary sections that are tied to
+setup code to be discarded after use from anciliary sections that need
+to stay resident without having to define multiple `exception_code'
+macros just for that purpose.
+
+ The optional FLAGS argument is a quoted string which may contain any
+combination of the following characters:
+
+`a'
+ section is allocatable
+
+`e'
+ section is excluded from executable and shared library.
+
+`w'
+ section is writable
+
+`x'
+ section is executable
+
+`M'
+ section is mergeable
+
+`S'
+ section contains zero terminated strings
+
+`G'
+ section is a member of a section group
+
+`T'
+ section is used for thread-local-storage
+
+`?'
+ section is a member of the previously-current section's group, if
+ any
+
+``<number>''
+ a numeric value indicating the bits to be set in the ELF section
+ header's flags field. Note - if one or more of the alphabetic
+ characters described above is also included in the flags field,
+ their bit values will be ORed into the resulting value.
+
+``<target specific>''
+ some targets extend this list with their own flag characters
+
+ Note - once a section's flags have been set they cannot be changed.
+There are a few exceptions to this rule however. Processor and
+application specific flags can be added to an already defined section.
+The `.interp', `.strtab' and `.symtab' sections can have the allocate
+flag (`a') set after they are initially defined, and the
+`.note-GNU-stack' section may have the executable (`x') flag added.
+
+ The optional TYPE argument may contain one of the following
+constants:
+
+`@progbits'
+ section contains data
+
+`@nobits'
+ section does not contain data (i.e., section only occupies space)
+
+`@note'
+ section contains data which is used by things other than the
+ program
+
+`@init_array'
+ section contains an array of pointers to init functions
+
+`@fini_array'
+ section contains an array of pointers to finish functions
+
+`@preinit_array'
+ section contains an array of pointers to pre-init functions
+
+`@`<number>''
+ a numeric value to be set as the ELF section header's type field.
+
+`@`<target specific>''
+ some targets extend this list with their own types
+
+ Many targets only support the first three section types. The type
+may be enclosed in double quotes if necessary.
+
+ Note on targets where the `@' character is the start of a comment (eg
+ARM) then another character is used instead. For example the ARM port
+uses the `%' character.
+
+ Note - some sections, eg `.text' and `.data' are considered to be
+special and have fixed types. Any attempt to declare them with a
+different type will generate an error from the assembler.
+
+ If FLAGS contains the `M' symbol then the TYPE argument must be
+specified as well as an extra argument--ENTSIZE--like this:
+
+ .section NAME , "FLAGS"M, @TYPE, ENTSIZE
+
+ Sections with the `M' flag but not `S' flag must contain fixed size
+constants, each ENTSIZE octets long. Sections with both `M' and `S'
+must contain zero terminated strings where each character is ENTSIZE
+bytes long. The linker may remove duplicates within sections with the
+same name, same entity size and same flags. ENTSIZE must be an
+absolute expression. For sections with both `M' and `S', a string
+which is a suffix of a larger string is considered a duplicate. Thus
+`"def"' will be merged with `"abcdef"'; A reference to the first
+`"def"' will be changed to a reference to `"abcdef"+3'.
+
+ If FLAGS contains the `G' symbol then the TYPE argument must be
+present along with an additional field like this:
+
+ .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
+
+ The GROUPNAME field specifies the name of the section group to which
+this particular section belongs. The optional linkage field can
+contain:
+
+`comdat'
+ indicates that only one copy of this section should be retained
+
+`.gnu.linkonce'
+ an alias for comdat
+
+ Note: if both the M and G flags are present then the fields for the
+Merge flag should come first, like this:
+
+ .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
+
+ If FLAGS contains the `?' symbol then it may not also contain the
+`G' symbol and the GROUPNAME or LINKAGE fields should not be present.
+Instead, `?' says to consider the section that's current before this
+directive. If that section used `G', then the new section will use `G'
+with those same GROUPNAME and LINKAGE fields implicitly. If not, then
+the `?' symbol has no effect.
+
+ If no flags are specified, the default flags depend upon the section
+name. If the section name is not recognized, the default will be for
+the section to have none of the above flags: it will not be allocated
+in memory, nor writable, nor executable. The section will contain data.
+
+ For ELF targets, the assembler supports another type of `.section'
+directive for compatibility with the Solaris assembler:
+
+ .section "NAME"[, FLAGS...]
+
+ Note that the section name is quoted. There may be a sequence of
+comma separated flags:
+
+`#alloc'
+ section is allocatable
+
+`#write'
+ section is writable
+
+`#execinstr'
+ section is executable
+
+`#exclude'
+ section is excluded from executable and shared library.
+
+`#tls'
+ section is used for thread local storage
+
+ This directive replaces the current section and subsection. See the
+contents of the gas testsuite directory `gas/testsuite/gas/elf' for
+some examples of how this directive and the other section stack
+directives work.
+
+
+File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops
+
+7.79 `.set SYMBOL, EXPRESSION'
+==============================
+
+Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and
+type to conform to EXPRESSION. If SYMBOL was flagged as external, it
+remains flagged (*note Symbol Attributes::).
+
+ You may `.set' a symbol many times in the same assembly provided
+that the values given to the symbol are constants. Values that are
+based on expressions involving other symbols are allowed, but some
+targets may restrict this to only being done once per assembly. This
+is because those targets do not set the addresses of symbols at
+assembly time, but rather delay the assignment until a final link is
+performed. This allows the linker a chance to change the code in the
+files, changing the location of, and the relative distance between,
+various different symbols.
+
+ If you `.set' a global symbol, the value stored in the object file
+is the last value stored into it.
+
+ On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION'
+instead.
+
+
+File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops
+
+7.80 `.short EXPRESSIONS'
+=========================
+
+`.short' is normally the same as `.word'. *Note `.word': Word.
+
+ In some configurations, however, `.short' and `.word' generate
+numbers of different lengths. *Note Machine Dependencies::.
+
+
+File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops
+
+7.81 `.single FLONUMS'
+======================
+
+This directive assembles zero or more flonums, separated by commas. It
+has the same effect as `.float'. The exact kind of floating point
+numbers emitted depends on how `as' is configured. *Note Machine
+Dependencies::.
+
+
+File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops
+
+7.82 `.size'
+============
+
+This directive is used to set the size associated with a symbol.
+
+COFF Version
+------------
+
+ For COFF targets, the `.size' directive is only permitted inside
+`.def'/`.endef' pairs. It is used like this:
+
+ .size EXPRESSION
+
+ELF Version
+-----------
+
+ For ELF targets, the `.size' directive is used like this:
+
+ .size NAME , EXPRESSION
+
+ This directive sets the size associated with a symbol NAME. The
+size in bytes is computed from EXPRESSION which can make use of label
+arithmetic. This directive is typically used to set the size of
+function symbols.
+
+
+File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops
+
+7.83 `.skip SIZE , FILL'
+========================
+
+This directive emits SIZE bytes, each of value FILL. Both SIZE and
+FILL are absolute expressions. If the comma and FILL are omitted, FILL
+is assumed to be zero. This is the same as `.space'.
+
+
+File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops
+
+7.84 `.sleb128 EXPRESSIONS'
+===========================
+
+SLEB128 stands for "signed little endian base 128." This is a compact,
+variable length representation of numbers used by the DWARF symbolic
+debugging format. *Note `.uleb128': Uleb128.
+
+
+File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops
+
+7.85 `.space SIZE , FILL'
+=========================
+
+This directive emits SIZE bytes, each of value FILL. Both SIZE and
+FILL are absolute expressions. If the comma and FILL are omitted, FILL
+is assumed to be zero. This is the same as `.skip'.
+
+ _Warning:_ `.space' has a completely different meaning for HPPA
+ targets; use `.block' as a substitute. See `HP9000 Series 800
+ Assembly Language Reference Manual' (HP 92432-90001) for the
+ meaning of the `.space' directive. *Note HPPA Assembler
+ Directives: HPPA Directives, for a summary.
+
+
+File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops
+
+7.86 `.stabd, .stabn, .stabs'
+=============================
+
+There are three directives that begin `.stab'. All emit symbols (*note
+Symbols::), for use by symbolic debuggers. The symbols are not entered
+in the `as' hash table: they cannot be referenced elsewhere in the
+source file. Up to five fields are required:
+
+STRING
+ This is the symbol's name. It may contain any character except
+ `\000', so is more general than ordinary symbol names. Some
+ debuggers used to code arbitrarily complex structures into symbol
+ names using this field.
+
+TYPE
+ An absolute expression. The symbol's type is set to the low 8
+ bits of this expression. Any bit pattern is permitted, but `ld'
+ and debuggers choke on silly bit patterns.
+
+OTHER
+ An absolute expression. The symbol's "other" attribute is set to
+ the low 8 bits of this expression.
+
+DESC
+ An absolute expression. The symbol's descriptor is set to the low
+ 16 bits of this expression.
+
+VALUE
+ An absolute expression which becomes the symbol's value.
+
+ If a warning is detected while reading a `.stabd', `.stabn', or
+`.stabs' statement, the symbol has probably already been created; you
+get a half-formed symbol in your object file. This is compatible with
+earlier assemblers!
+
+`.stabd TYPE , OTHER , DESC'
+ The "name" of the symbol generated is not even an empty string.
+ It is a null pointer, for compatibility. Older assemblers used a
+ null pointer so they didn't waste space in object files with empty
+ strings.
+
+ The symbol's value is set to the location counter, relocatably.
+ When your program is linked, the value of this symbol is the
+ address of the location counter when the `.stabd' was assembled.
+
+`.stabn TYPE , OTHER , DESC , VALUE'
+ The name of the symbol is set to the empty string `""'.
+
+`.stabs STRING , TYPE , OTHER , DESC , VALUE'
+ All five fields are specified.
+
+
+File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops
+
+7.87 `.string' "STR", `.string8' "STR", `.string16'
+===================================================
+
+"STR", `.string32' "STR", `.string64' "STR"
+
+ Copy the characters in STR to the object file. You may specify more
+than one string to copy, separated by commas. Unless otherwise
+specified for a particular machine, the assembler marks the end of each
+string with a 0 byte. You can use any of the escape sequences
+described in *Note Strings: Strings.
+
+ The variants `string16', `string32' and `string64' differ from the
+`string' pseudo opcode in that each 8-bit character from STR is copied
+and expanded to 16, 32 or 64 bits respectively. The expanded characters
+are stored in target endianness byte order.
+
+ Example:
+ .string32 "BYE"
+ expands to:
+ .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */
+ .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */
+
+
+File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops
+
+7.88 `.struct EXPRESSION'
+=========================
+
+Switch to the absolute section, and set the section offset to
+EXPRESSION, which must be an absolute expression. You might use this
+as follows:
+ .struct 0
+ field1:
+ .struct field1 + 4
+ field2:
+ .struct field2 + 4
+ field3:
+ This would define the symbol `field1' to have the value 0, the symbol
+`field2' to have the value 4, and the symbol `field3' to have the value
+8. Assembly would be left in the absolute section, and you would need
+to use a `.section' directive of some sort to change to some other
+section before further assembly.
+
+
+File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops
+
+7.89 `.subsection NAME'
+=======================
+
+This is one of the ELF section stack manipulation directives. The
+others are `.section' (*note Section::), `.pushsection' (*note
+PushSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+ This directive replaces the current subsection with `name'. The
+current section is not changed. The replaced subsection is put onto
+the section stack in place of the then current top of stack subsection.
+
+
+File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops
+
+7.90 `.symver'
+==============
+
+Use the `.symver' directive to bind symbols to specific version nodes
+within a source file. This is only supported on ELF platforms, and is
+typically used when assembling files to be linked into a shared library.
+There are cases where it may make sense to use this in objects to be
+bound into an application itself so as to override a versioned symbol
+from a shared library.
+
+ For ELF targets, the `.symver' directive can be used like this:
+ .symver NAME, NAME2@NODENAME
+ If the symbol NAME is defined within the file being assembled, the
+`.symver' directive effectively creates a symbol alias with the name
+NAME2@NODENAME, and in fact the main reason that we just don't try and
+create a regular alias is that the @ character isn't permitted in
+symbol names. The NAME2 part of the name is the actual name of the
+symbol by which it will be externally referenced. The name NAME itself
+is merely a name of convenience that is used so that it is possible to
+have definitions for multiple versions of a function within a single
+source file, and so that the compiler can unambiguously know which
+version of a function is being mentioned. The NODENAME portion of the
+alias should be the name of a node specified in the version script
+supplied to the linker when building a shared library. If you are
+attempting to override a versioned symbol from a shared library, then
+NODENAME should correspond to the nodename of the symbol you are trying
+to override.
+
+ If the symbol NAME is not defined within the file being assembled,
+all references to NAME will be changed to NAME2@NODENAME. If no
+reference to NAME is made, NAME2@NODENAME will be removed from the
+symbol table.
+
+ Another usage of the `.symver' directive is:
+ .symver NAME, NAME2@@NODENAME
+ In this case, the symbol NAME must exist and be defined within the
+file being assembled. It is similar to NAME2@NODENAME. The difference
+is NAME2@@NODENAME will also be used to resolve references to NAME2 by
+the linker.
+
+ The third usage of the `.symver' directive is:
+ .symver NAME, NAME2@@@NODENAME
+ When NAME is not defined within the file being assembled, it is
+treated as NAME2@NODENAME. When NAME is defined within the file being
+assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
+
+
+File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops
+
+7.91 `.tag STRUCTNAME'
+======================
+
+This directive is generated by compilers to include auxiliary debugging
+information in the symbol table. It is only permitted inside
+`.def'/`.endef' pairs. Tags are used to link structure definitions in
+the symbol table with instances of those structures.
+
+
+File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops
+
+7.92 `.text SUBSECTION'
+=======================
+
+Tells `as' to assemble the following statements onto the end of the
+text subsection numbered SUBSECTION, which is an absolute expression.
+If SUBSECTION is omitted, subsection number zero is used.
+
+
+File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops
+
+7.93 `.title "HEADING"'
+=======================
+
+Use HEADING as the title (second line, immediately after the source
+file name and pagenumber) when generating assembly listings.
+
+ This directive affects subsequent pages, as well as the current page
+if it appears within ten lines of the top of a page.
+
+
+File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops
+
+7.94 `.type'
+============
+
+This directive is used to set the type of a symbol.
+
+COFF Version
+------------
+
+ For COFF targets, this directive is permitted only within
+`.def'/`.endef' pairs. It is used like this:
+
+ .type INT
+
+ This records the integer INT as the type attribute of a symbol table
+entry.
+
+ELF Version
+-----------
+
+ For ELF targets, the `.type' directive is used like this:
+
+ .type NAME , TYPE DESCRIPTION
+
+ This sets the type of symbol NAME to be either a function symbol or
+an object symbol. There are five different syntaxes supported for the
+TYPE DESCRIPTION field, in order to provide compatibility with various
+other assemblers.
+
+ Because some of the characters used in these syntaxes (such as `@'
+and `#') are comment characters for some architectures, some of the
+syntaxes below do not work on all architectures. The first variant
+will be accepted by the GNU assembler on all architectures so that
+variant should be used for maximum portability, if you do not need to
+assemble your code with other assemblers.
+
+ The syntaxes supported are:
+
+ .type <name> STT_<TYPE_IN_UPPER_CASE>
+ .type <name>,#<type>
+ .type <name>,@<type>
+ .type <name>,%<type>
+ .type <name>,"<type>"
+
+ The types supported are:
+
+`STT_FUNC'
+`function'
+ Mark the symbol as being a function name.
+
+`STT_GNU_IFUNC'
+`gnu_indirect_function'
+ Mark the symbol as an indirect function when evaluated during reloc
+ processing. (This is only supported on assemblers targeting GNU
+ systems).
+
+`STT_OBJECT'
+`object'
+ Mark the symbol as being a data object.
+
+`STT_TLS'
+`tls_object'
+ Mark the symbol as being a thead-local data object.
+
+`STT_COMMON'
+`common'
+ Mark the symbol as being a common data object.
+
+`STT_NOTYPE'
+`notype'
+ Does not mark the symbol in any way. It is supported just for
+ completeness.
+
+`gnu_unique_object'
+ Marks the symbol as being a globally unique data object. The
+ dynamic linker will make sure that in the entire process there is
+ just one symbol with this name and type in use. (This is only
+ supported on assemblers targeting GNU systems).
+
+
+ Note: Some targets support extra types in addition to those listed
+above.
+
+
+File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops
+
+7.95 `.uleb128 EXPRESSIONS'
+===========================
+
+ULEB128 stands for "unsigned little endian base 128." This is a
+compact, variable length representation of numbers used by the DWARF
+symbolic debugging format. *Note `.sleb128': Sleb128.
+
+
+File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops
+
+7.96 `.val ADDR'
+================
+
+This directive, permitted only within `.def'/`.endef' pairs, records
+the address ADDR as the value attribute of a symbol table entry.
+
+
+File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops
+
+7.97 `.version "STRING"'
+========================
+
+This directive creates a `.note' section and places into it an ELF
+formatted note of type NT_VERSION. The note's name is set to `string'.
+
+
+File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops
+
+7.98 `.vtable_entry TABLE, OFFSET'
+==================================
+
+This directive finds or creates a symbol `table' and creates a
+`VTABLE_ENTRY' relocation for it with an addend of `offset'.
+
+
+File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops
+
+7.99 `.vtable_inherit CHILD, PARENT'
+====================================
+
+This directive finds the symbol `child' and finds or creates the symbol
+`parent' and then creates a `VTABLE_INHERIT' relocation for the parent
+whose addend is the value of the child symbol. As a special case the
+parent name of `0' is treated as referring to the `*ABS*' section.
+
+
+File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops
+
+7.100 `.warning "STRING"'
+=========================
+
+Similar to the directive `.error' (*note `.error "STRING"': Error.),
+but just emits a warning.
+
+
+File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops
+
+7.101 `.weak NAMES'
+===================
+
+This directive sets the weak attribute on the comma separated list of
+symbol `names'. If the symbols do not already exist, they will be
+created.
+
+ On COFF targets other than PE, weak symbols are a GNU extension.
+This directive sets the weak attribute on the comma separated list of
+symbol `names'. If the symbols do not already exist, they will be
+created.
+
+ On the PE target, weak symbols are supported natively as weak
+aliases. When a weak symbol is created that is not an alias, GAS
+creates an alternate symbol to hold the default value.
+
+
+File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops
+
+7.102 `.weakref ALIAS, TARGET'
+==============================
+
+This directive creates an alias to the target symbol that enables the
+symbol to be referenced with weak-symbol semantics, but without
+actually making it weak. If direct references or definitions of the
+symbol are present, then the symbol will not be weak, but if all
+references to it are through weak references, the symbol will be marked
+as weak in the symbol table.
+
+ The effect is equivalent to moving all references to the alias to a
+separate assembly source file, renaming the alias to the symbol in it,
+declaring the symbol as weak there, and running a reloadable link to
+merge the object files resulting from the assembly of the new source
+file and the old source file that had the references to the alias
+removed.
+
+ The alias itself never makes to the symbol table, and is entirely
+handled within the assembler.
+
+
+File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops
+
+7.103 `.word EXPRESSIONS'
+=========================
+
+This directive expects zero or more EXPRESSIONS, of any section,
+separated by commas.
+
+ The size of the number emitted, and its byte order, depend on what
+target computer the assembly is for.
+
+ _Warning: Special Treatment to support Compilers_
+
+ Machines with a 32-bit address space, but that do less than 32-bit
+addressing, require the following special treatment. If the machine of
+interest to you does 32-bit addressing (or doesn't require it; *note
+Machine Dependencies::), you can ignore this issue.
+
+ In order to assemble compiler output into something that works, `as'
+occasionally does strange things to `.word' directives. Directives of
+the form `.word sym1-sym2' are often emitted by compilers as part of
+jump tables. Therefore, when `as' assembles a directive of the form
+`.word sym1-sym2', and the difference between `sym1' and `sym2' does
+not fit in 16 bits, `as' creates a "secondary jump table", immediately
+before the next label. This secondary jump table is preceded by a
+short-jump to the first byte after the secondary table. This
+short-jump prevents the flow of control from accidentally falling into
+the new table. Inside the table is a long-jump to `sym2'. The
+original `.word' contains `sym1' minus the address of the long-jump to
+`sym2'.
+
+ If there were several occurrences of `.word sym1-sym2' before the
+secondary jump table, all of them are adjusted. If there was a `.word
+sym3-sym4', that also did not fit in sixteen bits, a long-jump to
+`sym4' is included in the secondary jump table, and the `.word'
+directives are adjusted to contain `sym3' minus the address of the
+long-jump to `sym4'; and so on, for as many entries in the original
+jump table as necessary.
+
+
+File: as.info, Node: Zero, Next: Deprecated, Prev: Word, Up: Pseudo Ops
+
+7.104 `.zero SIZE'
+==================
+
+This directive emits SIZE 0-valued bytes. SIZE must be an absolute
+expression. This directive is actually an alias for the `.skip'
+directive so in can take an optional second argument of the value to
+store in the bytes instead of zero. Using `.zero' in this way would be
+confusing however.
+
+
+File: as.info, Node: Deprecated, Prev: Zero, Up: Pseudo Ops
+
+7.105 Deprecated Directives
+===========================
+
+One day these directives won't work. They are included for
+compatibility with older assemblers.
+.abort
+
+.line
+
+
+File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top
+
+8 Object Attributes
+*******************
+
+`as' assembles source files written for a specific architecture into
+object files for that architecture. But not all object files are alike.
+Many architectures support incompatible variations. For instance,
+floating point arguments might be passed in floating point registers if
+the object file requires hardware floating point support--or floating
+point arguments might be passed in integer registers if the object file
+supports processors with no hardware floating point unit. Or, if two
+objects are built for different generations of the same architecture,
+the combination may require the newer generation at run-time.
+
+ This information is useful during and after linking. At link time,
+`ld' can warn about incompatible object files. After link time, tools
+like `gdb' can use it to process the linked file correctly.
+
+ Compatibility information is recorded as a series of object
+attributes. Each attribute has a "vendor", "tag", and "value". The
+vendor is a string, and indicates who sets the meaning of the tag. The
+tag is an integer, and indicates what property the attribute describes.
+The value may be a string or an integer, and indicates how the
+property affects this object. Missing attributes are the same as
+attributes with a zero value or empty string value.
+
+ Object attributes were developed as part of the ABI for the ARM
+Architecture. The file format is documented in `ELF for the ARM
+Architecture'.
+
+* Menu:
+
+* GNU Object Attributes:: GNU Object Attributes
+* Defining New Object Attributes:: Defining New Object Attributes
+
+
+File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes
+
+8.1 GNU Object Attributes
+=========================
+
+The `.gnu_attribute' directive records an object attribute with vendor
+`gnu'.
+
+ Except for `Tag_compatibility', which has both an integer and a
+string for its value, GNU attributes have a string value if the tag
+number is odd and an integer value if the tag number is even. The
+second bit (`TAG & 2' is set for architecture-independent attributes
+and clear for architecture-dependent ones.
+
+8.1.1 Common GNU attributes
+---------------------------
+
+These attributes are valid on all architectures.
+
+Tag_compatibility (32)
+ The compatibility attribute takes an integer flag value and a
+ vendor name. If the flag value is 0, the file is compatible with
+ other toolchains. If it is 1, then the file is only compatible
+ with the named toolchain. If it is greater than 1, the file can
+ only be processed by other toolchains under some private
+ arrangement indicated by the flag value and the vendor name.
+
+8.1.2 MIPS Attributes
+---------------------
+
+Tag_GNU_MIPS_ABI_FP (4)
+ The floating-point ABI used by this object file. The value will
+ be:
+
+ * 0 for files not affected by the floating-point ABI.
+
+ * 1 for files using the hardware floating-point ABI with a
+ standard double-precision FPU.
+
+ * 2 for files using the hardware floating-point ABI with a
+ single-precision FPU.
+
+ * 3 for files using the software floating-point ABI.
+
+ * 4 for files using the deprecated hardware floating-point ABI
+ which used 64-bit floating-point registers, 32-bit
+ general-purpose registers and increased the number of
+ callee-saved floating-point registers.
+
+ * 5 for files using the hardware floating-point ABI with a
+ double-precision FPU with either 32-bit or 64-bit
+ floating-point registers and 32-bit general-purpose registers.
+
+ * 6 for files using the hardware floating-point ABI with 64-bit
+ floating-point registers and 32-bit general-purpose registers.
+
+ * 7 for files using the hardware floating-point ABI with 64-bit
+ floating-point registers, 32-bit general-purpose registers
+ and a rule that forbids the direct use of odd-numbered
+ single-precision floating-point registers.
+
+8.1.3 PowerPC Attributes
+------------------------
+
+Tag_GNU_Power_ABI_FP (4)
+ The floating-point ABI used by this object file. The value will
+ be:
+
+ * 0 for files not affected by the floating-point ABI.
+
+ * 1 for files using double-precision hardware floating-point
+ ABI.
+
+ * 2 for files using the software floating-point ABI.
+
+ * 3 for files using single-precision hardware floating-point
+ ABI.
+
+Tag_GNU_Power_ABI_Vector (8)
+ The vector ABI used by this object file. The value will be:
+
+ * 0 for files not affected by the vector ABI.
+
+ * 1 for files using general purpose registers to pass vectors.
+
+ * 2 for files using AltiVec registers to pass vectors.
+
+ * 3 for files using SPE registers to pass vectors.
+
+8.1.4 IBM z Systems Attributes
+------------------------------
+
+Tag_GNU_S390_ABI_Vector (8)
+ The vector ABI used by this object file. The value will be:
+
+ * 0 for files not affected by the vector ABI.
+
+ * 1 for files using software vector ABI.
+
+ * 2 for files using hardware vector ABI.
+
+
+File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes
+
+8.2 Defining New Object Attributes
+==================================
+
+If you want to define a new GNU object attribute, here are the places
+you will need to modify. New attributes should be discussed on the
+`binutils' mailing list.
+
+ * This manual, which is the official register of attributes.
+
+ * The header for your architecture `include/elf', to define the tag.
+
+ * The `bfd' support file for your architecture, to merge the
+ attribute and issue any appropriate link warnings.
+
+ * Test cases in `ld/testsuite' for merging and link warnings.
+
+ * `binutils/readelf.c' to display your attribute.
+
+ * GCC, if you want the compiler to mark the attribute automatically.
+
+
+File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top
+
+9 Machine Dependent Features
+****************************
+
+The machine instruction sets are (almost by definition) different on
+each machine where `as' runs. Floating point representations vary as
+well, and `as' often supports a few additional directives or
+command-line options for compatibility with other assemblers on a
+particular platform. Finally, some versions of `as' support special
+pseudo-instructions for branch optimization.
+
+ This chapter discusses most of these differences, though it does not
+include details on any machine's instruction set. For details on that
+subject, see the hardware manufacturer's manual.
+
+* Menu:
+
+
+* AArch64-Dependent:: AArch64 Dependent Features
+
+* Alpha-Dependent:: Alpha Dependent Features
+
+* ARC-Dependent:: ARC Dependent Features
+
+* ARM-Dependent:: ARM Dependent Features
+
+* AVR-Dependent:: AVR Dependent Features
+
+* Blackfin-Dependent:: Blackfin Dependent Features
+
+* CR16-Dependent:: CR16 Dependent Features
+
+* CRIS-Dependent:: CRIS Dependent Features
+
+* D10V-Dependent:: D10V Dependent Features
+
+* D30V-Dependent:: D30V Dependent Features
+
+* Epiphany-Dependent:: EPIPHANY Dependent Features
+
+* H8/300-Dependent:: Renesas H8/300 Dependent Features
+
+* HPPA-Dependent:: HPPA Dependent Features
+
+* ESA/390-Dependent:: IBM ESA/390 Dependent Features
+
+* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
+
+* i860-Dependent:: Intel 80860 Dependent Features
+
+* i960-Dependent:: Intel 80960 Dependent Features
+
+* IA-64-Dependent:: Intel IA-64 Dependent Features
+
+* IP2K-Dependent:: IP2K Dependent Features
+
+* LM32-Dependent:: LM32 Dependent Features
+
+* M32C-Dependent:: M32C Dependent Features
+
+* M32R-Dependent:: M32R Dependent Features
+
+* M68K-Dependent:: M680x0 Dependent Features
+
+* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
+
+* Meta-Dependent :: Meta Dependent Features
+
+* MicroBlaze-Dependent:: MICROBLAZE Dependent Features
+
+* MIPS-Dependent:: MIPS Dependent Features
+
+* MMIX-Dependent:: MMIX Dependent Features
+
+* MSP430-Dependent:: MSP430 Dependent Features
+
+* NDS32-Dependent:: Andes NDS32 Dependent Features
+
+* NiosII-Dependent:: Altera Nios II Dependent Features
+
+* NS32K-Dependent:: NS32K Dependent Features
+
+* PDP-11-Dependent:: PDP-11 Dependent Features
+
+* PJ-Dependent:: picoJava Dependent Features
+
+* PPC-Dependent:: PowerPC Dependent Features
+
+* RL78-Dependent:: RL78 Dependent Features
+
+* RISC-V-Dependent:: RISC-V Dependent Features
+
+* RX-Dependent:: RX Dependent Features
+
+* S/390-Dependent:: IBM S/390 Dependent Features
+
+* SCORE-Dependent:: SCORE Dependent Features
+
+* SH-Dependent:: Renesas / SuperH SH Dependent Features
+* SH64-Dependent:: SuperH SH64 Dependent Features
+
+* Sparc-Dependent:: SPARC Dependent Features
+
+* TIC54X-Dependent:: TI TMS320C54x Dependent Features
+
+* TIC6X-Dependent :: TI TMS320C6x Dependent Features
+
+* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features
+
+* TILEPro-Dependent :: Tilera TILEPro Dependent Features
+
+* V850-Dependent:: V850 Dependent Features
+
+* Vax-Dependent:: VAX Dependent Features
+
+* Visium-Dependent:: Visium Dependent Features
+
+* XGATE-Dependent:: XGATE Features
+
+* XSTORMY16-Dependent:: XStormy16 Dependent Features
+
+* Xtensa-Dependent:: Xtensa Dependent Features
+
+* Z80-Dependent:: Z80 Dependent Features
+
+* Z8000-Dependent:: Z8000 Dependent Features
+
+
+File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies
+
+9.1 AArch64 Dependent Features
+==============================
+
+* Menu:
+
+* AArch64 Options:: Options
+* AArch64 Extensions:: Extensions
+* AArch64 Syntax:: Syntax
+* AArch64 Floating Point:: Floating Point
+* AArch64 Directives:: AArch64 Machine Directives
+* AArch64 Opcodes:: Opcodes
+* AArch64 Mapping Symbols:: Mapping Symbols
+
+
+File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent
+
+9.1.1 Options
+-------------
+
+`-EB'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a big-endian processor.
+
+`-EL'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a little-endian processor.
+
+`-mabi=ABI'
+ Specify which ABI the source code uses. The recognized arguments
+ are: `ilp32' and `lp64', which decides the generated object file
+ in ELF32 and ELF64 format respectively. The default is `lp64'.
+
+`-mcpu=PROCESSOR[+EXTENSION...]'
+ This option specifies the target processor. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target processor. The
+ following processor names are recognized: `cortex-a35',
+ `cortex-a53', `cortex-a57', `cortex-a72', `cortex-a73',
+ `exynos-m1', `falkor', `qdf24xx', `thunderx', `vulcan', `xgene1'
+ and `xgene2'. The special name `all' may be used to allow the
+ assembler to accept instructions valid for any supported
+ processor, including all optional extensions.
+
+ In addition to the basic instruction set, the assembler can be
+ told to accept, or restrict, various extension mnemonics that
+ extend the processor. *Note AArch64 Extensions::.
+
+ If some implementations of a particular processor can have an
+ extension, then then those extensions are automatically enabled.
+ Consequently, you will not normally have to specify any additional
+ extensions.
+
+`-march=ARCHITECTURE[+EXTENSION...]'
+ This option specifies the target architecture. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target architecture. The
+ following architecture names are recognized: `armv8-a',
+ `armv8.1-a', `armv8.2-a' and `armv8.3-a'.
+
+ If both `-mcpu' and `-march' are specified, the assembler will use
+ the setting for `-mcpu'. If neither are specified, the assembler
+ will default to `-mcpu=all'.
+
+ The architecture option can be extended with the same instruction
+ set extension options as the `-mcpu' option. Unlike `-mcpu',
+ extensions are not always enabled by default, *Note AArch64
+ Extensions::.
+
+`-mverbose-error'
+ This option enables verbose error messages for AArch64 gas. This
+ option is enabled by default.
+
+`-mno-verbose-error'
+ This option disables verbose error messages in AArch64 gas.
+
+
+
+File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent
+
+9.1.2 Architecture Extensions
+-----------------------------
+
+The table below lists the permitted architecture extensions that are
+supported by the assembler and the conditions under which they are
+automatically enabled.
+
+ Multiple extensions may be specified, separated by a `+'. Extension
+mnemonics may also be removed from those the assembler accepts. This
+is done by prepending `no' to the option that adds the extension.
+Extensions that are removed must be listed after all extensions that
+have been added.
+
+ Enabling an extension that requires other extensions will
+automatically cause those extensions to be enabled. Similarly,
+disabling an extension that is required by other extensions will
+automatically cause those extensions to be disabled.
+
+Extension Minimum Enabled by Description
+ Architecture default
+----------------------------------------------------------------------------
+`compnum' ARMv8.2-A ARMv8.3-A Enable the complex number SIMD
+ or later extensions. This implies `fp16' and
+ `simd'.
+`crc' ARMv8-A ARMv8.1-A Enable CRC instructions.
+ or later
+`crypto' ARMv8-A No Enable cryptographic extensions. This
+ implies `fp' and `simd'.
+`fp' ARMv8-A ARMv8-A or Enable floating-point extensions.
+ later
+`fp16' ARMv8.2-A ARMv8.2-A Enable ARMv8.2 16-bit floating-point
+ or later support. This implies `fp'.
+`lor' ARMv8-A ARMv8.1-A Enable Limited Ordering Regions
+ or later extensions.
+`lse' ARMv8-A ARMv8.1-A Enable Large System extensions.
+ or later
+`pan' ARMv8-A ARMv8.1-A Enable Privileged Access Never support.
+ or later
+`profile' ARMv8.2-A No Enable statistical profiling
+ extensions.
+`ras' ARMv8-A ARMv8.2-A Enable the Reliability, Availability
+ or later and Serviceability extension.
+`rdma' ARMv8-A ARMv8.1-A Enable ARMv8.1 Advanced SIMD
+ or later extensions. This implies `simd'.
+`simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions. This
+ later implies `fp'.
+`sve' ARMv8.2-A No Enable the Scalable Vector Extensions.
+ This implies `fp16', `simd' and
+ `compnum'.
+
+
+File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent
+
+9.1.3 Syntax
+------------
+
+* Menu:
+
+* AArch64-Chars:: Special Characters
+* AArch64-Regs:: Register Names
+* AArch64-Relocations:: Relocations
+
+
+File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax
+
+9.1.3.1 Special Characters
+..........................
+
+The presence of a `//' on a line indicates the start of a comment that
+extends to the end of the current line. If a `#' appears as the first
+character of a line, the whole line is treated as a comment.
+
+ The `;' character can be used instead of a newline to separate
+statements.
+
+ The `#' can be optionally used to indicate immediate operands.
+
+
+File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax
+
+9.1.3.2 Register Names
+......................
+
+Please refer to the section `4.4 Register Names' of `ARMv8 Instruction
+Set Overview', which is available at `http://infocenter.arm.com'.
+
+
+File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax
+
+9.1.3.3 Relocations
+...................
+
+Relocations for `MOVZ' and `MOVK' instructions can be generated by
+prefixing the label with `#:abs_g2:' etc. For example to load the
+48-bit absolute address of FOO into x0:
+
+ movz x0, #:abs_g2:foo // bits 32-47, overflow check
+ movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
+ movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
+
+ Relocations for `ADRP', and `ADD', `LDR' or `STR' instructions can
+be generated by prefixing the label with `:pg_hi21:' and `#:lo12:'
+respectively.
+
+ For example to use 33-bit (+/-4GB) pc-relative addressing to load
+the address of FOO into x0:
+
+ adrp x0, :pg_hi21:foo
+ add x0, x0, #:lo12:foo
+
+ Or to load the value of FOO into x0:
+
+ adrp x0, :pg_hi21:foo
+ ldr x0, [x0, #:lo12:foo]
+
+ Note that `:pg_hi21:' is optional.
+
+ adrp x0, foo
+
+ is equivalent to
+
+ adrp x0, :pg_hi21:foo
+
+
+File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent
+
+9.1.4 Floating Point
+--------------------
+
+The AArch64 architecture uses IEEE floating-point numbers.
+
+
+File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent
+
+9.1.5 AArch64 Machine Directives
+--------------------------------
+
+`.arch NAME'
+ Select the target architecture. Valid values for NAME are the
+ same as for the `-march' commandline option.
+
+ Specifying `.arch' clears any previously selected architecture
+ extensions.
+
+`.arch_extension NAME'
+ Add or remove an architecture extension to the target
+ architecture. Valid values for NAME are the same as those
+ accepted as architectural extensions by the `-mcpu' commandline
+ option.
+
+ `.arch_extension' may be used multiple times to add or remove
+ extensions incrementally to the architecture being compiled for.
+
+`.bss'
+ This directive switches to the `.bss' section.
+
+`.cpu NAME'
+ Set the target processor. Valid values for NAME are the same as
+ those accepted by the `-mcpu=' command line option.
+
+`.dword EXPRESSIONS'
+ The `.dword' directive produces 64 bit values.
+
+`.even'
+ The `.even' directive aligns the output on the next even byte
+ boundary.
+
+`.inst EXPRESSIONS'
+ Inserts the expressions into the output as if they were
+ instructions, rather than data.
+
+`.ltorg'
+ This directive causes the current contents of the literal pool to
+ be dumped into the current section (which is assumed to be the
+ .text section) at the current location (aligned to a word
+ boundary). GAS maintains a separate literal pool for each section
+ and each sub-section. The `.ltorg' directive will only affect the
+ literal pool of the current section and sub-section. At the end
+ of assembly all remaining, un-empty literal pools will
+ automatically be dumped.
+
+ Note - older versions of GAS would dump the current literal pool
+ any time a section change occurred. This is no longer done, since
+ it prevents accurate control of the placement of literal pools.
+
+`.pool'
+ This is a synonym for .ltorg.
+
+`NAME .req REGISTER NAME'
+ This creates an alias for REGISTER NAME called NAME. For example:
+
+ foo .req w0
+
+``.tlsdescadd''
+ Emits a TLSDESC_ADD reloc on the next instruction.
+
+``.tlsdesccall''
+ Emits a TLSDESC_CALL reloc on the next instruction.
+
+``.tlsdescldr''
+ Emits a TLSDESC_LDR reloc on the next instruction.
+
+`.unreq ALIAS-NAME'
+ This undefines a register alias which was previously defined using
+ the `req' directive. For example:
+
+ foo .req w0
+ .unreq foo
+
+ An error occurs if the name is undefined. Note - this pseudo op
+ can be used to delete builtin in register name aliases (eg 'w0').
+ This should only be done if it is really necessary.
+
+`.xword EXPRESSIONS'
+ The `.xword' directive produces 64 bit values. This is the same
+ as the `.dword' directive.
+
+
+
+File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent
+
+9.1.6 Opcodes
+-------------
+
+GAS implements all the standard AArch64 opcodes. It also implements
+several pseudo opcodes, including several synthetic load instructions.
+
+`LDR ='
+ ldr <register> , =<expression>
+
+ The constant expression will be placed into the nearest literal
+ pool (if it not already there) and a PC-relative LDR instruction
+ will be generated.
+
+
+ For more information on the AArch64 instruction set and assembly
+language notation, see `ARMv8 Instruction Set Overview' available at
+`http://infocenter.arm.com'.
+
+
+File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent
+
+9.1.7 Mapping Symbols
+---------------------
+
+The AArch64 ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+`$x'
+ At the start of a region of code containing AArch64 instructions.
+
+`$d'
+ At the start of a region of data.
+
+
+
+File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies
+
+9.2 Alpha Dependent Features
+============================
+
+* Menu:
+
+* Alpha Notes:: Notes
+* Alpha Options:: Options
+* Alpha Syntax:: Syntax
+* Alpha Floating Point:: Floating Point
+* Alpha Directives:: Alpha Machine Directives
+* Alpha Opcodes:: Opcodes
+
+
+File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent
+
+9.2.1 Notes
+-----------
+
+The documentation here is primarily for the ELF object format. `as'
+also supports the ECOFF and EVAX formats, but features specific to
+these formats are not yet documented.
+
+
+File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent
+
+9.2.2 Options
+-------------
+
+`-mCPU'
+ This option specifies the target processor. If an attempt is made
+ to assemble an instruction which will not execute on the target
+ processor, the assembler may either expand the instruction as a
+ macro or issue an error message. This option is equivalent to the
+ `.arch' directive.
+
+ The following processor names are recognized: `21064', `21064a',
+ `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a',
+ `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6',
+ `ev67', `ev68'. The special name `all' may be used to allow the
+ assembler to accept instructions valid for any Alpha processor.
+
+ In order to support existing practice in OSF/1 with respect to
+ `.arch', and existing practice within `MILO' (the Linux ARC
+ bootloader), the numbered processor names (e.g. 21064) enable the
+ processor-specific PALcode instructions, while the
+ "electro-vlasic" names (e.g. `ev4') do not.
+
+`-mdebug'
+`-no-mdebug'
+ Enables or disables the generation of `.mdebug' encapsulation for
+ stabs directives and procedure descriptors. The default is to
+ automatically enable `.mdebug' when the first stabs directive is
+ seen.
+
+`-relax'
+ This option forces all relocations to be put into the object file,
+ instead of saving space and resolving some relocations at assembly
+ time. Note that this option does not propagate all symbol
+ arithmetic into the object file, because not all symbol arithmetic
+ can be represented. However, the option can still be useful in
+ specific applications.
+
+`-replace'
+`-noreplace'
+ Enables or disables the optimization of procedure calls, both at
+ assemblage and at link time. These options are only available for
+ VMS targets and `-replace' is the default. See section 1.4.1 of
+ the OpenVMS Linker Utility Manual.
+
+`-g'
+ This option is used when the compiler generates debug information.
+ When `gcc' is using `mips-tfile' to generate debug information
+ for ECOFF, local labels must be passed through to the object file.
+ Otherwise this option has no effect.
+
+`-GSIZE'
+ A local common symbol larger than SIZE is placed in `.bss', while
+ smaller symbols are placed in `.sbss'.
+
+`-F'
+`-32addr'
+ These options are ignored for backward compatibility.
+
+
+File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent
+
+9.2.3 Syntax
+------------
+
+The assembler syntax closely follow the Alpha Reference Manual;
+assembler directives and general syntax closely follow the OSF/1 and
+OpenVMS syntax, with a few differences for ELF.
+
+* Menu:
+
+* Alpha-Chars:: Special Characters
+* Alpha-Regs:: Register Names
+* Alpha-Relocs:: Relocations
+
+
+File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax
+
+9.2.3.1 Special Characters
+..........................
+
+`#' is the line comment character. Note that if `#' is the first
+character on a line then it can also be a logical line number directive
+(*note Comments::) or a preprocessor control command (*note
+Preprocessing::).
+
+ `;' can be used instead of a newline to separate statements.
+
+
+File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax
+
+9.2.3.2 Register Names
+......................
+
+The 32 integer registers are referred to as `$N' or `$rN'. In
+addition, registers 15, 28, 29, and 30 may be referred to by the
+symbols `$fp', `$at', `$gp', and `$sp' respectively.
+
+ The 32 floating-point registers are referred to as `$fN'.
+
+
+File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax
+
+9.2.3.3 Relocations
+...................
+
+Some of these relocations are available for ECOFF, but mostly only for
+ELF. They are modeled after the relocation format introduced in
+Digital Unix 4.0, but there are additions.
+
+ The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the
+relocation. In some cases NUMBER is used to relate specific
+instructions.
+
+ The relocation is placed at the end of the instruction like so:
+
+ ldah $0,a($29) !gprelhigh
+ lda $0,a($0) !gprellow
+ ldq $1,b($29) !literal!100
+ ldl $2,0($1) !lituse_base!100
+
+`!literal'
+`!literal!N'
+ Used with an `ldq' instruction to load the address of a symbol
+ from the GOT.
+
+ A sequence number N is optional, and if present is used to pair
+ `lituse' relocations with this `literal' relocation. The `lituse'
+ relocations are used by the linker to optimize the code based on
+ the final location of the symbol.
+
+ Note that these optimizations are dependent on the data flow of the
+ program. Therefore, if _any_ `lituse' is paired with a `literal'
+ relocation, then _all_ uses of the register set by the `literal'
+ instruction must also be marked with `lituse' relocations. This
+ is because the original `literal' instruction may be deleted or
+ transformed into another instruction.
+
+ Also note that there may be a one-to-many relationship between
+ `literal' and `lituse', but not a many-to-one. That is, if there
+ are two code paths that load up the same address and feed the
+ value to a single use, then the use may not use a `lituse'
+ relocation.
+
+`!lituse_base!N'
+ Used with any memory format instruction (e.g. `ldl') to indicate
+ that the literal is used for an address load. The offset field of
+ the instruction must be zero. During relaxation, the code may be
+ altered to use a gp-relative load.
+
+`!lituse_jsr!N'
+ Used with a register branch format instruction (e.g. `jsr') to
+ indicate that the literal is used for a call. During relaxation,
+ the code may be altered to use a direct branch (e.g. `bsr').
+
+`!lituse_jsrdirect!N'
+ Similar to `lituse_jsr', but also that this call cannot be vectored
+ through a PLT entry. This is useful for functions with special
+ calling conventions which do not allow the normal call-clobbered
+ registers to be clobbered.
+
+`!lituse_bytoff!N'
+ Used with a byte mask instruction (e.g. `extbl') to indicate that
+ only the low 3 bits of the address are relevant. During
+ relaxation, the code may be altered to use an immediate instead of
+ a register shift.
+
+`!lituse_addr!N'
+ Used with any other instruction to indicate that the original
+ address is in fact used, and the original `ldq' instruction may
+ not be altered or deleted. This is useful in conjunction with
+ `lituse_jsr' to test whether a weak symbol is defined.
+
+ ldq $27,foo($29) !literal!1
+ beq $27,is_undef !lituse_addr!1
+ jsr $26,($27),foo !lituse_jsr!1
+
+`!lituse_tlsgd!N'
+ Used with a register branch format instruction to indicate that the
+ literal is the call to `__tls_get_addr' used to compute the
+ address of the thread-local storage variable whose descriptor was
+ loaded with `!tlsgd!N'.
+
+`!lituse_tlsldm!N'
+ Used with a register branch format instruction to indicate that the
+ literal is the call to `__tls_get_addr' used to compute the
+ address of the base of the thread-local storage block for the
+ current module. The descriptor for the module must have been
+ loaded with `!tlsldm!N'.
+
+`!gpdisp!N'
+ Used with `ldah' and `lda' to load the GP from the current
+ address, a-la the `ldgp' macro. The source register for the
+ `ldah' instruction must contain the address of the `ldah'
+ instruction. There must be exactly one `lda' instruction paired
+ with the `ldah' instruction, though it may appear anywhere in the
+ instruction stream. The immediate operands must be zero.
+
+ bsr $26,foo
+ ldah $29,0($26) !gpdisp!1
+ lda $29,0($29) !gpdisp!1
+
+`!gprelhigh'
+ Used with an `ldah' instruction to add the high 16 bits of a
+ 32-bit displacement from the GP.
+
+`!gprellow'
+ Used with any memory format instruction to add the low 16 bits of a
+ 32-bit displacement from the GP.
+
+`!gprel'
+ Used with any memory format instruction to add a 16-bit
+ displacement from the GP.
+
+`!samegp'
+ Used with any branch format instruction to skip the GP load at the
+ target address. The referenced symbol must have the same GP as the
+ source object file, and it must be declared to either not use `$27'
+ or perform a standard GP load in the first two instructions via the
+ `.prologue' directive.
+
+`!tlsgd'
+`!tlsgd!N'
+ Used with an `lda' instruction to load the address of a TLS
+ descriptor for a symbol in the GOT.
+
+ The sequence number N is optional, and if present it used to pair
+ the descriptor load with both the `literal' loading the address of
+ the `__tls_get_addr' function and the `lituse_tlsgd' marking the
+ call to that function.
+
+ For proper relaxation, both the `tlsgd', `literal' and `lituse'
+ relocations must be in the same extended basic block. That is,
+ the relocation with the lowest address must be executed first at
+ runtime.
+
+`!tlsldm'
+`!tlsldm!N'
+ Used with an `lda' instruction to load the address of a TLS
+ descriptor for the current module in the GOT.
+
+ Similar in other respects to `tlsgd'.
+
+`!gotdtprel'
+ Used with an `ldq' instruction to load the offset of the TLS
+ symbol within its module's thread-local storage block. Also known
+ as the dynamic thread pointer offset or dtp-relative offset.
+
+`!dtprelhi'
+`!dtprello'
+`!dtprel'
+ Like `gprel' relocations except they compute dtp-relative offsets.
+
+`!gottprel'
+ Used with an `ldq' instruction to load the offset of the TLS
+ symbol from the thread pointer. Also known as the tp-relative
+ offset.
+
+`!tprelhi'
+`!tprello'
+`!tprel'
+ Like `gprel' relocations except they compute tp-relative offsets.
+
+
+File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent
+
+9.2.4 Floating Point
+--------------------
+
+The Alpha family uses both IEEE and VAX floating-point numbers.
+
+
+File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent
+
+9.2.5 Alpha Assembler Directives
+--------------------------------
+
+`as' for the Alpha supports many additional directives for
+compatibility with the native assembler. This section describes them
+only briefly.
+
+ These are the additional directives in `as' for the Alpha:
+
+`.arch CPU'
+ Specifies the target processor. This is equivalent to the `-mCPU'
+ command-line option. *Note Options: Alpha Options, for a list of
+ values for CPU.
+
+`.ent FUNCTION[, N]'
+ Mark the beginning of FUNCTION. An optional number may follow for
+ compatibility with the OSF/1 assembler, but is ignored. When
+ generating `.mdebug' information, this will create a procedure
+ descriptor for the function. In ELF, it will mark the symbol as a
+ function a-la the generic `.type' directive.
+
+`.end FUNCTION'
+ Mark the end of FUNCTION. In ELF, it will set the size of the
+ symbol a-la the generic `.size' directive.
+
+`.mask MASK, OFFSET'
+ Indicate which of the integer registers are saved in the current
+ function's stack frame. MASK is interpreted a bit mask in which
+ bit N set indicates that register N is saved. The registers are
+ saved in a block located OFFSET bytes from the "canonical frame
+ address" (CFA) which is the value of the stack pointer on entry to
+ the function. The registers are saved sequentially, except that
+ the return address register (normally `$26') is saved first.
+
+ This and the other directives that describe the stack frame are
+ currently only used when generating `.mdebug' information. They
+ may in the future be used to generate DWARF2 `.debug_frame' unwind
+ information for hand written assembly.
+
+`.fmask MASK, OFFSET'
+ Indicate which of the floating-point registers are saved in the
+ current stack frame. The MASK and OFFSET parameters are
+ interpreted as with `.mask'.
+
+`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
+ Describes the shape of the stack frame. The frame pointer in use
+ is FRAMEREG; normally this is either `$fp' or `$sp'. The frame
+ pointer is FRAMEOFFSET bytes below the CFA. The return address is
+ initially located in RETREG until it is saved as indicated in
+ `.mask'. For compatibility with OSF/1 an optional ARGOFFSET
+ parameter is accepted and ignored. It is believed to indicate the
+ offset from the CFA to the saved argument registers.
+
+`.prologue N'
+ Indicate that the stack frame is set up and all registers have been
+ spilled. The argument N indicates whether and how the function
+ uses the incoming "procedure vector" (the address of the called
+ function) in `$27'. 0 indicates that `$27' is not used; 1
+ indicates that the first two instructions of the function use `$27'
+ to perform a load of the GP register; 2 indicates that `$27' is
+ used in some non-standard way and so the linker cannot elide the
+ load of the procedure vector during relaxation.
+
+`.usepv FUNCTION, WHICH'
+ Used to indicate the use of the `$27' register, similar to
+ `.prologue', but without the other semantics of needing to be
+ inside an open `.ent'/`.end' block.
+
+ The WHICH argument should be either `no', indicating that `$27' is
+ not used, or `std', indicating that the first two instructions of
+ the function perform a GP load.
+
+ One might use this directive instead of `.prologue' if you are
+ also using dwarf2 CFI directives.
+
+`.gprel32 EXPRESSION'
+ Computes the difference between the address in EXPRESSION and the
+ GP for the current object file, and stores it in 4 bytes. In
+ addition to being smaller than a full 8 byte address, this also
+ does not require a dynamic relocation when used in a shared
+ library.
+
+`.t_floating EXPRESSION'
+ Stores EXPRESSION as an IEEE double precision value.
+
+`.s_floating EXPRESSION'
+ Stores EXPRESSION as an IEEE single precision value.
+
+`.f_floating EXPRESSION'
+ Stores EXPRESSION as a VAX F format value.
+
+`.g_floating EXPRESSION'
+ Stores EXPRESSION as a VAX G format value.
+
+`.d_floating EXPRESSION'
+ Stores EXPRESSION as a VAX D format value.
+
+`.set FEATURE'
+ Enables or disables various assembler features. Using the positive
+ name of the feature enables while using `noFEATURE' disables.
+
+ `at'
+ Indicates that macro expansions may clobber the "assembler
+ temporary" (`$at' or `$28') register. Some macros may not be
+ expanded without this and will generate an error message if
+ `noat' is in effect. When `at' is in effect, a warning will
+ be generated if `$at' is used by the programmer.
+
+ `macro'
+ Enables the expansion of macro instructions. Note that
+ variants of real instructions, such as `br label' vs `br
+ $31,label' are considered alternate forms and not macros.
+
+ `move'
+ `reorder'
+ `volatile'
+ These control whether and how the assembler may re-order
+ instructions. Accepted for compatibility with the OSF/1
+ assembler, but `as' does not do instruction scheduling, so
+ these features are ignored.
+
+ The following directives are recognized for compatibility with the
+OSF/1 assembler but are ignored.
+
+ .proc .aproc
+ .reguse .livereg
+ .option .aent
+ .ugen .eflag
+ .alias .noalias
+
+
+File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent
+
+9.2.6 Opcodes
+-------------
+
+For detailed information on the Alpha machine instruction set, see the
+Alpha Architecture Handbook
+(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
+
+
+File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies
+
+9.3 ARC Dependent Features
+==========================
+
+* Menu:
+
+* ARC Options:: Options
+* ARC Syntax:: Syntax
+* ARC Directives:: ARC Machine Directives
+* ARC Modifiers:: ARC Assembler Modifiers
+* ARC Symbols:: ARC Pre-defined Symbols
+* ARC Opcodes:: Opcodes
+
+
+File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent
+
+9.3.1 Options
+-------------
+
+The following options control the type of CPU for which code is
+assembled, and generic constraints on the code generated:
+
+`-mcpu=CPU'
+ Set architecture type and register usage for CPU. There are also
+ shortcut alias options available for backward compatibility and
+ convenience. Supported values for CPU are
+
+ `arc600'
+ Assemble for ARC 600. Aliases: `-mA6', `-mARC600'.
+
+ `arc600_norm'
+ Assemble for ARC 600 with norm instructions.
+
+ `arc600_mul64'
+ Assemble for ARC 600 with mul64 instructions.
+
+ `arc600_mul32x16'
+ Assemble for ARC 600 with mul32x16 instructions.
+
+ `arc601'
+ Assemble for ARC 601. Alias: `-mARC601'.
+
+ `arc601_norm'
+ Assemble for ARC 601 with norm instructions.
+
+ `arc601_mul64'
+ Assemble for ARC 601 with mul64 instructions.
+
+ `arc601_mul32x16'
+ Assemble for ARC 601 with mul32x16 instructions.
+
+ `arc700'
+ Assemble for ARC 700. Aliases: `-mA7', `-mARC700'.
+
+ `arcem'
+ Assemble for ARC EM. Aliases: `-mEM'
+
+ `em'
+ Assemble for ARC EM, identical as arcem variant.
+
+ `em4'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_dmips'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_fpus'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_fpuda'
+ Assemble for ARC EM with code-density, and double-precision
+ assist instructions.
+
+ `quarkse_em'
+ Assemble for QuarkSE-EM cpu.
+
+ `archs'
+ Assemble for ARC HS. Aliases: `-mHS', `-mav2hs'.
+
+ `hs'
+ Assemble for ARC HS.
+
+ `hs34'
+ Assemble for ARC HS34.
+
+ `hs38'
+ Assemble for ARC HS38.
+
+ `hs38_linux'
+ Assemble for ARC HS38 with floating point support on.
+
+ `nps400'
+ Assemble for ARC 700 with NPS-400 extended instructions.
+
+
+ Note: the `.cpu' directive (*note ARC Directives::) can to be used
+ to select a core variant from within assembly code.
+
+`-EB'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a big-endian processor.
+
+`-EL'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a little-endian processor -
+ this is the default.
+
+`-mcode-density'
+ This option turns on Code Density instructions. Only valid for
+ ARC EM processors.
+
+`-mrelax'
+ Enable support for assembly-time relaxation. The assembler will
+ replace a longer version of an instruction with a shorter one,
+ whenever it is possible.
+
+`-mnps400'
+ Enable support for NPS-400 extended instructions.
+
+`-mspfp'
+ Enable support for single-precision floating point instructions.
+
+`-mdpfp'
+ Enable support for double-precision floating point instructions.
+
+`-mfpuda'
+ Enable support for double-precision assist floating point
+ instructions. Only valid for ARC EM processors.
+
+
+
+File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent
+
+9.3.2 Syntax
+------------
+
+* Menu:
+
+* ARC-Chars:: Special Characters
+* ARC-Regs:: Register Names
+
+
+File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax
+
+9.3.2.1 Special Characters
+..........................
+
+`%'
+ A register name can optionally be prefixed by a `%' character. So
+ register `%r0' is equivalent to `r0' in the assembly code.
+
+`#'
+ The presence of a `#' character within a line (but not at the
+ start of a line) indicates the start of a comment that extends to
+ the end of the current line.
+
+ _Note:_ if a line starts with a `#' character then it can also be
+ a logical line number directive (*note Comments::) or a
+ preprocessor control command (*note Preprocessing::).
+
+`@'
+ Prefixing an operand with an `@' specifies that the operand is a
+ symbol and not a register. This is how the assembler disambiguates
+ the use of an ARC register name as a symbol. So the instruction
+ mov r0, @r0
+ moves the address of symbol `r0' into register `r0'.
+
+``'
+ The ``' (backtick) character is used to separate statements on a
+ single line.
+
+`-'
+ Used as a separator to obtain a sequence of commands from a C
+ preprocessor macro.
+
+
+
+File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax
+
+9.3.2.2 Register Names
+......................
+
+The ARC assembler uses the following register names for its core
+registers:
+
+`r0-r31'
+ The core general registers. Registers `r26' through `r31' have
+ special functions, and are usually referred to by those synonyms.
+
+`gp'
+ The global pointer and a synonym for `r26'.
+
+`fp'
+ The frame pointer and a synonym for `r27'.
+
+`sp'
+ The stack pointer and a synonym for `r28'.
+
+`ilink1'
+ For ARC 600 and ARC 700, the level 1 interrupt link register and a
+ synonym for `r29'. Not supported for ARCv2.
+
+`ilink'
+ For ARCv2, the interrupt link register and a synonym for `r29'.
+ Not supported for ARC 600 and ARC 700.
+
+`ilink2'
+ For ARC 600 and ARC 700, the level 2 interrupt link register and a
+ synonym for `r30'. Not supported for ARC v2.
+
+`blink'
+ The link register and a synonym for `r31'.
+
+`r32-r59'
+ The extension core registers.
+
+`lp_count'
+ The loop count register.
+
+`pcl'
+ The word aligned program counter.
+
+
+ In addition the ARC processor has a large number of _auxiliary
+registers_. The precise set depends on the extensions being supported,
+but the following baseline set are always defined:
+
+`identity'
+ Processor Identification register. Auxiliary register address 0x4.
+
+`pc'
+ Program Counter. Auxiliary register address 0x6.
+
+`status32'
+ Status register. Auxiliary register address 0x0a.
+
+`bta'
+ Branch Target Address. Auxiliary register address 0x412.
+
+`ecr'
+ Exception Cause Register. Auxiliary register address 0x403.
+
+`int_vector_base'
+ Interrupt Vector Base address. Auxiliary register address 0x25.
+
+`status32_p0'
+ Stored STATUS32 register on entry to level P0 interrupts.
+ Auxiliary register address 0xb.
+
+`aux_user_sp'
+ Saved User Stack Pointer. Auxiliary register address 0xd.
+
+`eret'
+ Exception Return Address. Auxiliary register address 0x400.
+
+`erbta'
+ BTA saved on exception entry. Auxiliary register address 0x401.
+
+`erstatus'
+ STATUS32 saved on exception. Auxiliary register address 0x402.
+
+`bcr_ver'
+ Build Configuration Registers Version. Auxiliary register address
+ 0x60.
+
+`bta_link_build'
+ Build configuration for: BTA Registers. Auxiliary register
+ address 0x63.
+
+`vecbase_ac_build'
+ Build configuration for: Interrupts. Auxiliary register address
+ 0x68.
+
+`rf_build'
+ Build configuration for: Core Registers. Auxiliary register
+ address 0x6e.
+
+`dccm_build'
+ DCCM RAM Configuration Register. Auxiliary register address 0xc1.
+
+
+ Additional auxiliary register names are defined according to the
+processor architecture version and extensions selected by the options.
+
+
+File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent
+
+9.3.3 ARC Machine Directives
+----------------------------
+
+The ARC version of `as' supports the following additional machine
+directives:
+
+`.lcomm SYMBOL, LENGTH[, ALIGNMENT]'
+ Reserve LENGTH (an absolute expression) bytes for a local common
+ denoted by SYMBOL. The section and value of SYMBOL are those of
+ the new local common. The addresses are allocated in the bss
+ section, so that at run-time the bytes start off zeroed. Since
+ SYMBOL is not declared global, it is normally not visible to `ld'.
+ The optional third parameter, ALIGNMENT, specifies the desired
+ alignment of the symbol in the bss section, specified as a byte
+ boundary (for example, an alignment of 16 means that the least
+ significant 4 bits of the address should be zero). The alignment
+ must be an absolute expression, and it must be a power of two. If
+ no alignment is specified, as will set the alignment to the
+ largest power of two less than or equal to the size of the symbol,
+ up to a maximum of 16.
+
+`.lcommon SYMBOL, LENGTH[, ALIGNMENT]'
+ The same as `lcomm' directive.
+
+`.cpu CPU'
+ The `.cpu' directive must be followed by the desired core version.
+ Permitted values for CPU are:
+ `ARC600'
+ Assemble for the ARC600 instruction set.
+
+ `arc600_norm'
+ Assemble for ARC 600 with norm instructions.
+
+ `arc600_mul64'
+ Assemble for ARC 600 with mul64 instructions.
+
+ `arc600_mul32x16'
+ Assemble for ARC 600 with mul32x16 instructions.
+
+ `arc601'
+ Assemble for ARC 601 instruction set.
+
+ `arc601_norm'
+ Assemble for ARC 601 with norm instructions.
+
+ `arc601_mul64'
+ Assemble for ARC 601 with mul64 instructions.
+
+ `arc601_mul32x16'
+ Assemble for ARC 601 with mul32x16 instructions.
+
+ `ARC700'
+ Assemble for the ARC700 instruction set.
+
+ `NPS400'
+ Assemble for the NPS400 instruction set.
+
+ `EM'
+ Assemble for the ARC EM instruction set.
+
+ `arcem'
+ Assemble for ARC EM instruction set
+
+ `em4'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_dmips'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_fpus'
+ Assemble for ARC EM with code-density instructions.
+
+ `em4_fpuda'
+ Assemble for ARC EM with code-density, and double-precision
+ assist instructions.
+
+ `quarkse_em'
+ Assemble for QuarkSE-EM instruction set.
+
+ `HS'
+ Assemble for the ARC HS instruction set.
+
+ `archs'
+ Assemble for ARC HS instruction set.
+
+ `hs'
+ Assemble for ARC HS instruction set.
+
+ `hs34'
+ Assemble for ARC HS34 instruction set.
+
+ `hs38'
+ Assemble for ARC HS38 instruction set.
+
+ `hs38_linux'
+ Assemble for ARC HS38 with floating point support on.
+
+
+ Note: the `.cpu' directive overrides the command line option
+ `-mcpu=CPU'; a warning is emitted when the version is not
+ consistent between the two.
+
+`.extAuxRegister NAME, ADDR, MODE'
+ Auxiliary registers can be defined in the assembler source code by
+ using this directive. The first parameter, NAME, is the name of
+ the new auxiliary register. The second parameter, ADDR, is
+ address the of the auxiliary register. The third parameter, MODE,
+ specifies whether the register is readable and/or writable and is
+ one of:
+ `r'
+ Read only;
+
+ `w'
+ Write only;
+
+ `r|w'
+ Read and write.
+
+
+ For example:
+ .extAuxRegister mulhi, 0x12, w
+ specifies a write only extension auxiliary register, MULHI at
+ address 0x12.
+
+`.extCondCode SUFFIX, VAL'
+ ARC supports extensible condition codes. This directive defines a
+ new condition code, to be known by the suffix, SUFFIX and will
+ depend on the value, VAL in the condition code.
+
+ For example:
+ .extCondCode is_busy,0x14
+ add.is_busy r1,r2,r3
+ will only execute the `add' instruction if the condition code
+ value is 0x14.
+
+`.extCoreRegister NAME, REGNUM, MODE, SHORTCUT'
+ Specifies an extension core register named NAME as a synonym for
+ the register numbered REGNUM. The register number must be between
+ 32 and 59. The third argument, MODE, indicates whether the
+ register is readable and/or writable and is one of:
+ `r'
+ Read only;
+
+ `w'
+ Write only;
+
+ `r|w'
+ Read and write.
+
+
+ The final parameter, SHORTCUT indicates whether the register has a
+ short cut in the pipeline. The valid values are:
+ `can_shortcut'
+ The register has a short cut in the pipeline;
+
+ `cannot_shortcut'
+ The register does not have a short cut in the pipeline.
+
+ For example:
+ .extCoreRegister mlo, 57, r , can_shortcut
+ defines a read only extension core register, `mlo', which is
+ register 57, and can short cut the pipeline.
+
+`.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS'
+ ARC allows the user to specify extension instructions. These
+ extension instructions are not macros; the assembler creates
+ encodings for use of these instructions according to the
+ specification by the user.
+
+ The first argument, NAME, gives the name of the instruction.
+
+ The second argument, OPCODE, is the opcode to be used (bits 31:27
+ in the encoding).
+
+ The third argument, SUBOPCODE, is the sub-opcode to be used, but
+ the correct value also depends on the fifth argument, SYNTAXCLASS
+
+ The fourth argument, SUFFIXCLASS, determines the kinds of suffixes
+ to be allowed. Valid values are:
+ `SUFFIX_NONE'
+ No suffixes are permitted;
+
+ `SUFFIX_COND'
+ Conditional suffixes are permitted;
+
+ `SUFFIX_FLAG'
+ Flag setting suffixes are permitted.
+
+ `SUFFIX_COND|SUFFIX_FLAG'
+ Both conditional and flag setting suffices are permitted.
+
+
+ The fifth and final argument, SYNTAXCLASS, determines the syntax
+ class for the instruction. It can have the following values:
+ `SYNTAX_2OP'
+ Two Operand Instruction;
+
+ `SYNTAX_3OP'
+ Three Operand Instruction.
+
+ `SYNTAX_1OP'
+ One Operand Instruction.
+
+ `SYNTAX_NOP'
+ No Operand Instruction.
+
+ The syntax class may be followed by `|' and one of the following
+ modifiers.
+ `OP1_MUST_BE_IMM'
+ Modifies syntax class `SYNTAX_3OP', specifying that the first
+ operand of a three-operand instruction must be an immediate
+ (i.e., the result is discarded). This is usually used to set
+ the flags using specific instructions and not retain results.
+
+ `OP1_IMM_IMPLIED'
+ Modifies syntax class `SYNTAX_20P', specifying that there is
+ an implied immediate destination operand which does not
+ appear in the syntax.
+
+ For example, if the source code contains an instruction like:
+ inst r1,r2
+ the first argument is an implied immediate (that is, the
+ result is discarded). This is the same as though the source
+ code were: inst 0,r1,r2.
+
+
+ For example, defining a 64-bit multiplier with immediate operands:
+ .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
+ SYNTAX_3OP|OP1_MUST_BE_IMM
+ which specifies an extension instruction named `mp64' with 3
+ operands. It sets the flags and can be used with a condition code,
+ for which the first operand is an immediate, i.e. equivalent to
+ discarding the result of the operation.
+
+ A two operands instruction variant would be:
+ .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
+ SYNTAX_2OP|OP1_IMM_IMPLIED
+ which describes a two operand instruction with an implicit first
+ immediate operand. The result of this operation would be
+ discarded.
+
+
+
+File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent
+
+9.3.4 ARC Assembler Modifiers
+-----------------------------
+
+The following additional assembler modifiers have been added for
+position-independent code. These modifiers are available only with the
+ARC 700 and above processors and generate relocation entries, which are
+interpreted by the linker as follows:
+
+`@pcl(SYMBOL)'
+ Relative distance of SYMBOL's from the current program counter
+ location.
+
+`@gotpc(SYMBOL)'
+ Relative distance of SYMBOL's Global Offset Table entry from the
+ current program counter location.
+
+`@gotoff(SYMBOL)'
+ Distance of SYMBOL from the base of the Global Offset Table.
+
+`@plt(SYMBOL)'
+ Distance of SYMBOL's Procedure Linkage Table entry from the
+ current program counter. This is valid only with branch and link
+ instructions and PC-relative calls.
+
+`@sda(SYMBOL)'
+ Relative distance of SYMBOL from the base of the Small Data
+ Pointer.
+
+
+
+File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent
+
+9.3.5 ARC Pre-defined Symbols
+-----------------------------
+
+The following assembler symbols will prove useful when developing
+position-independent code. These symbols are available only with the
+ARC 700 and above processors.
+
+`__GLOBAL_OFFSET_TABLE__'
+ Symbol referring to the base of the Global Offset Table.
+
+`__DYNAMIC__'
+ An alias for the Global Offset Table
+ `Base__GLOBAL_OFFSET_TABLE__'. It can be used only with `@gotpc'
+ modifiers.
+
+
+
+File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent
+
+9.3.6 Opcodes
+-------------
+
+For information on the ARC instruction set, see `ARC Programmers
+Reference Manual', available where you download the processor IP
+library.
+
+
+File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies
+
+9.4 ARM Dependent Features
+==========================
+
+* Menu:
+
+* ARM Options:: Options
+* ARM Syntax:: Syntax
+* ARM Floating Point:: Floating Point
+* ARM Directives:: ARM Machine Directives
+* ARM Opcodes:: Opcodes
+* ARM Mapping Symbols:: Mapping Symbols
+* ARM Unwinding Tutorial:: Unwinding
+
+
+File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent
+
+9.4.1 Options
+-------------
+
+`-mcpu=PROCESSOR[+EXTENSION...]'
+ This option specifies the target processor. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target processor. The
+ following processor names are recognized: `arm1', `arm2', `arm250',
+ `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
+ `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
+ `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t',
+ `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
+ `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
+ `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
+ `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday
+ FA526 processor), `fa626' (Faraday FA626 processor), `arm9e',
+ `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s',
+ `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t',
+ `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e',
+ `arm1022e', `arm1026ej-s', `fa606te' (Faraday FA606TE processor),
+ `fa616te' (Faraday FA616TE processor), `fa626te' (Faraday FA626TE
+ processor), `fmp626' (Faraday FMP626 processor), `fa726te'
+ (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s',
+ `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s',
+ `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a7', `cortex-a8',
+ `cortex-a9', `cortex-a15', `cortex-a17', `cortex-a32',
+ `cortex-a35', `cortex-a53', `cortex-a57', `cortex-a72',
+ `cortex-a73', `cortex-r4', `cortex-r4f', `cortex-r5', `cortex-r7',
+ `cortex-r8', `cortex-m33', `cortex-m23', `cortex-m7', `cortex-m4',
+ `cortex-m3', `cortex-m1', `cortex-m0', `cortex-m0plus',
+ `exynos-m1', `marvell-pj4', `marvell-whitney', `falkor', `qdf24xx',
+ `xgene1', `xgene2', `ep9312' (ARM920 with Cirrus Maverick
+ coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r)
+ XScale processor with Wireless MMX(tm) technology coprocessor) and
+ `xscale'. The special name `all' may be used to allow the
+ assembler to accept instructions valid for any ARM processor.
+
+ In addition to the basic instruction set, the assembler can be
+ told to accept various extension mnemonics that extend the
+ processor using the co-processor instruction space. For example,
+ `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'.
+
+ Multiple extensions may be specified, separated by a `+'. The
+ extensions should be specified in ascending alphabetical order.
+
+ Some extensions may be restricted to particular architectures;
+ this is documented in the list of extensions below.
+
+ Extension mnemonics may also be removed from those the assembler
+ accepts. This is done be prepending `no' to the option that adds
+ the extension. Extensions that are removed should be listed after
+ all extensions which have been added, again in ascending
+ alphabetical order. For example, `-mcpu=ep9312+nomaverick' is
+ equivalent to specifying `-mcpu=arm920'.
+
+ The following extensions are currently supported: `crc' `crypto'
+ (Cryptography Extensions for v8-A architecture, implies `fp+simd'),
+ `fp' (Floating Point Extensions for v8-A architecture), `idiv'
+ (Integer Divide Extensions for v7-A and v7-R architectures),
+ `iwmmxt', `iwmmxt2', `xscale', `maverick', `mp' (Multiprocessing
+ Extensions for v7-A and v7-R architectures), `os' (Operating
+ System for v6M architecture), `sec' (Security Extensions for v6K
+ and v7-A architectures), `simd' (Advanced SIMD Extensions for v8-A
+ architecture, implies `fp'), `virt' (Virtualization Extensions for
+ v7-A architecture, implies `idiv'), `pan' (Priviliged Access Never
+ Extensions for v8-A architecture), `ras' (Reliability,
+ Availability and Serviceability extensions for v8-A architecture),
+ `rdma' (ARMv8.1 Advanced SIMD extensions for v8-A architecture,
+ implies `simd') and `xscale'.
+
+`-march=ARCHITECTURE[+EXTENSION...]'
+ This option specifies the target architecture. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target architecture.
+ The following architecture names are recognized: `armv1', `armv2',
+ `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm',
+ `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te',
+ `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6kz',
+ `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7ve', `armv7-r',
+ `armv7-m', `armv7e-m', `armv8-a', `armv8.1-a', `armv8.2-a',
+ `armv8.3-a', `iwmmxt' `iwmmxt2' and `xscale'. If both `-mcpu' and
+ `-march' are specified, the assembler will use the setting for
+ `-mcpu'.
+
+ The architecture option can be extended with the same instruction
+ set extension options as the `-mcpu' option.
+
+`-mfpu=FLOATING-POINT-FORMAT'
+ This option specifies the floating point format to assemble for.
+ The assembler will issue an error message if an attempt is made to
+ assemble an instruction which will not execute on the target
+ floating point unit. The following format options are recognized:
+ `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
+ `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
+ `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16',
+ `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16',
+ `fpv4-sp-d16', `fpv5-sp-d16', `fpv5-d16', `fp-armv8', `arm1020t',
+ `arm1020e', `arm1136jf-s', `maverick', `neon', `neon-vfpv4',
+ `neon-fp-armv8', `crypto-neon-fp-armv8', `neon-fp-armv8.1' and
+ `crypto-neon-fp-armv8.1'.
+
+ In addition to determining which instructions are assembled, this
+ option also affects the way in which the `.double' assembler
+ directive behaves when assembling little-endian code.
+
+ The default is dependent on the processor selected. For
+ Architecture 5 or later, the default is to assembler for VFP
+ instructions; for earlier architectures the default is to assemble
+ for FPA instructions.
+
+`-mthumb'
+ This option specifies that the assembler should start assembling
+ Thumb instructions; that is, it should behave as though the file
+ starts with a `.code 16' directive.
+
+`-mthumb-interwork'
+ This option specifies that the output generated by the assembler
+ should be marked as supporting interworking.
+
+`-mimplicit-it=never'
+`-mimplicit-it=always'
+`-mimplicit-it=arm'
+`-mimplicit-it=thumb'
+ The `-mimplicit-it' option controls the behavior of the assembler
+ when conditional instructions are not enclosed in IT blocks.
+ There are four possible behaviors. If `never' is specified, such
+ constructs cause a warning in ARM code and an error in Thumb-2
+ code. If `always' is specified, such constructs are accepted in
+ both ARM and Thumb-2 code, where the IT instruction is added
+ implicitly. If `arm' is specified, such constructs are accepted
+ in ARM code and cause an error in Thumb-2 code. If `thumb' is
+ specified, such constructs cause a warning in ARM code and are
+ accepted in Thumb-2 code. If you omit this option, the behavior
+ is equivalent to `-mimplicit-it=arm'.
+
+`-mapcs-26'
+`-mapcs-32'
+ These options specify that the output generated by the assembler
+ should be marked as supporting the indicated version of the Arm
+ Procedure. Calling Standard.
+
+`-matpcs'
+ This option specifies that the output generated by the assembler
+ should be marked as supporting the Arm/Thumb Procedure Calling
+ Standard. If enabled this option will cause the assembler to
+ create an empty debugging section in the object file called
+ .arm.atpcs. Debuggers can use this to determine the ABI being
+ used by.
+
+`-mapcs-float'
+ This indicates the floating point variant of the APCS should be
+ used. In this variant floating point arguments are passed in FP
+ registers rather than integer registers.
+
+`-mapcs-reentrant'
+ This indicates that the reentrant variant of the APCS should be
+ used. This variant supports position independent code.
+
+`-mfloat-abi=ABI'
+ This option specifies that the output generated by the assembler
+ should be marked as using specified floating point ABI. The
+ following values are recognized: `soft', `softfp' and `hard'.
+
+`-meabi=VER'
+ This option specifies which EABI version the produced object files
+ should conform to. The following values are recognized: `gnu', `4'
+ and `5'.
+
+`-EB'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a big-endian processor.
+
+ Note: If a program is being built for a system with big-endian data
+ and little-endian instructions then it should be assembled with the
+ `-EB' option, (all of it, code and data) and then linked with the
+ `--be8' option. This will reverse the endianness of the
+ instructions back to little-endian, but leave the data as
+ big-endian.
+
+`-EL'
+ This option specifies that the output generated by the assembler
+ should be marked as being encoded for a little-endian processor.
+
+`-k'
+ This option specifies that the output of the assembler should be
+ marked as position-independent code (PIC).
+
+`--fix-v4bx'
+ Allow `BX' instructions in ARMv4 code. This is intended for use
+ with the linker option of the same name.
+
+`-mwarn-deprecated'
+`-mno-warn-deprecated'
+ Enable or disable warnings about using deprecated options or
+ features. The default is to warn.
+
+`-mccs'
+ Turns on CodeComposer Studio assembly syntax compatibility mode.
+
+`-mwarn-syms'
+`-mno-warn-syms'
+ Enable or disable warnings about symbols that match the names of
+ ARM instructions. The default is to warn.
+
+
+
+File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent
+
+9.4.2 Syntax
+------------
+
+* Menu:
+
+* ARM-Instruction-Set:: Instruction Set
+* ARM-Chars:: Special Characters
+* ARM-Regs:: Register Names
+* ARM-Relocations:: Relocations
+* ARM-Neon-Alignment:: NEON Alignment Specifiers
+
+
+File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax
+
+9.4.2.1 Instruction Set Syntax
+..............................
+
+Two slightly different syntaxes are support for ARM and THUMB
+instructions. The default, `divided', uses the old style where ARM and
+THUMB instructions had their own, separate syntaxes. The new,
+`unified' syntax, which can be selected via the `.syntax' directive,
+and has the following main features:
+
+ * Immediate operands do not require a `#' prefix.
+
+ * The `IT' instruction may appear, and if it does it is validated
+ against subsequent conditional affixes. In ARM mode it does not
+ generate machine code, in THUMB mode it does.
+
+ * For ARM instructions the conditional affixes always appear at the
+ end of the instruction. For THUMB instructions conditional
+ affixes can be used, but only inside the scope of an `IT'
+ instruction.
+
+ * All of the instructions new to the V6T2 architecture (and later)
+ are available. (Only a few such instructions can be written in the
+ `divided' syntax).
+
+ * The `.N' and `.W' suffixes are recognized and honored.
+
+ * All instructions set the flags if and only if they have an `s'
+ affix.
+
+
+File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax
+
+9.4.2.2 Special Characters
+..........................
+
+The presence of a `@' anywhere on a line indicates the start of a
+comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used instead of a newline to separate
+statements.
+
+ Either `#' or `$' can be used to indicate immediate operands.
+
+ *TODO* Explain about /data modifier on symbols.
+
+
+File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax
+
+9.4.2.3 Register Names
+......................
+
+*TODO* Explain about ARM register naming, and the predefined names.
+
+
+File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax
+
+9.4.2.4 ARM relocation generation
+.................................
+
+Specific data relocations can be generated by putting the relocation
+name in parentheses after the symbol name. For example:
+
+ .word foo(TARGET1)
+
+ This will generate an `R_ARM_TARGET1' relocation against the symbol
+FOO. The following relocations are supported: `GOT', `GOTOFF',
+`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `TLSDESC',
+`TLSCALL', `GOTTPOFF', `GOT_PREL' and `TPOFF'.
+
+ For compatibility with older toolchains the assembler also accepts
+`(PLT)' after branch targets. On legacy targets this will generate the
+deprecated `R_ARM_PLT32' relocation. On EABI targets it will encode
+either the `R_ARM_CALL' or `R_ARM_JUMP24' relocation, as appropriate.
+
+ Relocations for `MOVW' and `MOVT' instructions can be generated by
+prefixing the value with `#:lower16:' and `#:upper16' respectively.
+For example to load the 32-bit address of foo into r0:
+
+ MOVW r0, #:lower16:foo
+ MOVT r0, #:upper16:foo
+
+ Relocations `R_ARM_THM_ALU_ABS_G0_NC', `R_ARM_THM_ALU_ABS_G1_NC',
+`R_ARM_THM_ALU_ABS_G2_NC' and `R_ARM_THM_ALU_ABS_G3_NC' can be
+generated by prefixing the value with `#:lower0_7:#', `#:lower8_15:#',
+`#:upper0_7:#' and `#:upper8_15:#' respectively. For example to load
+the 32-bit address of foo into r0:
+
+ MOVS r0, #:upper8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:upper0_7:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower0_7:#foo
+
+
+File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax
+
+9.4.2.5 NEON Alignment Specifiers
+.................................
+
+Some NEON load/store instructions allow an optional address alignment
+qualifier. The ARM documentation specifies that this is indicated by
+`@ ALIGN'. However GAS already interprets the `@' character as a "line
+comment" start, so `: ALIGN' is used instead. For example:
+
+ vld1.8 {q0}, [r0, :128]
+
+
+File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent
+
+9.4.3 Floating Point
+--------------------
+
+The ARM family uses IEEE floating-point numbers.
+
+
+File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent
+
+9.4.4 ARM Machine Directives
+----------------------------
+
+`.2byte EXPRESSION [, EXPRESSION]*'
+`.4byte EXPRESSION [, EXPRESSION]*'
+`.8byte EXPRESSION [, EXPRESSION]*'
+ These directives write 2, 4 or 8 byte values to the output section.
+
+`.align EXPRESSION [, EXPRESSION]'
+ This is the generic .ALIGN directive. For the ARM however if the
+ first argument is zero (ie no alignment is needed) the assembler
+ will behave as if the argument had been 2 (ie pad to the next four
+ byte boundary). This is for compatibility with ARM's own
+ assembler.
+
+`.arch NAME'
+ Select the target architecture. Valid values for NAME are the
+ same as for the `-march' commandline option.
+
+ Specifying `.arch' clears any previously selected architecture
+ extensions.
+
+`.arch_extension NAME'
+ Add or remove an architecture extension to the target
+ architecture. Valid values for NAME are the same as those
+ accepted as architectural extensions by the `-mcpu' commandline
+ option.
+
+ `.arch_extension' may be used multiple times to add or remove
+ extensions incrementally to the architecture being compiled for.
+
+`.arm'
+ This performs the same action as .CODE 32.
+
+`.bss'
+ This directive switches to the `.bss' section.
+
+`.cantunwind'
+ Prevents unwinding through the current function. No personality
+ routine or exception table data is required or permitted.
+
+`.code `[16|32]''
+ This directive selects the instruction set being generated. The
+ value 16 selects Thumb, with the value 32 selecting ARM.
+
+`.cpu NAME'
+ Select the target processor. Valid values for NAME are the same as
+ for the `-mcpu' commandline option.
+
+ Specifying `.cpu' clears any previously selected architecture
+ extensions.
+
+`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
+`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]'
+ The `dn' and `qn' directives are used to create typed and/or
+ indexed register aliases for use in Advanced SIMD Extension (Neon)
+ instructions. The former should be used to create aliases of
+ double-precision registers, and the latter to create aliases of
+ quad-precision registers.
+
+ If these directives are used to create typed aliases, those
+ aliases can be used in Neon instructions instead of writing types
+ after the mnemonic or after each operand. For example:
+
+ x .dn d2.f32
+ y .dn d3.f32
+ z .dn d4.f32[1]
+ vmul x,y,z
+
+ This is equivalent to writing the following:
+
+ vmul.f32 d2,d3,d4[1]
+
+ Aliases created using `dn' or `qn' can be destroyed using `unreq'.
+
+`.eabi_attribute TAG, VALUE'
+ Set the EABI object attribute TAG to VALUE.
+
+ The TAG is either an attribute number, or one of the following:
+ `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch',
+ `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use',
+ `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch',
+ `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data',
+ `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use',
+ `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding',
+ `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions',
+ `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model',
+ `Tag_ABI_align_needed', `Tag_ABI_align_preserved',
+ `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args',
+ `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals',
+ `Tag_ABI_FP_optimization_goals', `Tag_compatibility',
+ `Tag_CPU_unaligned_access', `Tag_FP_HP_extension',
+ `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use',
+ `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance',
+ `Tag_T2EE_use', `Tag_Virtualization_use'
+
+ The VALUE is either a `number', `"string"', or `number, "string"'
+ depending on the tag.
+
+ Note - the following legacy values are also accepted by TAG:
+ `Tag_VFP_arch', `Tag_ABI_align8_needed',
+ `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension',
+
+`.even'
+ This directive aligns to an even-numbered address.
+
+`.extend EXPRESSION [, EXPRESSION]*'
+`.ldouble EXPRESSION [, EXPRESSION]*'
+ These directives write 12byte long double floating-point values to
+ the output section. These are not compatible with current ARM
+ processors or ABIs.
+
+`.fnend'
+ Marks the end of a function with an unwind table entry. The
+ unwind index table entry is created when this directive is
+ processed.
+
+ If no personality routine has been specified then standard
+ personality routine 0 or 1 will be used, depending on the number
+ of unwind opcodes required.
+
+`.fnstart'
+ Marks the start of a function with an unwind table entry.
+
+`.force_thumb'
+ This directive forces the selection of Thumb instructions, even if
+ the target processor does not support those instructions
+
+`.fpu NAME'
+ Select the floating-point unit to assemble for. Valid values for
+ NAME are the same as for the `-mfpu' commandline option.
+
+`.handlerdata'
+ Marks the end of the current function, and the start of the
+ exception table entry for that function. Anything between this
+ directive and the `.fnend' directive will be added to the
+ exception table entry.
+
+ Must be preceded by a `.personality' or `.personalityindex'
+ directive.
+
+`.inst OPCODE [ , ... ]'
+`.inst.n OPCODE [ , ... ]'
+`.inst.w OPCODE [ , ... ]'
+ Generates the instruction corresponding to the numerical value
+ OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size
+ to be specified explicitly, overriding the normal encoding rules.
+
+`.ldouble EXPRESSION [, EXPRESSION]*'
+ See `.extend'.
+
+`.ltorg'
+ This directive causes the current contents of the literal pool to
+ be dumped into the current section (which is assumed to be the
+ .text section) at the current location (aligned to a word
+ boundary). `GAS' maintains a separate literal pool for each
+ section and each sub-section. The `.ltorg' directive will only
+ affect the literal pool of the current section and sub-section.
+ At the end of assembly all remaining, un-empty literal pools will
+ automatically be dumped.
+
+ Note - older versions of `GAS' would dump the current literal pool
+ any time a section change occurred. This is no longer done, since
+ it prevents accurate control of the placement of literal pools.
+
+`.movsp REG [, #OFFSET]'
+ Tell the unwinder that REG contains an offset from the current
+ stack pointer. If OFFSET is not specified then it is assumed to be
+ zero.
+
+`.object_arch NAME'
+ Override the architecture recorded in the EABI object attribute
+ section. Valid values for NAME are the same as for the `.arch'
+ directive. Typically this is useful when code uses runtime
+ detection of CPU features.
+
+`.packed EXPRESSION [, EXPRESSION]*'
+ This directive writes 12-byte packed floating-point values to the
+ output section. These are not compatible with current ARM
+ processors or ABIs.
+
+`.pad #COUNT'
+ Generate unwinder annotations for a stack adjustment of COUNT
+ bytes. A positive value indicates the function prologue allocated
+ stack space by decrementing the stack pointer.
+
+`.personality NAME'
+ Sets the personality routine for the current function to NAME.
+
+`.personalityindex INDEX'
+ Sets the personality routine for the current function to the EABI
+ standard routine number INDEX
+
+`.pool'
+ This is a synonym for .ltorg.
+
+`NAME .req REGISTER NAME'
+ This creates an alias for REGISTER NAME called NAME. For example:
+
+ foo .req r0
+
+`.save REGLIST'
+ Generate unwinder annotations to restore the registers in REGLIST.
+ The format of REGLIST is the same as the corresponding
+ store-multiple instruction.
+
+ _core registers_
+ .save {r4, r5, r6, lr}
+ stmfd sp!, {r4, r5, r6, lr}
+ _FPA registers_
+ .save f4, 2
+ sfmfd f4, 2, [sp]!
+ _VFP registers_
+ .save {d8, d9, d10}
+ fstmdx sp!, {d8, d9, d10}
+ _iWMMXt registers_
+ .save {wr10, wr11}
+ wstrd wr11, [sp, #-8]!
+ wstrd wr10, [sp, #-8]!
+ or
+ .save wr11
+ wstrd wr11, [sp, #-8]!
+ .save wr10
+ wstrd wr10, [sp, #-8]!
+
+`.setfp FPREG, SPREG [, #OFFSET]'
+ Make all unwinder annotations relative to a frame pointer.
+ Without this the unwinder will use offsets from the stack pointer.
+
+ The syntax of this directive is the same as the `add' or `mov'
+ instruction used to set the frame pointer. SPREG must be either
+ `sp' or mentioned in a previous `.movsp' directive.
+
+ .movsp ip
+ mov ip, sp
+ ...
+ .setfp fp, ip, #4
+ add fp, ip, #4
+
+`.secrel32 EXPRESSION [, EXPRESSION]*'
+ This directive emits relocations that evaluate to the
+ section-relative offset of each expression's symbol. This
+ directive is only supported for PE targets.
+
+`.syntax [`unified' | `divided']'
+ This directive sets the Instruction Set Syntax as described in the
+ *Note ARM-Instruction-Set:: section.
+
+`.thumb'
+ This performs the same action as .CODE 16.
+
+`.thumb_func'
+ This directive specifies that the following symbol is the name of a
+ Thumb encoded function. This information is necessary in order to
+ allow the assembler and linker to generate correct code for
+ interworking between Arm and Thumb instructions and should be used
+ even if interworking is not going to be performed. The presence
+ of this directive also implies `.thumb'
+
+ This directive is not neccessary when generating EABI objects. On
+ these targets the encoding is implicit when generating Thumb code.
+
+`.thumb_set'
+ This performs the equivalent of a `.set' directive in that it
+ creates a symbol which is an alias for another symbol (possibly
+ not yet defined). This directive also has the added property in
+ that it marks the aliased symbol as being a thumb function entry
+ point, in the same way that the `.thumb_func' directive does.
+
+`.tlsdescseq TLS-VARIABLE'
+ This directive is used to annotate parts of an inlined TLS
+ descriptor trampoline. Normally the trampoline is provided by the
+ linker, and this directive is not needed.
+
+`.unreq ALIAS-NAME'
+ This undefines a register alias which was previously defined using
+ the `req', `dn' or `qn' directives. For example:
+
+ foo .req r0
+ .unreq foo
+
+ An error occurs if the name is undefined. Note - this pseudo op
+ can be used to delete builtin in register name aliases (eg 'r0').
+ This should only be done if it is really necessary.
+
+`.unwind_raw OFFSET, BYTE1, ...'
+ Insert one of more arbitary unwind opcode bytes, which are known
+ to adjust the stack pointer by OFFSET bytes.
+
+ For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
+ {r0}'
+
+`.vsave VFP-REGLIST'
+ Generate unwinder annotations to restore the VFP registers in
+ VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are
+ to be restored using VLDM. The format of VFP-REGLIST is the same
+ as the corresponding store-multiple instruction.
+
+ _VFP registers_
+ .vsave {d8, d9, d10}
+ fstmdd sp!, {d8, d9, d10}
+ _VFPv3 registers_
+ .vsave {d15, d16, d17}
+ vstm sp!, {d15, d16, d17}
+
+ Since FLDMX and FSTMX are now deprecated, this directive should be
+ used in favour of `.save' for saving VFP registers for ARMv6 and
+ above.
+
+
+
+File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent
+
+9.4.5 Opcodes
+-------------
+
+`as' implements all the standard ARM opcodes. It also implements
+several pseudo opcodes, including several synthetic load instructions.
+
+`NOP'
+ nop
+
+ This pseudo op will always evaluate to a legal ARM instruction
+ that does nothing. Currently it will evaluate to MOV r0, r0.
+
+`LDR'
+ ldr <register> , = <expression>
+
+ If expression evaluates to a numeric constant then a MOV or MVN
+ instruction will be used in place of the LDR instruction, if the
+ constant can be generated by either of these instructions.
+ Otherwise the constant will be placed into the nearest literal
+ pool (if it not already there) and a PC relative LDR instruction
+ will be generated.
+
+`ADR'
+ adr <register> <label>
+
+ This instruction will load the address of LABEL into the indicated
+ register. The instruction will evaluate to a PC relative ADD or
+ SUB instruction depending upon where the label is located. If the
+ label is out of range, or if it is not defined in the same file
+ (and section) as the ADR instruction, then an error will be
+ generated. This instruction will not make use of the literal pool.
+
+`ADRL'
+ adrl <register> <label>
+
+ This instruction will load the address of LABEL into the indicated
+ register. The instruction will evaluate to one or two PC relative
+ ADD or SUB instructions depending upon where the label is located.
+ If a second instruction is not needed a NOP instruction will be
+ generated in its place, so that this instruction is always 8 bytes
+ long.
+
+ If the label is out of range, or if it is not defined in the same
+ file (and section) as the ADRL instruction, then an error will be
+ generated. This instruction will not make use of the literal pool.
+
+
+ For information on the ARM or Thumb instruction sets, see `ARM
+Software Development Toolkit Reference Manual', Advanced RISC Machines
+Ltd.
+
+
+File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent
+
+9.4.6 Mapping Symbols
+---------------------
+
+The ARM ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+`$a'
+ At the start of a region of code containing ARM instructions.
+
+`$t'
+ At the start of a region of code containing THUMB instructions.
+
+`$d'
+ At the start of a region of data.
+
+
+ The assembler will automatically insert these symbols for you - there
+is no need to code them yourself. Support for tagging symbols ($b, $f,
+$p and $m) which is also mentioned in the current ARM ELF specification
+is not implemented. This is because they have been dropped from the
+new EABI and so tools cannot rely upon their presence.
+
+
+File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent
+
+9.4.7 Unwinding
+---------------
+
+The ABI for the ARM Architecture specifies a standard format for
+exception unwind information. This information is used when an
+exception is thrown to determine where control should be transferred.
+In particular, the unwind information is used to determine which
+function called the function that threw the exception, and which
+function called that one, and so forth. This information is also used
+to restore the values of callee-saved registers in the function
+catching the exception.
+
+ If you are writing functions in assembly code, and those functions
+call other functions that throw exceptions, you must use assembly
+pseudo ops to ensure that appropriate exception unwind information is
+generated. Otherwise, if one of the functions called by your assembly
+code throws an exception, the run-time library will be unable to unwind
+the stack through your assembly code and your program will not behave
+correctly.
+
+ To illustrate the use of these pseudo ops, we will examine the code
+that G++ generates for the following C++ input:
+
+
+void callee (int *);
+
+int
+caller ()
+{
+ int i;
+ callee (&i);
+ return i;
+}
+
+ This example does not show how to throw or catch an exception from
+assembly code. That is a much more complex operation and should always
+be done in a high-level language, such as C++, that directly supports
+exceptions.
+
+ The code generated by one particular version of G++ when compiling
+the example above is:
+
+
+_Z6callerv:
+ .fnstart
+.LFB2:
+ @ Function supports interworking.
+ @ args = 0, pretend = 0, frame = 8
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {fp, lr}
+ .save {fp, lr}
+.LCFI0:
+ .setfp fp, sp, #4
+ add fp, sp, #4
+.LCFI1:
+ .pad #8
+ sub sp, sp, #8
+.LCFI2:
+ sub r3, fp, #8
+ mov r0, r3
+ bl _Z6calleePi
+ ldr r3, [fp, #-8]
+ mov r0, r3
+ sub sp, fp, #4
+ ldmfd sp!, {fp, lr}
+ bx lr
+.LFE2:
+ .fnend
+
+ Of course, the sequence of instructions varies based on the options
+you pass to GCC and on the version of GCC in use. The exact
+instructions are not important since we are focusing on the pseudo ops
+that are used to generate unwind information.
+
+ An important assumption made by the unwinder is that the stack frame
+does not change during the body of the function. In particular, since
+we assume that the assembly code does not itself throw an exception,
+the only point where an exception can be thrown is from a call, such as
+the `bl' instruction above. At each call site, the same saved
+registers (including `lr', which indicates the return address) must be
+located in the same locations relative to the frame pointer.
+
+ The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op
+appears immediately before the first instruction of the function while
+the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears
+immediately after the last instruction of the function. These pseudo
+ops specify the range of the function.
+
+ Only the order of the other pseudos ops (e.g., `.setfp' or `.pad')
+matters; their exact locations are irrelevant. In the example above,
+the compiler emits the pseudo ops with particular instructions. That
+makes it easier to understand the code, but it is not required for
+correctness. It would work just as well to emit all of the pseudo ops
+other than `.fnend' in the same order, but immediately after `.fnstart'.
+
+ The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates
+registers that have been saved to the stack so that they can be
+restored before the function returns. The argument to the `.save'
+pseudo op is a list of registers to save. If a register is
+"callee-saved" (as specified by the ABI) and is modified by the
+function you are writing, then your code must save the value before it
+is modified and restore the original value before the function returns.
+If an exception is thrown, the run-time library restores the values of
+these registers from their locations on the stack before returning
+control to the exception handler. (Of course, if an exception is not
+thrown, the function that contains the `.save' pseudo op restores these
+registers in the function epilogue, as is done with the `ldmfd'
+instruction above.)
+
+ You do not have to save callee-saved registers at the very beginning
+of the function and you do not need to use the `.save' pseudo op
+immediately following the point at which the registers are saved.
+However, if you modify a callee-saved register, you must save it on the
+stack before modifying it and before calling any functions which might
+throw an exception. And, you must use the `.save' pseudo op to
+indicate that you have done so.
+
+ The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification
+of the stack pointer that does not save any registers. The argument is
+the number of bytes (in decimal) that are subtracted from the stack
+pointer. (On ARM CPUs, the stack grows downwards, so subtracting from
+the stack pointer increases the size of the stack.)
+
+ The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op
+indicates the register that contains the frame pointer. The first
+argument is the register that is set, which is typically `fp'. The
+second argument indicates the register from which the frame pointer
+takes its value. The third argument, if present, is the value (in
+decimal) added to the register specified by the second argument to
+compute the value of the frame pointer. You should not modify the
+frame pointer in the body of the function.
+
+ If you do not use a frame pointer, then you should not use the
+`.setfp' pseudo op. If you do not use a frame pointer, then you should
+avoid modifying the stack pointer outside of the function prologue.
+Otherwise, the run-time library will be unable to find saved registers
+when it is unwinding the stack.
+
+ The pseudo ops described above are sufficient for writing assembly
+code that calls functions which may throw exceptions. If you need to
+know more about the object-file format used to represent unwind
+information, you may consult the `Exception Handling ABI for the ARM
+Architecture' available from `http://infocenter.arm.com'.
+
+
+File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies
+
+9.5 AVR Dependent Features
+==========================
+
+* Menu:
+
+* AVR Options:: Options
+* AVR Syntax:: Syntax
+* AVR Opcodes:: Opcodes
+
+
+File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent
+
+9.5.1 Options
+-------------
+
+`-mmcu=MCU'
+ Specify ATMEL AVR instruction set or MCU type.
+
+ Instruction set avr1 is for the minimal AVR core, not supported by
+ the C compiler, only for assembler programs (MCU types: at90s1200,
+ attiny11, attiny12, attiny15, attiny28).
+
+ Instruction set avr2 (default) is for the classic AVR core with up
+ to 8K program memory space (MCU types: at90s2313, at90s2323,
+ at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433,
+ at90s4434, at90s8515, at90c8534, at90s8535).
+
+ Instruction set avr25 is for the classic AVR core with up to 8K
+ program memory space plus the MOVW instruction (MCU types:
+ attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a,
+ attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25,
+ attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a,
+ attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88,
+ attiny828, at86rf401, ata6289, ata5272).
+
+ Instruction set avr3 is for the classic AVR core with up to 128K
+ program memory space (MCU types: at43usb355, at76c711).
+
+ Instruction set avr31 is for the classic AVR core with exactly
+ 128K program memory space (MCU types: atmega103, at43usb320).
+
+ Instruction set avr35 is for classic AVR core plus MOVW, CALL, and
+ JMP instructions (MCU types: attiny167, attiny1634, at90usb82,
+ at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505).
+
+ Instruction set avr4 is for the enhanced AVR core with up to 8K
+ program memory space (MCU types: atmega48, atmega48a, atmega48pa,
+ atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p,
+ atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1,
+ at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285,
+ ata6286).
+
+ Instruction set avr5 is for the enhanced AVR core with up to 128K
+ program memory space (MCU types: at90pwm161, atmega16, atmega16a,
+ atmega161, atmega162, atmega163, atmega164a, atmega164p,
+ atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa,
+ atmega168, atmega168a, atmega168p, atmega168pa, atmega169,
+ atmega169a, atmega169p, atmega169pa, atmega32, atmega323,
+ atmega324a, atmega324p, atmega324pa, atmega325, atmega325a,
+ atmega32, atmega32a, atmega323, atmega324a, atmega324p,
+ atmega324pa, atmega325, atmega325a, atmega325p, atmega325p,
+ atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa,
+ atmega328, atmega328p, atmega329, atmega329a, atmega329p,
+ atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406,
+ atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640,
+ atmega644, atmega644a, atmega644p, atmega644pa, atmega645,
+ atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p,
+ atmega649, atmega649a, atmega649p, atmega6490, atmega6490a,
+ atmega6490p, atmega16hva, atmega16hva2, atmega16hvb,
+ atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve,
+ at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316,
+ atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1,
+ atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k,
+ at90scr100, ata5790, ata5795).
+
+ Instruction set avr51 is for the enhanced AVR core with exactly
+ 128K program memory space (MCU types: atmega128, atmega128a,
+ atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1,
+ atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
+ at90usb1287, m3000).
+
+ Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
+ (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
+
+ Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K
+ program memory space and less than 64K data space (MCU types:
+ atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1,
+ atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5,
+ atxmega8e5, atxmega32e5, atxmega32x1).
+
+ Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K
+ program memory space and greater than 64K data space (MCU types:
+ none).
+
+ Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K
+ program memory space and less than 64K data space (MCU types:
+ atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3,
+ atxmega64c3, atxmega64d3, atxmega64d4).
+
+ Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K
+ program memory space and greater than 64K data space (MCU types:
+ atxmega64a1, atxmega64a1u).
+
+ Instruction set avrxmega6 is for the XMEGA AVR core with larger
+ than 64K program memory space and less than 64K data space (MCU
+ types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3,
+ atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1,
+ atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3,
+ atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3,
+ atxmega256d3, atxmega384c3, atxmega256d3).
+
+ Instruction set avrxmega7 is for the XMEGA AVR core with larger
+ than 64K program memory space and greater than 64K data space (MCU
+ types: atxmega128a1, atxmega128a1u, atxmega128a4u).
+
+ Instruction set avrtiny is for the ATtiny4/5/9/10/20/40
+ microcontrollers.
+
+`-mall-opcodes'
+ Accept all AVR opcodes, even if not supported by `-mmcu'.
+
+`-mno-skip-bug'
+ This option disable warnings for skipping two-word instructions.
+
+`-mno-wrap'
+ This option reject `rjmp/rcall' instructions with 8K wrap-around.
+
+`-mrmw'
+ Accept Read-Modify-Write (`XCH,LAC,LAS,LAT') instructions.
+
+`-mlink-relax'
+ Enable support for link-time relaxation. This is now on by default
+ and this flag no longer has any effect.
+
+`-mno-link-relax'
+ Disable support for link-time relaxation. The assembler will
+ resolve relocations when it can, and may be able to better
+ compress some debug information.
+
+
+
+File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent
+
+9.5.2 Syntax
+------------
+
+* Menu:
+
+* AVR-Chars:: Special Characters
+* AVR-Regs:: Register Names
+* AVR-Modifiers:: Relocatable Expression Modifiers
+
+
+File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax
+
+9.5.2.1 Special Characters
+..........................
+
+The presence of a `;' anywhere on a line indicates the start of a
+comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The `$' character can be used instead of a newline to separate
+statements.
+
+
+File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax
+
+9.5.2.2 Register Names
+......................
+
+The AVR has 32 x 8-bit general purpose working registers `r0', `r1',
+... `r31'. Six of the 32 registers can be used as three 16-bit
+indirect address register pointers for Data Space addressing. One of
+the these address pointers can also be used as an address pointer for
+look up tables in Flash program memory. These added function registers
+are the 16-bit `X', `Y' and `Z' - registers.
+
+ X = r26:r27
+ Y = r28:r29
+ Z = r30:r31
+
+
+File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax
+
+9.5.2.3 Relocatable Expression Modifiers
+........................................
+
+The assembler supports several modifiers when using relocatable
+addresses in AVR instruction operands. The general syntax is the
+following:
+
+ modifier(relocatable-expression)
+
+`lo8'
+ This modifier allows you to use bits 0 through 7 of an address
+ expression as 8 bit relocatable expression.
+
+`hi8'
+ This modifier allows you to use bits 7 through 15 of an address
+ expression as 8 bit relocatable expression. This is useful with,
+ for example, the AVR `ldi' instruction and `lo8' modifier.
+
+ For example
+
+ ldi r26, lo8(sym+10)
+ ldi r27, hi8(sym+10)
+
+`hh8'
+ This modifier allows you to use bits 16 through 23 of an address
+ expression as 8 bit relocatable expression. Also, can be useful
+ for loading 32 bit constants.
+
+`hlo8'
+ Synonym of `hh8'.
+
+`hhi8'
+ This modifier allows you to use bits 24 through 31 of an
+ expression as 8 bit expression. This is useful with, for example,
+ the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8',
+ modifier.
+
+ For example
+
+ ldi r26, lo8(285774925)
+ ldi r27, hi8(285774925)
+ ldi r28, hlo8(285774925)
+ ldi r29, hhi8(285774925)
+ ; r29,r28,r27,r26 = 285774925
+
+`pm_lo8'
+ This modifier allows you to use bits 0 through 7 of an address
+ expression as 8 bit relocatable expression. This modifier useful
+ for addressing data or code from Flash/Program memory. The using
+ of `pm_lo8' similar to `lo8'.
+
+`pm_hi8'
+ This modifier allows you to use bits 8 through 15 of an address
+ expression as 8 bit relocatable expression. This modifier useful
+ for addressing data or code from Flash/Program memory.
+
+`pm_hh8'
+ This modifier allows you to use bits 15 through 23 of an address
+ expression as 8 bit relocatable expression. This modifier useful
+ for addressing data or code from Flash/Program memory.
+
+
+
+File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent
+
+9.5.3 Opcodes
+-------------
+
+For detailed information on the AVR machine instruction set, see
+`www.atmel.com/products/AVR'.
+
+ `as' implements all the standard AVR opcodes. The following table
+summarizes the AVR opcodes, and their arguments.
+
+ Legend:
+ r any register
+ d `ldi' register (r16-r31)
+ v `movw' even register (r0, r2, ..., r28, r30)
+ a `fmul' register (r16-r23)
+ w `adiw' register (r24,r26,r28,r30)
+ e pointer registers (X,Y,Z)
+ b base pointer register and displacement ([YZ]+disp)
+ z Z pointer register (for [e]lpm Rd,Z[+])
+ M immediate value from 0 to 255
+ n immediate value from 0 to 255 ( n = ~M ). Relocation impossible
+ s immediate value from 0 to 7
+ P Port address value from 0 to 63. (in, out)
+ p Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
+ K immediate value from 0 to 63 (used in `adiw', `sbiw')
+ i immediate value
+ l signed pc relative offset from -64 to 63
+ L signed pc relative offset from -2048 to 2047
+ h absolute code address (call, jmp)
+ S immediate value from 0 to 7 (S = s << 4)
+ ? use this opcode entry if no parameters, else use next opcode entry
+
+ 1001010010001000 clc
+ 1001010011011000 clh
+ 1001010011111000 cli
+ 1001010010101000 cln
+ 1001010011001000 cls
+ 1001010011101000 clt
+ 1001010010111000 clv
+ 1001010010011000 clz
+ 1001010000001000 sec
+ 1001010001011000 seh
+ 1001010001111000 sei
+ 1001010000101000 sen
+ 1001010001001000 ses
+ 1001010001101000 set
+ 1001010000111000 sev
+ 1001010000011000 sez
+ 100101001SSS1000 bclr S
+ 100101000SSS1000 bset S
+ 1001010100001001 icall
+ 1001010000001001 ijmp
+ 1001010111001000 lpm ?
+ 1001000ddddd010+ lpm r,z
+ 1001010111011000 elpm ?
+ 1001000ddddd011+ elpm r,z
+ 0000000000000000 nop
+ 1001010100001000 ret
+ 1001010100011000 reti
+ 1001010110001000 sleep
+ 1001010110011000 break
+ 1001010110101000 wdr
+ 1001010111101000 spm
+ 000111rdddddrrrr adc r,r
+ 000011rdddddrrrr add r,r
+ 001000rdddddrrrr and r,r
+ 000101rdddddrrrr cp r,r
+ 000001rdddddrrrr cpc r,r
+ 000100rdddddrrrr cpse r,r
+ 001001rdddddrrrr eor r,r
+ 001011rdddddrrrr mov r,r
+ 100111rdddddrrrr mul r,r
+ 001010rdddddrrrr or r,r
+ 000010rdddddrrrr sbc r,r
+ 000110rdddddrrrr sub r,r
+ 001001rdddddrrrr clr r
+ 000011rdddddrrrr lsl r
+ 000111rdddddrrrr rol r
+ 001000rdddddrrrr tst r
+ 0111KKKKddddKKKK andi d,M
+ 0111KKKKddddKKKK cbr d,n
+ 1110KKKKddddKKKK ldi d,M
+ 11101111dddd1111 ser d
+ 0110KKKKddddKKKK ori d,M
+ 0110KKKKddddKKKK sbr d,M
+ 0011KKKKddddKKKK cpi d,M
+ 0100KKKKddddKKKK sbci d,M
+ 0101KKKKddddKKKK subi d,M
+ 1111110rrrrr0sss sbrc r,s
+ 1111111rrrrr0sss sbrs r,s
+ 1111100ddddd0sss bld r,s
+ 1111101ddddd0sss bst r,s
+ 10110PPdddddPPPP in r,P
+ 10111PPrrrrrPPPP out P,r
+ 10010110KKddKKKK adiw w,K
+ 10010111KKddKKKK sbiw w,K
+ 10011000pppppsss cbi p,s
+ 10011010pppppsss sbi p,s
+ 10011001pppppsss sbic p,s
+ 10011011pppppsss sbis p,s
+ 111101lllllll000 brcc l
+ 111100lllllll000 brcs l
+ 111100lllllll001 breq l
+ 111101lllllll100 brge l
+ 111101lllllll101 brhc l
+ 111100lllllll101 brhs l
+ 111101lllllll111 brid l
+ 111100lllllll111 brie l
+ 111100lllllll000 brlo l
+ 111100lllllll100 brlt l
+ 111100lllllll010 brmi l
+ 111101lllllll001 brne l
+ 111101lllllll010 brpl l
+ 111101lllllll000 brsh l
+ 111101lllllll110 brtc l
+ 111100lllllll110 brts l
+ 111101lllllll011 brvc l
+ 111100lllllll011 brvs l
+ 111101lllllllsss brbc s,l
+ 111100lllllllsss brbs s,l
+ 1101LLLLLLLLLLLL rcall L
+ 1100LLLLLLLLLLLL rjmp L
+ 1001010hhhhh111h call h
+ 1001010hhhhh110h jmp h
+ 1001010rrrrr0101 asr r
+ 1001010rrrrr0000 com r
+ 1001010rrrrr1010 dec r
+ 1001010rrrrr0011 inc r
+ 1001010rrrrr0110 lsr r
+ 1001010rrrrr0001 neg r
+ 1001000rrrrr1111 pop r
+ 1001001rrrrr1111 push r
+ 1001010rrrrr0111 ror r
+ 1001010rrrrr0010 swap r
+ 00000001ddddrrrr movw v,v
+ 00000010ddddrrrr muls d,d
+ 000000110ddd0rrr mulsu a,a
+ 000000110ddd1rrr fmul a,a
+ 000000111ddd0rrr fmuls a,a
+ 000000111ddd1rrr fmulsu a,a
+ 1001001ddddd0000 sts i,r
+ 1001000ddddd0000 lds r,i
+ 10o0oo0dddddbooo ldd r,b
+ 100!000dddddee-+ ld r,e
+ 10o0oo1rrrrrbooo std b,r
+ 100!001rrrrree-+ st e,r
+ 1001010100011001 eicall
+ 1001010000011001 eijmp
+
+
+File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies
+
+9.6 Blackfin Dependent Features
+===============================
+
+* Menu:
+
+* Blackfin Options:: Blackfin Options
+* Blackfin Syntax:: Blackfin Syntax
+* Blackfin Directives:: Blackfin Directives
+
+
+File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent
+
+9.6.1 Options
+-------------
+
+`-mcpu=PROCESSOR[-SIREVISION]'
+ This option specifies the target processor. The optional
+ SIREVISION is not used in assembler. It's here such that GCC can
+ easily pass down its `-mcpu=' option. The assembler will issue an
+ error message if an attempt is made to assemble an instruction
+ which will not execute on the target processor. The following
+ processor names are recognized: `bf504', `bf506', `bf512', `bf514',
+ `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526',
+ `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not
+ implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542',
+ `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m',
+ `bf549', `bf549m', `bf561', and `bf592'.
+
+`-mfdpic'
+ Assemble for the FDPIC ABI.
+
+`-mno-fdpic'
+`-mnopic'
+ Disable -mfdpic.
+
+
+File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent
+
+9.6.2 Syntax
+------------
+
+`Special Characters'
+ Assembler input is free format and may appear anywhere on the line.
+ One instruction may extend across multiple lines or more than one
+ instruction may appear on the same line. White space (space, tab,
+ comments or newline) may appear anywhere between tokens. A token
+ must not have embedded spaces. Tokens include numbers, register
+ names, keywords, user identifiers, and also some multicharacter
+ special symbols like "+=", "/*" or "||".
+
+ Comments are introduced by the `#' character and extend to the end
+ of the current line. If the `#' appears as the first character of
+ a line, the whole line is treated as a comment, but in this case
+ the line can also be a logical line number directive (*note
+ Comments::) or a preprocessor control command (*note
+ Preprocessing::).
+
+`Instruction Delimiting'
+ A semicolon must terminate every instruction. Sometimes a complete
+ instruction will consist of more than one operation. There are two
+ cases where this occurs. The first is when two general operations
+ are combined. Normally a comma separates the different parts, as
+ in
+
+ a0= r3.h * r2.l, a1 = r3.l * r2.h ;
+
+ The second case occurs when a general instruction is combined with
+ one or two memory references for joint issue. The latter portions
+ are set off by a "||" token.
+
+ a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
+
+ Multiple instructions can occur on the same line. Each must be
+ terminated by a semicolon character.
+
+`Register Names'
+ The assembler treats register names and instruction keywords in a
+ case insensitive manner. User identifiers are case sensitive.
+ Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
+ assembler.
+
+ Register names are reserved and may not be used as program
+ identifiers.
+
+ Some operations (such as "Move Register") require a register pair.
+ Register pairs are always data registers and are denoted using a
+ colon, eg., R3:2. The larger number must be written firsts. Note
+ that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
+ R3:2, and R1:0.
+
+ Some instructions (such as -SP (Push Multiple)) require a group of
+ adjacent registers. Adjacent registers are denoted in the syntax
+ by the range enclosed in parentheses and separated by a colon,
+ eg., (R7:3). Again, the larger number appears first.
+
+ Portions of a particular register may be individually specified.
+ This is written with a dot (".") following the register name and
+ then a letter denoting the desired portion. For 32-bit registers,
+ ".H" denotes the most significant ("High") portion. ".L" denotes
+ the least-significant portion. The subdivisions of the 40-bit
+ registers are described later.
+
+`Accumulators'
+ The set of 40-bit registers A1 and A0 that normally contain data
+ that is being manipulated. Each accumulator can be accessed in
+ four ways.
+
+ `one 40-bit register'
+ The register will be referred to as A1 or A0.
+
+ `one 32-bit register'
+ The registers are designated as A1.W or A0.W.
+
+ `two 16-bit registers'
+ The registers are designated as A1.H, A1.L, A0.H or A0.L.
+
+ `one 8-bit register'
+ The registers are designated as A1.X or A0.X for the bits that
+ extend beyond bit 31.
+
+`Data Registers'
+ The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
+ that normally contain data for manipulation. These are
+ abbreviated as D-register or Dreg. Data registers can be accessed
+ as 32-bit registers or as two independent 16-bit registers. The
+ least significant 16 bits of each register is called the "low"
+ half and is designated with ".L" following the register name. The
+ most significant 16 bits are called the "high" half and is
+ designated with ".H" following the name.
+
+ R7.L, r2.h, r4.L, R0.H
+
+`Pointer Registers'
+ The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
+ that normally contain byte addresses of data structures. These are
+ abbreviated as P-register or Preg.
+
+ p2, p5, fp, sp
+
+`Stack Pointer SP'
+ The stack pointer contains the 32-bit address of the last occupied
+ byte location in the stack. The stack grows by decrementing the
+ stack pointer.
+
+`Frame Pointer FP'
+ The frame pointer contains the 32-bit address of the previous frame
+ pointer in the stack. It is located at the top of a frame.
+
+`Loop Top'
+ LT0 and LT1. These registers contain the 32-bit address of the
+ top of a zero overhead loop.
+
+`Loop Count'
+ LC0 and LC1. These registers contain the 32-bit counter of the
+ zero overhead loop executions.
+
+`Loop Bottom'
+ LB0 and LB1. These registers contain the 32-bit address of the
+ bottom of a zero overhead loop.
+
+`Index Registers'
+ The set of 32-bit registers (I0, I1, I2, I3) that normally contain
+ byte addresses of data structures. Abbreviated I-register or Ireg.
+
+`Modify Registers'
+ The set of 32-bit registers (M0, M1, M2, M3) that normally contain
+ offset values that are added and subtracted to one of the index
+ registers. Abbreviated as Mreg.
+
+`Length Registers'
+ The set of 32-bit registers (L0, L1, L2, L3) that normally contain
+ the length in bytes of the circular buffer. Abbreviated as Lreg.
+ Clear the Lreg to disable circular addressing for the
+ corresponding Ireg.
+
+`Base Registers'
+ The set of 32-bit registers (B0, B1, B2, B3) that normally contain
+ the base address in bytes of the circular buffer. Abbreviated as
+ Breg.
+
+`Floating Point'
+ The Blackfin family has no hardware floating point but the .float
+ directive generates ieee floating point numbers for use with
+ software floating point libraries.
+
+`Blackfin Opcodes'
+ For detailed information on the Blackfin machine instruction set,
+ see the Blackfin(r) Processor Instruction Set Reference.
+
+
+
+File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent
+
+9.6.3 Directives
+----------------
+
+The following directives are provided for compatibility with the VDSP
+assembler.
+
+`.byte2'
+ Initializes a two byte data object.
+
+ This maps to the `.short' directive.
+
+`.byte4'
+ Initializes a four byte data object.
+
+ This maps to the `.int' directive.
+
+`.db'
+ Initializes a single byte data object.
+
+ This directive is a synonym for `.byte'.
+
+`.dw'
+ Initializes a two byte data object.
+
+ This directive is a synonym for `.byte2'.
+
+`.dd'
+ Initializes a four byte data object.
+
+ This directive is a synonym for `.byte4'.
+
+`.var'
+ Define and initialize a 32 bit data object.
+
+
+File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies
+
+9.7 CR16 Dependent Features
+===========================
+
+* Menu:
+
+* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
+* CR16 Syntax:: Syntax for the CR16
+
+
+File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent
+
+9.7.1 CR16 Operand Qualifiers
+-----------------------------
+
+The National Semiconductor CR16 target of `as' has a few machine
+dependent operand qualifiers.
+
+ Operand expression type qualifier is an optional field in the
+instruction operand, to determines the type of the expression field of
+an operand. The `@' is required. CR16 architecture uses one of the
+following expression qualifiers:
+
+`s'
+ - `Specifies expression operand type as small'
+
+`m'
+ - `Specifies expression operand type as medium'
+
+`l'
+ - `Specifies expression operand type as large'
+
+`c'
+ - `Specifies the CR16 Assembler generates a relocation entry for
+ the operand, where pc has implied bit, the expression is adjusted
+ accordingly. The linker uses the relocation entry to update the
+ operand address at link time.'
+
+`got/GOT'
+ - `Specifies the CR16 Assembler generates a relocation entry for
+ the operand, offset from Global Offset Table. The linker uses this
+ relocation entry to update the operand address at link time'
+
+`cgot/cGOT'
+ - `Specifies the CompactRISC Assembler generates a relocation
+ entry for the operand, where pc has implied bit, the expression is
+ adjusted accordingly. The linker uses the relocation entry to
+ update the operand address at link time.'
+
+ CR16 target operand qualifiers and its size (in bits):
+
+`Immediate Operand: s'
+ 4 bits.
+
+`Immediate Operand: m'
+ 16 bits, for movb and movw instructions.
+
+`Immediate Operand: m'
+ 20 bits, movd instructions.
+
+`Immediate Operand: l'
+ 32 bits.
+
+`Absolute Operand: s'
+ Illegal specifier for this operand.
+
+`Absolute Operand: m'
+ 20 bits, movd instructions.
+
+`Displacement Operand: s'
+ 8 bits.
+
+`Displacement Operand: m'
+ 16 bits.
+
+`Displacement Operand: l'
+ 24 bits.
+
+
+ For example:
+ 1 `movw $_myfun@c,r1'
+
+ This loads the address of _myfun, shifted right by 1, into r1.
+
+ 2 `movd $_myfun@c,(r2,r1)'
+
+ This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
+
+ 3 `_myfun_ptr:'
+ `.long _myfun@c'
+ `loadd _myfun_ptr, (r1,r0)'
+ `jal (r1,r0)'
+
+ This .long directive, the address of _myfunc, shifted right by 1 at link time.
+
+ 4 `loadd _data1@GOT(r12), (r1,r0)'
+
+ This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
+
+ 5 `loadd _myfunc@cGOT(r12), (r1,r0)'
+
+ This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
+
+
+File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent
+
+9.7.2 CR16 Syntax
+-----------------
+
+* Menu:
+
+* CR16-Chars:: Special Characters
+
+
+File: as.info, Node: CR16-Chars, Up: CR16 Syntax
+
+9.7.2.1 Special Characters
+..........................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line. If the `#' appears as the
+first character of a line, the whole line is treated as a comment, but
+in this case the line can also be a logical line number directive
+(*note Comments::) or a preprocessor control command (*note
+Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies
+
+9.8 CRIS Dependent Features
+===========================
+
+* Menu:
+
+* CRIS-Opts:: Command-line Options
+* CRIS-Expand:: Instruction expansion
+* CRIS-Symbols:: Symbols
+* CRIS-Syntax:: Syntax
+
+
+File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent
+
+9.8.1 Command-line Options
+--------------------------
+
+The CRIS version of `as' has these machine-dependent command-line
+options.
+
+ The format of the generated object files can be either ELF or a.out,
+specified by the command-line options `--emulation=crisaout' and
+`--emulation=criself'. The default is ELF (criself), unless `as' has
+been configured specifically for a.out by using the configuration name
+`cris-axis-aout'.
+
+ There are two different link-incompatible ELF object file variants
+for CRIS, for use in environments where symbols are expected to be
+prefixed by a leading `_' character and for environments without such a
+symbol prefix. The variant used for GNU/Linux port has no symbol
+prefix. Which variant to produce is specified by either of the options
+`--underscore' and `--no-underscore'. The default is `--underscore'.
+Since symbols in CRIS a.out objects are expected to have a `_' prefix,
+specifying `--no-underscore' when generating a.out objects is an error.
+Besides the object format difference, the effect of this option is to
+parse register names differently (*note crisnous::). The
+`--no-underscore' option makes a `$' register prefix mandatory.
+
+ The option `--pic' must be passed to `as' in order to recognize the
+symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
+crispic::). This will also affect expansion of instructions. The
+expansion with `--pic' will use PC-relative rather than (slightly
+faster) absolute addresses in those expansions. This option is only
+valid when generating ELF format object files.
+
+ The option `--march=ARCHITECTURE' specifies the recognized
+instruction set and recognized register names. It also controls the
+architecture type of the object file. Valid values for ARCHITECTURE
+are:
+`v0_v10'
+ All instructions and register names for any architecture variant
+ in the set v0...v10 are recognized. This is the default if the
+ target is configured as cris-*.
+
+`v10'
+ Only instructions and register names for CRIS v10 (as found in
+ ETRAX 100 LX) are recognized. This is the default if the target
+ is configured as crisv10-*.
+
+`v32'
+ Only instructions and register names for CRIS v32 (code name
+ Guinness) are recognized. This is the default if the target is
+ configured as crisv32-*. This value implies `--no-mul-bug-abort'.
+ (A subsequent `--mul-bug-abort' will turn it back on.)
+
+`common_v10_v32'
+ Only instructions with register names and addressing modes with
+ opcodes common to the v10 and v32 are recognized.
+
+ When `-N' is specified, `as' will emit a warning when a 16-bit
+branch instruction is expanded into a 32-bit multiple-instruction
+construct (*note CRIS-Expand::).
+
+ Some versions of the CRIS v10, for example in the Etrax 100 LX,
+contain a bug that causes destabilizing memory accesses when a multiply
+instruction is executed with certain values in the first operand just
+before a cache-miss. When the `--mul-bug-abort' command line option is
+active (the default value), `as' will refuse to assemble a file
+containing a multiply instruction at a dangerous offset, one that could
+be the last on a cache-line, or is in a section with insufficient
+alignment. This placement checking does not catch any case where the
+multiply instruction is dangerously placed because it is located in a
+delay-slot. The `--mul-bug-abort' command line option turns off the
+checking.
+
+
+File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent
+
+9.8.2 Instruction expansion
+---------------------------
+
+`as' will silently choose an instruction that fits the operand size for
+`[register+constant]' operands. For example, the offset `127' in
+`move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
+Similarly, `move.d [r2+32767],r1' will generate an instruction using a
+16-bit offset. For symbolic expressions and constants that do not fit
+in 16 bits including the sign bit, a 32-bit offset is generated.
+
+ For branches, `as' will expand from a 16-bit branch instruction into
+a sequence of instructions that can reach a full 32-bit address. Since
+this does not correspond to a single instruction, such expansions can
+optionally be warned about. *Note CRIS-Opts::.
+
+ If the operand is found to fit the range, a `lapc' mnemonic will
+translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit
+`lapc' instruction.
+
+ Similarly, the `addo' mnemonic will translate to the shortest
+fitting instruction of `addoq', `addo.w' and `addo.d', when used with a
+operand that is a constant known at assembly time.
+
+
+File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent
+
+9.8.3 Symbols
+-------------
+
+Some symbols are defined by the assembler. They're intended to be used
+in conditional assembly, for example:
+ .if ..asm.arch.cris.v32
+ CODE FOR CRIS V32
+ .elseif ..asm.arch.cris.common_v10_v32
+ CODE COMMON TO CRIS V32 AND CRIS V10
+ .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
+ CODE FOR V10
+ .else
+ .error "Code needs to be added here."
+ .endif
+
+ These symbols are defined in the assembler, reflecting command-line
+options, either when specified or the default. They are always
+defined, to 0 or 1.
+`..asm.arch.cris.any_v0_v10'
+ This symbol is non-zero when `--march=v0_v10' is specified or the
+ default.
+
+`..asm.arch.cris.common_v10_v32'
+ Set according to the option `--march=common_v10_v32'.
+
+`..asm.arch.cris.v10'
+ Reflects the option `--march=v10'.
+
+`..asm.arch.cris.v32'
+ Corresponds to `--march=v10'.
+
+ Speaking of symbols, when a symbol is used in code, it can have a
+suffix modifying its value for use in position-independent code. *Note
+CRIS-Pic::.
+
+
+File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent
+
+9.8.4 Syntax
+------------
+
+There are different aspects of the CRIS assembly syntax.
+
+* Menu:
+
+* CRIS-Chars:: Special Characters
+* CRIS-Pic:: Position-Independent Code Symbols
+* CRIS-Regs:: Register Names
+* CRIS-Pseudos:: Assembler Directives
+
+
+File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax
+
+9.8.4.1 Special Characters
+..........................
+
+The character `#' is a line comment character. It starts a comment if
+and only if it is placed at the beginning of a line.
+
+ A `;' character starts a comment anywhere on the line, causing all
+characters up to the end of the line to be ignored.
+
+ A `@' character is handled as a line separator equivalent to a
+logical new-line character (except in a comment), so separate
+instructions can be specified on a single line.
+
+
+File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax
+
+9.8.4.2 Symbols in position-independent code
+............................................
+
+When generating position-independent code (SVR4 PIC) for use in
+cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
+suffixes are used to specify what kind of run-time symbol lookup will
+be used, expressed in the object as different _relocation types_.
+Usually, all absolute symbol values must be located in a table, the
+_global offset table_, leaving the code position-independent;
+independent of values of global symbols and independent of the address
+of the code. The suffix modifies the value of the symbol, into for
+example an index into the global offset table where the real symbol
+value is entered, or a PC-relative value, or a value relative to the
+start of the global offset table. All symbol suffixes start with the
+character `:' (omitted in the list below). Every symbol use in code or
+a read-only section must therefore have a PIC suffix to enable a useful
+shared library to be created. Usually, these constructs must not be
+used with an additive constant offset as is usually allowed, i.e. no 4
+as in `symbol + 4' is allowed. This restriction is checked at
+link-time, not at assembly-time.
+
+`GOT'
+ Attaching this suffix to a symbol in an instruction causes the
+ symbol to be entered into the global offset table. The value is a
+ 32-bit index for that symbol into the global offset table. The
+ name of the corresponding relocation is `R_CRIS_32_GOT'. Example:
+ `move.d [$r0+extsym:GOT],$r9'
+
+`GOT16'
+ Same as for `GOT', but the value is a 16-bit index into the global
+ offset table. The corresponding relocation is `R_CRIS_16_GOT'.
+ Example: `move.d [$r0+asymbol:GOT16],$r10'
+
+`PLT'
+ This suffix is used for function symbols. It causes a _procedure
+ linkage table_, an array of code stubs, to be created at the time
+ the shared object is created or linked against, together with a
+ global offset table entry. The value is a pc-relative offset to
+ the corresponding stub code in the procedure linkage table. This
+ arrangement causes the run-time symbol resolver to be called to
+ look up and set the value of the symbol the first time the
+ function is called (at latest; depending environment variables).
+ It is only safe to leave the symbol unresolved this way if all
+ references are function calls. The name of the relocation is
+ `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc'
+
+`PLTG'
+ Like PLT, but the value is relative to the beginning of the global
+ offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example:
+ `move.d fnname:PLTG,$r3'
+
+`GOTPLT'
+ Similar to `PLT', but the value of the symbol is a 32-bit index
+ into the global offset table. This is somewhat of a mix between
+ the effect of the `GOT' and the `PLT' suffix; the difference to
+ `GOT' is that there will be a procedure linkage table entry
+ created, and that the symbol is assumed to be a function entry and
+ will be resolved by the run-time resolver as with `PLT'. The
+ relocation is `R_CRIS_32_GOTPLT'. Example: `jsr
+ [$r0+fnname:GOTPLT]'
+
+`GOTPLT16'
+ A variant of `GOTPLT' giving a 16-bit value. Its relocation name
+ is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]'
+
+`GOTOFF'
+ This suffix must only be attached to a local symbol, but may be
+ used in an expression adding an offset. The value is the address
+ of the symbol relative to the start of the global offset table.
+ The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d
+ [$r0+localsym:GOTOFF],r3'
+
+
+File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax
+
+9.8.4.3 Register names
+......................
+
+A `$' character may always prefix a general or special register name in
+an instruction operand but is mandatory when the option
+`--no-underscore' is specified or when the `.syntax register_prefix'
+directive is in effect (*note crisnous::). Register names are
+case-insensitive.
+
+
+File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax
+
+9.8.4.4 Assembler Directives
+............................
+
+There are a few CRIS-specific pseudo-directives in addition to the
+generic ones. *Note Pseudo Ops::. Constants emitted by
+pseudo-directives are in little-endian order for CRIS. There is no
+support for floating-point-specific directives for CRIS.
+
+`.dword EXPRESSIONS'
+ The `.dword' directive is a synonym for `.int', expecting zero or
+ more EXPRESSIONS, separated by commas. For each expression, a
+ 32-bit little-endian constant is emitted.
+
+`.syntax ARGUMENT'
+ The `.syntax' directive takes as ARGUMENT one of the following
+ case-sensitive choices.
+
+ `no_register_prefix'
+ The `.syntax no_register_prefix' directive makes a `$'
+ character prefix on all registers optional. It overrides a
+ previous setting, including the corresponding effect of the
+ option `--no-underscore'. If this directive is used when
+ ordinary symbols do not have a `_' character prefix, care
+ must be taken to avoid ambiguities whether an operand is a
+ register or a symbol; using symbols with names the same as
+ general or special registers then invoke undefined behavior.
+
+ `register_prefix'
+ This directive makes a `$' character prefix on all registers
+ mandatory. It overrides a previous setting, including the
+ corresponding effect of the option `--underscore'.
+
+ `leading_underscore'
+ This is an assertion directive, emitting an error if the
+ `--no-underscore' option is in effect.
+
+ `no_leading_underscore'
+ This is the opposite of the `.syntax leading_underscore'
+ directive and emits an error if the option `--underscore' is
+ in effect.
+
+`.arch ARGUMENT'
+ This is an assertion directive, giving an error if the specified
+ ARGUMENT is not the same as the specified or default value for the
+ `--march=ARCHITECTURE' option (*note march-option::).
+
+
+
+File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies
+
+9.9 D10V Dependent Features
+===========================
+
+* Menu:
+
+* D10V-Opts:: D10V Options
+* D10V-Syntax:: Syntax
+* D10V-Float:: Floating Point
+* D10V-Opcodes:: Opcodes
+
+
+File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent
+
+9.9.1 D10V Options
+------------------
+
+The Mitsubishi D10V version of `as' has a few machine dependent options.
+
+`-O'
+ The D10V can often execute two sub-instructions in parallel. When
+ this option is used, `as' will attempt to optimize its output by
+ detecting when instructions can be executed in parallel.
+
+`--nowarnswap'
+ To optimize execution performance, `as' will sometimes swap the
+ order of instructions. Normally this generates a warning. When
+ this option is used, no warning will be generated when
+ instructions are swapped.
+
+`--gstabs-packing'
+`--no-gstabs-packing'
+ `as' packs adjacent short instructions into a single packed
+ instruction. `--no-gstabs-packing' turns instruction packing off if
+ `--gstabs' is specified as well; `--gstabs-packing' (the default)
+ turns instruction packing on even when `--gstabs' is specified.
+
+
+File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent
+
+9.9.2 Syntax
+------------
+
+The D10V syntax is based on the syntax in Mitsubishi's D10V
+architecture manual. The differences are detailed below.
+
+* Menu:
+
+* D10V-Size:: Size Modifiers
+* D10V-Subs:: Sub-Instructions
+* D10V-Chars:: Special Characters
+* D10V-Regs:: Register Names
+* D10V-Addressing:: Addressing Modes
+* D10V-Word:: @WORD Modifier
+
+
+File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax
+
+9.9.2.1 Size Modifiers
+......................
+
+The D10V version of `as' uses the instruction names in the D10V
+Architecture Manual. However, the names in the manual are sometimes
+ambiguous. There are instruction names that can assemble to a short or
+long form opcode. How does the assembler pick the correct form? `as'
+will always pick the smallest form if it can. When dealing with a
+symbol that is not defined yet when a line is being assembled, it will
+always use the long form. If you need to force the assembler to use
+either the short or long form of the instruction, you can append either
+`.s' (short) or `.l' (long) to it. For example, if you are writing an
+assembly program and you want to do a branch to a symbol that is
+defined later in your program, you can write `bra.s foo'. Objdump
+and GDB will always append `.s' or `.l' to instructions which have both
+short and long forms.
+
+
+File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax
+
+9.9.2.2 Sub-Instructions
+........................
+
+The D10V assembler takes as input a series of instructions, either
+one-per-line, or in the special two-per-line format described in the
+next section. Some of these instructions will be short-form or
+sub-instructions. These sub-instructions can be packed into a single
+instruction. The assembler will do this automatically. It will also
+detect when it should not pack instructions. For example, when a label
+is defined, the next instruction will never be packaged with the
+previous one. Whenever a branch and link instruction is called, it
+will not be packaged with the next instruction so the return address
+will be valid. Nops are automatically inserted when necessary.
+
+ If you do not want the assembler automatically making these
+decisions, you can control the packaging and execution type (parallel
+or sequential) with the special execution symbols described in the next
+section.
+
+
+File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax
+
+9.9.2.3 Special Characters
+..........................
+
+A semicolon (`;') can be used anywhere on a line to start a comment
+that extends to the end of the line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line could also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ Sub-instructions may be executed in order, in reverse-order, or in
+parallel. Instructions listed in the standard one-per-line format will
+be executed sequentially. To specify the executing order, use the
+following symbols:
+`->'
+ Sequential with instruction on the left first.
+
+`<-'
+ Sequential with instruction on the right first.
+
+`||'
+ Parallel
+ The D10V syntax allows either one instruction per line, one
+instruction per line with the execution symbol, or two instructions per
+line. For example
+`abs a1 -> abs r0'
+ Execute these sequentially. The instruction on the right is in
+ the right container and is executed second.
+
+`abs r0 <- abs a1'
+ Execute these reverse-sequentially. The instruction on the right
+ is in the right container, and is executed first.
+
+`ld2w r2,@r8+ || mac a0,r0,r7'
+ Execute these in parallel.
+
+`ld2w r2,@r8+ ||'
+`mac a0,r0,r7'
+ Two-line format. Execute these in parallel.
+
+`ld2w r2,@r8+'
+`mac a0,r0,r7'
+ Two-line format. Execute these sequentially. Assembler will put
+ them in the proper containers.
+
+`ld2w r2,@r8+ ->'
+`mac a0,r0,r7'
+ Two-line format. Execute these sequentially. Same as above but
+ second instruction will always go into right container.
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax
+
+9.9.2.4 Register Names
+......................
+
+You can use the predefined symbols `r0' through `r15' to refer to the
+D10V registers. You can also use `sp' as an alias for `r15'. The
+accumulators are `a0' and `a1'. There are special register-pair names
+that may optionally be used in opcodes that require even-numbered
+registers. Register names are not case sensitive.
+
+ Register Pairs
+`r0-r1'
+
+`r2-r3'
+
+`r4-r5'
+
+`r6-r7'
+
+`r8-r9'
+
+`r10-r11'
+
+`r12-r13'
+
+`r14-r15'
+
+ The D10V also has predefined symbols for these control registers and
+status bits:
+`psw'
+ Processor Status Word
+
+`bpsw'
+ Backup Processor Status Word
+
+`pc'
+ Program Counter
+
+`bpc'
+ Backup Program Counter
+
+`rpt_c'
+ Repeat Count
+
+`rpt_s'
+ Repeat Start address
+
+`rpt_e'
+ Repeat End address
+
+`mod_s'
+ Modulo Start address
+
+`mod_e'
+ Modulo End address
+
+`iba'
+ Instruction Break Address
+
+`f0'
+ Flag 0
+
+`f1'
+ Flag 1
+
+`c'
+ Carry flag
+
+
+File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax
+
+9.9.2.5 Addressing Modes
+........................
+
+`as' understands the following addressing modes for the D10V. `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+`RN'
+ Register direct
+
+`@RN'
+ Register indirect
+
+`@RN+'
+ Register indirect with post-increment
+
+`@RN-'
+ Register indirect with post-decrement
+
+`@-SP'
+ Register indirect with pre-decrement
+
+`@(DISP, RN)'
+ Register indirect with displacement
+
+`ADDR'
+ PC relative address (for branch or rep).
+
+`#IMM'
+ Immediate data (the `#' is optional and ignored)
+
+
+File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax
+
+9.9.2.6 @WORD Modifier
+......................
+
+Any symbol followed by `@word' will be replaced by the symbol's value
+shifted right by 2. This is used in situations such as loading a
+register with the address of a function (or any other code fragment).
+For example, if you want to load a register with the location of the
+function `main' then jump to that function, you could do it as follows:
+ ldi r2, main@word
+ jmp r2
+
+
+File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent
+
+9.9.3 Floating Point
+--------------------
+
+The D10V has no hardware floating point, but the `.float' and `.double'
+directives generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent
+
+9.9.4 Opcodes
+-------------
+
+For detailed information on the D10V machine instruction set, see `D10V
+Architecture: A VLIW Microprocessor for Multimedia Applications'
+(Mitsubishi Electric Corp.). `as' implements all the standard D10V
+opcodes. The only changes are those described in the section on size
+modifiers
+
+
+File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies
+
+9.10 D30V Dependent Features
+============================
+
+* Menu:
+
+* D30V-Opts:: D30V Options
+* D30V-Syntax:: Syntax
+* D30V-Float:: Floating Point
+* D30V-Opcodes:: Opcodes
+
+
+File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent
+
+9.10.1 D30V Options
+-------------------
+
+The Mitsubishi D30V version of `as' has a few machine dependent options.
+
+`-O'
+ The D30V can often execute two sub-instructions in parallel. When
+ this option is used, `as' will attempt to optimize its output by
+ detecting when instructions can be executed in parallel.
+
+`-n'
+ When this option is used, `as' will issue a warning every time it
+ adds a nop instruction.
+
+`-N'
+ When this option is used, `as' will issue a warning if it needs to
+ insert a nop after a 32-bit multiply before a load or 16-bit
+ multiply instruction.
+
+
+File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent
+
+9.10.2 Syntax
+-------------
+
+The D30V syntax is based on the syntax in Mitsubishi's D30V
+architecture manual. The differences are detailed below.
+
+* Menu:
+
+* D30V-Size:: Size Modifiers
+* D30V-Subs:: Sub-Instructions
+* D30V-Chars:: Special Characters
+* D30V-Guarded:: Guarded Execution
+* D30V-Regs:: Register Names
+* D30V-Addressing:: Addressing Modes
+
+
+File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax
+
+9.10.2.1 Size Modifiers
+.......................
+
+The D30V version of `as' uses the instruction names in the D30V
+Architecture Manual. However, the names in the manual are sometimes
+ambiguous. There are instruction names that can assemble to a short or
+long form opcode. How does the assembler pick the correct form? `as'
+will always pick the smallest form if it can. When dealing with a
+symbol that is not defined yet when a line is being assembled, it will
+always use the long form. If you need to force the assembler to use
+either the short or long form of the instruction, you can append either
+`.s' (short) or `.l' (long) to it. For example, if you are writing an
+assembly program and you want to do a branch to a symbol that is
+defined later in your program, you can write `bra.s foo'. Objdump and
+GDB will always append `.s' or `.l' to instructions which have both
+short and long forms.
+
+
+File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax
+
+9.10.2.2 Sub-Instructions
+.........................
+
+The D30V assembler takes as input a series of instructions, either
+one-per-line, or in the special two-per-line format described in the
+next section. Some of these instructions will be short-form or
+sub-instructions. These sub-instructions can be packed into a single
+instruction. The assembler will do this automatically. It will also
+detect when it should not pack instructions. For example, when a label
+is defined, the next instruction will never be packaged with the
+previous one. Whenever a branch and link instruction is called, it
+will not be packaged with the next instruction so the return address
+will be valid. Nops are automatically inserted when necessary.
+
+ If you do not want the assembler automatically making these
+decisions, you can control the packaging and execution type (parallel
+or sequential) with the special execution symbols described in the next
+section.
+
+
+File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax
+
+9.10.2.3 Special Characters
+...........................
+
+A semicolon (`;') can be used anywhere on a line to start a comment
+that extends to the end of the line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line could also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ Sub-instructions may be executed in order, in reverse-order, or in
+parallel. Instructions listed in the standard one-per-line format will
+be executed sequentially unless you use the `-O' option.
+
+ To specify the executing order, use the following symbols:
+`->'
+ Sequential with instruction on the left first.
+
+`<-'
+ Sequential with instruction on the right first.
+
+`||'
+ Parallel
+
+ The D30V syntax allows either one instruction per line, one
+instruction per line with the execution symbol, or two instructions per
+line. For example
+`abs r2,r3 -> abs r4,r5'
+ Execute these sequentially. The instruction on the right is in
+ the right container and is executed second.
+
+`abs r2,r3 <- abs r4,r5'
+ Execute these reverse-sequentially. The instruction on the right
+ is in the right container, and is executed first.
+
+`abs r2,r3 || abs r4,r5'
+ Execute these in parallel.
+
+`ldw r2,@(r3,r4) ||'
+`mulx r6,r8,r9'
+ Two-line format. Execute these in parallel.
+
+`mulx a0,r8,r9'
+`stw r2,@(r3,r4)'
+ Two-line format. Execute these sequentially unless `-O' option is
+ used. If the `-O' option is used, the assembler will determine if
+ the instructions could be done in parallel (the above two
+ instructions can be done in parallel), and if so, emit them as
+ parallel instructions. The assembler will put them in the proper
+ containers. In the above example, the assembler will put the
+ `stw' instruction in left container and the `mulx' instruction in
+ the right container.
+
+`stw r2,@(r3,r4) ->'
+`mulx a0,r8,r9'
+ Two-line format. Execute the `stw' instruction followed by the
+ `mulx' instruction sequentially. The first instruction goes in the
+ left container and the second instruction goes into right
+ container. The assembler will give an error if the machine
+ ordering constraints are violated.
+
+`stw r2,@(r3,r4) <-'
+`mulx a0,r8,r9'
+ Same as previous example, except that the `mulx' instruction is
+ executed before the `stw' instruction.
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax
+
+9.10.2.4 Guarded Execution
+..........................
+
+`as' supports the full range of guarded execution directives for each
+instruction. Just append the directive after the instruction proper.
+The directives are:
+
+`/tx'
+ Execute the instruction if flag f0 is true.
+
+`/fx'
+ Execute the instruction if flag f0 is false.
+
+`/xt'
+ Execute the instruction if flag f1 is true.
+
+`/xf'
+ Execute the instruction if flag f1 is false.
+
+`/tt'
+ Execute the instruction if both flags f0 and f1 are true.
+
+`/tf'
+ Execute the instruction if flag f0 is true and flag f1 is false.
+
+
+File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax
+
+9.10.2.5 Register Names
+.......................
+
+You can use the predefined symbols `r0' through `r63' to refer to the
+D30V registers. You can also use `sp' as an alias for `r63' and `link'
+as an alias for `r62'. The accumulators are `a0' and `a1'.
+
+ The D30V also has predefined symbols for these control registers and
+status bits:
+`psw'
+ Processor Status Word
+
+`bpsw'
+ Backup Processor Status Word
+
+`pc'
+ Program Counter
+
+`bpc'
+ Backup Program Counter
+
+`rpt_c'
+ Repeat Count
+
+`rpt_s'
+ Repeat Start address
+
+`rpt_e'
+ Repeat End address
+
+`mod_s'
+ Modulo Start address
+
+`mod_e'
+ Modulo End address
+
+`iba'
+ Instruction Break Address
+
+`f0'
+ Flag 0
+
+`f1'
+ Flag 1
+
+`f2'
+ Flag 2
+
+`f3'
+ Flag 3
+
+`f4'
+ Flag 4
+
+`f5'
+ Flag 5
+
+`f6'
+ Flag 6
+
+`f7'
+ Flag 7
+
+`s'
+ Same as flag 4 (saturation flag)
+
+`v'
+ Same as flag 5 (overflow flag)
+
+`va'
+ Same as flag 6 (sticky overflow flag)
+
+`c'
+ Same as flag 7 (carry/borrow flag)
+
+`b'
+ Same as flag 7 (carry/borrow flag)
+
+
+File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax
+
+9.10.2.6 Addressing Modes
+.........................
+
+`as' understands the following addressing modes for the D30V. `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+`RN'
+ Register direct
+
+`@RN'
+ Register indirect
+
+`@RN+'
+ Register indirect with post-increment
+
+`@RN-'
+ Register indirect with post-decrement
+
+`@-SP'
+ Register indirect with pre-decrement
+
+`@(DISP, RN)'
+ Register indirect with displacement
+
+`ADDR'
+ PC relative address (for branch or rep).
+
+`#IMM'
+ Immediate data (the `#' is optional and ignored)
+
+
+File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent
+
+9.10.3 Floating Point
+---------------------
+
+The D30V has no hardware floating point, but the `.float' and `.double'
+directives generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent
+
+9.10.4 Opcodes
+--------------
+
+For detailed information on the D30V machine instruction set, see `D30V
+Architecture: A VLIW Microprocessor for Multimedia Applications'
+(Mitsubishi Electric Corp.). `as' implements all the standard D30V
+opcodes. The only changes are those described in the section on size
+modifiers
+
+
+File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies
+
+9.11 Epiphany Dependent Features
+================================
+
+* Menu:
+
+* Epiphany Options:: Options
+* Epiphany Syntax:: Epiphany Syntax
+
+
+File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent
+
+9.11.1 Options
+--------------
+
+`as' has two additional command-line options for the Epiphany
+architecture.
+
+`-mepiphany'
+ Specifies that the both 32 and 16 bit instructions are allowed.
+ This is the default behavior.
+
+`-mepiphany16'
+ Restricts the permitted instructions to just the 16 bit set.
+
+
+File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent
+
+9.11.2 Epiphany Syntax
+----------------------
+
+* Menu:
+
+* Epiphany-Chars:: Special Characters
+
+
+File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax
+
+9.11.2.1 Special Characters
+...........................
+
+The presence of a `;' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The ``' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies
+
+9.12 H8/300 Dependent Features
+==============================
+
+* Menu:
+
+* H8/300 Options:: Options
+* H8/300 Syntax:: Syntax
+* H8/300 Floating Point:: Floating Point
+* H8/300 Directives:: H8/300 Machine Directives
+* H8/300 Opcodes:: Opcodes
+
+
+File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent
+
+9.12.1 Options
+--------------
+
+The Renesas H8/300 version of `as' has one machine-dependent option:
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
+`-mach=NAME'
+ Sets the H8300 machine variant. The following machine names are
+ recognised: `h8300h', `h8300hn', `h8300s', `h8300sn', `h8300sx' and
+ `h8300sxn'.
+
+
+
+File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent
+
+9.12.2 Syntax
+-------------
+
+* Menu:
+
+* H8/300-Chars:: Special Characters
+* H8/300-Regs:: Register Names
+* H8/300-Addressing:: Addressing Modes
+
+
+File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax
+
+9.12.2.1 Special Characters
+...........................
+
+`;' is the line comment character.
+
+ `$' can be used instead of a newline to separate statements.
+Therefore _you may not use `$' in symbol names_ on the H8/300.
+
+
+File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax
+
+9.12.2.2 Register Names
+.......................
+
+You can use predefined symbols of the form `rNh' and `rNl' to refer to
+the H8/300 registers as sixteen 8-bit general-purpose registers. N is
+a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid
+register names.
+
+ You can also use the eight predefined symbols `rN' to refer to the
+H8/300 registers as 16-bit registers (you must use this form for
+addressing).
+
+ On the H8/300H, you can also use the eight predefined symbols `erN'
+(`er0' ... `er7') to refer to the 32-bit general purpose registers.
+
+ The two control registers are called `pc' (program counter; a 16-bit
+register, except on the H8/300H where it is 24 bits) and `ccr'
+(condition code register; an 8-bit register). `r7' is used as the
+stack pointer, and can also be called `sp'.
+
+
+File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax
+
+9.12.2.3 Addressing Modes
+.........................
+
+as understands the following addressing modes for the H8/300:
+`rN'
+ Register direct
+
+`@rN'
+ Register indirect
+
+`@(D, rN)'
+`@(D:16, rN)'
+`@(D:24, rN)'
+ Register indirect: 16-bit or 24-bit displacement D from register
+ N. (24-bit displacements are only meaningful on the H8/300H.)
+
+`@rN+'
+ Register indirect with post-increment
+
+`@-rN'
+ Register indirect with pre-decrement
+
+``@'AA'
+``@'AA:8'
+``@'AA:16'
+``@'AA:24'
+ Absolute address `aa'. (The address size `:24' only makes sense
+ on the H8/300H.)
+
+`#XX'
+`#XX:8'
+`#XX:16'
+`#XX:32'
+ Immediate data XX. You may specify the `:8', `:16', or `:32' for
+ clarity, if you wish; but `as' neither requires this nor uses
+ it--the data size required is taken from context.
+
+``@'`@'AA'
+``@'`@'AA:8'
+ Memory indirect. You may specify the `:8' for clarity, if you
+ wish; but `as' neither requires this nor uses it.
+
+
+File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent
+
+9.12.3 Floating Point
+---------------------
+
+The H8/300 family has no hardware floating point, but the `.float'
+directive generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent
+
+9.12.4 H8/300 Machine Directives
+--------------------------------
+
+`as' has the following machine-dependent directives for the H8/300:
+
+`.h8300h'
+ Recognize and emit additional instructions for the H8/300H
+ variant, and also make `.int' emit 32-bit numbers rather than the
+ usual (16-bit) for the H8/300 family.
+
+`.h8300s'
+ Recognize and emit additional instructions for the H8S variant, and
+ also make `.int' emit 32-bit numbers rather than the usual (16-bit)
+ for the H8/300 family.
+
+`.h8300hn'
+ Recognize and emit additional instructions for the H8/300H variant
+ in normal mode, and also make `.int' emit 32-bit numbers rather
+ than the usual (16-bit) for the H8/300 family.
+
+`.h8300sn'
+ Recognize and emit additional instructions for the H8S variant in
+ normal mode, and also make `.int' emit 32-bit numbers rather than
+ the usual (16-bit) for the H8/300 family.
+
+ On the H8/300 family (including the H8/300H) `.word' directives
+generate 16-bit numbers.
+
+
+File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent
+
+9.12.5 Opcodes
+--------------
+
+For detailed information on the H8/300 machine instruction set, see
+`H8/300 Series Programming Manual'. For information specific to the
+H8/300H, see `H8/300H Series Programming Manual' (Renesas).
+
+ `as' implements all the standard H8/300 opcodes. No additional
+pseudo-instructions are needed on this family.
+
+ The following table summarizes the H8/300 opcodes, and their
+arguments. Entries marked `*' are opcodes used only on the H8/300H.
+
+ Legend:
+ Rs source register
+ Rd destination register
+ abs absolute address
+ imm immediate data
+ disp:N N-bit displacement from a register
+ pcrel:N N-bit displacement relative to program counter
+
+ add.b #imm,rd * andc #imm,ccr
+ add.b rs,rd band #imm,rd
+ add.w rs,rd band #imm,@rd
+ * add.w #imm,rd band #imm,@abs:8
+ * add.l rs,rd bra pcrel:8
+ * add.l #imm,rd * bra pcrel:16
+ adds #imm,rd bt pcrel:8
+ addx #imm,rd * bt pcrel:16
+ addx rs,rd brn pcrel:8
+ and.b #imm,rd * brn pcrel:16
+ and.b rs,rd bf pcrel:8
+ * and.w rs,rd * bf pcrel:16
+ * and.w #imm,rd bhi pcrel:8
+ * and.l #imm,rd * bhi pcrel:16
+ * and.l rs,rd bls pcrel:8
+
+ * bls pcrel:16 bld #imm,rd
+ bcc pcrel:8 bld #imm,@rd
+ * bcc pcrel:16 bld #imm,@abs:8
+ bhs pcrel:8 bnot #imm,rd
+ * bhs pcrel:16 bnot #imm,@rd
+ bcs pcrel:8 bnot #imm,@abs:8
+ * bcs pcrel:16 bnot rs,rd
+ blo pcrel:8 bnot rs,@rd
+ * blo pcrel:16 bnot rs,@abs:8
+ bne pcrel:8 bor #imm,rd
+ * bne pcrel:16 bor #imm,@rd
+ beq pcrel:8 bor #imm,@abs:8
+ * beq pcrel:16 bset #imm,rd
+ bvc pcrel:8 bset #imm,@rd
+ * bvc pcrel:16 bset #imm,@abs:8
+ bvs pcrel:8 bset rs,rd
+ * bvs pcrel:16 bset rs,@rd
+ bpl pcrel:8 bset rs,@abs:8
+ * bpl pcrel:16 bsr pcrel:8
+ bmi pcrel:8 bsr pcrel:16
+ * bmi pcrel:16 bst #imm,rd
+ bge pcrel:8 bst #imm,@rd
+ * bge pcrel:16 bst #imm,@abs:8
+ blt pcrel:8 btst #imm,rd
+ * blt pcrel:16 btst #imm,@rd
+ bgt pcrel:8 btst #imm,@abs:8
+ * bgt pcrel:16 btst rs,rd
+ ble pcrel:8 btst rs,@rd
+ * ble pcrel:16 btst rs,@abs:8
+ bclr #imm,rd bxor #imm,rd
+ bclr #imm,@rd bxor #imm,@rd
+ bclr #imm,@abs:8 bxor #imm,@abs:8
+ bclr rs,rd cmp.b #imm,rd
+ bclr rs,@rd cmp.b rs,rd
+ bclr rs,@abs:8 cmp.w rs,rd
+ biand #imm,rd cmp.w rs,rd
+ biand #imm,@rd * cmp.w #imm,rd
+ biand #imm,@abs:8 * cmp.l #imm,rd
+ bild #imm,rd * cmp.l rs,rd
+ bild #imm,@rd daa rs
+ bild #imm,@abs:8 das rs
+ bior #imm,rd dec.b rs
+ bior #imm,@rd * dec.w #imm,rd
+ bior #imm,@abs:8 * dec.l #imm,rd
+ bist #imm,rd divxu.b rs,rd
+ bist #imm,@rd * divxu.w rs,rd
+ bist #imm,@abs:8 * divxs.b rs,rd
+ bixor #imm,rd * divxs.w rs,rd
+ bixor #imm,@rd eepmov
+ bixor #imm,@abs:8 * eepmovw
+
+ * exts.w rd mov.w rs,@abs:16
+ * exts.l rd * mov.l #imm,rd
+ * extu.w rd * mov.l rs,rd
+ * extu.l rd * mov.l @rs,rd
+ inc rs * mov.l @(disp:16,rs),rd
+ * inc.w #imm,rd * mov.l @(disp:24,rs),rd
+ * inc.l #imm,rd * mov.l @rs+,rd
+ jmp @rs * mov.l @abs:16,rd
+ jmp abs * mov.l @abs:24,rd
+ jmp @@abs:8 * mov.l rs,@rd
+ jsr @rs * mov.l rs,@(disp:16,rd)
+ jsr abs * mov.l rs,@(disp:24,rd)
+ jsr @@abs:8 * mov.l rs,@-rd
+ ldc #imm,ccr * mov.l rs,@abs:16
+ ldc rs,ccr * mov.l rs,@abs:24
+ * ldc @abs:16,ccr movfpe @abs:16,rd
+ * ldc @abs:24,ccr movtpe rs,@abs:16
+ * ldc @(disp:16,rs),ccr mulxu.b rs,rd
+ * ldc @(disp:24,rs),ccr * mulxu.w rs,rd
+ * ldc @rs+,ccr * mulxs.b rs,rd
+ * ldc @rs,ccr * mulxs.w rs,rd
+ * mov.b @(disp:24,rs),rd neg.b rs
+ * mov.b rs,@(disp:24,rd) * neg.w rs
+ mov.b @abs:16,rd * neg.l rs
+ mov.b rs,rd nop
+ mov.b @abs:8,rd not.b rs
+ mov.b rs,@abs:8 * not.w rs
+ mov.b rs,rd * not.l rs
+ mov.b #imm,rd or.b #imm,rd
+ mov.b @rs,rd or.b rs,rd
+ mov.b @(disp:16,rs),rd * or.w #imm,rd
+ mov.b @rs+,rd * or.w rs,rd
+ mov.b @abs:8,rd * or.l #imm,rd
+ mov.b rs,@rd * or.l rs,rd
+ mov.b rs,@(disp:16,rd) orc #imm,ccr
+ mov.b rs,@-rd pop.w rs
+ mov.b rs,@abs:8 * pop.l rs
+ mov.w rs,@rd push.w rs
+ * mov.w @(disp:24,rs),rd * push.l rs
+ * mov.w rs,@(disp:24,rd) rotl.b rs
+ * mov.w @abs:24,rd * rotl.w rs
+ * mov.w rs,@abs:24 * rotl.l rs
+ mov.w rs,rd rotr.b rs
+ mov.w #imm,rd * rotr.w rs
+ mov.w @rs,rd * rotr.l rs
+ mov.w @(disp:16,rs),rd rotxl.b rs
+ mov.w @rs+,rd * rotxl.w rs
+ mov.w @abs:16,rd * rotxl.l rs
+ mov.w rs,@(disp:16,rd) rotxr.b rs
+ mov.w rs,@-rd * rotxr.w rs
+
+ * rotxr.l rs * stc ccr,@(disp:24,rd)
+ bpt * stc ccr,@-rd
+ rte * stc ccr,@abs:16
+ rts * stc ccr,@abs:24
+ shal.b rs sub.b rs,rd
+ * shal.w rs sub.w rs,rd
+ * shal.l rs * sub.w #imm,rd
+ shar.b rs * sub.l rs,rd
+ * shar.w rs * sub.l #imm,rd
+ * shar.l rs subs #imm,rd
+ shll.b rs subx #imm,rd
+ * shll.w rs subx rs,rd
+ * shll.l rs * trapa #imm
+ shlr.b rs xor #imm,rd
+ * shlr.w rs xor rs,rd
+ * shlr.l rs * xor.w #imm,rd
+ sleep * xor.w rs,rd
+ stc ccr,rd * xor.l #imm,rd
+ * stc ccr,@rs * xor.l rs,rd
+ * stc ccr,@(disp:16,rd) xorc #imm,ccr
+
+ Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
+with variants using the suffixes `.b', `.w', and `.l' to specify the
+size of a memory operand. `as' supports these suffixes, but does not
+require them; since one of the operands is always a register, `as' can
+deduce the correct size.
+
+ For example, since `r0' refers to a 16-bit register,
+ mov r0,@foo
+is equivalent to
+ mov.w r0,@foo
+
+ If you use the size suffixes, `as' issues a warning when the suffix
+and the register size do not match.
+
+
+File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies
+
+9.13 HPPA Dependent Features
+============================
+
+* Menu:
+
+* HPPA Notes:: Notes
+* HPPA Options:: Options
+* HPPA Syntax:: Syntax
+* HPPA Floating Point:: Floating Point
+* HPPA Directives:: HPPA Machine Directives
+* HPPA Opcodes:: Opcodes
+
+
+File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent
+
+9.13.1 Notes
+------------
+
+As a back end for GNU CC `as' has been throughly tested and should work
+extremely well. We have tested it only minimally on hand written
+assembly code and no one has tested it much on the assembly output from
+the HP compilers.
+
+ The format of the debugging sections has changed since the original
+`as' port (version 1.3X) was released; therefore, you must rebuild all
+HPPA objects and libraries with the new assembler so that you can debug
+the final executable.
+
+ The HPPA `as' port generates a small subset of the relocations
+available in the SOM and ELF object file formats. Additional relocation
+support will be added as it becomes necessary.
+
+
+File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent
+
+9.13.2 Options
+--------------
+
+`as' has no machine-dependent command-line options for the HPPA.
+
+
+File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
+
+9.13.3 Syntax
+-------------
+
+The assembler syntax closely follows the HPPA instruction set reference
+manual; assembler directives and general syntax closely follow the HPPA
+assembly language reference manual, with a few noteworthy differences.
+
+ First, a colon may immediately follow a label definition. This is
+simply for compatibility with how most assembly language programmers
+write code.
+
+ Some obscure expression parsing problems may affect hand written
+code which uses the `spop' instructions, or code which makes significant
+use of the `!' line separator.
+
+ `as' is much less forgiving about missing arguments and other
+similar oversights than the HP assembler. `as' notifies you of missing
+arguments as syntax errors; this is regarded as a feature, not a bug.
+
+ Finally, `as' allows you to use an external symbol without
+explicitly importing the symbol. _Warning:_ in the future this will be
+an error for HPPA targets.
+
+ Special characters for HPPA targets include:
+
+ `;' is the line comment character.
+
+ `!' can be used instead of a newline to separate statements.
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
+
+9.13.4 Floating Point
+---------------------
+
+The HPPA family uses IEEE floating-point numbers.
+
+
+File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
+
+9.13.5 HPPA Assembler Directives
+--------------------------------
+
+`as' for the HPPA supports many additional directives for compatibility
+with the native assembler. This section describes them only briefly.
+For detailed information on HPPA-specific assembler directives, see
+`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
+
+ `as' does _not_ support the following assembler directives described
+in the HP manual:
+
+ .endm .liston
+ .enter .locct
+ .leave .macro
+ .listoff
+
+ Beyond those implemented for compatibility, `as' supports one
+additional assembler directive for the HPPA: `.param'. It conveys
+register argument locations for static functions. Its syntax closely
+follows the `.export' directive.
+
+ These are the additional directives in `as' for the HPPA:
+
+`.block N'
+`.blockz N'
+ Reserve N bytes of storage, and initialize them to zero.
+
+`.call'
+ Mark the beginning of a procedure call. Only the special case
+ with _no arguments_ is allowed.
+
+`.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]'
+ Specify a number of parameters and flags that define the
+ environment for a procedure.
+
+ PARAM may be any of `frame' (frame size), `entry_gr' (end of
+ general register range), `entry_fr' (end of float register range),
+ `entry_sr' (end of space register range).
+
+ The values for FLAG are `calls' or `caller' (proc has
+ subroutines), `no_calls' (proc does not call subroutines),
+ `save_rp' (preserve return pointer), `save_sp' (proc preserves
+ stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
+ (proc is interrupt routine).
+
+`.code'
+ Assemble into the standard section called `$TEXT$', subsection
+ `$CODE$'.
+
+`.copyright "STRING"'
+ In the SOM object format, insert STRING into the object code,
+ marked as a copyright string.
+
+`.copyright "STRING"'
+ In the ELF object format, insert STRING into the object code,
+ marked as a version string.
+
+`.enter'
+ Not yet supported; the assembler rejects programs containing this
+ directive.
+
+`.entry'
+ Mark the beginning of a procedure.
+
+`.exit'
+ Mark the end of a procedure.
+
+`.export NAME [ ,TYP ] [ ,PARAM=R ]'
+ Make a procedure NAME available to callers. TYP, if present, must
+ be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
+ `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
+
+ PARAM, if present, provides either relocation information for the
+ procedure arguments and result, or a privilege level. PARAM may be
+ `argwN' (where N ranges from `0' to `3', and indicates one of four
+ one-word arguments); `rtnval' (the procedure's result); or
+ `priv_lev' (privilege level). For arguments or the result, R
+ specifies how to relocate, and must be one of `no' (not
+ relocatable), `gr' (argument is in general register), `fr' (in
+ floating point register), or `fu' (upper half of float register).
+ For `priv_lev', R is an integer.
+
+`.half N'
+ Define a two-byte integer constant N; synonym for the portable
+ `as' directive `.short'.
+
+`.import NAME [ ,TYP ]'
+ Converse of `.export'; make a procedure available to call. The
+ arguments use the same conventions as the first two arguments for
+ `.export'.
+
+`.label NAME'
+ Define NAME as a label for the current assembly location.
+
+`.leave'
+ Not yet supported; the assembler rejects programs containing this
+ directive.
+
+`.origin LC'
+ Advance location counter to LC. Synonym for the `as' portable
+ directive `.org'.
+
+`.param NAME [ ,TYP ] [ ,PARAM=R ]'
+ Similar to `.export', but used for static procedures.
+
+`.proc'
+ Use preceding the first statement of a procedure.
+
+`.procend'
+ Use following the last statement of a procedure.
+
+`LABEL .reg EXPR'
+ Synonym for `.equ'; define LABEL with the absolute expression EXPR
+ as its value.
+
+`.space SECNAME [ ,PARAMS ]'
+ Switch to section SECNAME, creating a new section by that name if
+ necessary. You may only use PARAMS when creating a new section,
+ not when switching to an existing one. SECNAME may identify a
+ section by number rather than by name.
+
+ If specified, the list PARAMS declares attributes of the section,
+ identified by keywords. The keywords recognized are `spnum=EXP'
+ (identify this section by the number EXP, an absolute expression),
+ `sort=EXP' (order sections according to this sort key when linking;
+ EXP is an absolute expression), `unloadable' (section contains no
+ loadable data), `notdefined' (this section defined elsewhere), and
+ `private' (data in this section not available to other programs).
+
+`.spnum SECNAM'
+ Allocate four bytes of storage, and initialize them with the
+ section number of the section named SECNAM. (You can define the
+ section number with the HPPA `.space' directive.)
+
+`.string "STR"'
+ Copy the characters in the string STR to the object file. *Note
+ Strings: Strings, for information on escape sequences you can use
+ in `as' strings.
+
+ _Warning!_ The HPPA version of `.string' differs from the usual
+ `as' definition: it does _not_ write a zero byte after copying STR.
+
+`.stringz "STR"'
+ Like `.string', but appends a zero byte after copying STR to object
+ file.
+
+`.subspa NAME [ ,PARAMS ]'
+`.nsubspa NAME [ ,PARAMS ]'
+ Similar to `.space', but selects a subsection NAME within the
+ current section. You may only specify PARAMS when you create a
+ subsection (in the first instance of `.subspa' for this NAME).
+
+ If specified, the list PARAMS declares attributes of the
+ subsection, identified by keywords. The keywords recognized are
+ `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
+ (alignment for beginning of this subsection; a power of two),
+ `access=EXPR' (value for "access rights" field), `sort=EXPR'
+ (sorting order for this subspace in link), `code_only' (subsection
+ contains only code), `unloadable' (subsection cannot be loaded
+ into memory), `comdat' (subsection is comdat), `common'
+ (subsection is common block), `dup_comm' (subsection may have
+ duplicate names), or `zero' (subsection is all zeros, do not write
+ in object file).
+
+ `.nsubspa' always creates a new subspace with the given name, even
+ if one with the same name already exists.
+
+ `comdat', `common' and `dup_comm' can be used to implement various
+ flavors of one-only support when using the SOM linker. The SOM
+ linker only supports specific combinations of these flags. The
+ details are not documented. A brief description is provided here.
+
+ `comdat' provides a form of linkonce support. It is useful for
+ both code and data subspaces. A `comdat' subspace has a key symbol
+ marked by the `is_comdat' flag or `ST_COMDAT'. Only the first
+ subspace for any given key is selected. The key symbol becomes
+ universal in shared links. This is similar to the behavior of
+ `secondary_def' symbols.
+
+ `common' provides Fortran named common support. It is only useful
+ for data subspaces. Symbols with the flag `is_common' retain this
+ flag in shared links. Referencing a `is_common' symbol in a shared
+ library from outside the library doesn't work. Thus, `is_common'
+ symbols must be output whenever they are needed.
+
+ `common' and `dup_comm' together provide Cobol common support.
+ The subspaces in this case must all be the same length.
+ Otherwise, this support is similar to the Fortran common support.
+
+ `dup_comm' by itself provides a type of one-only support for code.
+ Only the first `dup_comm' subspace is selected. There is a rather
+ complex algorithm to compare subspaces. Code symbols marked with
+ the `dup_common' flag are hidden. This support was intended for
+ "C++ duplicate inlines".
+
+ A simplified technique is used to mark the flags of symbols based
+ on the flags of their subspace. A symbol with the scope
+ SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
+ the corresponding settings of `comdat', `common' and `dup_comm'
+ from the subspace, respectively. This avoids having to introduce
+ additional directives to mark these symbols. The HP assembler
+ sets `is_common' from `common'. However, it doesn't set the
+ `dup_common' from `dup_comm'. It doesn't have `comdat' support.
+
+`.version "STR"'
+ Write STR as version identifier in object code.
+
+
+File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
+
+9.13.6 Opcodes
+--------------
+
+For detailed information on the HPPA machine instruction set, see
+`PA-RISC Architecture and Instruction Set Reference Manual' (HP
+09740-90039).
+
+
+File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
+
+9.14 ESA/390 Dependent Features
+===============================
+
+* Menu:
+
+* ESA/390 Notes:: Notes
+* ESA/390 Options:: Options
+* ESA/390 Syntax:: Syntax
+* ESA/390 Floating Point:: Floating Point
+* ESA/390 Directives:: ESA/390 Machine Directives
+* ESA/390 Opcodes:: Opcodes
+
+
+File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
+
+9.14.1 Notes
+------------
+
+The ESA/390 `as' port is currently intended to be a back-end for the
+GNU CC compiler. It is not HLASM compatible, although it does support
+a subset of some of the HLASM directives. The only supported binary
+file format is ELF; none of the usual MVS/VM/OE/USS object file
+formats, such as ESD or XSD, are supported.
+
+ When used with the GNU CC compiler, the ESA/390 `as' will produce
+correct, fully relocated, functional binaries, and has been used to
+compile and execute large projects. However, many aspects should still
+be considered experimental; these include shared library support,
+dynamically loadable objects, and any relocation other than the 31-bit
+relocation.
+
+
+File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
+
+9.14.2 Options
+--------------
+
+`as' has no machine-dependent command-line options for the ESA/390.
+
+
+File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
+
+9.14.3 Syntax
+-------------
+
+The opcode/operand syntax follows the ESA/390 Principles of Operation
+manual; assembler directives and general syntax are loosely based on the
+prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
+are _not_ supported for the most part, with the exception of those
+described herein.
+
+ A leading dot in front of directives is optional, and the case of
+directives is ignored; thus for example, .using and USING have the same
+effect.
+
+ A colon may immediately follow a label definition. This is simply
+for compatibility with how most assembly language programmers write
+code.
+
+ `#' is the line comment character.
+
+ `;' can be used instead of a newline to separate statements.
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+ Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
+fp6. By using thesse symbolic names, `as' can detect simple syntax
+errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
+r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
+for r3 and rpgt or r.pgt for r4.
+
+ `*' is the current location counter. Unlike `.' it is always
+relative to the last USING directive. Note that this means that
+expressions cannot use multiplication, as any occurrence of `*' will be
+interpreted as a location counter.
+
+ All labels are relative to the last USING. Thus, branches to a label
+always imply the use of base+displacement.
+
+ Many of the usual forms of address constants / address literals are
+supported. Thus,
+ .using *,r3
+ L r15,=A(some_routine)
+ LM r6,r7,=V(some_longlong_extern)
+ A r1,=F'12'
+ AH r0,=H'42'
+ ME r6,=E'3.1416'
+ MD r6,=D'3.14159265358979'
+ O r6,=XL4'cacad0d0'
+ .ltorg
+ should all behave as expected: that is, an entry in the literal pool
+will be created (or reused if it already exists), and the instruction
+operands will be the displacement into the literal pool using the
+current base register (as last declared with the `.using' directive).
+
+
+File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
+
+9.14.4 Floating Point
+---------------------
+
+The assembler generates only IEEE floating-point numbers. The older
+floating point formats are not supported.
+
+
+File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
+
+9.14.5 ESA/390 Assembler Directives
+-----------------------------------
+
+`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
+directives that are documented in the main part of this documentation.
+Several additional directives are supported in order to implement the
+ESA/390 addressing model. The most important of these are `.using' and
+`.ltorg'
+
+ These are the additional directives in `as' for the ESA/390:
+
+`.dc'
+ A small subset of the usual DC directive is supported.
+
+`.drop REGNO'
+ Stop using REGNO as the base register. The REGNO must have been
+ previously declared with a `.using' directive in the same section
+ as the current section.
+
+`.ebcdic STRING'
+ Emit the EBCDIC equivalent of the indicated string. The emitted
+ string will be null terminated. Note that the directives
+ `.string' etc. emit ascii strings by default.
+
+`EQU'
+ The standard HLASM-style EQU directive is not supported; however,
+ the standard `as' directive .equ can be used to the same effect.
+
+`.ltorg'
+ Dump the literal pool accumulated so far; begin a new literal pool.
+ The literal pool will be written in the current section; in order
+ to generate correct assembly, a `.using' must have been previously
+ specified in the same section.
+
+`.using EXPR,REGNO'
+ Use REGNO as the base register for all subsequent RX, RS, and SS
+ form instructions. The EXPR will be evaluated to obtain the base
+ address; usually, EXPR will merely be `*'.
+
+ This assembler allows two `.using' directives to be simultaneously
+ outstanding, one in the `.text' section, and one in another section
+ (typically, the `.data' section). This feature allows dynamically
+ loaded objects to be implemented in a relatively straightforward
+ way. A `.using' directive must always be specified in the `.text'
+ section; this will specify the base register that will be used for
+ branches in the `.text' section. A second `.using' may be
+ specified in another section; this will specify the base register
+ that is used for non-label address literals. When a second
+ `.using' is specified, then the subsequent `.ltorg' must be put in
+ the same section; otherwise an error will result.
+
+ Thus, for example, the following code uses `r3' to address branch
+ targets and `r4' to address the literal pool, which has been
+ written to the `.data' section. The is, the constants
+ `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
+ the `.data' section.
+
+ .data
+ .using LITPOOL,r4
+ .text
+ BASR r3,0
+ .using *,r3
+ B START
+ .long LITPOOL
+ START:
+ L r4,4(,r3)
+ L r15,=A(some_routine)
+ LTR r15,r15
+ BNE LABEL
+ AH r0,=H'42'
+ LABEL:
+ ME r6,=E'3.1416'
+ .data
+ LITPOOL:
+ .ltorg
+
+ Note that this dual-`.using' directive semantics extends and is
+ not compatible with HLASM semantics. Note that this assembler
+ directive does not support the full range of HLASM semantics.
+
+
+
+File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
+
+9.14.6 Opcodes
+--------------
+
+For detailed information on the ESA/390 machine instruction set, see
+`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
+
+
+File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
+
+9.15 80386 Dependent Features
+=============================
+
+ The i386 version `as' supports both the original Intel 386
+architecture in both 16 and 32-bit mode as well as AMD x86-64
+architecture extending the Intel architecture to 64-bits.
+
+* Menu:
+
+* i386-Options:: Options
+* i386-Directives:: X86 specific directives
+* i386-Syntax:: Syntactical considerations
+* i386-Mnemonics:: Instruction Naming
+* i386-Regs:: Register Naming
+* i386-Prefixes:: Instruction Prefixes
+* i386-Memory:: Memory References
+* i386-Jumps:: Handling of Jump Instructions
+* i386-Float:: Floating Point
+* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
+* i386-LWP:: AMD's Lightweight Profiling Instructions
+* i386-BMI:: Bit Manipulation Instruction
+* i386-TBM:: AMD's Trailing Bit Manipulation Instructions
+* i386-16bit:: Writing 16-bit Code
+* i386-Arch:: Specifying an x86 CPU architecture
+* i386-Bugs:: AT&T Syntax bugs
+* i386-Notes:: Notes
+
+
+File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent
+
+9.15.1 Options
+--------------
+
+The i386 version of `as' has a few machine dependent options:
+
+`--32 | --x32 | --64'
+ Select the word size, either 32 bits or 64 bits. `--32' implies
+ Intel i386 architecture, while `--x32' and `--64' imply AMD x86-64
+ architecture with 32-bit or 64-bit word-size respectively.
+
+ These options are only available with the ELF object file format,
+ and require that the necessary BFD support has been included (on a
+ 32-bit platform you have to add -enable-64-bit-bfd to configure
+ enable 64-bit usage and use x86-64 as target platform).
+
+`-n'
+ By default, x86 GAS replaces multiple nop instructions used for
+ alignment within code sections with multi-byte nop instructions
+ such as leal 0(%esi,1),%esi. This switch disables the
+ optimization.
+
+`--divide'
+ On SVR4-derived platforms, the character `/' is treated as a
+ comment character, which means that it cannot be used in
+ expressions. The `--divide' option turns `/' into a normal
+ character. This does not disable `/' at the beginning of a line
+ starting a comment, or affect using `#' for starting a comment.
+
+`-march=CPU[+EXTENSION...]'
+ This option specifies the target processor. The assembler will
+ issue an error message if an attempt is made to assemble an
+ instruction which will not execute on the target processor. The
+ following processor names are recognized: `i8086', `i186', `i286',
+ `i386', `i486', `i586', `i686', `pentium', `pentiumpro',
+ `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona',
+ `core', `core2', `corei7', `l1om', `k1om', `iamcu', `k6', `k6_2',
+ `athlon', `opteron', `k8', `amdfam10', `bdver1', `bdver2',
+ `bdver3', `bdver4', `znver1', `btver1', `btver2', `generic32' and
+ `generic64'.
+
+ In addition to the basic instruction set, the assembler can be
+ told to accept various extension mnemonics. For example,
+ `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
+ following extensions are currently supported: `8087', `287', `387',
+ `687', `no87', `no287', `no387', `no687', `mmx', `nommx', `sse',
+ `sse2', `sse3', `ssse3', `sse4.1', `sse4.2', `sse4', `nosse',
+ `nosse2', `nosse3', `nossse3', `nosse4.1', `nosse4.2', `nosse4',
+ `avx', `avx2', `noavx', `noavx2', `adx', `rdseed', `prfchw',
+ `smap', `mpx', `sha', `rdpid', `ptwrite', `prefetchwt1',
+ `clflushopt', `se1', `clwb', `avx512f', `avx512cd', `avx512er',
+ `avx512pf', `avx512vl', `avx512bw', `avx512dq', `avx512ifma',
+ `avx512vbmi', `avx512_4fmaps', `avx512_4vnniw', `avx512_vpopcntdq',
+ `noavx512f', `noavx512cd', `noavx512er', `noavx512pf',
+ `noavx512vl', `noavx512bw', `noavx512dq', `noavx512ifma',
+ `noavx512vbmi', `noavx512_4fmaps', `noavx512_4vnniw',
+ `noavx512_vpopcntdq', `vmx', `vmfunc', `smx', `xsave', `xsaveopt',
+ `xsavec', `xsaves', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c',
+ `bmi2', `fma', `movbe', `ept', `lzcnt', `hle', `rtm', `invpcid',
+ `clflush', `mwaitx', `clzero', `lwp', `fma4', `xop', `cx16',
+ `syscall', `rdtscp', `3dnow', `3dnowa', `sse4a', `sse5', `svme',
+ `abm' and `padlock'. Note that rather than extending a basic
+ instruction set, the extension mnemonics starting with `no' revoke
+ the respective functionality.
+
+ When the `.arch' directive is used with `-march', the `.arch'
+ directive will take precedent.
+
+`-mtune=CPU'
+ This option specifies a processor to optimize for. When used in
+ conjunction with the `-march' option, only instructions of the
+ processor specified by the `-march' option will be generated.
+
+ Valid CPU values are identical to the processor list of
+ `-march=CPU'.
+
+`-msse2avx'
+ This option specifies that the assembler should encode SSE
+ instructions with VEX prefix.
+
+`-msse-check=NONE'
+`-msse-check=WARNING'
+`-msse-check=ERROR'
+ These options control if the assembler should check SSE
+ instructions. `-msse-check=NONE' will make the assembler not to
+ check SSE instructions, which is the default.
+ `-msse-check=WARNING' will make the assembler issue a warning for
+ any SSE instruction. `-msse-check=ERROR' will make the assembler
+ issue an error for any SSE instruction.
+
+`-mavxscalar=128'
+`-mavxscalar=256'
+ These options control how the assembler should encode scalar AVX
+ instructions. `-mavxscalar=128' will encode scalar AVX
+ instructions with 128bit vector length, which is the default.
+ `-mavxscalar=256' will encode scalar AVX instructions with 256bit
+ vector length.
+
+`-mevexlig=128'
+`-mevexlig=256'
+`-mevexlig=512'
+ These options control how the assembler should encode
+ length-ignored (LIG) EVEX instructions. `-mevexlig=128' will
+ encode LIG EVEX instructions with 128bit vector length, which is
+ the default. `-mevexlig=256' and `-mevexlig=512' will encode LIG
+ EVEX instructions with 256bit and 512bit vector length,
+ respectively.
+
+`-mevexwig=0'
+`-mevexwig=1'
+ These options control how the assembler should encode w-ignored
+ (WIG) EVEX instructions. `-mevexwig=0' will encode WIG EVEX
+ instructions with evex.w = 0, which is the default. `-mevexwig=1'
+ will encode WIG EVEX instructions with evex.w = 1.
+
+`-mmnemonic=ATT'
+`-mmnemonic=INTEL'
+ This option specifies instruction mnemonic for matching
+ instructions. The `.att_mnemonic' and `.intel_mnemonic'
+ directives will take precedent.
+
+`-msyntax=ATT'
+`-msyntax=INTEL'
+ This option specifies instruction syntax when processing
+ instructions. The `.att_syntax' and `.intel_syntax' directives
+ will take precedent.
+
+`-mnaked-reg'
+ This opetion specifies that registers don't require a `%' prefix.
+ The `.att_syntax' and `.intel_syntax' directives will take
+ precedent.
+
+`-madd-bnd-prefix'
+ This option forces the assembler to add BND prefix to all
+ branches, even if such prefix was not explicitly specified in the
+ source code.
+
+`-mno-shared'
+ On ELF target, the assembler normally optimizes out non-PLT
+ relocations against defined non-weak global branch targets with
+ default visibility. The `-mshared' option tells the assembler to
+ generate code which may go into a shared library where all
+ non-weak global branch targets with default visibility can be
+ preempted. The resulting code is slightly bigger. This option
+ only affects the handling of branch instructions.
+
+`-mbig-obj'
+ On x86-64 PE/COFF target this option forces the use of big object
+ file format, which allows more than 32768 sections.
+
+`-momit-lock-prefix=NO'
+`-momit-lock-prefix=YES'
+ These options control how the assembler should encode lock prefix.
+ This option is intended as a workaround for processors, that fail
+ on lock prefix. This option can only be safely used with
+ single-core, single-thread computers `-momit-lock-prefix=YES' will
+ omit all lock prefixes. `-momit-lock-prefix=NO' will encode lock
+ prefix as usual, which is the default.
+
+`-mfence-as-lock-add=NO'
+`-mfence-as-lock-add=YES'
+ These options control how the assembler should encode lfence,
+ mfence and sfence. `-mfence-as-lock-add=YES' will encode lfence,
+ mfence and sfence as `lock addl $0x0, (%rsp)' in 64-bit mode and
+ `lock addl $0x0, (%esp)' in 32-bit mode. `-mfence-as-lock-add=NO'
+ will encode lfence, mfence and sfence as usual, which is the
+ default.
+
+`-mrelax-relocations=NO'
+`-mrelax-relocations=YES'
+ These options control whether the assembler should generate relax
+ relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
+ and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
+ `-mrelax-relocations=YES' will generate relax relocations.
+ `-mrelax-relocations=NO' will not generate relax relocations. The
+ default can be controlled by a configure option
+ `--enable-x86-relax-relocations'.
+
+`-mevexrcig=RNE'
+`-mevexrcig=RD'
+`-mevexrcig=RU'
+`-mevexrcig=RZ'
+ These options control how the assembler should encode SAE-only
+ EVEX instructions. `-mevexrcig=RNE' will encode RC bits of EVEX
+ instruction with 00, which is the default. `-mevexrcig=RD',
+ `-mevexrcig=RU' and `-mevexrcig=RZ' will encode SAE-only EVEX
+ instructions with 01, 10 and 11 RC bits, respectively.
+
+`-mamd64'
+`-mintel64'
+ This option specifies that the assembler should accept only AMD64
+ or Intel64 ISA in 64-bit mode. The default is to accept both.
+
+
+
+File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent
+
+9.15.2 x86 specific Directives
+------------------------------
+
+`.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
+ Reserve LENGTH (an absolute expression) bytes for a local common
+ denoted by SYMBOL. The section and value of SYMBOL are those of
+ the new local common. The addresses are allocated in the bss
+ section, so that at run-time the bytes start off zeroed. Since
+ SYMBOL is not declared global, it is normally not visible to `ld'.
+ The optional third parameter, ALIGNMENT, specifies the desired
+ alignment of the symbol in the bss section.
+
+ This directive is only available for COFF based x86 targets.
+
+
+
+File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent
+
+9.15.3 i386 Syntactical Considerations
+--------------------------------------
+
+* Menu:
+
+* i386-Variations:: AT&T Syntax versus Intel Syntax
+* i386-Chars:: Special Characters
+
+
+File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax
+
+9.15.3.1 AT&T Syntax versus Intel Syntax
+........................................
+
+`as' now supports assembly using Intel assembler syntax.
+`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
+the usual AT&T mode for compatibility with the output of `gcc'. Either
+of these directives may have an optional argument, `prefix', or
+`noprefix' specifying whether registers require a `%' prefix. AT&T
+System V/386 assembler syntax is quite different from Intel syntax. We
+mention these differences because almost all 80386 documents use Intel
+syntax. Notable differences between the two syntaxes are:
+
+ * AT&T immediate operands are preceded by `$'; Intel immediate
+ operands are undelimited (Intel `push 4' is AT&T `pushl $4').
+ AT&T register operands are preceded by `%'; Intel register operands
+ are undelimited. AT&T absolute (as opposed to PC relative)
+ jump/call operands are prefixed by `*'; they are undelimited in
+ Intel syntax.
+
+ * AT&T and Intel syntax use the opposite order for source and
+ destination operands. Intel `add eax, 4' is `addl $4, %eax'. The
+ `source, dest' convention is maintained for compatibility with
+ previous Unix assemblers. Note that `bound', `invlpga', and
+ instructions with 2 immediate operands, such as the `enter'
+ instruction, do _not_ have reversed order. *Note i386-Bugs::.
+
+ * In AT&T syntax the size of memory operands is determined from the
+ last character of the instruction mnemonic. Mnemonic suffixes of
+ `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
+ (32-bit) and quadruple word (64-bit) memory references. Intel
+ syntax accomplishes this by prefixing memory operands (_not_ the
+ instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
+ and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
+ %al' in AT&T syntax.
+
+ In 64-bit code, `movabs' can be used to encode the `mov'
+ instruction with the 64-bit displacement or immediate operand.
+
+ * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
+ $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
+ SECTION:OFFSET'. Also, the far return instruction is `lret
+ $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
+ STACK-ADJUST'.
+
+ * The AT&T assembler does not provide support for multiple section
+ programs. Unix style systems expect all programs to be single
+ sections.
+
+
+File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax
+
+9.15.3.2 Special Characters
+...........................
+
+The presence of a `#' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ If the `--divide' command line option has not been specified then
+the `/' character appearing anywhere on a line also introduces a line
+comment.
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
+
+9.15.4 i386-Mnemonics
+---------------------
+
+9.15.4.1 Instruction Naming
+...........................
+
+Instruction mnemonics are suffixed with one character modifiers which
+specify the size of operands. The letters `b', `w', `l' and `q'
+specify byte, word, long and quadruple word operands. If no suffix is
+specified by an instruction then `as' tries to fill in the missing
+suffix based on the destination register operand (the last one by
+convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
+also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is
+incompatible with the AT&T Unix assembler which assumes that a missing
+mnemonic suffix implies long operand size. (This incompatibility does
+not affect compiler output since compilers always explicitly specify
+the mnemonic suffix.)
+
+ Almost all instructions have the same names in AT&T and Intel format.
+There are a few exceptions. The sign extend and zero extend
+instructions need two sizes to specify them. They need a size to
+sign/zero extend _from_ and a size to zero extend _to_. This is
+accomplished by using two instruction mnemonic suffixes in AT&T syntax.
+Base names for sign extend and zero extend are `movs...' and `movz...'
+in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction
+mnemonic suffixes are tacked on to this base name, the _from_ suffix
+before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for
+"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are
+`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
+long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
+word), and `lq' (from long to quadruple word).
+
+ Different encoding options can be specified via optional mnemonic
+suffix. `.s' suffix swaps 2 register operands in encoding when moving
+from one register to another. `.d8' or `.d32' suffix prefers 8bit or
+32bit displacement in encoding.
+
+ The Intel-syntax conversion instructions
+
+ * `cbw' -- sign-extend byte in `%al' to word in `%ax',
+
+ * `cwde' -- sign-extend word in `%ax' to long in `%eax',
+
+ * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
+
+ * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
+
+ * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
+ only),
+
+ * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
+ (x86-64 only),
+
+are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
+naming. `as' accepts either naming for these instructions.
+
+ Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
+but are `call far' and `jump far' in Intel convention.
+
+9.15.4.2 AT&T Mnemonic versus Intel Mnemonic
+............................................
+
+`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects
+Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to
+the usual AT&T mnemonic with AT&T syntax for compatibility with the
+output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp',
+`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are
+implemented in AT&T System V/386 assembler with different mnemonics
+from those in Intel IA32 specification. `gcc' generates those
+instructions with AT&T mnemonic.
+
+
+File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
+
+9.15.5 Register Naming
+----------------------
+
+Register operands are always prefixed with `%'. The 80386 registers
+consist of
+
+ * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
+ `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
+ (the stack pointer).
+
+ * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
+ `%si', `%bp', and `%sp'.
+
+ * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
+ `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
+ `%bx', `%cx', and `%dx')
+
+ * the 6 section registers `%cs' (code section), `%ds' (data
+ section), `%ss' (stack section), `%es', `%fs', and `%gs'.
+
+ * the 5 processor control registers `%cr0', `%cr2', `%cr3', `%cr4',
+ and `%cr8'.
+
+ * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
+ `%db7'.
+
+ * the 2 test registers `%tr6' and `%tr7'.
+
+ * the 8 floating point register stack `%st' or equivalently
+ `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
+ `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX
+ registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
+ and `%mm7'.
+
+ * the 8 128-bit SSE registers registers `%xmm0', `%xmm1', `%xmm2',
+ `%xmm3', `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
+
+ The AMD x86-64 architecture extends the register set by:
+
+ * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
+ accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
+ frame pointer), `%rsp' (the stack pointer)
+
+ * the 8 extended registers `%r8'-`%r15'.
+
+ * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'.
+
+ * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'.
+
+ * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'.
+
+ * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
+
+ * the 8 debug registers: `%db8'-`%db15'.
+
+ * the 8 128-bit SSE registers: `%xmm8'-`%xmm15'.
+
+ With the AVX extensions more registers were made available:
+
+ * the 16 256-bit SSE `%ymm0'-`%ymm15' (only the first 8 available in
+ 32-bit mode). The bottom 128 bits are overlaid with the
+ `xmm0'-`xmm15' registers.
+
+
+ The AVX2 extensions made in 64-bit mode more registers available:
+
+ * the 16 128-bit registers `%xmm16'-`%xmm31' and the 16 256-bit
+ registers `%ymm16'-`%ymm31'.
+
+
+ The AVX512 extensions added the following registers:
+
+ * the 32 512-bit registers `%zmm0'-`%zmm31' (only the first 8
+ available in 32-bit mode). The bottom 128 bits are overlaid with
+ the `%xmm0'-`%xmm31' registers and the first 256 bits are overlaid
+ with the `%ymm0'-`%ymm31' registers.
+
+ * the 8 mask registers `%k0'-`%k7'.
+
+
+
+File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
+
+9.15.6 Instruction Prefixes
+---------------------------
+
+Instruction prefixes are used to modify the following instruction. They
+are used to repeat string instructions, to provide section overrides, to
+perform bus lock operations, and to change operand and address sizes.
+(Most instructions that normally operate on 32-bit operands will use
+16-bit operands if the instruction has an "operand size" prefix.)
+Instruction prefixes are best written on the same line as the
+instruction they act upon. For example, the `scas' (scan string)
+instruction is repeated with:
+
+ repne scas %es:(%edi),%al
+
+ You may also place prefixes on the lines immediately preceding the
+instruction, but this circumvents checks that `as' does with prefixes,
+and will not work with all prefixes.
+
+ Here is a list of instruction prefixes:
+
+ * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
+ These are automatically added by specifying using the
+ SECTION:MEMORY-OPERAND form for memory references.
+
+ * Operand/Address size prefixes `data16' and `addr16' change 32-bit
+ operands/addresses into 16-bit operands/addresses, while `data32'
+ and `addr32' change 16-bit ones (in a `.code16' section) into
+ 32-bit operands/addresses. These prefixes _must_ appear on the
+ same line of code as the instruction they modify. For example, in
+ a 16-bit `.code16' section, you might write:
+
+ addr32 jmpl *(%ebx)
+
+ * The bus lock prefix `lock' inhibits interrupts during execution of
+ the instruction it precedes. (This is only valid with certain
+ instructions; see a 80386 manual for details).
+
+ * The wait for coprocessor prefix `wait' waits for the coprocessor to
+ complete the current instruction. This should never be needed for
+ the 80386/80387 combination.
+
+ * The `rep', `repe', and `repne' prefixes are added to string
+ instructions to make them repeat `%ecx' times (`%cx' times if the
+ current address size is 16-bits).
+
+ * The `rex' family of prefixes is used by x86-64 to encode
+ extensions to i386 instruction set. The `rex' prefix has four
+ bits -- an operand size overwrite (`64') used to change operand
+ size from 32-bit to 64-bit and X, Y and Z extensions bits used to
+ extend the register set.
+
+ You may write the `rex' prefixes directly. The `rex64xyz'
+ instruction emits `rex' prefix with all the bits set. By omitting
+ the `64', `x', `y' or `z' you may write other prefixes as well.
+ Normally, there is no need to write the prefixes explicitly, since
+ gas will automatically generate them based on the instruction
+ operands.
+
+
+File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
+
+9.15.7 Memory References
+------------------------
+
+An Intel syntax indirect memory reference of the form
+
+ SECTION:[BASE + INDEX*SCALE + DISP]
+
+is translated into the AT&T syntax
+
+ SECTION:DISP(BASE, INDEX, SCALE)
+
+where BASE and INDEX are the optional 32-bit base and index registers,
+DISP is the optional displacement, and SCALE, taking the values 1, 2,
+4, and 8, multiplies INDEX to calculate the address of the operand. If
+no SCALE is specified, SCALE is taken to be 1. SECTION specifies the
+optional section register for the memory operand, and may override the
+default section register (see a 80386 manual for section register
+defaults). Note that section overrides in AT&T syntax _must_ be
+preceded by a `%'. If you specify a section override which coincides
+with the default section register, `as' does _not_ output any section
+register override prefixes to assemble the given instruction. Thus,
+section overrides can be specified to emphasize which section register
+is used for a given memory operand.
+
+ Here are some examples of Intel and AT&T style memory references:
+
+AT&T: `-4(%ebp)', Intel: `[ebp - 4]'
+ BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
+ section is used (`%ss' for addressing with `%ebp' as the base
+ register). INDEX, SCALE are both missing.
+
+AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
+ INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other
+ fields are missing. The section register here defaults to `%ds'.
+
+AT&T: `foo(,1)'; Intel `[foo]'
+ This uses the value pointed to by `foo' as a memory operand. Note
+ that BASE and INDEX are both missing, but there is only _one_ `,'.
+ This is a syntactic exception.
+
+AT&T: `%gs:foo'; Intel `gs:foo'
+ This selects the contents of the variable `foo' with section
+ register SECTION being `%gs'.
+
+ Absolute (as opposed to PC relative) call and jump operands must be
+prefixed with `*'. If no `*' is specified, `as' always chooses PC
+relative addressing for jump/call labels.
+
+ Any instruction that has a memory operand, but no register operand,
+_must_ specify its size (byte, word, long, or quadruple) with an
+instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
+
+ The x86-64 architecture adds an RIP (instruction pointer relative)
+addressing. This addressing mode is specified by using `rip' as a base
+register. Only constant offsets are valid. For example:
+
+AT&T: `1234(%rip)', Intel: `[rip + 1234]'
+ Points to the address 1234 bytes past the end of the current
+ instruction.
+
+AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
+ Points to the `symbol' in RIP relative way, this is shorter than
+ the default absolute addressing.
+
+ Other addressing modes remain unchanged in x86-64 architecture,
+except registers used are 64-bit instead of 32-bit.
+
+
+File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
+
+9.15.8 Handling of Jump Instructions
+------------------------------------
+
+Jump instructions are always optimized to use the smallest possible
+displacements. This is accomplished by using byte (8-bit) displacement
+jumps whenever the target is sufficiently close. If a byte displacement
+is insufficient a long displacement is used. We do not support word
+(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
+instruction with the `data16' instruction prefix), since the 80386
+insists upon masking `%eip' to 16 bits after the word displacement is
+added. (See also *note i386-Arch::)
+
+ Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
+and `loopne' instructions only come in byte displacements, so that if
+you use these instructions (`gcc' does not use them) you may get an
+error message (and incorrect code). The AT&T 80386 assembler tries to
+get around this problem by expanding `jcxz foo' to
+
+ jcxz cx_zero
+ jmp cx_nonzero
+ cx_zero: jmp foo
+ cx_nonzero:
+
+
+File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
+
+9.15.9 Floating Point
+---------------------
+
+All 80387 floating point types except packed BCD are supported. (BCD
+support may be added without much difficulty). These data types are
+16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
+and extended (80-bit) precision floating point. Each supported type
+has an instruction mnemonic suffix and a constructor associated with
+it. Instruction mnemonic suffixes specify the operand's data type.
+Constructors build these data types into memory.
+
+ * Floating point constructors are `.float' or `.single', `.double',
+ and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond
+ to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
+ 80-bit (ten byte) real. The 80387 only supports this format via
+ the `fldt' (load 80-bit real to stack top) and `fstpt' (store
+ 80-bit real and pop stack) instructions.
+
+ * Integer constructors are `.word', `.long' or `.int', and `.quad'
+ for the 16-, 32-, and 64-bit integer formats. The corresponding
+ instruction mnemonic suffixes are `s' (single), `l' (long), and
+ `q' (quad). As with the 80-bit real format, the 64-bit `q' format
+ is only present in the `fildq' (load quad integer to stack top)
+ and `fistpq' (store quad integer and pop stack) instructions.
+
+ Register to register operations should not use instruction mnemonic
+suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as
+if you wrote `fst %st, %st(1)', since all register to register
+operations use 80-bit floating point operands. (Contrast this with
+`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
+point format, then stores the result in the 4 byte location `mem')
+
+
+File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent
+
+9.15.10 Intel's MMX and AMD's 3DNow! SIMD Operations
+----------------------------------------------------
+
+`as' supports Intel's MMX instruction set (SIMD instructions for
+integer data), available on Intel's Pentium MMX processors and Pentium
+II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
+probably others. It also supports AMD's 3DNow! instruction set (SIMD
+instructions for 32-bit floating point data) available on AMD's K6-2
+processor and possibly others in the future.
+
+ Currently, `as' does not support Intel's floating point SIMD, Katmai
+(KNI).
+
+ The eight 64-bit MMX operands, also used by 3DNow!, are called
+`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four
+16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
+floating point values. The MMX registers cannot be used at the same
+time as the floating point stack.
+
+ See Intel and AMD documentation, keeping in mind that the operand
+order in instructions is reversed from the Intel syntax.
+
+
+File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent
+
+9.15.11 AMD's Lightweight Profiling Instructions
+------------------------------------------------
+
+`as' supports AMD's Lightweight Profiling (LWP) instruction set,
+available on AMD's Family 15h (Orochi) processors.
+
+ LWP enables applications to collect and manage performance data, and
+react to performance events. The collection of performance data
+requires no context switches. LWP runs in the context of a thread and
+so several counters can be used independently across multiple threads.
+LWP can be used in both 64-bit and legacy 32-bit modes.
+
+ For detailed information on the LWP instruction set, see the `AMD
+Lightweight Profiling Specification' available at Lightweight Profiling
+Specification (http://developer.amd.com/cpu/LWP).
+
+
+File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent
+
+9.15.12 Bit Manipulation Instructions
+-------------------------------------
+
+`as' supports the Bit Manipulation (BMI) instruction set.
+
+ BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.
+
+
+File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent
+
+9.15.13 AMD's Trailing Bit Manipulation Instructions
+----------------------------------------------------
+
+`as' supports AMD's Trailing Bit Manipulation (TBM) instruction set,
+available on AMD's BDVER2 processors (Trinity and Viperfish).
+
+ TBM instructions provide instructions implementing individual bit
+manipulation operations such as isolating, masking, setting, resetting,
+complementing, and operations on trailing zeros and ones.
+
+
+File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent
+
+9.15.14 Writing 16-bit Code
+---------------------------
+
+While `as' normally writes only "pure" 32-bit i386 code or 64-bit
+x86-64 code depending on the default configuration, it also supports
+writing code to run in real mode or in 16-bit protected mode code
+segments. To do this, put a `.code16' or `.code16gcc' directive before
+the assembly language instructions to be run in 16-bit mode. You can
+switch `as' to writing 32-bit code with the `.code32' directive or
+64-bit code with the `.code64' directive.
+
+ `.code16gcc' provides experimental support for generating 16-bit
+code from gcc, and differs from `.code16' in that `call', `ret',
+`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
+instructions default to 32-bit size. This is so that the stack pointer
+is manipulated in the same way over function calls, allowing access to
+function parameters at the same stack offsets as in 32-bit mode.
+`.code16gcc' also automatically adds address size prefixes where
+necessary to use the 32-bit addressing modes that gcc generates.
+
+ The code which `as' generates in 16-bit mode will not necessarily
+run on a 16-bit pre-80386 processor. To write code that runs on such a
+processor, you must refrain from using _any_ 32-bit constructs which
+require `as' to output address or operand size prefixes.
+
+ Note that writing 16-bit code instructions by explicitly specifying a
+prefix or an instruction mnemonic suffix within a 32-bit code section
+generates different machine instructions than those generated for a
+16-bit code segment. In a 32-bit code section, the following code
+generates the machine opcode bytes `66 6a 04', which pushes the value
+`4' onto the stack, decrementing `%esp' by 2.
+
+ pushw $4
+
+ The same code in a 16-bit code section would generate the machine
+opcode bytes `6a 04' (i.e., without the operand size prefix), which is
+correct since the processor default operand size is assumed to be 16
+bits in a 16-bit code section.
+
+
+File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent
+
+9.15.15 Specifying CPU Architecture
+-----------------------------------
+
+`as' may be told to assemble for a particular CPU (sub-)architecture
+with the `.arch CPU_TYPE' directive. This directive enables a warning
+when gas detects an instruction that is not supported on the CPU
+specified. The choices for CPU_TYPE are:
+
+`i8086' `i186' `i286' `i386'
+`i486' `i586' `i686' `pentium'
+`pentiumpro' `pentiumii' `pentiumiii' `pentium4'
+`prescott' `nocona' `core' `core2'
+`corei7' `l1om' `k1om' `iamcu'
+`k6' `k6_2' `athlon' `k8'
+`amdfam10' `bdver1' `bdver2' `bdver3'
+`bdver4' `znver1' `btver1' `btver2'
+`generic32' `generic64'
+`.mmx' `.sse' `.sse2' `.sse3'
+`.ssse3' `.sse4.1' `.sse4.2' `.sse4'
+`.avx' `.vmx' `.smx' `.ept'
+`.clflush' `.movbe' `.xsave' `.xsaveopt'
+`.aes' `.pclmul' `.fma' `.fsgsbase'
+`.rdrnd' `.f16c' `.avx2' `.bmi2'
+`.lzcnt' `.invpcid' `.vmfunc' `.hle'
+`.rtm' `.adx' `.rdseed' `.prfchw'
+`.smap' `.mpx' `.sha' `.prefetchwt1'
+`.clflushopt' `.xsavec' `.xsaves' `.se1'
+`.avx512f' `.avx512cd' `.avx512er' `.avx512pf'
+`.avx512vl' `.avx512bw' `.avx512dq' `.avx512ifma'
+`.avx512vbmi' `.avx512_4fmaps'`.avx512_4vnniw'
+`.avx512_vpopcntdq'`.clwb' `.rdpid' `.ptwrite'
+`.3dnow' `.3dnowa' `.sse4a' `.sse5'
+`.syscall' `.rdtscp' `.svme' `.abm'
+`.lwp' `.fma4' `.xop' `.cx16'
+`.padlock' `.clzero' `.mwaitx'
+
+ Apart from the warning, there are only two other effects on `as'
+operation; Firstly, if you specify a CPU other than `i486', then shift
+by one instructions such as `sarl $1, %eax' will automatically use a
+two byte opcode sequence. The larger three byte opcode sequence is
+used on the 486 (and when no architecture is specified) because it
+executes faster on the 486. Note that you can explicitly request the
+two byte opcode by writing `sarl %eax'. Secondly, if you specify
+`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
+offset conditional jumps will be promoted when necessary to a two
+instruction sequence consisting of a conditional jump of the opposite
+sense around an unconditional jump to the target.
+
+ Following the CPU architecture (but not a sub-architecture, which
+are those starting with a dot), you may specify `jumps' or `nojumps' to
+control automatic promotion of conditional jumps. `jumps' is the
+default, and enables jump promotion; All external jumps will be of the
+long variety, and file-local jumps will be promoted as necessary.
+(*note i386-Jumps::) `nojumps' leaves external conditional jumps as
+byte offset jumps, and warns about file-local conditional jumps that
+`as' promotes. Unconditional jumps are treated as for `jumps'.
+
+ For example
+
+ .arch i8086,nojumps
+
+
+File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
+
+9.15.16 AT&T Syntax bugs
+------------------------
+
+The UnixWare assembler, and probably other AT&T derived ix86 Unix
+assemblers, generate floating point instructions with reversed source
+and destination registers in certain cases. Unfortunately, gcc and
+possibly many other programs use this reversed syntax, so we're stuck
+with it.
+
+ For example
+
+ fsub %st,%st(3)
+ results in `%st(3)' being updated to `%st - %st(3)' rather than the
+expected `%st(3) - %st'. This happens with all the non-commutative
+arithmetic floating point operations with two register operands where
+the source register is `%st' and the destination register is `%st(i)'.
+
+
+File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
+
+9.15.17 Notes
+-------------
+
+There is some trickery concerning the `mul' and `imul' instructions
+that deserves mention. The 16-, 32-, 64- and 128-bit expanding
+multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
+can be output only in the one operand form. Thus, `imul %ebx, %eax'
+does _not_ select the expanding multiply; the expanding multiply would
+clobber the `%edx' register, and this would confuse `gcc' output. Use
+`imul %ebx' to get the 64-bit product in `%edx:%eax'.
+
+ We have added a two operand form of `imul' when the first operand is
+an immediate mode expression and the second operand is a register.
+This is just a shorthand, so that, multiplying `%eax' by 69, for
+example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
+%eax'.
+
+
+File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
+
+9.16 Intel i860 Dependent Features
+==================================
+
+* Menu:
+
+* Notes-i860:: i860 Notes
+* Options-i860:: i860 Command-line Options
+* Directives-i860:: i860 Machine Directives
+* Opcodes for i860:: i860 Opcodes
+* Syntax of i860:: i860 Syntax
+
+
+File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
+
+9.16.1 i860 Notes
+-----------------
+
+This is a fairly complete i860 assembler which is compatible with the
+UNIX System V/860 Release 4 assembler. However, it does not currently
+support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
+
+ Like the SVR4/860 assembler, the output object format is ELF32.
+Currently, this is the only supported object format. If there is
+sufficient interest, other formats such as COFF may be implemented.
+
+ Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
+being the default. One difference is that AT&T syntax requires the '%'
+prefix on register names while Intel syntax does not. Another
+difference is in the specification of relocatable expressions. The
+Intel syntax is `ha%expression' whereas the SVR4 syntax is
+`[expression]@ha' (and similarly for the "l" and "h" selectors).
+
+
+File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
+
+9.16.2 i860 Command-line Options
+--------------------------------
+
+9.16.2.1 SVR4 compatibility options
+...................................
+
+`-V'
+ Print assembler version.
+
+`-Qy'
+ Ignored.
+
+`-Qn'
+ Ignored.
+
+9.16.2.2 Other options
+......................
+
+`-EL'
+ Select little endian output (this is the default).
+
+`-EB'
+ Select big endian output. Note that the i860 always reads
+ instructions as little endian data, so this option only effects
+ data and not instructions.
+
+`-mwarn-expand'
+ Emit a warning message if any pseudo-instruction expansions
+ occurred. For example, a `or' instruction with an immediate
+ larger than 16-bits will be expanded into two instructions. This
+ is a very undesirable feature to rely on, so this flag can help
+ detect any code where it happens. One use of it, for instance, has
+ been to find and eliminate any place where `gcc' may emit these
+ pseudo-instructions.
+
+`-mxp'
+ Enable support for the i860XP instructions and control registers.
+ By default, this option is disabled so that only the base
+ instruction set (i.e., i860XR) is supported.
+
+`-mintel-syntax'
+ The i860 assembler defaults to AT&T/SVR4 syntax. This option
+ enables the Intel syntax.
+
+
+File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
+
+9.16.3 i860 Machine Directives
+------------------------------
+
+`.dual'
+ Enter dual instruction mode. While this directive is supported, the
+ preferred way to use dual instruction mode is to explicitly code
+ the dual bit with the `d.' prefix.
+
+`.enddual'
+ Exit dual instruction mode. While this directive is supported, the
+ preferred way to use dual instruction mode is to explicitly code
+ the dual bit with the `d.' prefix.
+
+`.atmp'
+ Change the temporary register used when expanding pseudo
+ operations. The default register is `r31'.
+
+ The `.dual', `.enddual', and `.atmp' directives are available only
+in the Intel syntax mode.
+
+ Both syntaxes allow for the standard `.align' directive. However,
+the Intel syntax additionally allows keywords for the alignment
+parameter: "`.align type'", where `type' is one of `.short', `.long',
+`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4,
+and 8, respectively.
+
+
+File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent
+
+9.16.4 i860 Opcodes
+-------------------
+
+All of the Intel i860XR and i860XP machine instructions are supported.
+Please see either _i860 Microprocessor Programmer's Reference Manual_
+or _i860 Microprocessor Architecture_ for more information.
+
+9.16.4.1 Other instruction support (pseudo-instructions)
+........................................................
+
+For compatibility with some other i860 assemblers, a number of
+pseudo-instructions are supported. While these are supported, they are
+a very undesirable feature that should be avoided - in particular, when
+they result in an expansion to multiple actual i860 instructions. Below
+are the pseudo-instructions that result in expansions.
+ * Load large immediate into general register:
+
+ The pseudo-instruction `mov imm,%rn' (where the immediate does not
+ fit within a signed 16-bit field) will be expanded into:
+ orh large_imm@h,%r0,%rn
+ or large_imm@l,%rn,%rn
+
+ * Load/store with relocatable address expression:
+
+ For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will
+ be expanded into:
+ orh addr_exp@ha,%rx,%r31
+ ld.l addr_exp@l(%r31),%rn
+
+ The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
+ fst.x', and `pst.x' as well.
+
+ * Signed large immediate with add/subtract:
+
+ If any of the arithmetic operations `adds, addu, subs, subu' are
+ used with an immediate larger than 16-bits (signed), then they
+ will be expanded. For instance, the pseudo-instruction `adds
+ large_imm,%rx,%rn' expands to:
+ orh large_imm@h,%r0,%r31
+ or large_imm@l,%r31,%r31
+ adds %r31,%rx,%rn
+
+ * Unsigned large immediate with logical operations:
+
+ Logical operations (`or, andnot, or, xor') also result in
+ expansions. The pseudo-instruction `or large_imm,%rx,%rn' results
+ in:
+ orh large_imm@h,%rx,%r31
+ or large_imm@l,%r31,%rn
+
+ Similarly for the others, except for `and' which expands to:
+ andnot (-1 - large_imm)@h,%rx,%r31
+ andnot (-1 - large_imm)@l,%r31,%rn
+
+
+File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent
+
+9.16.5 i860 Syntax
+------------------
+
+* Menu:
+
+* i860-Chars:: Special Characters
+
+
+File: as.info, Node: i860-Chars, Up: Syntax of i860
+
+9.16.5.1 Special Characters
+...........................
+
+The presence of a `#' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
+
+9.17 Intel 80960 Dependent Features
+===================================
+
+* Menu:
+
+* Options-i960:: i960 Command-line Options
+* Floating Point-i960:: Floating Point
+* Directives-i960:: i960 Machine Directives
+* Opcodes for i960:: i960 Opcodes
+* Syntax of i960:: i960 Syntax
+
+
+File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
+
+9.17.1 i960 Command-line Options
+--------------------------------
+
+`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
+ Select the 80960 architecture. Instructions or features not
+ supported by the selected architecture cause fatal errors.
+
+ `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
+ Synonyms are provided for compatibility with other tools.
+
+ If you do not specify any of these options, `as' generates code
+ for any instruction or feature that is supported by _some_ version
+ of the 960 (even if this means mixing architectures!). In
+ principle, `as' attempts to deduce the minimal sufficient
+ processor type if none is specified; depending on the object code
+ format, the processor type may be recorded in the object file. If
+ it is critical that the `as' output match a specific architecture,
+ specify that architecture explicitly.
+
+`-b'
+ Add code to collect information about conditional branches taken,
+ for later optimization using branch prediction bits. (The
+ conditional branch instructions have branch prediction bits in the
+ CA, CB, and CC architectures.) If BR represents a conditional
+ branch instruction, the following represents the code generated by
+ the assembler when `-b' is specified:
+
+ call INCREMENT ROUTINE
+ .word 0 # pre-counter
+ Label: BR
+ call INCREMENT ROUTINE
+ .word 0 # post-counter
+
+ The counter following a branch records the number of times that
+ branch was _not_ taken; the difference between the two counters is
+ the number of times the branch _was_ taken.
+
+ A table of every such `Label' is also generated, so that the
+ external postprocessor `gbr960' (supplied by Intel) can locate all
+ the counters. This table is always labeled `__BRANCH_TABLE__';
+ this is a local symbol to permit collecting statistics for many
+ separate object files. The table is word aligned, and begins with
+ a two-word header. The first word, initialized to 0, is used in
+ maintaining linked lists of branch tables. The second word is a
+ count of the number of entries in the table, which follow
+ immediately: each is a word, pointing to one of the labels
+ illustrated above.
+
+ +------------+------------+------------+ ... +------------+
+ | | | | | |
+ | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
+ | | | | | |
+ +------------+------------+------------+ ... +------------+
+
+ __BRANCH_TABLE__ layout
+
+ The first word of the header is used to locate multiple branch
+ tables, since each object file may contain one. Normally the links
+ are maintained with a call to an initialization routine, placed at
+ the beginning of each function in the file. The GNU C compiler
+ generates these calls automatically when you give it a `-b' option.
+ For further details, see the documentation of `gbr960'.
+
+`-no-relax'
+ Normally, Compare-and-Branch instructions with targets that require
+ displacements greater than 13 bits (or that have external targets)
+ are replaced with the corresponding compare (or `chkbit') and
+ branch instructions. You can use the `-no-relax' option to
+ specify that `as' should generate errors instead, if the target
+ displacement is larger than 13 bits.
+
+ This option does not affect the Compare-and-Jump instructions; the
+ code emitted for them is _always_ adjusted when necessary
+ (depending on displacement size), regardless of whether you use
+ `-no-relax'.
+
+
+File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
+
+9.17.2 Floating Point
+---------------------
+
+`as' generates IEEE floating-point numbers for the directives `.float',
+`.double', `.extended', and `.single'.
+
+
+File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent
+
+9.17.3 i960 Machine Directives
+------------------------------
+
+`.bss SYMBOL, LENGTH, ALIGN'
+ Reserve LENGTH bytes in the bss section for a local SYMBOL,
+ aligned to the power of two specified by ALIGN. LENGTH and ALIGN
+ must be positive absolute expressions. This directive differs
+ from `.lcomm' only in that it permits you to specify an alignment.
+ *Note `.lcomm': Lcomm.
+
+`.extended FLONUMS'
+ `.extended' expects zero or more flonums, separated by commas; for
+ each flonum, `.extended' emits an IEEE extended-format (80-bit)
+ floating-point number.
+
+`.leafproc CALL-LAB, BAL-LAB'
+ You can use the `.leafproc' directive in conjunction with the
+ optimized `callj' instruction to enable faster calls of leaf
+ procedures. If a procedure is known to call no other procedures,
+ you may define an entry point that skips procedure prolog code
+ (and that does not depend on system-supplied saved context), and
+ declare it as the BAL-LAB using `.leafproc'. If the procedure
+ also has an entry point that goes through the normal prolog, you
+ can specify that entry point as CALL-LAB.
+
+ A `.leafproc' declaration is meant for use in conjunction with the
+ optimized call instruction `callj'; the directive records the data
+ needed later to choose between converting the `callj' into a `bal'
+ or a `call'.
+
+ CALL-LAB is optional; if only one argument is present, or if the
+ two arguments are identical, the single argument is assumed to be
+ the `bal' entry point.
+
+`.sysproc NAME, INDEX'
+ The `.sysproc' directive defines a name for a system procedure.
+ After you define it using `.sysproc', you can use NAME to refer to
+ the system procedure identified by INDEX when calling procedures
+ with the optimized call instruction `callj'.
+
+ Both arguments are required; INDEX must be between 0 and 31
+ (inclusive).
+
+
+File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent
+
+9.17.4 i960 Opcodes
+-------------------
+
+All Intel 960 machine instructions are supported; *note i960
+Command-line Options: Options-i960. for a discussion of selecting the
+instruction subset for a particular 960 architecture.
+
+ Some opcodes are processed beyond simply emitting a single
+corresponding instruction: `callj', and Compare-and-Branch or
+Compare-and-Jump instructions with target displacements larger than 13
+bits.
+
+* Menu:
+
+* callj-i960:: `callj'
+* Compare-and-branch-i960:: Compare-and-Branch
+
+
+File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960
+
+9.17.4.1 `callj'
+................
+
+You can write `callj' to have the assembler or the linker determine the
+most appropriate form of subroutine call: `call', `bal', or `calls'.
+If the assembly source contains enough information--a `.leafproc' or
+`.sysproc' directive defining the operand--then `as' translates the
+`callj'; if not, it simply emits the `callj', leaving it for the linker
+to resolve.
+
+
+File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
+
+9.17.4.2 Compare-and-Branch
+...........................
+
+The 960 architectures provide combined Compare-and-Branch instructions
+that permit you to store the branch target in the lower 13 bits of the
+instruction word itself. However, if you specify a branch target far
+enough away that its address won't fit in 13 bits, the assembler can
+either issue an error, or convert your Compare-and-Branch instruction
+into separate instructions to do the compare and the branch.
+
+ Whether `as' gives an error or expands the instruction depends on
+two choices you can make: whether you use the `-no-relax' option, and
+whether you use a "Compare and Branch" instruction or a "Compare and
+Jump" instruction. The "Jump" instructions are _always_ expanded if
+necessary; the "Branch" instructions are expanded when necessary
+_unless_ you specify `-no-relax'--in which case `as' gives an error
+instead.
+
+ These are the Compare-and-Branch instructions, their "Jump" variants,
+and the instruction pairs they may expand into:
+
+ Compare and
+ Branch Jump Expanded to
+ ------ ------ ------------
+ bbc chkbit; bno
+ bbs chkbit; bo
+ cmpibe cmpije cmpi; be
+ cmpibg cmpijg cmpi; bg
+ cmpibge cmpijge cmpi; bge
+ cmpibl cmpijl cmpi; bl
+ cmpible cmpijle cmpi; ble
+ cmpibno cmpijno cmpi; bno
+ cmpibne cmpijne cmpi; bne
+ cmpibo cmpijo cmpi; bo
+ cmpobe cmpoje cmpo; be
+ cmpobg cmpojg cmpo; bg
+ cmpobge cmpojge cmpo; bge
+ cmpobl cmpojl cmpo; bl
+ cmpoble cmpojle cmpo; ble
+ cmpobne cmpojne cmpo; bne
+
+
+File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent
+
+9.17.5 Syntax for the i960
+--------------------------
+
+* Menu:
+
+* i960-Chars:: Special Characters
+
+
+File: as.info, Node: i960-Chars, Up: Syntax of i960
+
+9.17.5.1 Special Characters
+...........................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
+
+9.18 IA-64 Dependent Features
+=============================
+
+* Menu:
+
+* IA-64 Options:: Options
+* IA-64 Syntax:: Syntax
+* IA-64 Opcodes:: Opcodes
+
+
+File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent
+
+9.18.1 Options
+--------------
+
+`-mconstant-gp'
+ This option instructs the assembler to mark the resulting object
+ file as using the "constant GP" model. With this model, it is
+ assumed that the entire program uses a single global pointer (GP)
+ value. Note that this option does not in any fashion affect the
+ machine code emitted by the assembler. All it does is turn on the
+ EF_IA_64_CONS_GP flag in the ELF file header.
+
+`-mauto-pic'
+ This option instructs the assembler to mark the resulting object
+ file as using the "constant GP without function descriptor" data
+ model. This model is like the "constant GP" model, except that it
+ additionally does away with function descriptors. What this means
+ is that the address of a function refers directly to the
+ function's code entry-point. Normally, such an address would
+ refer to a function descriptor, which contains both the code
+ entry-point and the GP-value needed by the function. Note that
+ this option does not in any fashion affect the machine code
+ emitted by the assembler. All it does is turn on the
+ EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
+
+`-milp32'
+`-milp64'
+`-mlp64'
+`-mp64'
+ These options select the data model. The assembler defaults to
+ `-mlp64' (LP64 data model).
+
+`-mle'
+`-mbe'
+ These options select the byte order. The `-mle' option selects
+ little-endian byte order (default) and `-mbe' selects big-endian
+ byte order. Note that IA-64 machine code always uses
+ little-endian byte order.
+
+`-mtune=itanium1'
+`-mtune=itanium2'
+ Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
+ is ITANIUM2.
+
+`-munwind-check=warning'
+`-munwind-check=error'
+ These options control what the assembler will do when performing
+ consistency checks on unwind directives. `-munwind-check=warning'
+ will make the assembler issue a warning when an unwind directive
+ check fails. This is the default. `-munwind-check=error' will
+ make the assembler issue an error when an unwind directive check
+ fails.
+
+`-mhint.b=ok'
+`-mhint.b=warning'
+`-mhint.b=error'
+ These options control what the assembler will do when the `hint.b'
+ instruction is used. `-mhint.b=ok' will make the assembler accept
+ `hint.b'. `-mint.b=warning' will make the assembler issue a
+ warning when `hint.b' is used. `-mhint.b=error' will make the
+ assembler treat `hint.b' as an error, which is the default.
+
+`-x'
+`-xexplicit'
+ These options turn on dependency violation checking.
+
+`-xauto'
+ This option instructs the assembler to automatically insert stop
+ bits where necessary to remove dependency violations. This is the
+ default mode.
+
+`-xnone'
+ This option turns off dependency violation checking.
+
+`-xdebug'
+ This turns on debug output intended to help tracking down bugs in
+ the dependency violation checker.
+
+`-xdebugn'
+ This is a shortcut for -xnone -xdebug.
+
+`-xdebugx'
+ This is a shortcut for -xexplicit -xdebug.
+
+
+
+File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent
+
+9.18.2 Syntax
+-------------
+
+The assembler syntax closely follows the IA-64 Assembly Language
+Reference Guide.
+
+* Menu:
+
+* IA-64-Chars:: Special Characters
+* IA-64-Regs:: Register Names
+* IA-64-Bits:: Bit Names
+* IA-64-Relocs:: Relocations
+
+
+File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax
+
+9.18.2.1 Special Characters
+...........................
+
+`//' is the line comment token.
+
+ `;' can be used instead of a newline to separate statements.
+
+
+File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax
+
+9.18.2.2 Register Names
+.......................
+
+The 128 integer registers are referred to as `rN'. The 128
+floating-point registers are referred to as `fN'. The 128 application
+registers are referred to as `arN'. The 128 control registers are
+referred to as `crN'. The 64 one-bit predicate registers are referred
+to as `pN'. The 8 branch registers are referred to as `bN'. In
+addition, the assembler defines a number of aliases: `gp' (`r1'), `sp'
+(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'),
+`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N').
+
+ For convenience, the assembler also defines aliases for all named
+application and control registers. For example, `ar.bsp' refers to the
+register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to
+the end-of-interrupt register (`cr67').
+
+
+File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax
+
+9.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
+........................................................
+
+The assembler defines bit masks for each of the bits in the IA-64
+processor status register. For example, `psr.ic' corresponds to a
+value of 0x2000. These masks are primarily intended for use with the
+`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere
+else where an integer constant is expected.
+
+
+File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax
+
+9.18.2.4 Relocations
+....................
+
+In addition to the standard IA-64 relocations, the following
+relocations are implemented by `as':
+
+`@slotcount(V)'
+ Convert the address offset V into a slot count. This pseudo
+ function is available only on VMS. The expression V must be known
+ at assembly time: it can't reference undefined symbols or symbols
+ in different sections.
+
+
+File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent
+
+9.18.3 Opcodes
+--------------
+
+For detailed information on the IA-64 machine instruction set, see the
+IA-64 Architecture Handbook
+(http://developer.intel.com/design/itanium/arch_spec.htm).
+
+
+File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
+
+9.19 IP2K Dependent Features
+============================
+
+* Menu:
+
+* IP2K-Opts:: IP2K Options
+* IP2K-Syntax:: IP2K Syntax
+
+
+File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent
+
+9.19.1 IP2K Options
+-------------------
+
+The Ubicom IP2K version of `as' has a few machine dependent options:
+
+`-mip2022ext'
+ `as' can assemble the extended IP2022 instructions, but it will
+ only do so if this is specifically allowed via this command line
+ option.
+
+`-mip2022'
+ This option restores the assembler's default behaviour of not
+ permitting the extended IP2022 instructions to be assembled.
+
+
+
+File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent
+
+9.19.2 IP2K Syntax
+------------------
+
+* Menu:
+
+* IP2K-Chars:: Special Characters
+
+
+File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax
+
+9.19.2.1 Special Characters
+...........................
+
+The presence of a `;' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The IP2K assembler does not currently support a line separator
+character.
+
+
+File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
+
+9.20 LM32 Dependent Features
+============================
+
+* Menu:
+
+* LM32 Options:: Options
+* LM32 Syntax:: Syntax
+* LM32 Opcodes:: Opcodes
+
+
+File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent
+
+9.20.1 Options
+--------------
+
+`-mmultiply-enabled'
+ Enable multiply instructions.
+
+`-mdivide-enabled'
+ Enable divide instructions.
+
+`-mbarrel-shift-enabled'
+ Enable barrel-shift instructions.
+
+`-msign-extend-enabled'
+ Enable sign extend instructions.
+
+`-muser-enabled'
+ Enable user defined instructions.
+
+`-micache-enabled'
+ Enable instruction cache related CSRs.
+
+`-mdcache-enabled'
+ Enable data cache related CSRs.
+
+`-mbreak-enabled'
+ Enable break instructions.
+
+`-mall-enabled'
+ Enable all instructions and CSRs.
+
+
+
+File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent
+
+9.20.2 Syntax
+-------------
+
+* Menu:
+
+* LM32-Regs:: Register Names
+* LM32-Modifiers:: Relocatable Expression Modifiers
+* LM32-Chars:: Special Characters
+
+
+File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax
+
+9.20.2.1 Register Names
+.......................
+
+LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'.
+
+ The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp'
+- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'.
+
+ LM32 has the following Control and Status Registers (CSRs).
+
+`IE'
+ Interrupt enable.
+
+`IM'
+ Interrupt mask.
+
+`IP'
+ Interrupt pending.
+
+`ICC'
+ Instruction cache control.
+
+`DCC'
+ Data cache control.
+
+`CC'
+ Cycle counter.
+
+`CFG'
+ Configuration.
+
+`EBA'
+ Exception base address.
+
+`DC'
+ Debug control.
+
+`DEBA'
+ Debug exception base address.
+
+`JTX'
+ JTAG transmit.
+
+`JRX'
+ JTAG receive.
+
+`BP0'
+ Breakpoint 0.
+
+`BP1'
+ Breakpoint 1.
+
+`BP2'
+ Breakpoint 2.
+
+`BP3'
+ Breakpoint 3.
+
+`WP0'
+ Watchpoint 0.
+
+`WP1'
+ Watchpoint 1.
+
+`WP2'
+ Watchpoint 2.
+
+`WP3'
+ Watchpoint 3.
+
+
+File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax
+
+9.20.2.2 Relocatable Expression Modifiers
+.........................................
+
+The assembler supports several modifiers when using relocatable
+addresses in LM32 instruction operands. The general syntax is the
+following:
+
+ modifier(relocatable-expression)
+
+`lo'
+ This modifier allows you to use bits 0 through 15 of an address
+ expression as 16 bit relocatable expression.
+
+`hi'
+ This modifier allows you to use bits 16 through 23 of an address
+ expression as 16 bit relocatable expression.
+
+ For example
+
+ ori r4, r4, lo(sym+10)
+ orhi r4, r4, hi(sym+10)
+
+`gp'
+ This modified creates a 16-bit relocatable expression that is the
+ offset of the symbol from the global pointer.
+
+ mva r4, gp(sym)
+
+`got'
+ This modifier places a symbol in the GOT and creates a 16-bit
+ relocatable expression that is the offset into the GOT of this
+ symbol.
+
+ lw r4, (gp+got(sym))
+
+`gotofflo16'
+ This modifier allows you to use the bits 0 through 15 of an
+ address which is an offset from the GOT.
+
+`gotoffhi16'
+ This modifier allows you to use the bits 16 through 31 of an
+ address which is an offset from the GOT.
+
+ orhi r4, r4, gotoffhi16(lsym)
+ addi r4, r4, gotofflo16(lsym)
+
+
+
+File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax
+
+9.20.2.3 Special Characters
+...........................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line. Note that if a line starts
+with a `#' character then it can also be a logical line number
+directive (*note Comments::) or a preprocessor control command (*note
+Preprocessing::).
+
+ A semicolon (`;') can be used to separate multiple statements on the
+same line.
+
+
+File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent
+
+9.20.3 Opcodes
+--------------
+
+For detailed information on the LM32 machine instruction set, see
+`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'.
+
+ `as' implements all the standard LM32 opcodes.
+
+
+File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies
+
+9.21 M32C Dependent Features
+============================
+
+ `as' can assemble code for several different members of the Renesas
+M32C family. Normally the default is to assemble code for the M16C
+microprocessor. The `-m32c' option may be used to change the default
+to the M32C microprocessor.
+
+* Menu:
+
+* M32C-Opts:: M32C Options
+* M32C-Syntax:: M32C Syntax
+
+
+File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent
+
+9.21.1 M32C Options
+-------------------
+
+The Renesas M32C version of `as' has these machine-dependent options:
+
+`-m32c'
+ Assemble M32C instructions.
+
+`-m16c'
+ Assemble M16C instructions (default).
+
+`-relax'
+ Enable support for link-time relaxations.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
+
+
+File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent
+
+9.21.2 M32C Syntax
+------------------
+
+* Menu:
+
+* M32C-Modifiers:: Symbolic Operand Modifiers
+* M32C-Chars:: Special Characters
+
+
+File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax
+
+9.21.2.1 Symbolic Operand Modifiers
+...................................
+
+The assembler supports several modifiers when using symbol addresses in
+M32C instruction operands. The general syntax is the following:
+
+ %modifier(symbol)
+
+`%dsp8'
+`%dsp16'
+ These modifiers override the assembler's assumptions about how big
+ a symbol's address is. Normally, when it sees an operand like
+ `sym[a0]' it assumes `sym' may require the widest displacement
+ field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers
+ tell it to assume the address will fit in an 8 or 16 bit
+ (respectively) unsigned displacement. Note that, of course, if it
+ doesn't actually fit you will get linker errors. Example:
+
+ mov.w %dsp8(sym)[a0],r1
+ mov.b #0,%dsp8(sym)[a0]
+
+`%hi8'
+ This modifier allows you to load bits 16 through 23 of a 24 bit
+ address into an 8 bit register. This is useful with, for example,
+ the M16C `smovf' instruction, which expects a 20 bit address in
+ `r1h' and `a0'. Example:
+
+ mov.b #%hi8(sym),r1h
+ mov.w #%lo16(sym),a0
+ smovf.b
+
+`%lo16'
+ Likewise, this modifier allows you to load bits 0 through 15 of a
+ 24 bit address into a 16 bit register.
+
+`%hi16'
+ This modifier allows you to load bits 16 through 31 of a 32 bit
+ address into a 16 bit register. While the M32C family only has 24
+ bits of address space, it does support addresses in pairs of 16 bit
+ registers (like `a1a0' for the `lde' instruction). This modifier
+ is for loading the upper half in such cases. Example:
+
+ mov.w #%hi16(sym),a1
+ mov.w #%lo16(sym),a0
+ ...
+ lde.w [a1a0],r1
+
+
+
+File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax
+
+9.21.2.2 Special Characters
+...........................
+
+The presence of a `;' character on a line indicates the start of a
+comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The `|' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies
+
+9.22 M32R Dependent Features
+============================
+
+* Menu:
+
+* M32R-Opts:: M32R Options
+* M32R-Directives:: M32R Directives
+* M32R-Warnings:: M32R Warnings
+
+
+File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent
+
+9.22.1 M32R Options
+-------------------
+
+The Renease M32R version of `as' has a few machine dependent options:
+
+`-m32rx'
+ `as' can assemble code for several different members of the
+ Renesas M32R family. Normally the default is to assemble code for
+ the M32R microprocessor. This option may be used to change the
+ default to the M32RX microprocessor, which adds some more
+ instructions to the basic M32R instruction set, and some
+ additional parameters to some of the original instructions.
+
+`-m32r2'
+ This option changes the target processor to the M32R2
+ microprocessor.
+
+`-m32r'
+ This option can be used to restore the assembler's default
+ behaviour of assembling for the M32R microprocessor. This can be
+ useful if the default has been changed by a previous command line
+ option.
+
+`-little'
+ This option tells the assembler to produce little-endian code and
+ data. The default is dependent upon how the toolchain was
+ configured.
+
+`-EL'
+ This is a synonym for _-little_.
+
+`-big'
+ This option tells the assembler to produce big-endian code and
+ data.
+
+`-EB'
+ This is a synonum for _-big_.
+
+`-KPIC'
+ This option specifies that the output of the assembler should be
+ marked as position-independent code (PIC).
+
+`-parallel'
+ This option tells the assembler to attempts to combine two
+ sequential instructions into a single, parallel instruction, where
+ it is legal to do so.
+
+`-no-parallel'
+ This option disables a previously enabled _-parallel_ option.
+
+`-no-bitinst'
+ This option disables the support for the extended bit-field
+ instructions provided by the M32R2. If this support needs to be
+ re-enabled the _-bitinst_ switch can be used to restore it.
+
+`-O'
+ This option tells the assembler to attempt to optimize the
+ instructions that it produces. This includes filling delay slots
+ and converting sequential instructions into parallel ones. This
+ option implies _-parallel_.
+
+`-warn-explicit-parallel-conflicts'
+ Instructs `as' to produce warning messages when questionable
+ parallel instructions are encountered. This option is enabled by
+ default, but `gcc' disables it when it invokes `as' directly.
+ Questionable instructions are those whose behaviour would be
+ different if they were executed sequentially. For example the
+ code fragment `mv r1, r2 || mv r3, r1' produces a different result
+ from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
+ and then r2 into r1, whereas the later moves r2 into r1 and r3.
+
+`-Wp'
+ This is a shorter synonym for the
+ _-warn-explicit-parallel-conflicts_ option.
+
+`-no-warn-explicit-parallel-conflicts'
+ Instructs `as' not to produce warning messages when questionable
+ parallel instructions are encountered.
+
+`-Wnp'
+ This is a shorter synonym for the
+ _-no-warn-explicit-parallel-conflicts_ option.
+
+`-ignore-parallel-conflicts'
+ This option tells the assembler's to stop checking parallel
+ instructions for constraint violations. This ability is provided
+ for hardware vendors testing chip designs and should not be used
+ under normal circumstances.
+
+`-no-ignore-parallel-conflicts'
+ This option restores the assembler's default behaviour of checking
+ parallel instructions to detect constraint violations.
+
+`-Ip'
+ This is a shorter synonym for the _-ignore-parallel-conflicts_
+ option.
+
+`-nIp'
+ This is a shorter synonym for the _-no-ignore-parallel-conflicts_
+ option.
+
+`-warn-unmatched-high'
+ This option tells the assembler to produce a warning message if a
+ `.high' pseudo op is encountered without a matching `.low' pseudo
+ op. The presence of such an unmatched pseudo op usually indicates
+ a programming error.
+
+`-no-warn-unmatched-high'
+ Disables a previously enabled _-warn-unmatched-high_ option.
+
+`-Wuh'
+ This is a shorter synonym for the _-warn-unmatched-high_ option.
+
+`-Wnuh'
+ This is a shorter synonym for the _-no-warn-unmatched-high_ option.
+
+
+
+File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent
+
+9.22.2 M32R Directives
+----------------------
+
+The Renease M32R version of `as' has a few architecture specific
+directives:
+
+`low EXPRESSION'
+ The `low' directive computes the value of its expression and
+ places the lower 16-bits of the result into the immediate-field of
+ the instruction. For example:
+
+ or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
+ add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
+
+`high EXPRESSION'
+ The `high' directive computes the value of its expression and
+ places the upper 16-bits of the result into the immediate-field of
+ the instruction. For example:
+
+ seth r0, #high(0x12345678) ; compute r0 = 0x12340000
+ seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
+
+`shigh EXPRESSION'
+ The `shigh' directive is very similar to the `high' directive. It
+ also computes the value of its expression and places the upper
+ 16-bits of the result into the immediate-field of the instruction.
+ The difference is that `shigh' also checks to see if the lower
+ 16-bits could be interpreted as a signed number, and if so it
+ assumes that a borrow will occur from the upper-16 bits. To
+ compensate for this the `shigh' directive pre-biases the upper 16
+ bit value by adding one to it. For example:
+
+ For example:
+
+ seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
+ seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
+
+ In the second example the lower 16-bits are 0x8000. If these are
+ treated as a signed value and sign extended to 32-bits then the
+ value becomes 0xffff8000. If this value is then added to
+ 0x00010000 then the result is 0x00008000.
+
+ This behaviour is to allow for the different semantics of the
+ `or3' and `add3' instructions. The `or3' instruction treats its
+ 16-bit immediate argument as unsigned whereas the `add3' treats
+ its 16-bit immediate as a signed value. So for example:
+
+ seth r0, #shigh(0x00008000)
+ add3 r0, r0, #low(0x00008000)
+
+ Produces the correct result in r0, whereas:
+
+ seth r0, #shigh(0x00008000)
+ or3 r0, r0, #low(0x00008000)
+
+ Stores 0xffff8000 into r0.
+
+ Note - the `shigh' directive does not know where in the assembly
+ source code the lower 16-bits of the value are going set, so it
+ cannot check to make sure that an `or3' instruction is being used
+ rather than an `add3' instruction. It is up to the programmer to
+ make sure that correct directives are used.
+
+`.m32r'
+ The directive performs a similar thing as the _-m32r_ command line
+ option. It tells the assembler to only accept M32R instructions
+ from now on. An instructions from later M32R architectures are
+ refused.
+
+`.m32rx'
+ The directive performs a similar thing as the _-m32rx_ command
+ line option. It tells the assembler to start accepting the extra
+ instructions in the M32RX ISA as well as the ordinary M32R ISA.
+
+`.m32r2'
+ The directive performs a similar thing as the _-m32r2_ command
+ line option. It tells the assembler to start accepting the extra
+ instructions in the M32R2 ISA as well as the ordinary M32R ISA.
+
+`.little'
+ The directive performs a similar thing as the _-little_ command
+ line option. It tells the assembler to start producing
+ little-endian code and data. This option should be used with care
+ as producing mixed-endian binary files is fraught with danger.
+
+`.big'
+ The directive performs a similar thing as the _-big_ command line
+ option. It tells the assembler to start producing big-endian code
+ and data. This option should be used with care as producing
+ mixed-endian binary files is fraught with danger.
+
+
+
+File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent
+
+9.22.3 M32R Warnings
+--------------------
+
+There are several warning and error messages that can be produced by
+`as' which are specific to the M32R:
+
+`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
+ This message is only produced if warnings for explicit parallel
+ conflicts have been enabled. It indicates that the assembler has
+ encountered a parallel instruction in which the destination
+ register of the left hand instruction is used as an input register
+ in the right hand instruction. For example in this code fragment
+ `mv r1, r2 || neg r3, r1' register r1 is the destination of the
+ move instruction and the input to the neg instruction.
+
+`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
+ This message is only produced if warnings for explicit parallel
+ conflicts have been enabled. It indicates that the assembler has
+ encountered a parallel instruction in which the destination
+ register of the right hand instruction is used as an input
+ register in the left hand instruction. For example in this code
+ fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
+ of the neg instruction and the input to the move instruction.
+
+`instruction `...' is for the M32RX only'
+ This message is produced when the assembler encounters an
+ instruction which is only supported by the M32Rx processor, and
+ the `-m32rx' command line flag has not been specified to allow
+ assembly of such instructions.
+
+`unknown instruction `...''
+ This message is produced when the assembler encounters an
+ instruction which it does not recognize.
+
+`only the NOP instruction can be issued in parallel on the m32r'
+ This message is produced when the assembler encounters a parallel
+ instruction which does not involve a NOP instruction and the
+ `-m32rx' command line flag has not been specified. Only the M32Rx
+ processor is able to execute two instructions in parallel.
+
+`instruction `...' cannot be executed in parallel.'
+ This message is produced when the assembler encounters a parallel
+ instruction which is made up of one or two instructions which
+ cannot be executed in parallel.
+
+`Instructions share the same execution pipeline'
+ This message is produced when the assembler encounters a parallel
+ instruction whoes components both use the same execution pipeline.
+
+`Instructions write to the same destination register.'
+ This message is produced when the assembler encounters a parallel
+ instruction where both components attempt to modify the same
+ register. For example these code fragments will produce this
+ message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
+ @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
+ r3, r4' (Both write to the condition bit)
+
+
+
+File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies
+
+9.23 M680x0 Dependent Features
+==============================
+
+* Menu:
+
+* M68K-Opts:: M680x0 Options
+* M68K-Syntax:: Syntax
+* M68K-Moto-Syntax:: Motorola Syntax
+* M68K-Float:: Floating Point
+* M68K-Directives:: 680x0 Machine Directives
+* M68K-opcodes:: Opcodes
+
+
+File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
+
+9.23.1 M680x0 Options
+---------------------
+
+The Motorola 680x0 version of `as' has a few machine dependent options:
+
+`-march=ARCHITECTURE'
+ This option specifies a target architecture. The following
+ architectures are recognized: `68000', `68010', `68020', `68030',
+ `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and
+ `cfv4e'.
+
+`-mcpu=CPU'
+ This option specifies a target cpu. When used in conjunction with
+ the `-march' option, the cpu must be within the specified
+ architecture. Also, the generic features of the architecture are
+ used for instruction generation, rather than those of the specific
+ chip.
+
+`-m[no-]68851'
+`-m[no-]68881'
+`-m[no-]div'
+`-m[no-]usp'
+`-m[no-]float'
+`-m[no-]mac'
+`-m[no-]emac'
+ Enable or disable various architecture specific features. If a
+ chip or architecture by default supports an option (for instance
+ `-march=isaaplus' includes the `-mdiv' option), explicitly
+ disabling the option will override the default.
+
+`-l'
+ You can use the `-l' option to shorten the size of references to
+ undefined symbols. If you do not use the `-l' option, references
+ to undefined symbols are wide enough for a full `long' (32 bits).
+ (Since `as' cannot know where these symbols end up, `as' can only
+ allocate space for the linker to fill in later. Since `as' does
+ not know how far away these symbols are, it allocates as much
+ space as it can.) If you use this option, the references are only
+ one word wide (16 bits). This may be useful if you want the
+ object file to be as small as possible, and you know that the
+ relevant symbols are always less than 17 bits away.
+
+`--register-prefix-optional'
+ For some configurations, especially those where the compiler
+ normally does not prepend an underscore to the names of user
+ variables, the assembler requires a `%' before any use of a
+ register name. This is intended to let the assembler distinguish
+ between C variables and functions named `a0' through `a7', and so
+ on. The `%' is always accepted, but is not required for certain
+ configurations, notably `sun3'. The `--register-prefix-optional'
+ option may be used to permit omitting the `%' even for
+ configurations for which it is normally required. If this is
+ done, it will generally be impossible to refer to C variables and
+ functions with the same names as register names.
+
+`--bitwise-or'
+ Normally the character `|' is treated as a comment character, which
+ means that it can not be used in expressions. The `--bitwise-or'
+ option turns `|' into a normal character. In this mode, you must
+ either use C style comments, or start comments with a `#' character
+ at the beginning of a line.
+
+`--base-size-default-16 --base-size-default-32'
+ If you use an addressing mode with a base register without
+ specifying the size, `as' will normally use the full 32 bit value.
+ For example, the addressing mode `%a0@(%d0)' is equivalent to
+ `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to
+ tell `as' to default to using the 16 bit value. In this case,
+ `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the
+ `--base-size-default-32' option to restore the default behaviour.
+
+`--disp-size-default-16 --disp-size-default-32'
+ If you use an addressing mode with a displacement, and the value
+ of the displacement is not known, `as' will normally assume that
+ the value is 32 bits. For example, if the symbol `disp' has not
+ been defined, `as' will assemble the addressing mode
+ `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use
+ the `--disp-size-default-16' option to tell `as' to instead assume
+ that the displacement is 16 bits. In this case, `as' will
+ assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You
+ may use the `--disp-size-default-32' option to restore the default
+ behaviour.
+
+`--pcrel'
+ Always keep branches PC-relative. In the M680x0 architecture all
+ branches are defined as PC-relative. However, on some processors
+ they are limited to word displacements maximum. When `as' needs a
+ long branch that is not available, it normally emits an absolute
+ jump instead. This option disables this substitution. When this
+ option is given and no long branches are available, only word
+ branches will be emitted. An error message will be generated if a
+ word branch cannot reach its target. This option has no effect on
+ 68020 and other processors that have long branches. *note Branch
+ Improvement: M68K-Branch.
+
+`-m68000'
+ `as' can assemble code for several different members of the
+ Motorola 680x0 family. The default depends upon how `as' was
+ configured when it was built; normally, the default is to assemble
+ code for the 68020 microprocessor. The following options may be
+ used to change the default. These options control which
+ instructions and addressing modes are permitted. The members of
+ the 680x0 family are very similar. For detailed information about
+ the differences, see the Motorola manuals.
+
+ `-m68000'
+ `-m68ec000'
+ `-m68hc000'
+ `-m68hc001'
+ `-m68008'
+ `-m68302'
+ `-m68306'
+ `-m68307'
+ `-m68322'
+ `-m68356'
+ Assemble for the 68000. `-m68008', `-m68302', and so on are
+ synonyms for `-m68000', since the chips are the same from the
+ point of view of the assembler.
+
+ `-m68010'
+ Assemble for the 68010.
+
+ `-m68020'
+ `-m68ec020'
+ Assemble for the 68020. This is normally the default.
+
+ `-m68030'
+ `-m68ec030'
+ Assemble for the 68030.
+
+ `-m68040'
+ `-m68ec040'
+ Assemble for the 68040.
+
+ `-m68060'
+ `-m68ec060'
+ Assemble for the 68060.
+
+ `-mcpu32'
+ `-m68330'
+ `-m68331'
+ `-m68332'
+ `-m68333'
+ `-m68334'
+ `-m68336'
+ `-m68340'
+ `-m68341'
+ `-m68349'
+ `-m68360'
+ Assemble for the CPU32 family of chips.
+
+ `-m5200'
+ `-m5202'
+ `-m5204'
+ `-m5206'
+ `-m5206e'
+ `-m521x'
+ `-m5249'
+ `-m528x'
+ `-m5307'
+ `-m5407'
+ `-m547x'
+ `-m548x'
+ `-mcfv4'
+ `-mcfv4e'
+ Assemble for the ColdFire family of chips.
+
+ `-m68881'
+ `-m68882'
+ Assemble 68881 floating point instructions. This is the
+ default for the 68020, 68030, and the CPU32. The 68040 and
+ 68060 always support floating point instructions.
+
+ `-mno-68881'
+ Do not assemble 68881 floating point instructions. This is
+ the default for 68000 and the 68010. The 68040 and 68060
+ always support floating point instructions, even if this
+ option is used.
+
+ `-m68851'
+ Assemble 68851 MMU instructions. This is the default for the
+ 68020, 68030, and 68060. The 68040 accepts a somewhat
+ different set of MMU instructions; `-m68851' and `-m68040'
+ should not be used together.
+
+ `-mno-68851'
+ Do not assemble 68851 MMU instructions. This is the default
+ for the 68000, 68010, and the CPU32. The 68040 accepts a
+ somewhat different set of MMU instructions.
+
+
+File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
+
+9.23.2 Syntax
+-------------
+
+This syntax for the Motorola 680x0 was developed at MIT.
+
+ The 680x0 version of `as' uses instructions names and syntax
+compatible with the Sun assembler. Intervening periods are ignored;
+for example, `movl' is equivalent to `mov.l'.
+
+ In the following table APC stands for any of the address registers
+(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
+relative to the program counter (`%zpc'), a suppressed address register
+(`%za0' through `%za7'), or it may be omitted entirely. The use of
+SIZE means one of `w' or `l', and it may be omitted, along with the
+leading colon, unless a scale is also specified. The use of SCALE
+means one of `1', `2', `4', or `8', and it may always be omitted along
+with the leading colon.
+
+ The following addressing modes are understood:
+"Immediate"
+ `#NUMBER'
+
+"Data Register"
+ `%d0' through `%d7'
+
+"Address Register"
+ `%a0' through `%a7'
+ `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is
+ also known as `%fp', the Frame Pointer.
+
+"Address Register Indirect"
+ `%a0@' through `%a7@'
+
+"Address Register Postincrement"
+ `%a0@+' through `%a7@+'
+
+"Address Register Predecrement"
+ `%a0@-' through `%a7@-'
+
+"Indirect Plus Offset"
+ `APC@(NUMBER)'
+
+"Index"
+ `APC@(NUMBER,REGISTER:SIZE:SCALE)'
+
+ The NUMBER may be omitted.
+
+"Postindex"
+ `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
+
+ The ONUMBER or the REGISTER, but not both, may be omitted.
+
+"Preindex"
+ `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
+
+ The NUMBER may be omitted. Omitting the REGISTER produces the
+ Postindex addressing mode.
+
+"Absolute"
+ `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.
+
+
+File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
+
+9.23.3 Motorola Syntax
+----------------------
+
+The standard Motorola syntax for this chip differs from the syntax
+already discussed (*note Syntax: M68K-Syntax.). `as' can accept
+Motorola syntax for operands, even if MIT syntax is used for other
+operands in the same instruction. The two kinds of syntax are fully
+compatible.
+
+ In the following table APC stands for any of the address registers
+(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
+relative to the program counter (`%zpc'), or a suppressed address
+register (`%za0' through `%za7'). The use of SIZE means one of `w' or
+`l', and it may always be omitted along with the leading dot. The use
+of SCALE means one of `1', `2', `4', or `8', and it may always be
+omitted along with the leading asterisk.
+
+ The following additional addressing modes are understood:
+
+"Address Register Indirect"
+ `(%a0)' through `(%a7)'
+ `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is
+ also known as `%fp', the Frame Pointer.
+
+"Address Register Postincrement"
+ `(%a0)+' through `(%a7)+'
+
+"Address Register Predecrement"
+ `-(%a0)' through `-(%a7)'
+
+"Indirect Plus Offset"
+ `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
+
+ The NUMBER may also appear within the parentheses, as in
+ `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted
+ (with an address register, omitting the NUMBER produces Address
+ Register Indirect mode).
+
+"Index"
+ `NUMBER(APC,REGISTER.SIZE*SCALE)'
+
+ The NUMBER may be omitted, or it may appear within the
+ parentheses. The APC may be omitted. The REGISTER and the APC
+ may appear in either order. If both APC and REGISTER are address
+ registers, and the SIZE and SCALE are omitted, then the first
+ register is taken as the base register, and the second as the
+ index register.
+
+"Postindex"
+ `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
+
+ The ONUMBER, or the REGISTER, or both, may be omitted. Either the
+ NUMBER or the APC may be omitted, but not both.
+
+"Preindex"
+ `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
+
+ The NUMBER, or the APC, or the REGISTER, or any two of them, may
+ be omitted. The ONUMBER may be omitted. The REGISTER and the APC
+ may appear in either order. If both APC and REGISTER are address
+ registers, and the SIZE and SCALE are omitted, then the first
+ register is taken as the base register, and the second as the
+ index register.
+
+
+File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
+
+9.23.4 Floating Point
+---------------------
+
+Packed decimal (P) format floating literals are not supported. Feel
+free to add the code!
+
+ The floating point formats generated by directives are these.
+
+`.float'
+ `Single' precision floating point constants.
+
+`.double'
+ `Double' precision floating point constants.
+
+`.extend'
+`.ldouble'
+ `Extended' precision (`long double') floating point constants.
+
+
+File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
+
+9.23.5 680x0 Machine Directives
+-------------------------------
+
+In order to be compatible with the Sun assembler the 680x0 assembler
+understands the following directives.
+
+`.data1'
+ This directive is identical to a `.data 1' directive.
+
+`.data2'
+ This directive is identical to a `.data 2' directive.
+
+`.even'
+ This directive is a special case of the `.align' directive; it
+ aligns the output to an even byte boundary.
+
+`.skip'
+ This directive is identical to a `.space' directive.
+
+`.arch NAME'
+ Select the target architecture and extension features. Valid
+ values for NAME are the same as for the `-march' command line
+ option. This directive cannot be specified after any instructions
+ have been assembled. If it is given multiple times, or in
+ conjunction with the `-march' option, all uses must be for the
+ same architecture and extension set.
+
+`.cpu NAME'
+ Select the target cpu. Valid valuse for NAME are the same as for
+ the `-mcpu' command line option. This directive cannot be
+ specified after any instructions have been assembled. If it is
+ given multiple times, or in conjunction with the `-mopt' option,
+ all uses must be for the same cpu.
+
+
+
+File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
+
+9.23.6 Opcodes
+--------------
+
+* Menu:
+
+* M68K-Branch:: Branch Improvement
+* M68K-Chars:: Special Characters
+
+
+File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
+
+9.23.6.1 Branch Improvement
+...........................
+
+Certain pseudo opcodes are permitted for branch instructions. They
+expand to the shortest branch instruction that reach the target.
+Generally these mnemonics are made by substituting `j' for `b' at the
+start of a Motorola mnemonic.
+
+ The following table summarizes the pseudo-operations. A `*' flags
+cases that are more fully described after the table:
+
+ Displacement
+ +------------------------------------------------------------
+ | 68020 68000/10, not PC-relative OK
+ Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
+ +------------------------------------------------------------
+ jbsr |bsrs bsrw bsrl jsr
+ jra |bras braw bral jmp
+ * jXX |bXXs bXXw bXXl bNXs;jmp
+ * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
+ fjXX | N/A fbXXw fbXXl N/A
+
+ XX: condition
+ NX: negative of condition XX
+ `*'--see full description below
+ `**'--this expansion mode is disallowed by `--pcrel'
+
+`jbsr'
+`jra'
+ These are the simplest jump pseudo-operations; they always map to
+ one particular machine instruction, depending on the displacement
+ to the branch target. This instruction will be a byte or word
+ branch is that is sufficient. Otherwise, a long branch will be
+ emitted if available. If no long branches are available and the
+ `--pcrel' option is not given, an absolute long jump will be
+ emitted instead. If no long branches are available, the `--pcrel'
+ option is given, and a word branch cannot reach the target, an
+ error message is generated.
+
+ In addition to standard branch operands, `as' allows these
+ pseudo-operations to have all operands that are allowed for jsr
+ and jmp, substituting these instructions if the operand given is
+ not valid for a branch instruction.
+
+`jXX'
+ Here, `jXX' stands for an entire family of pseudo-operations,
+ where XX is a conditional branch or condition-code test. The full
+ list of pseudo-ops in this family is:
+ jhi jls jcc jcs jne jeq jvc
+ jvs jpl jmi jge jlt jgt jle
+
+ Usually, each of these pseudo-operations expands to a single branch
+ instruction. However, if a word branch is not sufficient, no long
+ branches are available, and the `--pcrel' option is not given, `as'
+ issues a longer code fragment in terms of NX, the opposite
+ condition to XX. For example, under these conditions:
+ jXX foo
+ gives
+ bNXs oof
+ jmp foo
+ oof:
+
+`dbXX'
+ The full family of pseudo-operations covered here is
+ dbhi dbls dbcc dbcs dbne dbeq dbvc
+ dbvs dbpl dbmi dbge dblt dbgt dble
+ dbf dbra dbt
+
+ Motorola `dbXX' instructions allow word displacements only. When
+ a word displacement is sufficient, each of these pseudo-operations
+ expands to the corresponding Motorola instruction. When a word
+ displacement is not sufficient and long branches are available,
+ when the source reads `dbXX foo', `as' emits
+ dbXX oo1
+ bras oo2
+ oo1:bral foo
+ oo2:
+
+ If, however, long branches are not available and the `--pcrel'
+ option is not given, `as' emits
+ dbXX oo1
+ bras oo2
+ oo1:jmp foo
+ oo2:
+
+`fjXX'
+ This family includes
+ fjne fjeq fjge fjlt fjgt fjle fjf
+ fjt fjgl fjgle fjnge fjngl fjngle fjngt
+ fjnle fjnlt fjoge fjogl fjogt fjole fjolt
+ fjor fjseq fjsf fjsne fjst fjueq fjuge
+ fjugt fjule fjult fjun
+
+ Each of these pseudo-operations always expands to a single Motorola
+ coprocessor branch instruction, word or long. All Motorola
+ coprocessor branch instructions allow both word and long
+ displacements.
+
+
+
+File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
+
+9.23.6.2 Special Characters
+...........................
+
+Line comments are introduced by the `|' character appearing anywhere on
+a line, unless the `--bitwise-or' command line option has been
+specified.
+
+ An asterisk (`*') as the first character on a line marks the start
+of a line comment as well.
+
+ A hash character (`#') as the first character on a line also marks
+the start of a line comment, but in this case it could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::). If the hash character appears
+elsewhere on a line it is used to introduce an immediate value. (This
+is for compatibility with Sun's assembler).
+
+ Multiple statements on the same line can appear if they are separated
+by the `;' character.
+
+
+File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
+
+9.24 M68HC11 and M68HC12 Dependent Features
+===========================================
+
+* Menu:
+
+* M68HC11-Opts:: M68HC11 and M68HC12 Options
+* M68HC11-Syntax:: Syntax
+* M68HC11-Modifiers:: Symbolic Operand Modifiers
+* M68HC11-Directives:: Assembler Directives
+* M68HC11-Float:: Floating Point
+* M68HC11-opcodes:: Opcodes
+
+
+File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent
+
+9.24.1 M68HC11 and M68HC12 Options
+----------------------------------
+
+The Motorola 68HC11 and 68HC12 version of `as' have a few machine
+dependent options.
+
+`-m68hc11'
+ This option switches the assembler into the M68HC11 mode. In this
+ mode, the assembler only accepts 68HC11 operands and mnemonics. It
+ produces code for the 68HC11.
+
+`-m68hc12'
+ This option switches the assembler into the M68HC12 mode. In this
+ mode, the assembler also accepts 68HC12 operands and mnemonics. It
+ produces code for the 68HC12. A few 68HC11 instructions are
+ replaced by some 68HC12 instructions as recommended by Motorola
+ specifications.
+
+`-m68hcs12'
+ This option switches the assembler into the M68HCS12 mode. This
+ mode is similar to `-m68hc12' but specifies to assemble for the
+ 68HCS12 series. The only difference is on the assembling of the
+ `movb' and `movw' instruction when a PC-relative operand is used.
+
+`-mm9s12x'
+ This option switches the assembler into the M9S12X mode. This
+ mode is similar to `-m68hc12' but specifies to assemble for the
+ S12X series which is a superset of the HCS12.
+
+`-mm9s12xg'
+ This option switches the assembler into the XGATE mode for the RISC
+ co-processor featured on some S12X-family chips.
+
+`--xgate-ramoffset'
+ This option instructs the linker to offset RAM addresses from S12X
+ address space into XGATE address space.
+
+`-mshort'
+ This option controls the ABI and indicates to use a 16-bit integer
+ ABI. It has no effect on the assembled instructions. This is the
+ default.
+
+`-mlong'
+ This option controls the ABI and indicates to use a 32-bit integer
+ ABI.
+
+`-mshort-double'
+ This option controls the ABI and indicates to use a 32-bit float
+ ABI. This is the default.
+
+`-mlong-double'
+ This option controls the ABI and indicates to use a 64-bit float
+ ABI.
+
+`--strict-direct-mode'
+ You can use the `--strict-direct-mode' option to disable the
+ automatic translation of direct page mode addressing into extended
+ mode when the instruction does not support direct mode. For
+ example, the `clr' instruction does not support direct page mode
+ addressing. When it is used with the direct page mode, `as' will
+ ignore it and generate an absolute addressing. This option
+ prevents `as' from doing this, and the wrong usage of the direct
+ page mode will raise an error.
+
+`--short-branches'
+ The `--short-branches' option turns off the translation of
+ relative branches into absolute branches when the branch offset is
+ out of range. By default `as' transforms the relative branch
+ (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc',
+ `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch
+ when the offset is out of the -128 .. 127 range. In that case,
+ the `bsr' instruction is translated into a `jsr', the `bra'
+ instruction is translated into a `jmp' and the conditional
+ branches instructions are inverted and followed by a `jmp'. This
+ option disables these translations and `as' will generate an error
+ if a relative branch is out of range. This option does not affect
+ the optimization associated to the `jbra', `jbsr' and `jbXX'
+ pseudo opcodes.
+
+`--force-long-branches'
+ The `--force-long-branches' option forces the translation of
+ relative branches into absolute branches. This option does not
+ affect the optimization associated to the `jbra', `jbsr' and
+ `jbXX' pseudo opcodes.
+
+`--print-insn-syntax'
+ You can use the `--print-insn-syntax' option to obtain the syntax
+ description of the instruction when an error is detected.
+
+`--print-opcodes'
+ The `--print-opcodes' option prints the list of all the
+ instructions with their syntax. The first item of each line
+ represents the instruction name and the rest of the line indicates
+ the possible operands for that instruction. The list is printed in
+ alphabetical order. Once the list is printed `as' exits.
+
+`--generate-example'
+ The `--generate-example' option is similar to `--print-opcodes'
+ but it generates an example for each instruction instead.
+
+
+File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent
+
+9.24.2 Syntax
+-------------
+
+In the M68HC11 syntax, the instruction name comes first and it may be
+followed by one or several operands (up to three). Operands are
+separated by comma (`,'). In the normal mode, `as' will complain if too
+many operands are specified for a given instruction. In the MRI mode
+(turned on with `-M' option), it will treat them as comments. Example:
+
+ inx
+ lda #23
+ bset 2,x #4
+ brclr *bot #8 foo
+
+ The presence of a `;' character or a `!' character anywhere on a
+line indicates the start of a comment that extends to the end of that
+line.
+
+ A `*' or a `#' character at the start of a line also introduces a
+line comment, but these characters do not work elsewhere on the line.
+If the first character of the line is a `#' then as well as starting a
+comment, the line could also be logical line number directive (*note
+Comments::) or a preprocessor control command (*note Preprocessing::).
+
+ The M68HC11 assembler does not currently support a line separator
+character.
+
+ The following addressing modes are understood for 68HC11 and 68HC12:
+"Immediate"
+ `#NUMBER'
+
+"Address Register"
+ `NUMBER,X', `NUMBER,Y'
+
+ The NUMBER may be omitted in which case 0 is assumed.
+
+"Direct Addressing mode"
+ `*SYMBOL', or `*DIGITS'
+
+"Absolute"
+ `SYMBOL', or `DIGITS'
+
+ The M68HC12 has other more complex addressing modes. All of them are
+supported and they are represented below:
+
+"Constant Offset Indexed Addressing Mode"
+ `NUMBER,REG'
+
+ The NUMBER may be omitted in which case 0 is assumed. The
+ register can be either `X', `Y', `SP' or `PC'. The assembler will
+ use the smaller post-byte definition according to the constant
+ value (5-bit constant offset, 9-bit constant offset or 16-bit
+ constant offset). If the constant is not known by the assembler
+ it will use the 16-bit constant offset post-byte and the value
+ will be resolved at link time.
+
+"Offset Indexed Indirect"
+ `[NUMBER,REG]'
+
+ The register can be either `X', `Y', `SP' or `PC'.
+
+"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
+ `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+'
+
+ The number must be in the range `-8'..`+8' and must not be 0. The
+ register can be either `X', `Y', `SP' or `PC'.
+
+"Accumulator Offset"
+ `ACC,REG'
+
+ The accumulator register can be either `A', `B' or `D'. The
+ register can be either `X', `Y', `SP' or `PC'.
+
+"Accumulator D offset indexed-indirect"
+ `[D,REG]'
+
+ The register can be either `X', `Y', `SP' or `PC'.
+
+
+ For example:
+
+ ldab 1024,sp
+ ldd [10,x]
+ orab 3,+x
+ stab -2,y-
+ ldx a,pc
+ sty [d,sp]
+
+
+File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent
+
+9.24.3 Symbolic Operand Modifiers
+---------------------------------
+
+The assembler supports several modifiers when using symbol addresses in
+68HC11 and 68HC12 instruction operands. The general syntax is the
+following:
+
+ %modifier(symbol)
+
+`%addr'
+ This modifier indicates to the assembler and linker to use the
+ 16-bit physical address corresponding to the symbol. This is
+ intended to be used on memory window systems to map a symbol in
+ the memory bank window. If the symbol is in a memory expansion
+ part, the physical address corresponds to the symbol address
+ within the memory bank window. If the symbol is not in a memory
+ expansion part, this is the symbol address (using or not using the
+ %addr modifier has no effect in that case).
+
+`%page'
+ This modifier indicates to use the memory page number corresponding
+ to the symbol. If the symbol is in a memory expansion part, its
+ page number is computed by the linker as a number used to map the
+ page containing the symbol in the memory bank window. If the
+ symbol is not in a memory expansion part, the page number is 0.
+
+`%hi'
+ This modifier indicates to use the 8-bit high part of the physical
+ address of the symbol.
+
+`%lo'
+ This modifier indicates to use the 8-bit low part of the physical
+ address of the symbol.
+
+
+ For example a 68HC12 call to a function `foo_example' stored in
+memory expansion part could be written as follows:
+
+ call %addr(foo_example),%page(foo_example)
+
+ and this is equivalent to
+
+ call foo_example
+
+ And for 68HC11 it could be written as follows:
+
+ ldab #%page(foo_example)
+ stab _page_switch
+ jsr %addr(foo_example)
+
+
+File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent
+
+9.24.4 Assembler Directives
+---------------------------
+
+The 68HC11 and 68HC12 version of `as' have the following specific
+assembler directives:
+
+`.relax'
+ The relax directive is used by the `GNU Compiler' to emit a
+ specific relocation to mark a group of instructions for linker
+ relaxation. The sequence of instructions within the group must be
+ known to the linker so that relaxation can be performed.
+
+`.mode [mshort|mlong|mshort-double|mlong-double]'
+ This directive specifies the ABI. It overrides the `-mshort',
+ `-mlong', `-mshort-double' and `-mlong-double' options.
+
+`.far SYMBOL'
+ This directive marks the symbol as a `far' symbol meaning that it
+ uses a `call/rtc' calling convention as opposed to `jsr/rts'.
+ During a final link, the linker will identify references to the
+ `far' symbol and will verify the proper calling convention.
+
+`.interrupt SYMBOL'
+ This directive marks the symbol as an interrupt entry point. This
+ information is then used by the debugger to correctly unwind the
+ frame across interrupts.
+
+`.xrefb SYMBOL'
+ This directive is defined for compatibility with the
+ `Specification for Motorola 8 and 16-Bit Assembly Language Input
+ Standard' and is ignored.
+
+
+
+File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent
+
+9.24.5 Floating Point
+---------------------
+
+Packed decimal (P) format floating literals are not supported. Feel
+free to add the code!
+
+ The floating point formats generated by directives are these.
+
+`.float'
+ `Single' precision floating point constants.
+
+`.double'
+ `Double' precision floating point constants.
+
+`.extend'
+`.ldouble'
+ `Extended' precision (`long double') floating point constants.
+
+
+File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent
+
+9.24.6 Opcodes
+--------------
+
+* Menu:
+
+* M68HC11-Branch:: Branch Improvement
+
+
+File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes
+
+9.24.6.1 Branch Improvement
+...........................
+
+Certain pseudo opcodes are permitted for branch instructions. They
+expand to the shortest branch instruction that reach the target.
+Generally these mnemonics are made by prepending `j' to the start of
+Motorola mnemonic. These pseudo opcodes are not affected by the
+`--short-branches' or `--force-long-branches' options.
+
+ The following table summarizes the pseudo-operations.
+
+ Displacement Width
+ +-------------------------------------------------------------+
+ | Options |
+ | --short-branches --force-long-branches |
+ +--------------------------+----------------------------------+
+ Op |BYTE WORD | BYTE WORD |
+ +--------------------------+----------------------------------+
+ bsr | bsr <pc-rel> <error> | jsr <abs> |
+ bra | bra <pc-rel> <error> | jmp <abs> |
+ jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
+ jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
+ bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
+ jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
+ | jmp <abs> | |
+ +--------------------------+----------------------------------+
+ XX: condition
+ NX: negative of condition XX
+
+`jbsr'
+`jbra'
+ These are the simplest jump pseudo-operations; they always map to
+ one particular machine instruction, depending on the displacement
+ to the branch target.
+
+`jbXX'
+ Here, `jbXX' stands for an entire family of pseudo-operations,
+ where XX is a conditional branch or condition-code test. The full
+ list of pseudo-ops in this family is:
+ jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
+ jbcs jbne jblt jble jbls jbvc jbmi
+
+ For the cases of non-PC relative displacements and long
+ displacements, `as' issues a longer code fragment in terms of NX,
+ the opposite condition to XX. For example, for the non-PC
+ relative case:
+ jbXX foo
+ gives
+ bNXs oof
+ jmp foo
+ oof:
+
+
+
+File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
+
+9.25 Meta Dependent Features
+============================
+
+* Menu:
+
+* Meta Options:: Options
+* Meta Syntax:: Meta Assembler Syntax
+
+
+File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent
+
+9.25.1 Options
+--------------
+
+The Imagination Technologies Meta architecture is implemented in a
+number of versions, with each new version adding new features such as
+instructions and registers. For precise details of what instructions
+each core supports, please see the chip's technical reference manual.
+
+ The following table lists all available Meta options.
+
+`-mcpu=metac11'
+ Generate code for Meta 1.1.
+
+`-mcpu=metac12'
+ Generate code for Meta 1.2.
+
+`-mcpu=metac21'
+ Generate code for Meta 2.1.
+
+`-mfpu=metac21'
+ Allow code to use FPU hardware of Meta 2.1.
+
+
+
+File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent
+
+9.25.2 Syntax
+-------------
+
+* Menu:
+
+* Meta-Chars:: Special Characters
+* Meta-Regs:: Register Names
+
+
+File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax
+
+9.25.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+ You can use `;' instead of a newline to separate statements.
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax
+
+9.25.2.2 Register Names
+.......................
+
+Registers can be specified either using their mnemonic names, such as
+`D0Re0', or using the unit plus register number separated by a `.',
+such as `D0.0'.
+
+
+File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies
+
+9.26 MicroBlaze Dependent Features
+==================================
+
+ The Xilinx MicroBlaze processor family includes several variants,
+all using the same core instruction set. This chapter covers features
+of the GNU assembler that are specific to the MicroBlaze architecture.
+For details about the MicroBlaze instruction set, please see the
+`MicroBlaze Processor Reference Guide (UG081)' available at
+www.xilinx.com.
+
+* Menu:
+
+* MicroBlaze Directives:: Directives for MicroBlaze Processors.
+* MicroBlaze Syntax:: Syntax for the MicroBlaze
+
+
+File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent
+
+9.26.1 Directives
+-----------------
+
+A number of assembler directives are available for MicroBlaze.
+
+`.data8 EXPRESSION,...'
+ This directive is an alias for `.byte'. Each expression is
+ assembled into an eight-bit value.
+
+`.data16 EXPRESSION,...'
+ This directive is an alias for `.hword'. Each expression is
+ assembled into an 16-bit value.
+
+`.data32 EXPRESSION,...'
+ This directive is an alias for `.word'. Each expression is
+ assembled into an 32-bit value.
+
+`.ent NAME[,LABEL]'
+ This directive is an alias for `.func' denoting the start of
+ function NAME at (optional) LABEL.
+
+`.end NAME[,LABEL]'
+ This directive is an alias for `.endfunc' denoting the end of
+ function NAME.
+
+`.gpword LABEL,...'
+ This directive is an alias for `.rva'. The resolved address of
+ LABEL is stored in the data section.
+
+`.weakext LABEL'
+ Declare that LABEL is a weak external symbol.
+
+`.rodata'
+ Switch to .rodata section. Equivalent to `.section .rodata'
+
+`.sdata2'
+ Switch to .sdata2 section. Equivalent to `.section .sdata2'
+
+`.sdata'
+ Switch to .sdata section. Equivalent to `.section .sdata'
+
+`.bss'
+ Switch to .bss section. Equivalent to `.section .bss'
+
+`.sbss'
+ Switch to .sbss section. Equivalent to `.section .sbss'
+
+
+File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent
+
+9.26.2 Syntax for the MicroBlaze
+--------------------------------
+
+* Menu:
+
+* MicroBlaze-Chars:: Special Characters
+
+
+File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax
+
+9.26.2.1 Special Characters
+...........................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies
+
+9.27 MIPS Dependent Features
+============================
+
+ GNU `as' for MIPS architectures supports several different MIPS
+processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For
+information about the MIPS instruction set, see `MIPS RISC
+Architecture', by Kane and Heindrich (Prentice-Hall). For an overview
+of MIPS assembly conventions, see "Appendix D: Assembly Language
+Programming" in the same work.
+
+* Menu:
+
+* MIPS Options:: Assembler options
+* MIPS Macros:: High-level assembly macros
+* MIPS Symbol Sizes:: Directives to override the size of symbols
+* MIPS Small Data:: Controlling the use of small data accesses
+* MIPS ISA:: Directives to override the ISA level
+* MIPS assembly options:: Directives to control code generation
+* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
+* MIPS insn:: Directive to mark data as an instruction
+* MIPS FP ABIs:: Marking which FP ABI is in use
+* MIPS NaN Encodings:: Directives to record which NaN encoding is being used
+* MIPS Option Stack:: Directives to save and restore options
+* MIPS ASE Instruction Generation Overrides:: Directives to control
+ generation of MIPS ASE instructions
+* MIPS Floating-Point:: Directives to override floating-point options
+* MIPS Syntax:: MIPS specific syntactical considerations
+
+
+File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent
+
+9.27.1 Assembler options
+------------------------
+
+The MIPS configurations of GNU `as' support these special options:
+
+`-G NUM'
+ Set the "small data" limit to N bytes. The default limit is 8
+ bytes. *Note Controlling the use of small data accesses: MIPS
+ Small Data.
+
+`-EB'
+`-EL'
+ Any MIPS configuration of `as' can select big-endian or
+ little-endian output at run time (unlike the other GNU development
+ tools, which must be configured for one or the other). Use `-EB'
+ to select big-endian output, and `-EL' for little-endian.
+
+`-KPIC'
+ Generate SVR4-style PIC. This option tells the assembler to
+ generate SVR4-style position-independent macro expansions. It
+ also tells the assembler to mark the output file as PIC.
+
+`-mvxworks-pic'
+ Generate VxWorks PIC. This option tells the assembler to generate
+ VxWorks-style position-independent macro expansions.
+
+`-mips1'
+`-mips2'
+`-mips3'
+`-mips4'
+`-mips5'
+`-mips32'
+`-mips32r2'
+`-mips32r3'
+`-mips32r5'
+`-mips32r6'
+`-mips64'
+`-mips64r2'
+`-mips64r3'
+`-mips64r5'
+`-mips64r6'
+ Generate code for a particular MIPS Instruction Set Architecture
+ level. `-mips1' corresponds to the R2000 and R3000 processors,
+ `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
+ and `-mips4' to the R8000 and R10000 processors. `-mips5',
+ `-mips32', `-mips32r2', `-mips32r3', `-mips32r5', `-mips32r6',
+ `-mips64', `-mips64r2', `-mips64r3', `-mips64r5', and `-mips64r6'
+ correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
+ Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
+ Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release
+ 6 ISA processors, respectively. You can also switch instruction
+ sets during the assembly; see *Note Directives to override the ISA
+ level: MIPS ISA.
+
+`-mgp32'
+`-mfp32'
+ Some macros have different expansions for 32-bit and 64-bit
+ registers. The register sizes are normally inferred from the ISA
+ and ABI, but these flags force a certain group of registers to be
+ treated as 32 bits wide at all times. `-mgp32' controls the size
+ of general-purpose registers and `-mfp32' controls the size of
+ floating-point registers.
+
+ The `.set gp=32' and `.set fp=32' directives allow the size of
+ registers to be changed for parts of an object. The default value
+ is restored by `.set gp=default' and `.set fp=default'.
+
+ On some MIPS variants there is a 32-bit mode flag; when this flag
+ is set, 64-bit instructions generate a trap. Also, some 32-bit
+ OSes only save the 32-bit registers on a context switch, so it is
+ essential never to use the 64-bit registers.
+
+`-mgp64'
+`-mfp64'
+ Assume that 64-bit registers are available. This is provided in
+ the interests of symmetry with `-mgp32' and `-mfp32'.
+
+ The `.set gp=64' and `.set fp=64' directives allow the size of
+ registers to be changed for parts of an object. The default value
+ is restored by `.set gp=default' and `.set fp=default'.
+
+`-mfpxx'
+ Make no assumptions about whether 32-bit or 64-bit floating-point
+ registers are available. This is provided to support having modules
+ compatible with either `-mfp32' or `-mfp64'. This option can only
+ be used with MIPS II and above.
+
+ The `.set fp=xx' directive allows a part of an object to be marked
+ as not making assumptions about 32-bit or 64-bit FP registers. The
+ default value is restored by `.set fp=default'.
+
+`-modd-spreg'
+`-mno-odd-spreg'
+ Enable use of floating-point operations on odd-numbered
+ single-precision registers when supported by the ISA. `-mfpxx'
+ implies `-mno-odd-spreg', otherwise the default is `-modd-spreg'
+
+`-mips16'
+`-no-mips16'
+ Generate code for the MIPS 16 processor. This is equivalent to
+ putting `.set mips16' at the start of the assembly file.
+ `-no-mips16' turns off this option.
+
+`-mmicromips'
+`-mno-micromips'
+ Generate code for the microMIPS processor. This is equivalent to
+ putting `.set micromips' at the start of the assembly file.
+ `-mno-micromips' turns off this option. This is equivalent to
+ putting `.set nomicromips' at the start of the assembly file.
+
+`-msmartmips'
+`-mno-smartmips'
+ Enables the SmartMIPS extensions to the MIPS32 instruction set,
+ which provides a number of new instructions which target smartcard
+ and cryptographic applications. This is equivalent to putting
+ `.set smartmips' at the start of the assembly file.
+ `-mno-smartmips' turns off this option.
+
+`-mips3d'
+`-no-mips3d'
+ Generate code for the MIPS-3D Application Specific Extension.
+ This tells the assembler to accept MIPS-3D instructions.
+ `-no-mips3d' turns off this option.
+
+`-mdmx'
+`-no-mdmx'
+ Generate code for the MDMX Application Specific Extension. This
+ tells the assembler to accept MDMX instructions. `-no-mdmx' turns
+ off this option.
+
+`-mdsp'
+`-mno-dsp'
+ Generate code for the DSP Release 1 Application Specific Extension.
+ This tells the assembler to accept DSP Release 1 instructions.
+ `-mno-dsp' turns off this option.
+
+`-mdspr2'
+`-mno-dspr2'
+ Generate code for the DSP Release 2 Application Specific Extension.
+ This option implies `-mdsp'. This tells the assembler to accept
+ DSP Release 2 instructions. `-mno-dspr2' turns off this option.
+
+`-mdspr3'
+`-mno-dspr3'
+ Generate code for the DSP Release 3 Application Specific Extension.
+ This option implies `-mdsp' and `-mdspr2'. This tells the
+ assembler to accept DSP Release 3 instructions. `-mno-dspr3'
+ turns off this option.
+
+`-mmt'
+`-mno-mt'
+ Generate code for the MT Application Specific Extension. This
+ tells the assembler to accept MT instructions. `-mno-mt' turns
+ off this option.
+
+`-mmcu'
+`-mno-mcu'
+ Generate code for the MCU Application Specific Extension. This
+ tells the assembler to accept MCU instructions. `-mno-mcu' turns
+ off this option.
+
+`-mmsa'
+`-mno-msa'
+ Generate code for the MIPS SIMD Architecture Extension. This
+ tells the assembler to accept MSA instructions. `-mno-msa' turns
+ off this option.
+
+`-mxpa'
+`-mno-xpa'
+ Generate code for the MIPS eXtended Physical Address (XPA)
+ Extension. This tells the assembler to accept XPA instructions.
+ `-mno-xpa' turns off this option.
+
+`-mvirt'
+`-mno-virt'
+ Generate code for the Virtualization Application Specific
+ Extension. This tells the assembler to accept Virtualization
+ instructions. `-mno-virt' turns off this option.
+
+`-minsn32'
+`-mno-insn32'
+ Only use 32-bit instruction encodings when generating code for the
+ microMIPS processor. This option inhibits the use of any 16-bit
+ instructions. This is equivalent to putting `.set insn32' at the
+ start of the assembly file. `-mno-insn32' turns off this option.
+ This is equivalent to putting `.set noinsn32' at the start of the
+ assembly file. By default `-mno-insn32' is selected, allowing all
+ instructions to be used.
+
+`-mfix7000'
+`-mno-fix7000'
+ Cause nops to be inserted if the read of the destination register
+ of an mfhi or mflo instruction occurs in the following two
+ instructions.
+
+`-mfix-rm7000'
+`-mno-fix-rm7000'
+ Cause nops to be inserted if a dmult or dmultu instruction is
+ followed by a load instruction.
+
+`-mfix-loongson2f-jump'
+`-mno-fix-loongson2f-jump'
+ Eliminate instruction fetch from outside 256M region to work
+ around the Loongson2F `jump' instructions. Without it, under
+ extreme cases, the kernel may crash. The issue has been solved in
+ latest processor batches, but this fix has no side effect to them.
+
+`-mfix-loongson2f-nop'
+`-mno-fix-loongson2f-nop'
+ Replace nops by `or at,at,zero' to work around the Loongson2F
+ `nop' errata. Without it, under extreme cases, the CPU might
+ deadlock. The issue has been solved in later Loongson2F batches,
+ but this fix has no side effect to them.
+
+`-mfix-vr4120'
+`-mno-fix-vr4120'
+ Insert nops to work around certain VR4120 errata. This option is
+ intended to be used on GCC-generated code: it is not designed to
+ catch all problems in hand-written assembler code.
+
+`-mfix-vr4130'
+`-mno-fix-vr4130'
+ Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
+
+`-mfix-24k'
+`-mno-fix-24k'
+ Insert nops to work around the 24K `eret'/`deret' errata.
+
+`-mfix-cn63xxp1'
+`-mno-fix-cn63xxp1'
+ Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
+ certain CN63XXP1 errata.
+
+`-m4010'
+`-no-m4010'
+ Generate code for the LSI R4010 chip. This tells the assembler to
+ accept the R4010-specific instructions (`addciu', `ffc', etc.),
+ and to not schedule `nop' instructions around accesses to the `HI'
+ and `LO' registers. `-no-m4010' turns off this option.
+
+`-m4650'
+`-no-m4650'
+ Generate code for the MIPS R4650 chip. This tells the assembler
+ to accept the `mad' and `madu' instruction, and to not schedule
+ `nop' instructions around accesses to the `HI' and `LO' registers.
+ `-no-m4650' turns off this option.
+
+`-m3900'
+`-no-m3900'
+`-m4100'
+`-no-m4100'
+ For each option `-mNNNN', generate code for the MIPS RNNNN chip.
+ This tells the assembler to accept instructions specific to that
+ chip, and to schedule for that chip's hazards.
+
+`-march=CPU'
+ Generate code for a particular MIPS CPU. It is exactly equivalent
+ to `-mCPU', except that there are more value of CPU understood.
+ Valid CPU value are:
+
+ 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
+ vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
+ rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
+ 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
+ 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
+ 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
+ 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
+ 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1,
+ interaptiv, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1,
+ sb1a, i6400, p6600, loongson2e, loongson2f, loongson3a,
+ octeon, octeon+, octeon2, octeon3, xlr, xlp
+
+ For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms
+ for `Nf1_1'. These values are deprecated.
+
+`-mtune=CPU'
+ Schedule and tune for a particular MIPS CPU. Valid CPU values are
+ identical to `-march=CPU'.
+
+`-mabi=ABI'
+ Record which ABI the source code uses. The recognized arguments
+ are: `32', `n32', `o64', `64' and `eabi'.
+
+`-msym32'
+`-mno-sym32'
+ Equivalent to adding `.set sym32' or `.set nosym32' to the
+ beginning of the assembler input. *Note MIPS Symbol Sizes::.
+
+`-nocpp'
+ This option is ignored. It is accepted for command-line
+ compatibility with other assemblers, which use it to turn off C
+ style preprocessing. With GNU `as', there is no need for
+ `-nocpp', because the GNU assembler itself never runs the C
+ preprocessor.
+
+`-msoft-float'
+`-mhard-float'
+ Disable or enable floating-point instructions. Note that by
+ default floating-point instructions are always allowed even with
+ CPU targets that don't have support for these instructions.
+
+`-msingle-float'
+`-mdouble-float'
+ Disable or enable double-precision floating-point operations. Note
+ that by default double-precision floating-point operations are
+ always allowed even with CPU targets that don't have support for
+ these operations.
+
+`--construct-floats'
+`--no-construct-floats'
+ The `--no-construct-floats' option disables the construction of
+ double width floating point constants by loading the two halves of
+ the value into the two single width floating point registers that
+ make up the double width register. This feature is useful if the
+ processor support the FR bit in its status register, and this bit
+ is known (by the programmer) to be set. This bit prevents the
+ aliasing of the double width register by the single width
+ registers.
+
+ By default `--construct-floats' is selected, allowing construction
+ of these floating point constants.
+
+`--relax-branch'
+`--no-relax-branch'
+ The `--relax-branch' option enables the relaxation of out-of-range
+ branches. Any branches whose target cannot be reached directly are
+ converted to a small instruction sequence including an
+ inverse-condition branch to the physically next instruction, and a
+ jump to the original target is inserted between the two
+ instructions. In PIC code the jump will involve further
+ instructions for address calculation.
+
+ The `BC1ANY2F', `BC1ANY2T', `BC1ANY4F', `BC1ANY4T', `BPOSGE32' and
+ `BPOSGE64' instructions are excluded from relaxation, because they
+ have no complementing counterparts. They could be relaxed with
+ the use of a longer sequence involving another branch, however
+ this has not been implemented and if their target turns out of
+ reach, they produce an error even if branch relaxation is enabled.
+
+ Also no MIPS16 branches are ever relaxed.
+
+ By default `--no-relax-branch' is selected, causing any
+ out-of-range branches to produce an error.
+
+`-mignore-branch-isa'
+`-mno-ignore-branch-isa'
+ Ignore branch checks for invalid transitions between ISA modes.
+
+ The semantics of branches does not provide for an ISA mode switch,
+ so in most cases the ISA mode a branch has been encoded for has to
+ be the same as the ISA mode of the branch's target label. If the
+ ISA modes do not match, then such a branch, if taken, will cause
+ the ISA mode to remain unchanged and instructions that follow will
+ be executed in the wrong ISA mode causing the program to misbehave
+ or crash.
+
+ In the case of the `BAL' instruction it may be possible to relax
+ it to an equivalent `JALX' instruction so that the ISA mode is
+ switched at the run time as required. For other branches no
+ relaxation is possible and therefore GAS has checks implemented
+ that verify in branch assembly that the two ISA modes match, and
+ report an error otherwise so that the problem with code can be
+ diagnosed at the assembly time rather than at the run time.
+
+ However some assembly code, including generated code produced by
+ some versions of GCC, may incorrectly include branches to data
+ labels, which appear to require a mode switch but are either dead
+ or immediately followed by valid instructions encoded for the same
+ ISA the branch has been encoded for. While not strictly correct
+ at the source level such code will execute as intended, so to help
+ with these cases `-mignore-branch-isa' is supported which disables
+ ISA mode checks for branches.
+
+ By default `-mno-ignore-branch-isa' is selected, causing any
+ invalid branch requiring a transition between ISA modes to produce
+ an error.
+
+`-mnan=ENCODING'
+ This option indicates whether the source code uses the IEEE 2008
+ NaN encoding (`-mnan=2008') or the original MIPS encoding
+ (`-mnan=legacy'). It is equivalent to adding a `.nan' directive
+ to the beginning of the source file. *Note MIPS NaN Encodings::.
+
+ `-mnan=legacy' is the default if no `-mnan' option or `.nan'
+ directive is used.
+
+`--trap'
+`--no-break'
+ `as' automatically macro expands certain division and
+ multiplication instructions to check for overflow and division by
+ zero. This option causes `as' to generate code to take a trap
+ exception rather than a break exception when an error is detected.
+ The trap instructions are only supported at Instruction Set
+ Architecture level 2 and higher.
+
+`--break'
+`--no-trap'
+ Generate code to take a break exception rather than a trap
+ exception when an error is detected. This is the default.
+
+`-mpdr'
+`-mno-pdr'
+ Control generation of `.pdr' sections. Off by default on IRIX, on
+ elsewhere.
+
+`-mshared'
+`-mno-shared'
+ When generating code using the Unix calling conventions (selected
+ by `-KPIC' or `-mcall_shared'), gas will normally generate code
+ which can go into a shared library. The `-mno-shared' option
+ tells gas to generate code which uses the calling convention, but
+ can not go into a shared library. The resulting code is slightly
+ more efficient. This option only affects the handling of the
+ `.cpload' and `.cpsetup' pseudo-ops.
+
+
+File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent
+
+9.27.2 High-level assembly macros
+---------------------------------
+
+MIPS assemblers have traditionally provided a wider range of
+instructions than the MIPS architecture itself. These extra
+instructions are usually referred to as "macro" instructions (1).
+
+ Some MIPS macro instructions extend an underlying architectural
+instruction while others are entirely new. An example of the former
+type is `and', which allows the third operand to be either a register
+or an arbitrary immediate value. Examples of the latter type include
+`bgt', which branches to the third operand when the first operand is
+greater than the second operand, and `ulh', which implements an
+unaligned 2-byte load.
+
+ One of the most common extensions provided by macros is to expand
+memory offsets to the full address range (32 or 64 bits) and to allow
+symbolic offsets such as `my_data + 4' to be used in place of integer
+constants. For example, the architectural instruction `lbu' allows
+only a signed 16-bit offset, whereas the macro `lbu' allows code such
+as `lbu $4,array+32769($5)'. The implementation of these symbolic
+offsets depends on several factors, such as whether the assembler is
+generating SVR4-style PIC (selected by `-KPIC', *note Assembler
+options: MIPS Options.), the size of symbols (*note Directives to
+override the size of symbols: MIPS Symbol Sizes.), and the small data
+limit (*note Controlling the use of small data accesses: MIPS Small
+Data.).
+
+ Sometimes it is undesirable to have one assembly instruction expand
+to several machine instructions. The directive `.set nomacro' tells
+the assembler to warn when this happens. `.set macro' restores the
+default behavior.
+
+ Some macro instructions need a temporary register to store
+intermediate results. This register is usually `$1', also known as
+`$at', but it can be changed to any core register REG using `.set
+at=REG'. Note that `$at' always refers to `$1' regardless of which
+register is being used as the temporary register.
+
+ Implicit uses of the temporary register in macros could interfere
+with explicit uses in the assembly code. The assembler therefore warns
+whenever it sees an explicit use of the temporary register. The
+directive `.set noat' silences this warning while `.set at' restores
+the default behavior. It is safe to use `.set noat' while `.set
+nomacro' is in effect since single-instruction macros never need a
+temporary register.
+
+ Note that while the GNU assembler provides these macros for
+compatibility, it does not make any attempt to optimize them with the
+surrounding code.
+
+ ---------- Footnotes ----------
+
+ (1) The term "macro" is somewhat overloaded here, since these macros
+have no relation to those defined by `.macro', *note `.macro': Macro.
+
+
+File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent
+
+9.27.3 Directives to override the size of symbols
+-------------------------------------------------
+
+The n64 ABI allows symbols to have any 64-bit value. Although this
+provides a great deal of flexibility, it means that some macros have
+much longer expansions than their 32-bit counterparts. For example,
+the non-PIC expansion of `dla $4,sym' is usually:
+
+ lui $4,%highest(sym)
+ lui $1,%hi(sym)
+ daddiu $4,$4,%higher(sym)
+ daddiu $1,$1,%lo(sym)
+ dsll32 $4,$4,0
+ daddu $4,$4,$1
+
+ whereas the 32-bit expansion is simply:
+
+ lui $4,%hi(sym)
+ daddiu $4,$4,%lo(sym)
+
+ n64 code is sometimes constructed in such a way that all symbolic
+constants are known to have 32-bit values, and in such cases, it's
+preferable to use the 32-bit expansion instead of the 64-bit expansion.
+
+ You can use the `.set sym32' directive to tell the assembler that,
+from this point on, all expressions of the form `SYMBOL' or `SYMBOL +
+OFFSET' have 32-bit values. For example:
+
+ .set sym32
+ dla $4,sym
+ lw $4,sym+16
+ sw $4,sym+0x8000($4)
+
+ will cause the assembler to treat `sym', `sym+16' and `sym+0x8000'
+as 32-bit values. The handling of non-symbolic addresses is not
+affected.
+
+ The directive `.set nosym32' ends a `.set sym32' block and reverts
+to the normal behavior. It is also possible to change the symbol size
+using the command-line options `-msym32' and `-mno-sym32'.
+
+ These options and directives are always accepted, but at present,
+they have no effect for anything other than n64.
+
+
+File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent
+
+9.27.4 Controlling the use of small data accesses
+-------------------------------------------------
+
+It often takes several instructions to load the address of a symbol.
+For example, when `addr' is a 32-bit symbol, the non-PIC expansion of
+`dla $4,addr' is usually:
+
+ lui $4,%hi(addr)
+ daddiu $4,$4,%lo(addr)
+
+ The sequence is much longer when `addr' is a 64-bit symbol. *Note
+Directives to override the size of symbols: MIPS Symbol Sizes.
+
+ In order to cut down on this overhead, most embedded MIPS systems
+set aside a 64-kilobyte "small data" area and guarantee that all data
+of size N and smaller will be placed in that area. The limit N is
+passed to both the assembler and the linker using the command-line
+option `-G N', *note Assembler options: MIPS Options. Note that the
+same value of N must be used when linking and when assembling all input
+files to the link; any inconsistency could cause a relocation overflow
+error.
+
+ The size of an object in the `.bss' section is set by the `.comm' or
+`.lcomm' directive that defines it. The size of an external object may
+be set with the `.extern' directive. For example, `.extern sym,4'
+declares that the object at `sym' is 4 bytes in length, while leaving
+`sym' otherwise undefined.
+
+ When no `-G' option is given, the default limit is 8 bytes. The
+option `-G 0' prevents any data from being automatically classified as
+small.
+
+ It is also possible to mark specific objects as small by putting them
+in the special sections `.sdata' and `.sbss', which are "small"
+counterparts of `.data' and `.bss' respectively. The toolchain will
+treat such data as small regardless of the `-G' setting.
+
+ On startup, systems that support a small data area are expected to
+initialize register `$28', also known as `$gp', in such a way that
+small data can be accessed using a 16-bit offset from that register.
+For example, when `addr' is small data, the `dla $4,addr' instruction
+above is equivalent to:
+
+ daddiu $4,$28,%gp_rel(addr)
+
+ Small data is not supported for SVR4-style PIC.
+
+
+File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent
+
+9.27.5 Directives to override the ISA level
+-------------------------------------------
+
+GNU `as' supports an additional directive to change the MIPS
+Instruction Set Architecture level on the fly: `.set mipsN'. N should
+be a number from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3,
+64r5 or 64r6. The values other than 0 make the assembler accept
+instructions for the corresponding ISA level, from that point on in the
+assembly. `.set mipsN' affects not only which instructions are
+permitted, but also how certain macros are expanded. `.set mips0'
+restores the ISA level to its original level: either the level you
+selected with command line options, or the default for your
+configuration. You can use this feature to permit specific MIPS III
+instructions while assembling in 32 bit mode. Use this directive with
+care!
+
+ The `.set arch=CPU' directive provides even finer control. It
+changes the effective CPU target and allows the assembler to use
+instructions specific to a particular CPU. All CPUs supported by the
+`-march' command line option are also selectable by this directive.
+The original value is restored by `.set arch=default'.
+
+ The directive `.set mips16' puts the assembler into MIPS 16 mode, in
+which it will assemble instructions for the MIPS 16 processor. Use
+`.set nomips16' to return to normal 32 bit mode.
+
+ Traditional MIPS assemblers do not support this directive.
+
+ The directive `.set micromips' puts the assembler into microMIPS
+mode, in which it will assemble instructions for the microMIPS
+processor. Use `.set nomicromips' to return to normal 32 bit mode.
+
+ Traditional MIPS assemblers do not support this directive.
+
+
+File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent
+
+9.27.6 Directives to control code generation
+--------------------------------------------
+
+The `.module' directive allows command line options to be set directly
+from assembly. The format of the directive matches the `.set'
+directive but only those options which are relevant to a whole module
+are supported. The effect of a `.module' directive is the same as the
+corresponding command line option. Where `.set' directives support
+returning to a default then the `.module' directives do not as they
+define the defaults.
+
+ These module-level directives must appear first in assembly.
+
+ Traditional MIPS assemblers do not support this directive.
+
+ The directive `.set insn32' makes the assembler only use 32-bit
+instruction encodings when generating code for the microMIPS processor.
+This directive inhibits the use of any 16-bit instructions from that
+point on in the assembly. The `.set noinsn32' directive allows 16-bit
+instructions to be accepted.
+
+ Traditional MIPS assemblers do not support this directive.
+
+
+File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent
+
+9.27.7 Directives for extending MIPS 16 bit instructions
+--------------------------------------------------------
+
+By default, MIPS 16 instructions are automatically extended to 32 bits
+when necessary. The directive `.set noautoextend' will turn this off.
+When `.set noautoextend' is in effect, any 32 bit instruction must be
+explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The
+directive `.set autoextend' may be used to once again automatically
+extend instructions when necessary.
+
+ This directive is only meaningful when in MIPS 16 mode. Traditional
+MIPS assemblers do not support this directive.
+
+
+File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent
+
+9.27.8 Directive to mark data as an instruction
+-----------------------------------------------
+
+The `.insn' directive tells `as' that the following data is actually
+instructions. This makes a difference in MIPS 16 and microMIPS modes:
+when loading the address of a label which precedes instructions, `as'
+automatically adds 1 to the value, so that jumping to the loaded
+address will do the right thing.
+
+ The `.global' and `.globl' directives supported by `as' will by
+default mark the symbol as pointing to a region of data not code. This
+means that, for example, any instructions following such a symbol will
+not be disassembled by `objdump' as it will regard them as data. To
+change this behavior an optional section name can be placed after the
+symbol name in the `.global' directive. If this section exists and is
+known to be a code section, then the symbol will be marked as pointing
+at code not data. Ie the syntax for the directive is:
+
+ `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
+
+ Here is a short example:
+
+ .global foo .text, bar, baz .data
+ foo:
+ nop
+ bar:
+ .word 0x0
+ baz:
+ .word 0x1
+
+
+File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent
+
+9.27.9 Directives to control the FP ABI
+---------------------------------------
+
+* Menu:
+
+* MIPS FP ABI History:: History of FP ABIs
+* MIPS FP ABI Variants:: Supported FP ABIs
+* MIPS FP ABI Selection:: Automatic selection of FP ABI
+* MIPS FP ABI Compatibility:: Linking different FP ABI variants
+
+
+File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs
+
+9.27.9.1 History of FP ABIs
+...........................
+
+The MIPS ABIs support a variety of different floating-point extensions
+where calling-convention and register sizes vary for floating-point
+data. The extensions exist to support a wide variety of optional
+architecture features. The resulting ABI variants are generally
+incompatible with each other and must be tracked carefully.
+
+ Traditionally the use of an explicit `.gnu_attribute 4, N' directive
+is used to indicate which ABI is in use by a specific module. It was
+then left to the user to ensure that command line options and the
+selected ABI were compatible with some potential for inconsistencies.
+
+
+File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs
+
+9.27.9.2 Supported FP ABIs
+..........................
+
+The supported floating-point ABI variants are:
+
+`0 - No floating-point'
+ This variant is used to indicate that floating-point is not used
+ within the module at all and therefore has no impact on the ABI.
+ This is the default.
+
+`1 - Double-precision'
+ This variant indicates that double-precision support is used. For
+ 64-bit ABIs this means that 64-bit wide floating-point registers
+ are required. For 32-bit ABIs this means that 32-bit wide
+ floating-point registers are required and double-precision
+ operations use pairs of registers.
+
+`2 - Single-precision'
+ This variant indicates that single-precision support is used.
+ Double precision operations will be supported via soft-float
+ routines.
+
+`3 - Soft-float'
+ This variant indicates that although floating-point support is
+ used all operations are emulated in software. This means the ABI
+ is modified to pass all floating-point data in general-purpose
+ registers.
+
+`4 - Deprecated'
+ This variant existed as an initial attempt at supporting 64-bit
+ wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This
+ has been superseded by 5, 6 and 7.
+
+`5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU'
+ This variant is used by 32-bit ABIs to indicate that the
+ floating-point code in the module has been designed to operate
+ correctly with either 32-bit wide or 64-bit wide floating-point
+ registers. Double-precision support is used. Only O32 currently
+ supports this variant and requires a minimum architecture of MIPS
+ II.
+
+`6 - Double-precision 32-bit FPU, 64-bit FPU'
+ This variant is used by 32-bit ABIs to indicate that the
+ floating-point code in the module requires 64-bit wide
+ floating-point registers. Double-precision support is used. Only
+ O32 currently supports this variant and requires a minimum
+ architecture of MIPS32r2.
+
+`7 - Double-precision compat 32-bit FPU, 64-bit FPU'
+ This variant is used by 32-bit ABIs to indicate that the
+ floating-point code in the module requires 64-bit wide
+ floating-point registers. Double-precision support is used. This
+ differs from the previous ABI as it restricts use of odd-numbered
+ single-precision registers. Only O32 currently supports this
+ variant and requires a minimum architecture of MIPS32r2.
+
+
+File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs
+
+9.27.9.3 Automatic selection of FP ABI
+......................................
+
+In order to simplify and add safety to the process of selecting the
+correct floating-point ABI, the assembler will automatically infer the
+correct `.gnu_attribute 4, N' directive based on command line options
+and `.module' overrides. Where an explicit `.gnu_attribute 4, N'
+directive has been seen then a warning will be raised if it does not
+match an inferred setting.
+
+ The floating-point ABI is inferred as follows. If `-msoft-float'
+has been used the module will be marked as soft-float. If
+`-msingle-float' has been used then the module will be marked as
+single-precision. The remaining ABIs are then selected based on the FP
+register width. Double-precision is selected if the width of GP and FP
+registers match and the special double-precision variants for 32-bit
+ABIs are then selected depending on `-mfpxx', `-mfp64' and
+`-mno-odd-spreg'.
+
+
+File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs
+
+9.27.9.4 Linking different FP ABI variants
+..........................................
+
+Modules using the default FP ABI (no floating-point) can be linked with
+any other (singular) FP ABI variant.
+
+ Special compatibility support exists for O32 with the four
+double-precision FP ABI variants. The `-mfpxx' FP ABI is specifically
+designed to be compatible with the standard double-precision ABI and the
+`-mfp64' FP ABIs. This makes it desirable for O32 modules to be built
+as `-mfpxx' to ensure the maximum compatibility with other modules
+produced for more specific needs. The only FP ABIs which cannot be
+linked together are the standard double-precision ABI and the full
+`-mfp64' ABI with `-modd-spreg'.
+
+
+File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent
+
+9.27.10 Directives to record which NaN encoding is being used
+-------------------------------------------------------------
+
+The IEEE 754 floating-point standard defines two types of not-a-number
+(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version
+of the standard did not specify how these two types should be
+distinguished. Most implementations followed the i387 model, in which
+the first bit of the significand is set for quiet NaNs and clear for
+signalling NaNs. However, the original MIPS implementation assigned the
+opposite meaning to the bit, so that it was set for signalling NaNs and
+clear for quiet NaNs.
+
+ The 2008 revision of the standard formally suggested the i387 choice
+and as from Sep 2012 the current release of the MIPS architecture
+therefore optionally supports that form. Code that uses one NaN
+encoding would usually be incompatible with code that uses the other
+NaN encoding, so MIPS ELF objects have a flag (`EF_MIPS_NAN2008') to
+record which encoding is being used.
+
+ Assembly files can use the `.nan' directive to select between the
+two encodings. `.nan 2008' says that the assembly file uses the IEEE
+754-2008 encoding while `.nan legacy' says that the file uses the
+original MIPS encoding. If several `.nan' directives are given, the
+final setting is the one that is used.
+
+ The command-line options `-mnan=legacy' and `-mnan=2008' can be used
+instead of `.nan legacy' and `.nan 2008' respectively. However, any
+`.nan' directive overrides the command-line setting.
+
+ `.nan legacy' is the default if no `.nan' directive or `-mnan'
+option is given.
+
+ Note that GNU `as' does not produce NaNs itself and therefore these
+directives do not affect code generation. They simply control the
+setting of the `EF_MIPS_NAN2008' flag.
+
+ Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent
+
+9.27.11 Directives to save and restore options
+----------------------------------------------
+
+The directives `.set push' and `.set pop' may be used to save and
+restore the current settings for all the options which are controlled
+by `.set'. The `.set push' directive saves the current settings on a
+stack. The `.set pop' directive pops the stack and restores the
+settings.
+
+ These directives can be useful inside an macro which must change an
+option such as the ISA level or instruction reordering but does not want
+to change the state of the code which invoked the macro.
+
+ Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent
+
+9.27.12 Directives to control generation of MIPS ASE instructions
+-----------------------------------------------------------------
+
+The directive `.set mips3d' makes the assembler accept instructions
+from the MIPS-3D Application Specific Extension from that point on in
+the assembly. The `.set nomips3d' directive prevents MIPS-3D
+instructions from being accepted.
+
+ The directive `.set smartmips' makes the assembler accept
+instructions from the SmartMIPS Application Specific Extension to the
+MIPS32 ISA from that point on in the assembly. The `.set nosmartmips'
+directive prevents SmartMIPS instructions from being accepted.
+
+ The directive `.set mdmx' makes the assembler accept instructions
+from the MDMX Application Specific Extension from that point on in the
+assembly. The `.set nomdmx' directive prevents MDMX instructions from
+being accepted.
+
+ The directive `.set dsp' makes the assembler accept instructions
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly. The `.set nodsp' directive prevents DSP Release 1
+instructions from being accepted.
+
+ The directive `.set dspr2' makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly. This directive implies `.set dsp'. The `.set
+nodspr2' directive prevents DSP Release 2 instructions from being
+accepted.
+
+ The directive `.set dspr3' makes the assembler accept instructions
+from the DSP Release 3 Application Specific Extension from that point
+on in the assembly. This directive implies `.set dsp' and `.set
+dspr2'. The `.set nodspr3' directive prevents DSP Release 3
+instructions from being accepted.
+
+ The directive `.set mt' makes the assembler accept instructions from
+the MT Application Specific Extension from that point on in the
+assembly. The `.set nomt' directive prevents MT instructions from
+being accepted.
+
+ The directive `.set mcu' makes the assembler accept instructions
+from the MCU Application Specific Extension from that point on in the
+assembly. The `.set nomcu' directive prevents MCU instructions from
+being accepted.
+
+ The directive `.set msa' makes the assembler accept instructions
+from the MIPS SIMD Architecture Extension from that point on in the
+assembly. The `.set nomsa' directive prevents MSA instructions from
+being accepted.
+
+ The directive `.set virt' makes the assembler accept instructions
+from the Virtualization Application Specific Extension from that point
+on in the assembly. The `.set novirt' directive prevents Virtualization
+instructions from being accepted.
+
+ The directive `.set xpa' makes the assembler accept instructions
+from the XPA Extension from that point on in the assembly. The `.set
+noxpa' directive prevents XPA instructions from being accepted.
+
+ Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent
+
+9.27.13 Directives to override floating-point options
+-----------------------------------------------------
+
+The directives `.set softfloat' and `.set hardfloat' provide finer
+control of disabling and enabling float-point instructions. These
+directives always override the default (that hard-float instructions
+are accepted) or the command-line options (`-msoft-float' and
+`-mhard-float').
+
+ The directives `.set singlefloat' and `.set doublefloat' provide
+finer control of disabling and enabling double-precision float-point
+operations. These directives always override the default (that
+double-precision operations are accepted) or the command-line options
+(`-msingle-float' and `-mdouble-float').
+
+ Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent
+
+9.27.14 Syntactical considerations for the MIPS assembler
+---------------------------------------------------------
+
+* Menu:
+
+* MIPS-Chars:: Special Characters
+
+
+File: as.info, Node: MIPS-Chars, Up: MIPS Syntax
+
+9.27.14.1 Special Characters
+............................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line, the whole line is
+treated as a comment, but in this case the line can also be a logical
+line number directive (*note Comments::) or a preprocessor control
+command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
+
+9.28 MMIX Dependent Features
+============================
+
+* Menu:
+
+* MMIX-Opts:: Command-line Options
+* MMIX-Expand:: Instruction expansion
+* MMIX-Syntax:: Syntax
+* MMIX-mmixal:: Differences to `mmixal' syntax and semantics
+
+
+File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent
+
+9.28.1 Command-line Options
+---------------------------
+
+The MMIX version of `as' has some machine-dependent options.
+
+ When `--fixed-special-register-names' is specified, only the register
+names specified in *Note MMIX-Regs:: are recognized in the instructions
+`PUT' and `GET'.
+
+ You can use the `--globalize-symbols' to make all symbols global.
+This option is useful when splitting up a `mmixal' program into several
+files.
+
+ The `--gnu-syntax' turns off most syntax compatibility with
+`mmixal'. Its usability is currently doubtful.
+
+ The `--relax' option is not fully supported, but will eventually make
+the object file prepared for linker relaxation.
+
+ If you want to avoid inadvertently calling a predefined symbol and
+would rather get an error, for example when using `as' with a compiler
+or other machine-generated code, specify `--no-predefined-syms'. This
+turns off built-in predefined definitions of all such symbols,
+including rounding-mode symbols, segment symbols, `BIT' symbols, and
+`TRAP' symbols used in `mmix' "system calls". It also turns off
+predefined special-register names, except when used in `PUT' and `GET'
+instructions.
+
+ By default, some instructions are expanded to fit the size of the
+operand or an external symbol (*note MMIX-Expand::). By passing
+`--no-expand', no such expansion will be done, instead causing errors
+at link time if the operand does not fit.
+
+ The `mmixal' documentation (*note mmixsite::) specifies that global
+registers allocated with the `GREG' directive (*note MMIX-greg::) and
+initialized to the same non-zero value, will refer to the same global
+register. This isn't strictly enforceable in `as' since the final
+addresses aren't known until link-time, but it will do an effort unless
+the `--no-merge-gregs' option is specified. (Register merging isn't
+yet implemented in `ld'.)
+
+ `as' will warn every time it expands an instruction to fit an
+operand unless the option `-x' is specified. It is believed that this
+behaviour is more useful than just mimicking `mmixal''s behaviour, in
+which instructions are only expanded if the `-x' option is specified,
+and assembly fails otherwise, when an instruction needs to be expanded.
+It needs to be kept in mind that `mmixal' is both an assembler and
+linker, while `as' will expand instructions that at link stage can be
+contracted. (Though linker relaxation isn't yet implemented in `ld'.)
+The option `-x' also imples `--linker-allocated-gregs'.
+
+ If instruction expansion is enabled, `as' can expand a `PUSHJ'
+instruction into a series of instructions. The shortest expansion is
+to not expand it, but just mark the call as redirectable to a stub,
+which `ld' creates at link-time, but only if the original `PUSHJ'
+instruction is found not to reach the target. The stub consists of the
+necessary instructions to form a jump to the target. This happens if
+`as' can assert that the `PUSHJ' instruction can reach such a stub.
+The option `--no-pushj-stubs' disables this shorter expansion, and the
+longer series of instructions is then created at assembly-time. The
+option `--no-stubs' is a synonym, intended for compatibility with
+future releases, where generation of stubs for other instructions may
+be implemented.
+
+ Usually a two-operand-expression (*note GREG-base::) without a
+matching `GREG' directive is treated as an error by `as'. When the
+option `--linker-allocated-gregs' is in effect, they are instead passed
+through to the linker, which will allocate as many global registers as
+is needed.
+
+
+File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent
+
+9.28.2 Instruction expansion
+----------------------------
+
+When `as' encounters an instruction with an operand that is either not
+known or does not fit the operand size of the instruction, `as' (and
+`ld') will expand the instruction into a sequence of instructions
+semantically equivalent to the operand fitting the instruction.
+Expansion will take place for the following instructions:
+
+`GETA'
+ Expands to a sequence of four instructions: `SETL', `INCML',
+ `INCMH' and `INCH'. The operand must be a multiple of four.
+
+Conditional branches
+ A branch instruction is turned into a branch with the complemented
+ condition and prediction bit over five instructions; four
+ instructions setting `$255' to the operand value, which like with
+ `GETA' must be a multiple of four, and a final `GO $255,$255,0'.
+
+`PUSHJ'
+ Similar to expansion for conditional branches; four instructions
+ set `$255' to the operand value, followed by a `PUSHGO
+ $255,$255,0'.
+
+`JMP'
+ Similar to conditional branches and `PUSHJ'. The final instruction
+ is `GO $255,$255,0'.
+
+ The linker `ld' is expected to shrink these expansions for code
+assembled with `--relax' (though not currently implemented).
+
+
+File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent
+
+9.28.3 Syntax
+-------------
+
+The assembly syntax is supposed to be upward compatible with that
+described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
+Volume 1'. Draft versions of those chapters as well as other MMIX
+information is located at
+`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code
+examples from the mmixal package located there should work unmodified
+when assembled and linked as single files, with a few noteworthy
+exceptions (*note MMIX-mmixal::).
+
+ Before an instruction is emitted, the current location is aligned to
+the next four-byte boundary. If a label is defined at the beginning of
+the line, its value will be the aligned value.
+
+ In addition to the traditional hex-prefix `0x', a hexadecimal number
+can also be specified by the prefix character `#'.
+
+ After all operands to an MMIX instruction or directive have been
+specified, the rest of the line is ignored, treated as a comment.
+
+* Menu:
+
+* MMIX-Chars:: Special Characters
+* MMIX-Symbols:: Symbols
+* MMIX-Regs:: Register Names
+* MMIX-Pseudos:: Assembler Directives
+
+
+File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax
+
+9.28.3.1 Special Characters
+...........................
+
+The characters `*' and `#' are line comment characters; each start a
+comment at the beginning of a line, but only at the beginning of a
+line. A `#' prefixes a hexadecimal number if found elsewhere on a
+line. If a `#' appears at the start of a line the whole line is
+treated as a comment, but the line can also act as a logical line
+number directive (*note Comments::) or a preprocessor control command
+(*note Preprocessing::).
+
+ Two other characters, `%' and `!', each start a comment anywhere on
+the line. Thus you can't use the `modulus' and `not' operators in
+expressions normally associated with these two characters.
+
+ A `;' is a line separator, treated as a new-line, so separate
+instructions can be specified on a single line.
+
+
+File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax
+
+9.28.3.2 Symbols
+................
+
+The character `:' is permitted in identifiers. There are two
+exceptions to it being treated as any other symbol character: if a
+symbol begins with `:', it means that the symbol is in the global
+namespace and that the current prefix should not be prepended to that
+symbol (*note MMIX-prefix::). The `:' is then not considered part of
+the symbol. For a symbol in the label position (first on a line), a `:'
+at the end of a symbol is silently stripped off. A label is permitted,
+but not required, to be followed by a `:', as with many other assembly
+formats.
+
+ The character `@' in an expression, is a synonym for `.', the
+current location.
+
+ In addition to the common forward and backward local symbol formats
+(*note Symbol Names::), they can be specified with upper-case `B' and
+`F', as in `8B' and `9F'. A local label defined for the current
+position is written with a `H' appended to the number:
+ 3H LDB $0,$1,2
+ This and traditional local-label formats cannot be mixed: a label
+must be defined and referred to using the same format.
+
+ There's a minor caveat: just as for the ordinary local symbols, the
+local symbols are translated into ordinary symbols using control
+characters are to hide the ordinal number of the symbol.
+Unfortunately, these symbols are not translated back in error messages.
+Thus you may see confusing error messages when local symbols are used.
+Control characters `\003' (control-C) and `\004' (control-D) are used
+for the MMIX-specific local-symbol syntax.
+
+ The symbol `Main' is handled specially; it is always global.
+
+ By defining the symbols `__.MMIX.start..text' and
+`__.MMIX.start..data', the address of respectively the `.text' and
+`.data' segments of the final program can be defined, though when
+linking more than one object file, the code or data in the object file
+containing the symbol is not guaranteed to be start at that position;
+just the final executable. *Note MMIX-loc::.
+
+
+File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax
+
+9.28.3.3 Register names
+.......................
+
+Local and global registers are specified as `$0' to `$255'. The
+recognized special register names are `rJ', `rA', `rB', `rC', `rD',
+`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
+`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
+`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special
+register names.
+
+ Local and global symbols can be equated to register names and used in
+place of ordinary registers.
+
+ Similarly for special registers, local and global symbols can be
+used. Also, symbols equated from numbers and constant expressions are
+allowed in place of a special register, except when either of the
+options `--no-predefined-syms' and `--fixed-special-register-names' are
+specified. Then only the special register names above are allowed for
+the instructions having a special register operand; `GET' and `PUT'.
+
+
+File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax
+
+9.28.3.4 Assembler Directives
+.............................
+
+`LOC'
+ The `LOC' directive sets the current location to the value of the
+ operand field, which may include changing sections. If the
+ operand is a constant, the section is set to either `.data' if the
+ value is `0x2000000000000000' or larger, else it is set to `.text'.
+ Within a section, the current location may only be changed to
+ monotonically higher addresses. A LOC expression must be a
+ previously defined symbol or a "pure" constant.
+
+ An example, which sets the label PREV to the current location, and
+ updates the current location to eight bytes forward:
+ prev LOC @+8
+
+ When a LOC has a constant as its operand, a symbol
+ `__.MMIX.start..text' or `__.MMIX.start..data' is defined
+ depending on the address as mentioned above. Each such symbol is
+ interpreted as special by the linker, locating the section at that
+ address. Note that if multiple files are linked, the first object
+ file with that section will be mapped to that address (not
+ necessarily the file with the LOC definition).
+
+`LOCAL'
+ Example:
+ LOCAL external_symbol
+ LOCAL 42
+ .local asymbol
+
+ This directive-operation generates a link-time assertion that the
+ operand does not correspond to a global register. The operand is
+ an expression that at link-time resolves to a register symbol or a
+ number. A number is treated as the register having that number.
+ There is one restriction on the use of this directive: the
+ pseudo-directive must be placed in a section with contents, code
+ or data.
+
+`IS'
+ The `IS' directive:
+ asymbol IS an_expression
+ sets the symbol `asymbol' to `an_expression'. A symbol may not be
+ set more than once using this directive. Local labels may be set
+ using this directive, for example:
+ 5H IS @+4
+
+`GREG'
+ This directive reserves a global register, gives it an initial
+ value and optionally gives it a symbolic name. Some examples:
+
+ areg GREG
+ breg GREG data_value
+ GREG data_buffer
+ .greg creg, another_data_value
+
+ The symbolic register name can be used in place of a (non-special)
+ register. If a value isn't provided, it defaults to zero. Unless
+ the option `--no-merge-gregs' is specified, non-zero registers
+ allocated with this directive may be eliminated by `as'; another
+ register with the same value used in its place. Any of the
+ instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
+ `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
+ `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
+ `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
+ have a value nearby an initial value in place of its second and
+ third operands. Here, "nearby" is defined as within the range
+ 0...255 from the initial value of such an allocated register.
+
+ buffer1 BYTE 0,0,0,0,0
+ buffer2 BYTE 0,0,0,0,0
+ ...
+ GREG buffer1
+ LDOU $42,buffer2
+ In the example above, the `Y' field of the `LDOUI' instruction
+ (LDOU with a constant Z) will be replaced with the global register
+ allocated for `buffer1', and the `Z' field will have the value 5,
+ the offset from `buffer1' to `buffer2'. The result is equivalent
+ to this code:
+ buffer1 BYTE 0,0,0,0,0
+ buffer2 BYTE 0,0,0,0,0
+ ...
+ tmpreg GREG buffer1
+ LDOU $42,tmpreg,(buffer2-buffer1)
+
+ Global registers allocated with this directive are allocated in
+ order higher-to-lower within a file. Other than that, the exact
+ order of register allocation and elimination is undefined. For
+ example, the order is undefined when more than one file with such
+ directives are linked together. With the options `-x' and
+ `--linker-allocated-gregs', `GREG' directives for two-operand
+ cases like the one mentioned above can be omitted. Sufficient
+ global registers will then be allocated by the linker.
+
+`BYTE'
+ The `BYTE' directive takes a series of operands separated by a
+ comma. If an operand is a string (*note Strings::), each
+ character of that string is emitted as a byte. Other operands
+ must be constant expressions without forward references, in the
+ range 0...255. If you need operands having expressions with
+ forward references, use `.byte' (*note Byte::). An operand can be
+ omitted, defaulting to a zero value.
+
+`WYDE'
+`TETRA'
+`OCTA'
+ The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
+ four and eight bytes size respectively. Before anything else
+ happens for the directive, the current location is aligned to the
+ respective constant-size boundary. If a label is defined at the
+ beginning of the line, its value will be that after the alignment.
+ A single operand can be omitted, defaulting to a zero value
+ emitted for the directive. Operands can be expressed as strings
+ (*note Strings::), in which case each character in the string is
+ emitted as a separate constant of the size indicated by the
+ directive.
+
+`PREFIX'
+ The `PREFIX' directive sets a symbol name prefix to be prepended to
+ all symbols (except local symbols, *note MMIX-Symbols::), that are
+ not prefixed with `:', until the next `PREFIX' directive. Such
+ prefixes accumulate. For example,
+ PREFIX a
+ PREFIX b
+ c IS 0
+ defines a symbol `abc' with the value 0.
+
+`BSPEC'
+`ESPEC'
+ A pair of `BSPEC' and `ESPEC' directives delimit a section of
+ special contents (without specified semantics). Example:
+ BSPEC 42
+ TETRA 1,2,3
+ ESPEC
+ The single operand to `BSPEC' must be number in the range 0...255.
+ The `BSPEC' number 80 is used by the GNU binutils implementation.
+
+
+File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent
+
+9.28.4 Differences to `mmixal'
+------------------------------
+
+The binutils `as' and `ld' combination has a few differences in
+function compared to `mmixal' (*note mmixsite::).
+
+ The replacement of a symbol with a GREG-allocated register (*note
+GREG-base::) is not handled the exactly same way in `as' as in
+`mmixal'. This is apparent in the `mmixal' example file `inout.mms',
+where different registers with different offsets, eventually yielding
+the same address, are used in the first instruction. This type of
+difference should however not affect the function of any program unless
+it has specific assumptions about the allocated register number.
+
+ Line numbers (in the `mmo' object format) are currently not
+supported.
+
+ Expression operator precedence is not that of mmixal: operator
+precedence is that of the C programming language. It's recommended to
+use parentheses to explicitly specify wanted operator precedence
+whenever more than one type of operators are used.
+
+ The serialize unary operator `&', the fractional division operator
+`//', the logical not operator `!' and the modulus operator `%' are not
+available.
+
+ Symbols are not global by default, unless the option
+`--globalize-symbols' is passed. Use the `.global' directive to
+globalize symbols (*note Global::).
+
+ Operand syntax is a bit stricter with `as' than `mmixal'. For
+example, you can't say `addu 1,2,3', instead you must write `addu
+$1,$2,3'.
+
+ You can't LOC to a lower address than those already visited (i.e.,
+"backwards").
+
+ A LOC directive must come before any emitted code.
+
+ Predefined symbols are visible as file-local symbols after use. (In
+the ELF file, that is--the linked mmo file has no notion of a file-local
+symbol.)
+
+ Some mapping of constant expressions to sections in LOC expressions
+is attempted, but that functionality is easily confused and should be
+avoided unless compatibility with `mmixal' is required. A LOC
+expression to `0x2000000000000000' or higher, maps to the `.data'
+section and lower addresses map to the `.text' section (*note
+MMIX-loc::).
+
+ The code and data areas are each contiguous. Sparse programs with
+far-away LOC directives will take up the same amount of space as a
+contiguous program with zeros filled in the gaps between the LOC
+directives. If you need sparse programs, you might try and get the
+wanted effect with a linker script and splitting up the code parts into
+sections (*note Section::). Assembly code for this, to be compatible
+with `mmixal', would look something like:
+ .if 0
+ LOC away_expression
+ .else
+ .section away,"ax"
+ .fi
+ `as' will not execute the LOC directive and `mmixal' ignores the
+lines with `.'. This construct can be used generally to help
+compatibility.
+
+ Symbols can't be defined twice-not even to the same value.
+
+ Instruction mnemonics are recognized case-insensitive, though the
+`IS' and `GREG' pseudo-operations must be specified in upper-case
+characters.
+
+ There's no unicode support.
+
+ The following is a list of programs in `mmix.tar.gz', available at
+`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last
+checked with the version dated 2001-08-25 (md5sum
+c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
+not assemble with `as':
+
+`silly.mms'
+ LOC to a previous address.
+
+`sim.mms'
+ Redefines symbol `Done'.
+
+`test.mms'
+ Uses the serial operator `&'.
+
+
+File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies
+
+9.29 MSP 430 Dependent Features
+===============================
+
+* Menu:
+
+* MSP430 Options:: Options
+* MSP430 Syntax:: Syntax
+* MSP430 Floating Point:: Floating Point
+* MSP430 Directives:: MSP 430 Machine Directives
+* MSP430 Opcodes:: Opcodes
+* MSP430 Profiling Capability:: Profiling Capability
+
+
+File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent
+
+9.29.1 Options
+--------------
+
+`-mmcu'
+ selects the mcu architecture. If the architecture is 430Xv2 then
+ this also enables NOP generation unless the `-mN' is also
+ specified.
+
+`-mcpu'
+ selects the cpu architecture. If the architecture is 430Xv2 then
+ this also enables NOP generation unless the `-mN' is also
+ specified.
+
+`-msilicon-errata=NAME[,NAME...]'
+ Implements a fixup for named silicon errata. Multiple silicon
+ errata can be specified by multiple uses of the `-msilicon-errata'
+ option and/or by including the errata names, separated by commas,
+ on an individual `-msilicon-errata' option. Errata names
+ currently recognised by the assembler are:
+
+ `cpu4'
+ `PUSH #4' and `PUSH #8' need longer encodings on the MSP430.
+ This option is enabled by default, and cannot be disabled.
+
+ `cpu8'
+ Do not set the `SP' to an odd value.
+
+ `cpu11'
+ Do not update the `SR' and the `PC' in the same instruction.
+
+ `cpu12'
+ Do not use the `PC' in a `CMP' or `BIT' instruction.
+
+ `cpu13'
+ Do not use an arithmetic instruction to modify the `SR'.
+
+ `cpu19'
+ Insert `NOP' after `CPUOFF'.
+
+`-msilicon-errata-warn=NAME[,NAME...]'
+ Like the `-msilicon-errata' option except that instead of fixing
+ the specified errata, a warning message is issued instead. This
+ option can be used alongside `-msilicon-errata' to generate
+ messages whenever a problem is fixed, or on its own in order to
+ inspect code for potential problems.
+
+`-mP'
+ enables polymorph instructions handler.
+
+`-mQ'
+ enables relaxation at assembly time. DANGEROUS!
+
+`-ml'
+ indicates that the input uses the large code model.
+
+`-mn'
+ enables the generation of a NOP instruction following any
+ instruction that might change the interrupts enabled/disabled
+ state. The pipelined nature of the MSP430 core means that any
+ instruction that changes the interrupt state (`EINT', `DINT', `BIC
+ #8, SR', `BIS #8, SR' or `MOV.W <>, SR') must be followed by a NOP
+ instruction in order to ensure the correct processing of
+ interrupts. By default it is up to the programmer to supply these
+ NOP instructions, but this command line option enables the
+ automatic insertion by the assembler, if they are missing.
+
+`-mN'
+ disables the generation of a NOP instruction following any
+ instruction that might change the interrupts enabled/disabled
+ state. This is the default behaviour.
+
+`-my'
+ tells the assembler to generate a warning message if a NOP does not
+ immediately forllow an instruction that enables or disables
+ interrupts. This is the default.
+
+ Note that this option can be stacked with the `-mn' option so that
+ the assembler will both warn about missing NOP instructions and
+ then insert them automatically.
+
+`-mY'
+ disables warnings about missing NOP instructions.
+
+`-md'
+ mark the object file as one that requires data to copied from ROM
+ to RAM at execution startup. Disabled by default.
+
+
+
+File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent
+
+9.29.2 Syntax
+-------------
+
+* Menu:
+
+* MSP430-Macros:: Macros
+* MSP430-Chars:: Special Characters
+* MSP430-Regs:: Register Names
+* MSP430-Ext:: Assembler Extensions
+
+
+File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax
+
+9.29.2.1 Macros
+...............
+
+The macro syntax used on the MSP 430 is like that described in the MSP
+430 Family Assembler Specification. Normal `as' macros should still
+work.
+
+ Additional built-in macros are:
+
+`llo(exp)'
+ Extracts least significant word from 32-bit expression 'exp'.
+
+`lhi(exp)'
+ Extracts most significant word from 32-bit expression 'exp'.
+
+`hlo(exp)'
+ Extracts 3rd word from 64-bit expression 'exp'.
+
+`hhi(exp)'
+ Extracts 4rd word from 64-bit expression 'exp'.
+
+
+ They normally being used as an immediate source operand.
+ mov #llo(1), r10 ; == mov #1, r10
+ mov #lhi(1), r10 ; == mov #0, r10
+
+
+File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax
+
+9.29.2.2 Special Characters
+...........................
+
+A semicolon (`;') appearing anywhere on a line starts a comment that
+extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but it can also be a logical line number
+directive (*note Comments::) or a preprocessor control command (*note
+Preprocessing::).
+
+ Multiple statements can appear on the same line provided that they
+are separated by the `{' character.
+
+ The character `$' in jump instructions indicates current location and
+implemented only for TI syntax compatibility.
+
+
+File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax
+
+9.29.2.3 Register Names
+.......................
+
+General-purpose registers are represented by predefined symbols of the
+form `rN' (for global registers), where N represents a number between
+`0' and `15'. The leading letters may be in either upper or lower
+case; for example, `r13' and `R7' are both valid register names.
+
+ Register names `PC', `SP' and `SR' cannot be used as register names
+and will be treated as variables. Use `r0', `r1', and `r2' instead.
+
+
+File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax
+
+9.29.2.4 Assembler Extensions
+.............................
+
+`@rN'
+ As destination operand being treated as `0(rn)'
+
+`0(rN)'
+ As source operand being treated as `@rn'
+
+`jCOND +N'
+ Skips next N bytes followed by jump instruction and equivalent to
+ `jCOND $+N+2'
+
+
+ Also, there are some instructions, which cannot be found in other
+assemblers. These are branch instructions, which has different opcodes
+upon jump distance. They all got PC relative addressing mode.
+
+`beq label'
+ A polymorph instruction which is `jeq label' in case if jump
+ distance within allowed range for cpu's jump instruction. If not,
+ this unrolls into a sequence of
+ jne $+6
+ br label
+
+`bne label'
+ A polymorph instruction which is `jne label' or `jeq +4; br label'
+
+`blt label'
+ A polymorph instruction which is `jl label' or `jge +4; br label'
+
+`bltn label'
+ A polymorph instruction which is `jn label' or `jn +2; jmp +4; br
+ label'
+
+`bltu label'
+ A polymorph instruction which is `jlo label' or `jhs +2; br label'
+
+`bge label'
+ A polymorph instruction which is `jge label' or `jl +4; br label'
+
+`bgeu label'
+ A polymorph instruction which is `jhs label' or `jlo +4; br label'
+
+`bgt label'
+ A polymorph instruction which is `jeq +2; jge label' or `jeq +6;
+ jl +4; br label'
+
+`bgtu label'
+ A polymorph instruction which is `jeq +2; jhs label' or `jeq +6;
+ jlo +4; br label'
+
+`bleu label'
+ A polymorph instruction which is `jeq label; jlo label' or `jeq
+ +2; jhs +4; br label'
+
+`ble label'
+ A polymorph instruction which is `jeq label; jl label' or `jeq
+ +2; jge +4; br label'
+
+`jump label'
+ A polymorph instruction which is `jmp label' or `br label'
+
+
+File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent
+
+9.29.3 Floating Point
+---------------------
+
+The MSP 430 family uses IEEE 32-bit floating-point numbers.
+
+
+File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent
+
+9.29.4 MSP 430 Machine Directives
+---------------------------------
+
+`.file'
+ This directive is ignored; it is accepted for compatibility with
+ other MSP 430 assemblers.
+
+ _Warning:_ in other versions of the GNU assembler, `.file' is
+ used for the directive called `.app-file' in the MSP 430
+ support.
+
+`.line'
+ This directive is ignored; it is accepted for compatibility with
+ other MSP 430 assemblers.
+
+`.arch'
+ Sets the target microcontroller in the same way as the `-mmcu'
+ command line option.
+
+`.cpu'
+ Sets the target architecture in the same way as the `-mcpu'
+ command line option.
+
+`.profiler'
+ This directive instructs assembler to add new profile entry to the
+ object file.
+
+`.refsym'
+ This directive instructs assembler to add an undefined reference to
+ the symbol following the directive. The maximum symbol name
+ length is 1023 characters. No relocation is created for this
+ symbol; it will exist purely for pulling in object files from
+ archives. Note that this reloc is not sufficient to prevent
+ garbage collection; use a KEEP() directive in the linker file to
+ preserve such objects.
+
+
+
+File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent
+
+9.29.5 Opcodes
+--------------
+
+`as' implements all the standard MSP 430 opcodes. No additional
+pseudo-instructions are needed on this family.
+
+ For information on the 430 machine instruction set, see `MSP430
+User's Manual, document slau049d', Texas Instrument, Inc.
+
+
+File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent
+
+9.29.6 Profiling Capability
+---------------------------
+
+It is a performance hit to use gcc's profiling approach for this tiny
+target. Even more - jtag hardware facility does not perform any
+profiling functions. However we've got gdb's built-in simulator where
+we can do anything.
+
+ We define new section `.profiler' which holds all profiling
+information. We define new pseudo operation `.profiler' which will
+instruct assembler to add new profile entry to the object file. Profile
+should take place at the present address.
+
+ Pseudo operation format:
+
+ `.profiler flags,function_to_profile [, cycle_corrector, extra]'
+
+ where:
+
+ `flags' is a combination of the following characters:
+
+ `s'
+ function entry
+
+ `x'
+ function exit
+
+ `i'
+ function is in init section
+
+ `f'
+ function is in fini section
+
+ `l'
+ library call
+
+ `c'
+ libc standard call
+
+ `d'
+ stack value demand
+
+ `I'
+ interrupt service routine
+
+ `P'
+ prologue start
+
+ `p'
+ prologue end
+
+ `E'
+ epilogue start
+
+ `e'
+ epilogue end
+
+ `j'
+ long jump / sjlj unwind
+
+ `a'
+ an arbitrary code fragment
+
+ `t'
+ extra parameter saved (a constant value like frame size)
+
+`function_to_profile'
+ a function address
+
+`cycle_corrector'
+ a value which should be added to the cycle counter, zero if
+ omitted.
+
+`extra'
+ any extra parameter, zero if omitted.
+
+
+ For example:
+ .global fxx
+ .type fxx,@function
+ fxx:
+ .LFrameOffset_fxx=0x08
+ .profiler "scdP", fxx ; function entry.
+ ; we also demand stack value to be saved
+ push r11
+ push r10
+ push r9
+ push r8
+ .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
+ ; (this is a prologue end)
+ ; note, that spare var filled with
+ ; the farme size
+ mov r15,r8
+ ...
+ .profiler cdE,fxx ; check stack
+ pop r8
+ pop r9
+ pop r10
+ pop r11
+ .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
+ ret ; cause 'ret' insn takes 3 cycles
+
+
+File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies
+
+9.30 NDS32 Dependent Features
+=============================
+
+ The NDS32 processors family includes high-performance and low-power
+32-bit processors for high-end to low-end. GNU `as' for NDS32
+architectures supports NDS32 ISA version 3. For detail about NDS32
+instruction set, please see the AndeStar ISA User Manual which is
+availible at http://www.andestech.com/en/index/index.htm
+
+* Menu:
+
+* NDS32 Options:: Assembler options
+* NDS32 Syntax:: High-level assembly macros
+
+
+File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent
+
+9.30.1 NDS32 Options
+--------------------
+
+The NDS32 configurations of GNU `as' support these special options:
+
+`-O1'
+ Optimize for performance.
+
+`-Os'
+ Optimize for space.
+
+`-EL'
+ Produce little endian data output.
+
+`-EB'
+ Produce little endian data output.
+
+`-mpic'
+ Generate PIC.
+
+`-mno-fp-as-gp-relax'
+ Suppress fp-as-gp relaxation for this file.
+
+`-mb2bb-relax'
+ Back-to-back branch optimization.
+
+`-mno-all-relax'
+ Suppress all relaxation for this file.
+
+`-march=<arch name>'
+ Assemble for architecture <arch name> which could be v3, v3j, v3m,
+ v3f, v3s, v2, v2j, v2f, v2s.
+
+`-mbaseline=<baseline>'
+ Assemble for baseline <baseline> which could be v2, v3, v3m.
+
+`-mfpu-freg=FREG'
+ Specify a FPU configuration.
+ `0 8 SP / 4 DP registers'
+
+ `1 16 SP / 8 DP registers'
+
+ `2 32 SP / 16 DP registers'
+
+ `3 32 SP / 32 DP registers'
+
+`-mabi=ABI'
+ Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
+
+`-m[no-]mac'
+ Enable/Disable Multiply instructions support.
+
+`-m[no-]div'
+ Enable/Disable Divide instructions support.
+
+`-m[no-]16bit-ext'
+ Enable/Disable 16-bit extension
+
+`-m[no-]dx-regs'
+ Enable/Disable d0/d1 registers
+
+`-m[no-]perf-ext'
+ Enable/Disable Performance extension
+
+`-m[no-]perf2-ext'
+ Enable/Disable Performance extension 2
+
+`-m[no-]string-ext'
+ Enable/Disable String extension
+
+`-m[no-]reduced-regs'
+ Enable/Disable Reduced Register configuration (GPR16) option
+
+`-m[no-]audio-isa-ext'
+ Enable/Disable AUDIO ISA extension
+
+`-m[no-]fpu-sp-ext'
+ Enable/Disable FPU SP extension
+
+`-m[no-]fpu-dp-ext'
+ Enable/Disable FPU DP extension
+
+`-m[no-]fpu-fma'
+ Enable/Disable FPU fused-multiply-add instructions
+
+`-mall-ext'
+ Turn on all extensions and instructions support
+
+
+File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent
+
+9.30.2 Syntax
+-------------
+
+* Menu:
+
+* NDS32-Chars:: Special Characters
+* NDS32-Regs:: Register Names
+* NDS32-Ops:: Pseudo Instructions
+
+
+File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax
+
+9.30.2.1 Special Characters
+...........................
+
+Use `#' at column 1 and `!' anywhere in the line except inside quotes.
+
+ Multiple instructions in a line are allowed though not recommended
+and should be separated by `;'.
+
+ Assembler is not case-sensitive in general except user defined label.
+For example, `jral F1' is different from `jral f1' while it is the same
+as `JRAL F1'.
+
+
+File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax
+
+9.30.2.2 Register Names
+.......................
+
+`General purpose registers (GPR)'
+ There are 32 32-bit general purpose registers $r0 to $r31.
+
+`Accumulators d0 and d1'
+ 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
+
+`Assembler reserved register $ta'
+ Register $ta ($r15) is reserved for assembler using.
+
+`Operating system reserved registers $p0 and $p1'
+ Registers $p0 ($r26) and $p1 ($r27) are used by operating system
+ as scratch registers.
+
+`Frame pointer $fp'
+ Register $r28 is regarded as the frame pointer.
+
+`Global pointer'
+ Register $r29 is regarded as the global pointer.
+
+`Link pointer'
+ Register $r30 is regarded as the link pointer.
+
+`Stack pointer'
+ Register $r31 is regarded as the stack pointer.
+
+
+File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax
+
+9.30.2.3 Pseudo Instructions
+............................
+
+`li rt5,imm32'
+ load 32-bit integer into register rt5. `sethi rt5,hi20(imm32)'
+ and then `ori rt5,reg,lo12(imm32)'.
+
+`la rt5,var'
+ Load 32-bit address of var into register rt5. `sethi
+ rt5,hi20(var)' and then `ori reg,rt5,lo12(var)'
+
+`l.[bhw] rt5,var'
+ Load value of var into register rt5. `sethi $ta,hi20(var)' and
+ then `l[bhw]i rt5,[$ta+lo12(var)]'
+
+`l.[bh]s rt5,var'
+ Load value of var into register rt5. `sethi $ta,hi20(var)' and
+ then `l[bh]si rt5,[$ta+lo12(var)]'
+
+`l.[bhw]p rt5,var,inc'
+ Load value of var into register rt5 and increment $ta by amount
+ inc. `la $ta,var' and then `l[bhw]i.bi rt5,[$ta],inc'
+
+`l.[bhw]pc rt5,inc'
+ Continue loading value of var into register rt5 and increment $ta
+ by amount inc. `l[bhw]i.bi rt5,[$ta],inc.'
+
+`l.[bh]sp rt5,var,inc'
+ Load value of var into register rt5 and increment $ta by amount
+ inc. `la $ta,var' and then `l[bh]si.bi rt5,[$ta],inc'
+
+`l.[bh]spc rt5,inc'
+ Continue loading value of var into register rt5 and increment $ta
+ by amount inc. `l[bh]si.bi rt5,[$ta],inc.'
+
+`s.[bhw] rt5,var'
+ Store register rt5 to var. `sethi $ta,hi20(var)' and then
+ `s[bhw]i rt5,[$ta+lo12(var)]'
+
+`s.[bhw]p rt5,var,inc'
+ Store register rt5 to var and increment $ta by amount inc. `la
+ $ta,var' and then `s[bhw]i.bi rt5,[$ta],inc'
+
+`s.[bhw]pc rt5,inc'
+ Continue storing register rt5 to var and increment $ta by amount
+ inc. `s[bhw]i.bi rt5,[$ta],inc.'
+
+`not rt5,ra5'
+ Alias of `nor rt5,ra5,ra5'.
+
+`neg rt5,ra5'
+ Alias of `subri rt5,ra5,0'.
+
+`br rb5'
+ Depending on how it is assembled, it is translated into `r5 rb5'
+ or `jr rb5'.
+
+`b label'
+ Branch to label depending on how it is assembled, it is translated
+ into `j8 label', `j label', or "`la $ta,label' `br $ta'".
+
+`bral rb5'
+ Alias of jral br5 depending on how it is assembled, it is
+ translated into `jral5 rb5' or `jral rb5'.
+
+`bal fname'
+ Alias of jal fname depending on how it is assembled, it is
+ translated into `jal fname' or "`la $ta,fname' `bral $ta'".
+
+`call fname'
+ Call function fname same as `jal fname'.
+
+`move rt5,ra5'
+ For 16-bit, this is `mov55 rt5,ra5'. For no 16-bit, this is `ori
+ rt5,ra5,0'.
+
+`move rt5,var'
+ This is the same as `l.w rt5,var'.
+
+`move rt5,imm32'
+ This is the same as `li rt5,imm32'.
+
+`pushm ra5,rb5'
+ Push contents of registers from ra5 to rb5 into stack.
+
+`push ra5'
+ Push content of register ra5 into stack. (same `pushm ra5,ra5').
+
+`push.d var'
+ Push value of double-word variable var into stack.
+
+`push.w var'
+ Push value of word variable var into stack.
+
+`push.h var'
+ Push value of half-word variable var into stack.
+
+`push.b var'
+ Push value of byte variable var into stack.
+
+`pusha var'
+ Push 32-bit address of variable var into stack.
+
+`pushi imm32'
+ Push 32-bit immediate value into stack.
+
+`popm ra5,rb5'
+ Pop top of stack values into registers ra5 to rb5.
+
+`pop rt5'
+ Pop top of stack value into register. (same as `popm rt5,rt5'.)
+
+`pop.d var,ra5'
+ Pop value of double-word variable var from stack using register ra5
+ as 2nd scratch register. (1st is $ta)
+
+`pop.w var,ra5'
+ Pop value of word variable var from stack using register ra5.
+
+`pop.h var,ra5'
+ Pop value of half-word variable var from stack using register ra5.
+
+`pop.b var,ra5'
+ Pop value of byte variable var from stack using register ra5.
+
+
+
+File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies
+
+9.31 Nios II Dependent Features
+===============================
+
+* Menu:
+
+* Nios II Options:: Options
+* Nios II Syntax:: Syntax
+* Nios II Relocations:: Relocations
+* Nios II Directives:: Nios II Machine Directives
+* Nios II Opcodes:: Opcodes
+
+
+File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent
+
+9.31.1 Options
+--------------
+
+`-relax-section'
+ Replace identified out-of-range branches with PC-relative `jmp'
+ sequences when possible. The generated code sequences are suitable
+ for use in position-independent code, but there is a practical
+ limit on the extended branch range because of the length of the
+ sequences. This option is the default.
+
+`-relax-all'
+ Replace branch instructions not determinable to be in range and
+ all call instructions with `jmp' and `callr' sequences
+ (respectively). This option generates absolute relocations
+ against the target symbols and is not appropriate for
+ position-independent code.
+
+`-no-relax'
+ Do not replace any branches or calls.
+
+`-EB'
+ Generate big-endian output.
+
+`-EL'
+ Generate little-endian output. This is the default.
+
+`-march=ARCHITECTURE'
+ This option specifies the target architecture. The assembler
+ issues an error message if an attempt is made to assemble an
+ instruction which will not execute on the target architecture.
+ The following architecture names are recognized: `r1', `r2'. The
+ default is `r1'.
+
+
+
+File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent
+
+9.31.2 Syntax
+-------------
+
+* Menu:
+
+* Nios II Chars:: Special Characters
+
+
+File: as.info, Node: Nios II Chars, Up: Nios II Syntax
+
+9.31.2.1 Special Characters
+...........................
+
+`#' is the line comment character. `;' is the line separator character.
+
+
+File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent
+
+9.31.3 Nios II Machine Relocations
+----------------------------------
+
+`%hiadj(EXPRESSION)'
+ Extract the upper 16 bits of EXPRESSION and add one if the 15th
+ bit is set.
+
+ The value of `%hiadj(EXPRESSION)' is:
+ ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01)
+
+ The `%hiadj' relocation is intended to be used with the `addi',
+ `ld' or `st' instructions along with a `%lo', in order to load a
+ 32-bit constant.
+
+ movhi r2, %hiadj(symbol)
+ addi r2, r2, %lo(symbol)
+
+`%hi(EXPRESSION)'
+ Extract the upper 16 bits of EXPRESSION.
+
+`%lo(EXPRESSION)'
+ Extract the lower 16 bits of EXPRESSION.
+
+`%gprel(EXPRESSION)'
+ Subtract the value of the symbol `_gp' from EXPRESSION.
+
+ The intention of the `%gprel' relocation is to have a fast small
+ area of memory which only takes a 16-bit immediate to access.
+
+ .section .sdata
+ fastint:
+ .int 123
+ .section .text
+ ldw r4, %gprel(fastint)(gp)
+
+`%call(EXPRESSION)'
+
+`%call_lo(EXPRESSION)'
+
+`%call_hiadj(EXPRESSION)'
+`%got(EXPRESSION)'
+`%got_lo(EXPRESSION)'
+`%got_hiadj(EXPRESSION)'
+`%gotoff(EXPRESSION)'
+`%gotoff_lo(EXPRESSION)'
+`%gotoff_hiadj(EXPRESSION)'
+`%tls_gd(EXPRESSION)'
+`%tls_ie(EXPRESSION)'
+`%tls_le(EXPRESSION)'
+`%tls_ldm(EXPRESSION)'
+`%tls_ldo(EXPRESSION)'
+ These relocations support the ABI for Linux Systems documented in
+ the `Nios II Processor Reference Handbook'.
+
+
+File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent
+
+9.31.4 Nios II Machine Directives
+---------------------------------
+
+`.align EXPRESSION [, EXPRESSION]'
+ This is the generic `.align' directive, however this aligns to a
+ power of two.
+
+`.half EXPRESSION'
+ Create an aligned constant 2 bytes in size.
+
+`.word EXPRESSION'
+ Create an aligned constant 4 bytes in size.
+
+`.dword EXPRESSION'
+ Create an aligned constant 8 bytes in size.
+
+`.2byte EXPRESSION'
+ Create an unaligned constant 2 bytes in size.
+
+`.4byte EXPRESSION'
+ Create an unaligned constant 4 bytes in size.
+
+`.8byte EXPRESSION'
+ Create an unaligned constant 8 bytes in size.
+
+`.16byte EXPRESSION'
+ Create an unaligned constant 16 bytes in size.
+
+`.set noat'
+ Allows assembly code to use `at' register without warning. Macro
+ or relaxation expansions generate warnings.
+
+`.set at'
+ Assembly code using `at' register generates warnings, and macro
+ expansion and relaxation are enabled.
+
+`.set nobreak'
+ Allows assembly code to use `ba' and `bt' registers without
+ warning.
+
+`.set break'
+ Turns warnings back on for using `ba' and `bt' registers.
+
+`.set norelax'
+ Do not replace any branches or calls.
+
+`.set relaxsection'
+ Replace identified out-of-range branches with `jmp' sequences
+ (default).
+
+`.set relaxsection'
+ Replace all branch and call instructions with `jmp' and `callr'
+ sequences.
+
+`.set ...'
+ All other `.set' are the normal use.
+
+
+
+File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent
+
+9.31.5 Opcodes
+--------------
+
+`as' implements all the standard Nios II opcodes documented in the
+`Nios II Processor Reference Handbook', including the assembler
+pseudo-instructions.
+
+
+File: as.info, Node: NS32K-Dependent, Next: PDP-11-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies
+
+9.32 NS32K Dependent Features
+=============================
+
+* Menu:
+
+* NS32K Syntax:: Syntax
+
+
+File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent
+
+9.32.1 Syntax
+-------------
+
+* Menu:
+
+* NS32K-Chars:: Special Characters
+
+
+File: as.info, Node: NS32K-Chars, Up: NS32K Syntax
+
+9.32.1.1 Special Characters
+...........................
+
+The presence of a `#' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ If Sequent compatibility has been configured into the assembler then
+the `|' character appearing as the first character on a line will also
+indicate the start of a line comment.
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies
+
+9.33 PDP-11 Dependent Features
+==============================
+
+* Menu:
+
+* PDP-11-Options:: Options
+* PDP-11-Pseudos:: Assembler Directives
+* PDP-11-Syntax:: DEC Syntax versus BSD Syntax
+* PDP-11-Mnemonics:: Instruction Naming
+* PDP-11-Synthetic:: Synthetic Instructions
+
+
+File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent
+
+9.33.1 Options
+--------------
+
+The PDP-11 version of `as' has a rich set of machine dependent options.
+
+9.33.1.1 Code Generation Options
+................................
+
+`-mpic | -mno-pic'
+ Generate position-independent (or position-dependent) code.
+
+ The default is to generate position-independent code.
+
+9.33.1.2 Instruction Set Extension Options
+..........................................
+
+These options enables or disables the use of extensions over the base
+line instruction set as introduced by the first PDP-11 CPU: the KA11.
+Most options come in two variants: a `-m'EXTENSION that enables
+EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.
+
+ The default is to enable all extensions.
+
+`-mall | -mall-extensions'
+ Enable all instruction set extensions.
+
+`-mno-extensions'
+ Disable all instruction set extensions.
+
+`-mcis | -mno-cis'
+ Enable (or disable) the use of the commercial instruction set,
+ which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
+ `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
+ `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
+ `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
+ `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
+ `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
+ `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
+ `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.
+
+`-mcsm | -mno-csm'
+ Enable (or disable) the use of the `CSM' instruction.
+
+`-meis | -mno-eis'
+ Enable (or disable) the use of the extended instruction set, which
+ consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
+ `MUL', `RTT', `SOB' `SXT', and `XOR'.
+
+`-mfis | -mkev11'
+`-mno-fis | -mno-kev11'
+ Enable (or disable) the use of the KEV11 floating-point
+ instructions: `FADD', `FDIV', `FMUL', and `FSUB'.
+
+`-mfpp | -mfpu | -mfp-11'
+`-mno-fpp | -mno-fpu | -mno-fp-11'
+ Enable (or disable) the use of FP-11 floating-point instructions:
+ `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
+ `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
+ `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
+ `SUBF', and `TSTF'.
+
+`-mlimited-eis | -mno-limited-eis'
+ Enable (or disable) the use of the limited extended instruction
+ set: `MARK', `RTT', `SOB', `SXT', and `XOR'.
+
+ The -mno-limited-eis options also implies -mno-eis.
+
+`-mmfpt | -mno-mfpt'
+ Enable (or disable) the use of the `MFPT' instruction.
+
+`-mmultiproc | -mno-multiproc'
+ Enable (or disable) the use of multiprocessor instructions:
+ `TSTSET' and `WRTLCK'.
+
+`-mmxps | -mno-mxps'
+ Enable (or disable) the use of the `MFPS' and `MTPS' instructions.
+
+`-mspl | -mno-spl'
+ Enable (or disable) the use of the `SPL' instruction.
+
+ Enable (or disable) the use of the microcode instructions: `LDUB',
+ `MED', and `XFC'.
+
+9.33.1.3 CPU Model Options
+..........................
+
+These options enable the instruction set extensions supported by a
+particular CPU, and disables all other extensions.
+
+`-mka11'
+ KA11 CPU. Base line instruction set only.
+
+`-mkb11'
+ KB11 CPU. Enable extended instruction set and `SPL'.
+
+`-mkd11a'
+ KD11-A CPU. Enable limited extended instruction set.
+
+`-mkd11b'
+ KD11-B CPU. Base line instruction set only.
+
+`-mkd11d'
+ KD11-D CPU. Base line instruction set only.
+
+`-mkd11e'
+ KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'.
+
+`-mkd11f | -mkd11h | -mkd11q'
+ KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended
+ instruction set, `MFPS', and `MTPS'.
+
+`-mkd11k'
+ KD11-K CPU. Enable extended instruction set, `LDUB', `MED',
+ `MFPS', `MFPT', `MTPS', and `XFC'.
+
+`-mkd11z'
+ KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS',
+ `MFPT', `MTPS', and `SPL'.
+
+`-mf11'
+ F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and
+ `MTPS'.
+
+`-mj11'
+ J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT',
+ `MTPS', `SPL', `TSTSET', and `WRTLCK'.
+
+`-mt11'
+ T11 CPU. Enable limited extended instruction set, `MFPS', and
+ `MTPS'.
+
+9.33.1.4 Machine Model Options
+..............................
+
+These options enable the instruction set extensions supported by a
+particular machine model, and disables all other extensions.
+
+`-m11/03'
+ Same as `-mkd11f'.
+
+`-m11/04'
+ Same as `-mkd11d'.
+
+`-m11/05 | -m11/10'
+ Same as `-mkd11b'.
+
+`-m11/15 | -m11/20'
+ Same as `-mka11'.
+
+`-m11/21'
+ Same as `-mt11'.
+
+`-m11/23 | -m11/24'
+ Same as `-mf11'.
+
+`-m11/34'
+ Same as `-mkd11e'.
+
+`-m11/34a'
+ Ame as `-mkd11e' `-mfpp'.
+
+`-m11/35 | -m11/40'
+ Same as `-mkd11a'.
+
+`-m11/44'
+ Same as `-mkd11z'.
+
+`-m11/45 | -m11/50 | -m11/55 | -m11/70'
+ Same as `-mkb11'.
+
+`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
+ Same as `-mj11'.
+
+`-m11/60'
+ Same as `-mkd11k'.
+
+
+File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent
+
+9.33.2 Assembler Directives
+---------------------------
+
+The PDP-11 version of `as' has a few machine dependent assembler
+directives.
+
+`.bss'
+ Switch to the `bss' section.
+
+`.even'
+ Align the location counter to an even number.
+
+
+File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent
+
+9.33.3 PDP-11 Assembly Language Syntax
+--------------------------------------
+
+`as' supports both DEC syntax and BSD syntax. The only difference is
+that in DEC syntax, a `#' character is used to denote an immediate
+constants, while in BSD syntax the character for this purpose is `$'.
+
+ general-purpose registers are named `r0' through `r7'. Mnemonic
+alternatives for `r6' and `r7' are `sp' and `pc', respectively.
+
+ Floating-point registers are named `ac0' through `ac3', or
+alternatively `fr0' through `fr3'.
+
+ Comments are started with a `#' or a `/' character, and extend to
+the end of the line. (FIXME: clash with immediates?)
+
+ Multiple statements on the same line can be separated by the `;'
+character.
+
+
+File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent
+
+9.33.4 Instruction Naming
+-------------------------
+
+Some instructions have alternative names.
+
+`BCC'
+ `BHIS'
+
+`BCS'
+ `BLO'
+
+`L2DR'
+ `L2D'
+
+`L3DR'
+ `L3D'
+
+`SYS'
+ `TRAP'
+
+
+File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent
+
+9.33.5 Synthetic Instructions
+-----------------------------
+
+The `JBR' and `J'CC synthetic instructions are not supported yet.
+
+
+File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies
+
+9.34 picoJava Dependent Features
+================================
+
+* Menu:
+
+* PJ Options:: Options
+* PJ Syntax:: PJ Syntax
+
+
+File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent
+
+9.34.1 Options
+--------------
+
+`as' has two additional command-line options for the picoJava
+architecture.
+`-ml'
+ This option selects little endian data output.
+
+`-mb'
+ This option selects big endian data output.
+
+
+File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent
+
+9.34.2 PJ Syntax
+----------------
+
+* Menu:
+
+* PJ-Chars:: Special Characters
+
+
+File: as.info, Node: PJ-Chars, Up: PJ Syntax
+
+9.34.2.1 Special Characters
+...........................
+
+The presence of a `!' or `/' on a line indicates the start of a comment
+that extends to the end of the current line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
+
+9.35 PowerPC Dependent Features
+===============================
+
+* Menu:
+
+* PowerPC-Opts:: Options
+* PowerPC-Pseudo:: PowerPC Assembler Directives
+* PowerPC-Syntax:: PowerPC Syntax
+
+
+File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent
+
+9.35.1 Options
+--------------
+
+The PowerPC chip family includes several successive levels, using the
+same core instruction set, but including a few additional instructions
+at each level. There are exceptions to this however. For details on
+what instructions each variant supports, please see the chip's
+architecture reference manual.
+
+ The following table lists all available PowerPC options.
+
+`-a32'
+ Generate ELF32 or XCOFF32.
+
+`-a64'
+ Generate ELF64 or XCOFF64.
+
+`-K PIC'
+ Set EF_PPC_RELOCATABLE_LIB in ELF flags.
+
+`-mpwrx | -mpwr2'
+ Generate code for POWER/2 (RIOS2).
+
+`-mpwr'
+ Generate code for POWER (RIOS1)
+
+`-m601'
+ Generate code for PowerPC 601.
+
+`-mppc, -mppc32, -m603, -m604'
+ Generate code for PowerPC 603/604.
+
+`-m403, -m405'
+ Generate code for PowerPC 403/405.
+
+`-m440'
+ Generate code for PowerPC 440. BookE and some 405 instructions.
+
+`-m464'
+ Generate code for PowerPC 464.
+
+`-m476'
+ Generate code for PowerPC 476.
+
+`-m7400, -m7410, -m7450, -m7455'
+ Generate code for PowerPC 7400/7410/7450/7455.
+
+`-m750cl'
+ Generate code for PowerPC 750CL.
+
+`-m821, -m850, -m860'
+ Generate code for PowerPC 821/850/860.
+
+`-mppc64, -m620'
+ Generate code for PowerPC 620/625/630.
+
+`-me500, -me500x2'
+ Generate code for Motorola e500 core complex.
+
+`-me500mc'
+ Generate code for Freescale e500mc core complex.
+
+`-me500mc64'
+ Generate code for Freescale e500mc64 core complex.
+
+`-me5500'
+ Generate code for Freescale e5500 core complex.
+
+`-me6500'
+ Generate code for Freescale e6500 core complex.
+
+`-mspe'
+ Generate code for Motorola SPE instructions.
+
+`-mtitan'
+ Generate code for AppliedMicro Titan core complex.
+
+`-mppc64bridge'
+ Generate code for PowerPC 64, including bridge insns.
+
+`-mbooke'
+ Generate code for 32-bit BookE.
+
+`-ma2'
+ Generate code for A2 architecture.
+
+`-me300'
+ Generate code for PowerPC e300 family.
+
+`-maltivec'
+ Generate code for processors with AltiVec instructions.
+
+`-mvle'
+ Generate code for Freescale PowerPC VLE instructions.
+
+`-mvsx'
+ Generate code for processors with Vector-Scalar (VSX) instructions.
+
+`-mhtm'
+ Generate code for processors with Hardware Transactional Memory
+ instructions.
+
+`-mpower4, -mpwr4'
+ Generate code for Power4 architecture.
+
+`-mpower5, -mpwr5, -mpwr5x'
+ Generate code for Power5 architecture.
+
+`-mpower6, -mpwr6'
+ Generate code for Power6 architecture.
+
+`-mpower7, -mpwr7'
+ Generate code for Power7 architecture.
+
+`-mpower8, -mpwr8'
+ Generate code for Power8 architecture.
+
+`-mpower9, -mpwr9'
+ Generate code for Power9 architecture.
+
+`-mcell'
+
+`-mcell'
+ Generate code for Cell Broadband Engine architecture.
+
+`-mcom'
+ Generate code Power/PowerPC common instructions.
+
+`-many'
+ Generate code for any architecture (PWR/PWRX/PPC).
+
+`-mregnames'
+ Allow symbolic names for registers.
+
+`-mno-regnames'
+ Do not allow symbolic names for registers.
+
+`-mrelocatable'
+ Support for GCC's -mrelocatable option.
+
+`-mrelocatable-lib'
+ Support for GCC's -mrelocatable-lib option.
+
+`-memb'
+ Set PPC_EMB bit in ELF flags.
+
+`-mlittle, -mlittle-endian, -le'
+ Generate code for a little endian machine.
+
+`-mbig, -mbig-endian, -be'
+ Generate code for a big endian machine.
+
+`-msolaris'
+ Generate code for Solaris.
+
+`-mno-solaris'
+ Do not generate code for Solaris.
+
+`-nops=COUNT'
+ If an alignment directive inserts more than COUNT nops, put a
+ branch at the beginning to skip execution of the nops.
+
+
+File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent
+
+9.35.2 PowerPC Assembler Directives
+-----------------------------------
+
+A number of assembler directives are available for PowerPC. The
+following table is far from complete.
+
+`.machine "string"'
+ This directive allows you to change the machine for which code is
+ generated. `"string"' may be any of the -m cpu selection options
+ (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
+ `.machine "push"' saves the currently selected cpu, which may be
+ restored with `.machine "pop"'.
+
+
+File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent
+
+9.35.3 PowerPC Syntax
+---------------------
+
+* Menu:
+
+* PowerPC-Chars:: Special Characters
+
+
+File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax
+
+9.35.3.1 Special Characters
+...........................
+
+The presence of a `#' on a line indicates the start of a comment that
+extends to the end of the current line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ If the assembler has been configured for the ppc-*-solaris* target
+then the `!' character also acts as a line comment character. This can
+be disabled via the `-mno-solaris' command line option.
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: RL78-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
+
+9.36 RL78 Dependent Features
+============================
+
+* Menu:
+
+* RL78-Opts:: RL78 Assembler Command Line Options
+* RL78-Modifiers:: Symbolic Operand Modifiers
+* RL78-Directives:: Assembler Directives
+* RL78-Syntax:: Syntax
+
+
+File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent
+
+9.36.1 RL78 Options
+-------------------
+
+`relax'
+ Enable support for link-time relaxation.
+
+`norelax'
+ Disable support for link-time relaxation (default).
+
+`mg10'
+ Mark the generated binary as targeting the G10 variant of the RL78
+ architecture.
+
+`mg13'
+ Mark the generated binary as targeting the G13 variant of the RL78
+ architecture.
+
+`mg14'
+`mrl78'
+ Mark the generated binary as targeting the G14 variant of the RL78
+ architecture. This is the default.
+
+`m32bit-doubles'
+ Mark the generated binary as one that uses 32-bits to hold the
+ `double' floating point type. This is the default.
+
+`m64bit-doubles'
+ Mark the generated binary as one that uses 64-bits to hold the
+ `double' floating point type.
+
+
+
+File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent
+
+9.36.2 Symbolic Operand Modifiers
+---------------------------------
+
+The RL78 has three modifiers that adjust the relocations used by the
+linker:
+
+`%lo16()'
+ When loading a 20-bit (or wider) address into registers, this
+ modifier selects the 16 least significant bits.
+
+ movw ax,#%lo16(_sym)
+
+`%hi16()'
+ When loading a 20-bit (or wider) address into registers, this
+ modifier selects the 16 most significant bits.
+
+ movw ax,#%hi16(_sym)
+
+`%hi8()'
+ When loading a 20-bit (or wider) address into registers, this
+ modifier selects the 8 bits that would go into CS or ES (i.e. bits
+ 23..16).
+
+ mov es, #%hi8(_sym)
+
+
+
+File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent
+
+9.36.3 Assembler Directives
+---------------------------
+
+In addition to the common directives, the RL78 adds these:
+
+`.double'
+ Output a constant in "double" format, which is either a 32-bit or
+ a 64-bit floating point value, depending upon the setting of the
+ `-m32bit-doubles'|`-m64bit-doubles' command line option.
+
+`.bss'
+ Select the BSS section.
+
+`.3byte'
+ Output a constant value in a three byte format.
+
+`.int'
+`.word'
+ Output a constant value in a four byte format.
+
+
+
+File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent
+
+9.36.4 Syntax for the RL78
+--------------------------
+
+* Menu:
+
+* RL78-Chars:: Special Characters
+
+
+File: as.info, Node: RL78-Chars, Up: RL78-Syntax
+
+9.36.4.1 Special Characters
+...........................
+
+The presence of a `;' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `|' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: RISC-V-Dependent, Next: RX-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies
+
+9.37 RISC-V Dependent Features
+==============================
+
+* Menu:
+
+* RISC-V-Opts:: RISC-V Options
+
+
+File: as.info, Node: RISC-V-Opts, Up: RISC-V-Dependent
+
+9.37.1 Options
+--------------
+
+The following table lists all availiable RISC-V specific options
+
+`-march=ISA'
+ Select the base isa, as specified by ISA. For example
+ -march=rv32ima.
+
+`-mabi=ABI'
+ Selects the ABI, which is either "ilp32" or "lp64", optionally
+ followed by "f", "d", or "q" to indicate single-precision,
+ double-precision, or quad-precision floating-point calling
+ convention, or none to indicate the soft-float calling convention.
+
+
+
+File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies
+
+9.38 RX Dependent Features
+==========================
+
+* Menu:
+
+* RX-Opts:: RX Assembler Command Line Options
+* RX-Modifiers:: Symbolic Operand Modifiers
+* RX-Directives:: Assembler Directives
+* RX-Float:: Floating Point
+* RX-Syntax:: Syntax
+
+
+File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent
+
+9.38.1 RX Options
+-----------------
+
+The Renesas RX port of `as' has a few target specfic command line
+options:
+
+`-m32bit-doubles'
+ This option controls the ABI and indicates to use a 32-bit float
+ ABI. It has no effect on the assembled instructions, but it does
+ influence the behaviour of the `.double' pseudo-op. This is the
+ default.
+
+`-m64bit-doubles'
+ This option controls the ABI and indicates to use a 64-bit float
+ ABI. It has no effect on the assembled instructions, but it does
+ influence the behaviour of the `.double' pseudo-op.
+
+`-mbig-endian'
+ This option controls the ABI and indicates to use a big-endian data
+ ABI. It has no effect on the assembled instructions, but it does
+ influence the behaviour of the `.short', `.hword', `.int',
+ `.word', `.long', `.quad' and `.octa' pseudo-ops.
+
+`-mlittle-endian'
+ This option controls the ABI and indicates to use a little-endian
+ data ABI. It has no effect on the assembled instructions, but it
+ does influence the behaviour of the `.short', `.hword', `.int',
+ `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the
+ default.
+
+`-muse-conventional-section-names'
+ This option controls the default names given to the code (.text),
+ initialised data (.data) and uninitialised data sections (.bss).
+
+`-muse-renesas-section-names'
+ This option controls the default names given to the code (.P),
+ initialised data (.D_1) and uninitialised data sections (.B_1).
+ This is the default.
+
+`-msmall-data-limit'
+ This option tells the assembler that the small data limit feature
+ of the RX port of GCC is being used. This results in the assembler
+ generating an undefined reference to a symbol called `__gp' for
+ use by the relocations that are needed to support the small data
+ limit feature. This option is not enabled by default as it would
+ otherwise pollute the symbol table.
+
+`-mpid'
+ This option tells the assembler that the position independent data
+ of the RX port of GCC is being used. This results in the assembler
+ generating an undefined reference to a symbol called `__pid_base',
+ and also setting the RX_PID flag bit in the e_flags field of the
+ ELF header of the object file.
+
+`-mint-register=NUM'
+ This option tells the assembler how many registers have been
+ reserved for use by interrupt handlers. This is needed in order
+ to compute the correct values for the `%gpreg' and `%pidreg' meta
+ registers.
+
+`-mgcc-abi'
+ This option tells the assembler that the old GCC ABI is being used
+ by the assembled code. With this version of the ABI function
+ arguments that are passed on the stack are aligned to a 32-bit
+ boundary.
+
+`-mrx-abi'
+ This option tells the assembler that the official RX ABI is being
+ used by the assembled code. With this version of the ABI function
+ arguments that are passed on the stack are aligned to their natural
+ alignments. This option is the default.
+
+`-mcpu=NAME'
+ This option tells the assembler the target CPU type. Currently the
+ `rx100', `rx200', `rx600', `rx610' and `rxv2' are recognised as
+ valid cpu names. Attempting to assemble an instruction not
+ supported by the indicated cpu type will result in an error message
+ being generated.
+
+`-mno-allow-string-insns'
+ This option tells the assembler to mark the object file that it is
+ building as one that does not use the string instructions `SMOVF',
+ `SCMPU', `SMOVB', `SMOVU', `SUNTIL' `SWHILE' or the `RMPA'
+ instruction. In addition the mark tells the linker to complain if
+ an attempt is made to link the binary with another one that does
+ use any of these instructions.
+
+ Note - the inverse of this option, `-mallow-string-insns', is not
+ needed. The assembler automatically detects the use of the the
+ instructions in the source code and labels the resulting object
+ file appropriately. If no string instructions are detected then
+ the object file is labelled as being one that can be linked with
+ either string-using or string-banned object files.
+
+
+File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent
+
+9.38.2 Symbolic Operand Modifiers
+---------------------------------
+
+The assembler supports one modifier when using symbol addresses in RX
+instruction operands. The general syntax is the following:
+
+ %gp(symbol)
+
+ The modifier returns the offset from the __GP symbol to the
+specified symbol as a 16-bit value. The intent is that this offset
+should be used in a register+offset move instruction when generating
+references to small data. Ie, like this:
+
+ mov.W %gp(_foo)[%gpreg], r1
+
+ The assembler also supports two meta register names which can be used
+to refer to registers whose values may not be known to the programmer.
+These meta register names are:
+
+`%gpreg'
+ The small data address register.
+
+`%pidreg'
+ The PID base address register.
+
+
+ Both registers normally have the value r13, but this can change if
+some registers have been reserved for use by interrupt handlers or if
+both the small data limit and position independent data features are
+being used at the same time.
+
+
+File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent
+
+9.38.3 Assembler Directives
+---------------------------
+
+The RX version of `as' has the following specific assembler directives:
+
+`.3byte'
+ Inserts a 3-byte value into the output file at the current
+ location.
+
+`.fetchalign'
+ If the next opcode following this directive spans a fetch line
+ boundary (8 byte boundary), the opcode is aligned to that boundary.
+ If the next opcode does not span a fetch line, this directive has
+ no effect. Note that one or more labels may be between this
+ directive and the opcode; those labels are aligned as well. Any
+ inserted bytes due to alignment will form a NOP opcode.
+
+
+
+File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent
+
+9.38.4 Floating Point
+---------------------
+
+The floating point formats generated by directives are these.
+
+`.float'
+ `Single' precision (32-bit) floating point constants.
+
+`.double'
+ If the `-m64bit-doubles' command line option has been specified
+ then then `double' directive generates `double' precision (64-bit)
+ floating point constants, otherwise it generates `single'
+ precision (32-bit) floating point constants. To force the
+ generation of 64-bit floating point constants used the `dc.d'
+ directive instead.
+
+
+
+File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent
+
+9.38.5 Syntax for the RX
+------------------------
+
+* Menu:
+
+* RX-Chars:: Special Characters
+
+
+File: as.info, Node: RX-Chars, Up: RX-Syntax
+
+9.38.5.1 Special Characters
+...........................
+
+The presence of a `;' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `!' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies
+
+9.39 IBM S/390 Dependent Features
+=================================
+
+ The s390 version of `as' supports two architectures modes and eleven
+chip levels. The architecture modes are the Enterprise System
+Architecture (ESA) and the newer z/Architecture mode. The chip levels
+are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
+(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or
+arch11), and arch12.
+
+* Menu:
+
+* s390 Options:: Command-line Options.
+* s390 Characters:: Special Characters.
+* s390 Syntax:: Assembler Instruction syntax.
+* s390 Directives:: Assembler Directives.
+* s390 Floating Point:: Floating Point.
+
+
+File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent
+
+9.39.1 Options
+--------------
+
+The following table lists all available s390 specific options:
+
+`-m31 | -m64'
+ Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
+
+ These options are only available with the ELF object file format,
+ and require that the necessary BFD support has been included (on a
+ 31-bit platform you must add -enable-64-bit-bfd on the call to the
+ configure script to enable 64-bit usage and use s390x as target
+ platform).
+
+`-mesa | -mzarch'
+ Select the architecture mode, either the Enterprise System
+ Architecture (esa) mode or the z/Architecture mode (zarch).
+
+ The 64-bit instructions are only available with the z/Architecture
+ mode. The combination of `-m64' and `-mesa' results in a warning
+ message.
+
+`-march=CPU'
+ This option specifies the target processor. The following
+ processor names are recognized: `g5' (or `arch3'), `g6', `z900'
+ (or `arch5'), `z990' (or `arch6'), `z9-109', `z9-ec' (or `arch7'),
+ `z10' (or `arch8'), `z196' (or `arch9'), `zEC12' (or `arch10') and
+ `z13' (or `arch11').
+
+ Assembling an instruction that is not supported on the target
+ processor results in an error message.
+
+ The processor names starting with `arch' refer to the edition
+ number in the Principle of Operations manual. They can be used as
+ alternate processor names and have been added for compatibility
+ with the IBM XL compiler.
+
+ `arch3', `g5' and `g6' cannot be used with the `-mzarch' option
+ since the z/Architecture mode is not supported on these processor
+ levels.
+
+ There is no `arch4' option supported. `arch4' matches
+ `-march=arch5 -mesa'.
+
+`-mregnames'
+ Allow symbolic names for registers.
+
+`-mno-regnames'
+ Do not allow symbolic names for registers.
+
+`-mwarn-areg-zero'
+ Warn whenever the operand for a base or index register has been
+ specified but evaluates to zero. This can indicate the misuse of
+ general purpose register 0 as an address register.
+
+
+
+File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent
+
+9.39.2 Special Characters
+-------------------------
+
+`#' is the line comment character.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used instead of a newline to separate
+statements.
+
+
+File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent
+
+9.39.3 Instruction syntax
+-------------------------
+
+The assembler syntax closely follows the syntax outlined in Enterprise
+Systems Architecture/390 Principles of Operation (SA22-7201) and the
+z/Architecture Principles of Operation (SA22-7832).
+
+ Each instruction has two major parts, the instruction mnemonic and
+the instruction operands. The instruction format varies.
+
+* Menu:
+
+* s390 Register:: Register Naming
+* s390 Mnemonics:: Instruction Mnemonics
+* s390 Operands:: Instruction Operands
+* s390 Formats:: Instruction Formats
+* s390 Aliases:: Instruction Aliases
+* s390 Operand Modifier:: Instruction Operand Modifier
+* s390 Instruction Marker:: Instruction Marker
+* s390 Literal Pool Entries:: Literal Pool Entries
+
+
+File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax
+
+9.39.3.1 Register naming
+........................
+
+The `as' recognizes a number of predefined symbols for the various
+processor registers. A register specification in one of the instruction
+formats is an unsigned integer between 0 and 15. The specific
+instruction and the position of the register in the instruction format
+denotes the type of the register. The register symbols are prefixed with
+`%':
+
+ %rN the 16 general purpose registers, 0 <= N <= 15
+ %fN the 16 floating point registers, 0 <= N <= 15
+ %aN the 16 access registers, 0 <= N <= 15
+ %cN the 16 control registers, 0 <= N <= 15
+ %lit an alias for the general purpose register %r13
+ %sp an alias for the general purpose register %r15
+
+
+File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax
+
+9.39.3.2 Instruction Mnemonics
+..............................
+
+All instructions documented in the Principles of Operation are supported
+with the mnemonic and order of operands as described. The instruction
+mnemonic identifies the instruction format (*Note s390 Formats::) and
+the specific operation code for the instruction. For example, the `lr'
+mnemonic denotes the instruction format `RR' with the operation code
+`0x18'.
+
+ The definition of the various mnemonics follows a scheme, where the
+first character usually hint at the type of the instruction:
+
+ a add instruction, for example `al' for add logical 32-bit
+ b branch instruction, for example `bc' for branch on condition
+ c compare or convert instruction, for example `cr' for compare
+ register 32-bit
+ d divide instruction, for example `dlr' devide logical register
+ 64-bit to 32-bit
+ i insert instruction, for example `ic' insert character
+ l load instruction, for example `ltr' load and test register
+ mv move instruction, for example `mvc' move character
+ m multiply instruction, for example `mh' multiply halfword
+ n and instruction, for example `ni' and immediate
+ o or instruction, for example `oc' or character
+ sla, sll shift left single instruction
+ sra, srl shift right single instruction
+ st store instruction, for example `stm' store multiple
+ s subtract instruction, for example `slr' subtract
+ logical 32-bit
+ t test or translate instruction, of example `tm' test under mask
+ x exclusive or instruction, for example `xc' exclusive or
+ character
+
+ Certain characters at the end of the mnemonic may describe a property
+of the instruction:
+
+ c the instruction uses a 8-bit character operand
+ f the instruction extends a 32-bit operand to 64 bit
+ g the operands are treated as 64-bit values
+ h the operand uses a 16-bit halfword operand
+ i the instruction uses an immediate operand
+ l the instruction uses unsigned, logical operands
+ m the instruction uses a mask or operates on multiple values
+ r if r is the last character, the instruction operates on registers
+ y the instruction uses 20-bit displacements
+
+ There are many exceptions to the scheme outlined in the above lists,
+in particular for the priviledged instructions. For non-priviledged
+instruction it works quite well, for example the instruction `clgfr' c:
+compare instruction, l: unsigned operands, g: 64-bit operands, f: 32-
+to 64-bit extension, r: register operands. The instruction compares an
+64-bit value in a register with the zero extended 32-bit value from a
+second register. For a complete list of all mnemonics see appendix B
+in the Principles of Operation.
+
+
+File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax
+
+9.39.3.3 Instruction Operands
+.............................
+
+Instruction operands can be grouped into three classes, operands located
+in registers, immediate operands, and operands in storage.
+
+ A register operand can be located in general, floating-point, access,
+or control register. The register is identified by a four-bit field.
+The field containing the register operand is called the R field.
+
+ Immediate operands are contained within the instruction and can have
+8, 16 or 32 bits. The field containing the immediate operand is called
+the I field. Dependent on the instruction the I field is either signed
+or unsigned.
+
+ A storage operand consists of an address and a length. The address
+of a storage operands can be specified in any of these ways:
+
+ * The content of a single general R
+
+ * The sum of the content of a general register called the base
+ register B plus the content of a displacement field D
+
+ * The sum of the contents of two general registers called the index
+ register X and the base register B plus the content of a
+ displacement field
+
+ * The sum of the current instruction address and a 32-bit signed
+ immediate field multiplied by two.
+
+ The length of a storage operand can be:
+
+ * Implied by the instruction
+
+ * Specified by a bitmask
+
+ * Specified by a four-bit or eight-bit length field L
+
+ * Specified by the content of a general register
+
+ The notation for storage operand addresses formed from multiple
+fields is as follows:
+
+`Dn(Bn)'
+ the address for operand number n is formed from the content of
+ general register Bn called the base register and the displacement
+ field Dn.
+
+`Dn(Xn,Bn)'
+ the address for operand number n is formed from the content of
+ general register Xn called the index register, general register Bn
+ called the base register and the displacement field Dn.
+
+`Dn(Ln,Bn)'
+ the address for operand number n is formed from the content of
+ general regiser Bn called the base register and the displacement
+ field Dn. The length of the operand n is specified by the field
+ Ln.
+
+ The base registers Bn and the index registers Xn of a storage
+operand can be skipped. If Bn and Xn are skipped, a zero will be stored
+to the operand field. The notation changes as follows:
+
+ full notation short notation
+ ------------------------------------------
+ Dn(0,Bn) Dn(Bn)
+ Dn(0,0) Dn
+ Dn(0) Dn
+ Dn(Ln,0) Dn(Ln)
+
+
+File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax
+
+9.39.3.4 Instruction Formats
+............................
+
+The Principles of Operation manuals lists 26 instruction formats where
+some of the formats have multiple variants. For the `.insn' pseudo
+directive the assembler recognizes some of the formats. Typically, the
+most general variant of the instruction format is used by the `.insn'
+directive.
+
+ The following table lists the abbreviations used in the table of
+instruction formats:
+
+ OpCode / OpCd Part of the op code.
+ Bx Base register number for operand x.
+ Dx Displacement for operand x.
+ DLx Displacement lower 12 bits for operand x.
+ DHx Displacement higher 8-bits for operand x.
+ Rx Register number for operand x.
+ Xx Index register number for operand x.
+ Ix Signed immediate for operand x.
+ Ux Unsigned immediate for operand x.
+
+ An instruction is two, four, or six bytes in length and must be
+aligned on a 2 byte boundary. The first two bits of the instruction
+specify the length of the instruction, 00 indicates a two byte
+instruction, 01 and 10 indicates a four byte instruction, and 11
+indicates a six byte instruction.
+
+ The following table lists the s390 instruction formats that are
+available with the `.insn' pseudo directive:
+
+`E format'
+
+ +-------------+
+ | OpCode |
+ +-------------+
+ 0 15
+
+`RI format: <insn> R1,I2'
+
+ +--------+----+----+------------------+
+ | OpCode | R1 |OpCd| I2 |
+ +--------+----+----+------------------+
+ 0 8 12 16 31
+
+`RIE format: <insn> R1,R3,I2'
+
+ +--------+----+----+------------------+--------+--------+
+ | OpCode | R1 | R3 | I2 |////////| OpCode |
+ +--------+----+----+------------------+--------+--------+
+ 0 8 12 16 32 40 47
+
+`RIL format: <insn> R1,I2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 |OpCd| I2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RILU format: <insn> R1,U2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 |OpCd| U2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RIS format: <insn> R1,I2,M3,D4(B4)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 36 47
+
+`RR format: <insn> R1,R2'
+
+ +--------+----+----+
+ | OpCode | R1 | R2 |
+ +--------+----+----+
+ 0 8 12 15
+
+`RRE format: <insn> R1,R2'
+
+ +------------------+--------+----+----+
+ | OpCode |////////| R1 | R2 |
+ +------------------+--------+----+----+
+ 0 16 24 28 31
+
+`RRF format: <insn> R1,R2,R3,M4'
+
+ +------------------+----+----+----+----+
+ | OpCode | R3 | M4 | R1 | R2 |
+ +------------------+----+----+----+----+
+ 0 16 20 24 28 31
+
+`RRS format: <insn> R1,R2,M3,D4(B4)'
+
+ +--------+----+----+----+-------------+----+----+--------+
+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+ +--------+----+----+----+-------------+----+----+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`RS format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+
+ | OpCode | R1 | R3 | B2 | D2 |
+ +--------+----+----+----+-------------+
+ 0 8 12 16 20 31
+
+`RSE format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RSI format: <insn> R1,R3,I2'
+
+ +--------+----+----+------------------------------------+
+ | OpCode | R1 | R3 | I2 |
+ +--------+----+----+------------------------------------+
+ 0 8 12 16 47
+
+`RSY format: <insn> R1,R3,D2(B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RX format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+
+ | OpCode | R1 | X2 | B2 | D2 |
+ +--------+----+----+----+-------------+
+ 0 8 12 16 20 31
+
+`RXE format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 40 47
+
+`RXF format: <insn> R1,R3,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+----+---+--------+
+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
+ +--------+----+----+----+-------------+----+---+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`RXY format: <insn> R1,D2(X2,B2)'
+
+ +--------+----+----+----+-------------+--------+--------+
+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
+ +--------+----+----+----+-------------+--------+--------+
+ 0 8 12 16 20 32 36 40 47
+
+`S format: <insn> D2(B2)'
+
+ +------------------+----+-------------+
+ | OpCode | B2 | D2 |
+ +------------------+----+-------------+
+ 0 16 20 31
+
+`SI format: <insn> D1(B1),I2'
+
+ +--------+---------+----+-------------+
+ | OpCode | I2 | B1 | D1 |
+ +--------+---------+----+-------------+
+ 0 8 16 20 31
+
+`SIY format: <insn> D1(B1),U2'
+
+ +--------+---------+----+-------------+--------+--------+
+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode |
+ +--------+---------+----+-------------+--------+--------+
+ 0 8 16 20 32 36 40 47
+
+`SIL format: <insn> D1(B1),I2'
+
+ +------------------+----+-------------+-----------------+
+ | OpCode | B1 | D1 | I2 |
+ +------------------+----+-------------+-----------------+
+ 0 16 20 32 47
+
+`SS format: <insn> D1(R1,B1),D2(B3),R3'
+
+ +--------+----+----+----+-------------+----+------------+
+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
+ +--------+----+----+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+`SSE format: <insn> D1(B1),D2(B2)'
+
+ +------------------+----+-------------+----+------------+
+ | OpCode | B1 | D1 | B2 | D2 |
+ +------------------+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+`SSF format: <insn> D1(B1),D2(B2),R3'
+
+ +--------+----+----+----+-------------+----+------------+
+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
+ +--------+----+----+----+-------------+----+------------+
+ 0 8 12 16 20 32 36 47
+
+
+ For the complete list of all instruction format variants see the
+Principles of Operation manuals.
+
+
+File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax
+
+9.39.3.5 Instruction Aliases
+............................
+
+A specific bit pattern can have multiple mnemonics, for example the bit
+pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition,
+there are a number of mnemonics recognized by `as' that are not present
+in the Principles of Operation. These are the short forms of the
+branch instructions, where the condition code mask operand is encoded
+in the mnemonic. This is relevant for the branch instructions, the
+compare and branch instructions, and the compare and trap instructions.
+
+ For the branch instructions there are 20 condition code strings that
+can be used as part of the mnemonic in place of a mask operand in the
+instruction format:
+
+ instruction short form
+ ------------------------------------------
+ bcr M1,R2 b<m>r R2
+ bc M1,D2(X2,B2) b<m> D2(X2,B2)
+ brc M1,I2 j<m> I2
+ brcl M1,I2 jg<m> I2
+
+ In the mnemonic for a branch instruction the condition code string
+<m> can be any of the following:
+
+ o jump on overflow / if ones
+ h jump on A high
+ p jump on plus
+ nle jump on not low or equal
+ l jump on A low
+ m jump on minus
+ nhe jump on not high or equal
+ lh jump on low or high
+ ne jump on A not equal B
+ nz jump on not zero / if not zeros
+ e jump on A equal B
+ z jump on zero / if zeroes
+ nlh jump on not low or high
+ he jump on high or equal
+ nl jump on A not low
+ nm jump on not minus / if not mixed
+ le jump on low or equal
+ nh jump on A not high
+ np jump on not plus
+ no jump on not overflow / if not ones
+
+ For the compare and branch, and compare and trap instructions there
+are 12 condition code strings that can be used as part of the mnemonic
+in place of a mask operand in the instruction format:
+
+ instruction short form
+ --------------------------------------------------------
+ crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4)
+ cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4)
+ crj R1,R2,M3,I4 crj<m> R1,R2,I4
+ cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4
+ cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4)
+ cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4)
+ cij R1,I2,M3,I4 cij<m> R1,I2,I4
+ cgij R1,I2,M3,I4 cgij<m> R1,I2,I4
+ crt R1,R2,M3 crt<m> R1,R2
+ cgrt R1,R2,M3 cgrt<m> R1,R2
+ cit R1,I2,M3 cit<m> R1,I2
+ cgit R1,I2,M3 cgit<m> R1,I2
+ clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4)
+ clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4)
+ clrj R1,R2,M3,I4 clrj<m> R1,R2,I4
+ clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4
+ clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4)
+ clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4)
+ clij R1,I2,M3,I4 clij<m> R1,I2,I4
+ clgij R1,I2,M3,I4 clgij<m> R1,I2,I4
+ clrt R1,R2,M3 clrt<m> R1,R2
+ clgrt R1,R2,M3 clgrt<m> R1,R2
+ clfit R1,I2,M3 clfit<m> R1,I2
+ clgit R1,I2,M3 clgit<m> R1,I2
+
+ In the mnemonic for a compare and branch and compare and trap
+instruction the condition code string <m> can be any of the following:
+
+ h jump on A high
+ nle jump on not low or equal
+ l jump on A low
+ nhe jump on not high or equal
+ ne jump on A not equal B
+ lh jump on low or high
+ e jump on A equal B
+ nlh jump on not low or high
+ nl jump on A not low
+ he jump on high or equal
+ nh jump on A not high
+ le jump on low or equal
+
+
+File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax
+
+9.39.3.6 Instruction Operand Modifier
+.....................................
+
+If a symbol modifier is attached to a symbol in an expression for an
+instruction operand field, the symbol term is replaced with a reference
+to an object in the global offset table (GOT) or the procedure linkage
+table (PLT). The following expressions are allowed: `symbol@modifier +
+constant', `symbol@modifier + label + constant', and `symbol@modifier -
+label + constant'. The term `symbol' is the symbol that will be
+entered into the GOT or PLT, `label' is a local label, and `constant'
+is an arbitrary expression that the assembler can evaluate to a
+constant value.
+
+ The term `(symbol + constant1)@modifier +/- label + constant2' is
+also accepted but a warning message is printed and the term is
+converted to `symbol@modifier +/- label + constant1 + constant2'.
+
+`@got'
+`@got12'
+ The @got modifier can be used for displacement fields, 16-bit
+ immediate fields and 32-bit pc-relative immediate fields. The
+ @got12 modifier is synonym to @got. The symbol is added to the
+ GOT. For displacement fields and 16-bit immediate fields the
+ symbol term is replaced with the offset from the start of the GOT
+ to the GOT slot for the symbol. For a 32-bit pc-relative field
+ the pc-relative offset to the GOT slot from the current
+ instruction address is used.
+
+`@gotent'
+ The @gotent modifier can be used for 32-bit pc-relative immediate
+ fields. The symbol is added to the GOT and the symbol term is
+ replaced with the pc-relative offset from the current instruction
+ to the GOT slot for the symbol.
+
+`@gotoff'
+ The @gotoff modifier can be used for 16-bit immediate fields. The
+ symbol term is replaced with the offset from the start of the GOT
+ to the address of the symbol.
+
+`@gotplt'
+ The @gotplt modifier can be used for displacement fields, 16-bit
+ immediate fields, and 32-bit pc-relative immediate fields. A
+ procedure linkage table entry is generated for the symbol and a
+ jump slot for the symbol is added to the GOT. For displacement
+ fields and 16-bit immediate fields the symbol term is replaced
+ with the offset from the start of the GOT to the jump slot for the
+ symbol. For a 32-bit pc-relative field the pc-relative offset to
+ the jump slot from the current instruction address is used.
+
+`@plt'
+ The @plt modifier can be used for 16-bit and 32-bit pc-relative
+ immediate fields. A procedure linkage table entry is generated for
+ the symbol. The symbol term is replaced with the relative offset
+ from the current instruction to the PLT entry for the symbol.
+
+`@pltoff'
+ The @pltoff modifier can be used for 16-bit immediate fields. The
+ symbol term is replaced with the offset from the start of the PLT
+ to the address of the symbol.
+
+`@gotntpoff'
+ The @gotntpoff modifier can be used for displacement fields. The
+ symbol is added to the static TLS block and the negated offset to
+ the symbol in the static TLS block is added to the GOT. The symbol
+ term is replaced with the offset to the GOT slot from the start of
+ the GOT.
+
+`@indntpoff'
+ The @indntpoff modifier can be used for 32-bit pc-relative
+ immediate fields. The symbol is added to the static TLS block and
+ the negated offset to the symbol in the static TLS block is added
+ to the GOT. The symbol term is replaced with the pc-relative
+ offset to the GOT slot from the current instruction address.
+
+ For more information about the thread local storage modifiers
+`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF
+Handling For Thread-Local Storage'.
+
+
+File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax
+
+9.39.3.7 Instruction Marker
+...........................
+
+The thread local storage instruction markers are used by the linker to
+perform code optimization.
+
+`:tls_load'
+ The :tls_load marker is used to flag the load instruction in the
+ initial exec TLS model that retrieves the offset from the thread
+ pointer to a thread local storage variable from the GOT.
+
+`:tls_gdcall'
+ The :tls_gdcall marker is used to flag the branch-and-save
+ instruction to the __tls_get_offset function in the global dynamic
+ TLS model.
+
+`:tls_ldcall'
+ The :tls_ldcall marker is used to flag the branch-and-save
+ instruction to the __tls_get_offset function in the local dynamic
+ TLS model.
+
+ For more information about the thread local storage instruction
+marker and the linker optimizations see the ELF extension documentation
+`ELF Handling For Thread-Local Storage'.
+
+
+File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax
+
+9.39.3.8 Literal Pool Entries
+.............................
+
+A literal pool is a collection of values. To access the values a pointer
+to the literal pool is loaded to a register, the literal pool register.
+Usually, register %r13 is used as the literal pool register (*Note s390
+Register::). Literal pool entries are created by adding the suffix
+:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
+instruction operand. The expression is added to the literal pool and the
+operand is replaced with the offset to the literal in the literal pool.
+
+`:lit1'
+ The literal pool entry is created as an 8-bit value. An operand
+ modifier must not be used for the original expression.
+
+`:lit2'
+ The literal pool entry is created as a 16 bit value. The operand
+ modifier @got may be used in the original expression. The term
+ `x@got:lit2' will put the got offset for the global symbol x to
+ the literal pool as 16 bit value.
+
+`:lit4'
+ The literal pool entry is created as a 32-bit value. The operand
+ modifier @got and @plt may be used in the original expression. The
+ term `x@got:lit4' will put the got offset for the global symbol x
+ to the literal pool as a 32-bit value. The term `x@plt:lit4' will
+ put the plt offset for the global symbol x to the literal pool as
+ a 32-bit value.
+
+`:lit8'
+ The literal pool entry is created as a 64-bit value. The operand
+ modifier @got and @plt may be used in the original expression. The
+ term `x@got:lit8' will put the got offset for the global symbol x
+ to the literal pool as a 64-bit value. The term `x@plt:lit8' will
+ put the plt offset for the global symbol x to the literal pool as
+ a 64-bit value.
+
+ The assembler directive `.ltorg' is used to emit all literal pool
+entries to the current position.
+
+
+File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent
+
+9.39.4 Assembler Directives
+---------------------------
+
+`as' for s390 supports all of the standard ELF assembler directives as
+outlined in the main part of this document. Some directives have been
+extended and there are some additional directives, which are only
+available for the s390 `as'.
+
+`.insn'
+ This directive permits the numeric representation of an
+ instructions and makes the assembler insert the operands according
+ to one of the instructions formats for `.insn' (*Note s390
+ Formats::). For example, the instruction `l %r1,24(%r15)' could
+ be written as `.insn rx,0x58000000,%r1,24(%r15)'.
+
+`.short'
+`.long'
+`.quad'
+ This directive places one or more 16-bit (.short), 32-bit (.long),
+ or 64-bit (.quad) values into the current section. If an ELF or
+ TLS modifier is used only the following expressions are allowed:
+ `symbol@modifier + constant', `symbol@modifier + label +
+ constant', and `symbol@modifier - label + constant'. The
+ following modifiers are available:
+ `@got'
+ `@got12'
+ The @got modifier can be used for .short, .long and .quad.
+ The @got12 modifier is synonym to @got. The symbol is added
+ to the GOT. The symbol term is replaced with offset from the
+ start of the GOT to the GOT slot for the symbol.
+
+ `@gotoff'
+ The @gotoff modifier can be used for .short, .long and .quad.
+ The symbol term is replaced with the offset from the start of
+ the GOT to the address of the symbol.
+
+ `@gotplt'
+ The @gotplt modifier can be used for .long and .quad. A
+ procedure linkage table entry is generated for the symbol and
+ a jump slot for the symbol is added to the GOT. The symbol
+ term is replaced with the offset from the start of the GOT to
+ the jump slot for the symbol.
+
+ `@plt'
+ The @plt modifier can be used for .long and .quad. A
+ procedure linkage table entry us generated for the symbol.
+ The symbol term is replaced with the address of the PLT entry
+ for the symbol.
+
+ `@pltoff'
+ The @pltoff modifier can be used for .short, .long and .quad.
+ The symbol term is replaced with the offset from the start of
+ the PLT to the address of the symbol.
+
+ `@tlsgd'
+ `@tlsldm'
+ The @tlsgd and @tlsldm modifier can be used for .long and
+ .quad. A tls_index structure for the symbol is added to the
+ GOT. The symbol term is replaced with the offset from the
+ start of the GOT to the tls_index structure.
+
+ `@gotntpoff'
+ `@indntpoff'
+ The @gotntpoff and @indntpoff modifier can be used for .long
+ and .quad. The symbol is added to the static TLS block and
+ the negated offset to the symbol in the static TLS block is
+ added to the GOT. For @gotntpoff the symbol term is replaced
+ with the offset from the start of the GOT to the GOT slot,
+ for @indntpoff the symbol term is replaced with the address
+ of the GOT slot.
+
+ `@dtpoff'
+ The @dtpoff modifier can be used for .long and .quad. The
+ symbol term is replaced with the offset of the symbol
+ relative to the start of the TLS block it is contained in.
+
+ `@ntpoff'
+ The @ntpoff modifier can be used for .long and .quad. The
+ symbol term is replaced with the offset of the symbol
+ relative to the TCB pointer.
+
+ For more information about the thread local storage modifiers see
+ the ELF extension documentation `ELF Handling For Thread-Local
+ Storage'.
+
+`.ltorg'
+ This directive causes the current contents of the literal pool to
+ be dumped to the current location (*Note s390 Literal Pool
+ Entries::).
+
+`.machine STRING[+EXTENSION]...'
+ This directive allows changing the machine for which code is
+ generated. `string' may be any of the `-march=' selection
+ options, or `push', or `pop'. `.machine push' saves the currently
+ selected cpu, which may be restored with `.machine pop'. Be aware
+ that the cpu string has to be put into double quotes in case it
+ contains characters not appropriate for identifiers. So you have
+ to write `"z9-109"' instead of just `z9-109'. Extensions can be
+ specified after the cpu name, separated by plus charaters. Valid
+ extensions are: `htm', `nohtm', `vx', `novx'. They extend the
+ basic instruction set with features from a higher cpu level, or
+ remove support for a feature from the given cpu level.
+
+ Example: `z13+nohtm' allows all instructions of the z13 cpu except
+ instructions from the HTM facility.
+
+`.machinemode string'
+ This directive allows to change the architecture mode for which
+ code is being generated. `string' may be `esa', `zarch',
+ `zarch_nohighgprs', `push', or `pop'. `.machinemode
+ zarch_nohighgprs' can be used to prevent the `highgprs' flag from
+ being set in the ELF header of the output file. This is useful in
+ situations where the code is gated with a runtime check which
+ makes sure that the code is only executed on kernels providing the
+ `highgprs' feature. `.machinemode push' saves the currently
+ selected mode, which may be restored with `.machinemode pop'.
+
+
+File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent
+
+9.39.5 Floating Point
+---------------------
+
+The assembler recognizes both the IEEE floating-point instruction and
+the hexadecimal floating-point instructions. The floating-point
+constructors `.float', `.single', and `.double' always emit the IEEE
+format. To assemble hexadecimal floating-point constants the `.long'
+and `.quad' directives must be used.
+
+
+File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies
+
+9.40 SCORE Dependent Features
+=============================
+
+* Menu:
+
+* SCORE-Opts:: Assembler options
+* SCORE-Pseudo:: SCORE Assembler Directives
+* SCORE-Syntax:: Syntax
+
+
+File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent
+
+9.40.1 Options
+--------------
+
+The following table lists all available SCORE options.
+
+`-G NUM'
+ This option sets the largest size of an object that can be
+ referenced implicitly with the `gp' register. The default value is
+ 8.
+
+`-EB'
+ Assemble code for a big-endian cpu
+
+`-EL'
+ Assemble code for a little-endian cpu
+
+`-FIXDD'
+ Assemble code for fix data dependency
+
+`-NWARN'
+ Assemble code for no warning message for fix data dependency
+
+`-SCORE5'
+ Assemble code for target is SCORE5
+
+`-SCORE5U'
+ Assemble code for target is SCORE5U
+
+`-SCORE7'
+ Assemble code for target is SCORE7, this is default setting
+
+`-SCORE3'
+ Assemble code for target is SCORE3
+
+`-march=score7'
+ Assemble code for target is SCORE7, this is default setting
+
+`-march=score3'
+ Assemble code for target is SCORE3
+
+`-USE_R1'
+ Assemble code for no warning message when using temp register r1
+
+`-KPIC'
+ Generate code for PIC. This option tells the assembler to generate
+ score position-independent macro expansions. It also tells the
+ assembler to mark the output file as PIC.
+
+`-O0'
+ Assembler will not perform any optimizations
+
+`-V'
+ Sunplus release version
+
+
+
+File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent
+
+9.40.2 SCORE Assembler Directives
+---------------------------------
+
+A number of assembler directives are available for SCORE. The
+following table is far from complete.
+
+`.set nwarn'
+ Let the assembler not to generate warnings if the source machine
+ language instructions happen data dependency.
+
+`.set fixdd'
+ Let the assembler to insert bubbles (32 bit nop instruction / 16
+ bit nop! Instruction) if the source machine language instructions
+ happen data dependency.
+
+`.set nofixdd'
+ Let the assembler to generate warnings if the source machine
+ language instructions happen data dependency. (Default)
+
+`.set r1'
+ Let the assembler not to generate warnings if the source program
+ uses r1. allow user to use r1
+
+`set nor1'
+ Let the assembler to generate warnings if the source program uses
+ r1. (Default)
+
+`.sdata'
+ Tell the assembler to add subsequent data into the sdata section
+
+`.rdata'
+ Tell the assembler to add subsequent data into the rdata section
+
+`.frame "frame-register", "offset", "return-pc-register"'
+ Describe a stack frame. "frame-register" is the frame register,
+ "offset" is the distance from the frame register to the virtual
+ frame pointer, "return-pc-register" is the return program register.
+ You must use ".ent" before ".frame" and only one ".frame" can be
+ used per ".ent".
+
+`.mask "bitmask", "frameoffset"'
+ Indicate which of the integer registers are saved in the current
+ function's stack frame, this is for the debugger to explain the
+ frame chain.
+
+`.ent "proc-name"'
+ Set the beginning of the procedure "proc_name". Use this directive
+ when you want to generate information for the debugger.
+
+`.end proc-name'
+ Set the end of a procedure. Use this directive to generate
+ information for the debugger.
+
+`.bss'
+ Switch the destination of following statements into the bss
+ section, which is used for data that is uninitialized anywhere.
+
+
+
+File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent
+
+9.40.3 SCORE Syntax
+-------------------
+
+* Menu:
+
+* SCORE-Chars:: Special Characters
+
+
+File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax
+
+9.40.3.1 Special Characters
+...........................
+
+The presence of a `#' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies
+
+9.41 Renesas / SuperH SH Dependent Features
+===========================================
+
+* Menu:
+
+* SH Options:: Options
+* SH Syntax:: Syntax
+* SH Floating Point:: Floating Point
+* SH Directives:: SH Machine Directives
+* SH Opcodes:: Opcodes
+
+
+File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
+
+9.41.1 Options
+--------------
+
+`as' has following command-line options for the Renesas (formerly
+Hitachi) / SuperH SH family.
+
+`--little'
+ Generate little endian code.
+
+`--big'
+ Generate big endian code.
+
+`--relax'
+ Alter jump instructions for long displacements.
+
+`--small'
+ Align sections to 4 byte boundaries, not 16.
+
+`--dsp'
+ Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`--renesas'
+ Disable optimization with section symbol for compatibility with
+ Renesas assembler.
+
+`--allow-reg-prefix'
+ Allow '$' as a register name prefix.
+
+`--fdpic'
+ Generate an FDPIC object file.
+
+`--isa=sh4 | sh4a'
+ Specify the sh4 or sh4a instruction set.
+
+`--isa=dsp'
+ Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`--isa=fp'
+ Enable sh2e, sh3e, sh4, and sh4a insn sets.
+
+`--isa=all'
+ Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
+
+
+File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
+
+9.41.2 Syntax
+-------------
+
+* Menu:
+
+* SH-Chars:: Special Characters
+* SH-Regs:: Register Names
+* SH-Addressing:: Addressing Modes
+
+
+File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
+
+9.41.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+ You can use `;' instead of a newline to separate statements.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
+
+9.41.2.2 Register Names
+.......................
+
+You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
+`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
+refer to the SH registers.
+
+ The SH also has these control registers:
+
+`pr'
+ procedure register (holds return address)
+
+`pc'
+ program counter
+
+`mach'
+`macl'
+ high and low multiply accumulator registers
+
+`sr'
+ status register
+
+`gbr'
+ global base register
+
+`vbr'
+ vector base register (for interrupt vectors)
+
+
+File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
+
+9.41.2.3 Addressing Modes
+.........................
+
+`as' understands the following addressing modes for the SH. `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+
+`RN'
+ Register direct
+
+`@RN'
+ Register indirect
+
+`@-RN'
+ Register indirect with pre-decrement
+
+`@RN+'
+ Register indirect with post-increment
+
+`@(DISP, RN)'
+ Register indirect with displacement
+
+`@(R0, RN)'
+ Register indexed
+
+`@(DISP, GBR)'
+ `GBR' offset
+
+`@(R0, GBR)'
+ GBR indexed
+
+`ADDR'
+`@(DISP, PC)'
+ PC relative address (for branch or for addressing memory). The
+ `as' implementation allows you to use the simpler form ADDR
+ anywhere a PC relative address is called for; the alternate form
+ is supported for compatibility with other assemblers.
+
+`#IMM'
+ Immediate data
+
+
+File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
+
+9.41.3 Floating Point
+---------------------
+
+SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
+SH groups can use `.float' directive to generate IEEE floating-point
+numbers.
+
+ SH2E and SH3E support single-precision floating point calculations as
+well as entirely PCAPI compatible emulation of double-precision
+floating point calculations. SH2E and SH3E instructions are a subset of
+the floating point calculations conforming to the IEEE754 standard.
+
+ In addition to single-precision and double-precision floating-point
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic
+engine that enables 32-bit floating-point data to be processed 128 bits
+at a time. It also supports 4 * 4 array operations and inner product
+operations. Also, a superscalar architecture is employed that enables
+simultaneous execution of two instructions (including FPU
+instructions), providing performance of up to twice that of
+conventional architectures at the same frequency.
+
+
+File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
+
+9.41.4 SH Machine Directives
+----------------------------
+
+`uaword'
+`ualong'
+`uaquad'
+ `as' will issue a warning when a misaligned `.word', `.long', or
+ `.quad' directive is used. You may use `.uaword', `.ualong', or
+ `.uaquad' to indicate that the value is intentionally misaligned.
+
+
+File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
+
+9.41.5 Opcodes
+--------------
+
+For detailed information on the SH machine instruction set, see
+`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
+Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).
+
+ `as' implements all the standard SH opcodes. No additional
+pseudo-instructions are needed on this family. Note, however, that
+because `as' supports a simpler form of PC-relative addressing, you may
+simply write (for example)
+
+ mov.l bar,r0
+
+where other assemblers might require an explicit displacement to `bar'
+from the program counter:
+
+ mov.l @(DISP, PC)
+
+ Here is a summary of SH opcodes:
+
+ Legend:
+ Rn a numbered register
+ Rm another numbered register
+ #imm immediate data
+ disp displacement
+ disp8 8-bit displacement
+ disp12 12-bit displacement
+
+ add #imm,Rn lds.l @Rn+,PR
+ add Rm,Rn mac.w @Rm+,@Rn+
+ addc Rm,Rn mov #imm,Rn
+ addv Rm,Rn mov Rm,Rn
+ and #imm,R0 mov.b Rm,@(R0,Rn)
+ and Rm,Rn mov.b Rm,@-Rn
+ and.b #imm,@(R0,GBR) mov.b Rm,@Rn
+ bf disp8 mov.b @(disp,Rm),R0
+ bra disp12 mov.b @(disp,GBR),R0
+ bsr disp12 mov.b @(R0,Rm),Rn
+ bt disp8 mov.b @Rm+,Rn
+ clrmac mov.b @Rm,Rn
+ clrt mov.b R0,@(disp,Rm)
+ cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
+ cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
+ cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
+ cmp/gt Rm,Rn mov.l Rm,@-Rn
+ cmp/hi Rm,Rn mov.l Rm,@Rn
+ cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
+ cmp/pl Rn mov.l @(disp,GBR),R0
+ cmp/pz Rn mov.l @(disp,PC),Rn
+ cmp/str Rm,Rn mov.l @(R0,Rm),Rn
+ div0s Rm,Rn mov.l @Rm+,Rn
+ div0u mov.l @Rm,Rn
+ div1 Rm,Rn mov.l R0,@(disp,GBR)
+ exts.b Rm,Rn mov.w Rm,@(R0,Rn)
+ exts.w Rm,Rn mov.w Rm,@-Rn
+ extu.b Rm,Rn mov.w Rm,@Rn
+ extu.w Rm,Rn mov.w @(disp,Rm),R0
+ jmp @Rn mov.w @(disp,GBR),R0
+ jsr @Rn mov.w @(disp,PC),Rn
+ ldc Rn,GBR mov.w @(R0,Rm),Rn
+ ldc Rn,SR mov.w @Rm+,Rn
+ ldc Rn,VBR mov.w @Rm,Rn
+ ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
+ ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
+ ldc.l @Rn+,VBR mova @(disp,PC),R0
+ lds Rn,MACH movt Rn
+ lds Rn,MACL muls Rm,Rn
+ lds Rn,PR mulu Rm,Rn
+ lds.l @Rn+,MACH neg Rm,Rn
+ lds.l @Rn+,MACL negc Rm,Rn
+
+ nop stc VBR,Rn
+ not Rm,Rn stc.l GBR,@-Rn
+ or #imm,R0 stc.l SR,@-Rn
+ or Rm,Rn stc.l VBR,@-Rn
+ or.b #imm,@(R0,GBR) sts MACH,Rn
+ rotcl Rn sts MACL,Rn
+ rotcr Rn sts PR,Rn
+ rotl Rn sts.l MACH,@-Rn
+ rotr Rn sts.l MACL,@-Rn
+ rte sts.l PR,@-Rn
+ rts sub Rm,Rn
+ sett subc Rm,Rn
+ shal Rn subv Rm,Rn
+ shar Rn swap.b Rm,Rn
+ shll Rn swap.w Rm,Rn
+ shll16 Rn tas.b @Rn
+ shll2 Rn trapa #imm
+ shll8 Rn tst #imm,R0
+ shlr Rn tst Rm,Rn
+ shlr16 Rn tst.b #imm,@(R0,GBR)
+ shlr2 Rn xor #imm,R0
+ shlr8 Rn xor Rm,Rn
+ sleep xor.b #imm,@(R0,GBR)
+ stc GBR,Rn xtrct Rm,Rn
+ stc SR,Rn
+
+
+File: as.info, Node: SH64-Dependent, Next: Sparc-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
+
+9.42 SuperH SH64 Dependent Features
+===================================
+
+* Menu:
+
+* SH64 Options:: Options
+* SH64 Syntax:: Syntax
+* SH64 Directives:: SH64 Machine Directives
+* SH64 Opcodes:: Opcodes
+
+
+File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent
+
+9.42.1 Options
+--------------
+
+`-isa=sh4 | sh4a'
+ Specify the sh4 or sh4a instruction set.
+
+`-isa=dsp'
+ Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`-isa=fp'
+ Enable sh2e, sh3e, sh4, and sh4a insn sets.
+
+`-isa=all'
+ Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+
+`-isa=shmedia | -isa=shcompact'
+ Specify the default instruction set. `SHmedia' specifies the
+ 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
+ compatible with previous SH families. The default depends on the
+ ABI selected; the default for the 64-bit ABI is SHmedia, and the
+ default for the 32-bit ABI is SHcompact. If neither the ABI nor
+ the ISA is specified, the default is 32-bit SHcompact.
+
+ Note that the `.mode' pseudo-op is not permitted if the ISA is not
+ specified on the command line.
+
+`-abi=32 | -abi=64'
+ Specify the default ABI. If the ISA is specified and the ABI is
+ not, the default ABI depends on the ISA, with SHmedia defaulting
+ to 64-bit and SHcompact defaulting to 32-bit.
+
+ Note that the `.abi' pseudo-op is not permitted if the ABI is not
+ specified on the command line. When the ABI is specified on the
+ command line, any `.abi' pseudo-ops in the source must match it.
+
+`-shcompact-const-crange'
+ Emit code-range descriptors for constants in SHcompact code
+ sections.
+
+`-no-mix'
+ Disallow SHmedia code in the same section as constants and
+ SHcompact code.
+
+`-no-expand'
+ Do not expand MOVI, PT, PTA or PTB instructions.
+
+`-expand-pt32'
+ With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
+
+`-h-tick-hex'
+ Support H'00 style hex constants in addition to 0x00 style.
+
+
+
+File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent
+
+9.42.2 Syntax
+-------------
+
+* Menu:
+
+* SH64-Chars:: Special Characters
+* SH64-Regs:: Register Names
+* SH64-Addressing:: Addressing Modes
+
+
+File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax
+
+9.42.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ You can use `;' instead of a newline to separate statements.
+
+ Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax
+
+9.42.2.2 Register Names
+.......................
+
+You can use the predefined symbols `r0' through `r63' to refer to the
+SH64 general registers, `cr0' through `cr63' for control registers,
+`tr0' through `tr7' for target address registers, `fr0' through `fr63'
+for single-precision floating point registers, `dr0' through `dr62'
+(even numbered registers only) for double-precision floating point
+registers, `fv0' through `fv60' (multiples of four only) for
+single-precision floating point vectors, `fp0' through `fp62' (even
+numbered registers only) for single-precision floating point pairs,
+`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
+single-precision floating point registers, `pc' for the program
+counter, and `fpscr' for the floating point status and control register.
+
+ You can also refer to the control registers by the mnemonics `sr',
+`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
+`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.
+
+
+File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax
+
+9.42.2.3 Addressing Modes
+.........................
+
+SH64 operands consist of either a register or immediate value. The
+immediate value can be a constant or label reference (or portion of a
+label reference), as in this example:
+
+ movi 4,r2
+ pt function, tr4
+ movi (function >> 16) & 65535,r0
+ shori function & 65535, r0
+ ld.l r0,4,r0
+
+ Instruction label references can reference labels in either SHmedia
+or SHcompact. To differentiate between the two, labels in SHmedia
+sections will always have the least significant bit set (i.e. they will
+be odd), which SHcompact labels will have the least significant bit
+reset (i.e. they will be even). If you need to reference the actual
+address of a label, you can use the `datalabel' modifier, as in this
+example:
+
+ .long function
+ .long datalabel function
+
+ In that example, the first longword may or may not have the least
+significant bit set depending on whether the label is an SHmedia label
+or an SHcompact label. The second longword will be the actual address
+of the label, regardless of what type of label it is.
+
+
+File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent
+
+9.42.3 SH64 Machine Directives
+------------------------------
+
+In addition to the SH directives, the SH64 provides the following
+directives:
+
+`.mode [shmedia|shcompact]'
+`.isa [shmedia|shcompact]'
+ Specify the ISA for the following instructions (the two directives
+ are equivalent). Note that programs such as `objdump' rely on
+ symbolic labels to determine when such mode switches occur (by
+ checking the least significant bit of the label's address), so
+ such mode/isa changes should always be followed by a label (in
+ practice, this is true anyway). Note that you cannot use these
+ directives if you didn't specify an ISA on the command line.
+
+`.abi [32|64]'
+ Specify the ABI for the following instructions. Note that you
+ cannot use this directive unless you specified an ABI on the
+ command line, and the ABIs specified must match.
+
+
+
+File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent
+
+9.42.4 Opcodes
+--------------
+
+For detailed information on the SH64 machine instruction set, see
+`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
+
+ `as' implements all the standard SH64 opcodes. In addition, the
+following pseudo-opcodes may be expanded into one or more alternate
+opcodes:
+
+`movi'
+ If the value doesn't fit into a standard `movi' opcode, `as' will
+ replace the `movi' with a sequence of `movi' and `shori' opcodes.
+
+`pt'
+ This expands to a sequence of `movi' and `shori' opcode, followed
+ by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
+ the label referenced.
+
+
+
+File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies
+
+9.43 SPARC Dependent Features
+=============================
+
+* Menu:
+
+* Sparc-Opts:: Options
+* Sparc-Aligned-Data:: Option to enforce aligned data
+* Sparc-Syntax:: Syntax
+* Sparc-Float:: Floating Point
+* Sparc-Directives:: Sparc Machine Directives
+
+
+File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
+
+9.43.1 Options
+--------------
+
+The SPARC chip family includes several successive versions, using the
+same core instruction set, but including a few additional instructions
+at each version. There are exceptions to this however. For details on
+what instructions each variant supports, please see the chip's
+architecture reference manual.
+
+ By default, `as' assumes the core instruction set (SPARC v6), but
+"bumps" the architecture level as needed: it switches to successively
+higher architectures as it encounters instructions that only exist in
+the higher levels.
+
+ If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
+past sparclite by default, an option must be passed to enable the v9
+instructions.
+
+ GAS treats sparclite as being compatible with v8, unless an
+architecture is explicitly requested. SPARC v9 is always incompatible
+with sparclite.
+
+`-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite'
+`-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm'
+`-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m'
+`-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima'
+`-Asparcvis3 | -Asparcvis3r | -Asparc5'
+ Use one of the `-A' options to select one of the SPARC
+ architectures explicitly. If you select an architecture
+ explicitly, `as' reports a fatal error if it encounters an
+ instruction or feature requiring an incompatible or higher level.
+
+ `-Av8plus', `-Av8plusa', `-Av8plusb', `-Av8plusc', `-Av8plusd',
+ and `-Av8plusv' select a 32 bit environment.
+
+ `-Av9', `-Av9a', `-Av9b', `-Av9c', `-Av9d', `-Av9e', `-Av9v' and
+ `-Av9m' select a 64 bit environment and are not available unless
+ GAS is explicitly configured with 64 bit environment support.
+
+ `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
+ UltraSPARC VIS 1.0 extensions.
+
+ `-Av8plusb' and `-Av9b' enable the UltraSPARC VIS 2.0 instructions,
+ as well as the instructions enabled by `-Av8plusa' and `-Av9a'.
+
+ `-Av8plusc' and `-Av9c' enable the UltraSPARC Niagara instructions,
+ as well as the instructions enabled by `-Av8plusb' and `-Av9b'.
+
+ `-Av8plusd' and `-Av9d' enable the floating point fused
+ multiply-add, VIS 3.0, and HPC extension instructions, as well as
+ the instructions enabled by `-Av8plusc' and `-Av9c'.
+
+ `-Av8pluse' and `-Av9e' enable the cryptographic instructions, as
+ well as the instructions enabled by `-Av8plusd' and `-Av9d'.
+
+ `-Av8plusv' and `-Av9v' enable floating point unfused
+ multiply-add, and integer multiply-add, as well as the instructions
+ enabled by `-Av8pluse' and `-Av9e'.
+
+ `-Av8plusm' and `-Av9m' enable the VIS 4.0, subtract extended,
+ xmpmul, xmontmul and xmontsqr instructions, as well as the
+ instructions enabled by `-Av8plusv' and `-Av9v'.
+
+ `-Asparc' specifies a v9 environment. It is equivalent to `-Av9'
+ if the word size is 64-bit, and `-Av8plus' otherwise.
+
+ `-Asparcvis' specifies a v9a environment. It is equivalent to
+ `-Av9a' if the word size is 64-bit, and `-Av8plusa' otherwise.
+
+ `-Asparcvis2' specifies a v9b environment. It is equivalent to
+ `-Av9b' if the word size is 64-bit, and `-Av8plusb' otherwise.
+
+ `-Asparcfmaf' specifies a v9b environment with the floating point
+ fused multiply-add instructions enabled.
+
+ `-Asparcima' specifies a v9b environment with the integer
+ multiply-add instructions enabled.
+
+ `-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC ,
+ and floating point fused multiply-add instructions enabled.
+
+ `-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC,
+ and floating point unfused multiply-add instructions enabled.
+
+ `-Asparc5' is equivalent to `-Av9m'.
+
+`-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc'
+`-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a'
+`-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m'
+`-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2'
+`-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3'
+`-xarch=sparcvis3r | -xarch=sparc5'
+ For compatibility with the SunOS v9 assembler. These options are
+ equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
+ -Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e,
+ -Av9v, -Av9m, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf,
+ -Asparcima, -Asparcvis3, and -Asparcvis3r, respectively.
+
+`-bump'
+ Warn whenever it is necessary to switch to another level. If an
+ architecture level is explicitly requested, GAS will not issue
+ warnings until that level is reached, and will then bump the level
+ as required (except between incompatible levels).
+
+`-32 | -64'
+ Select the word size, either 32 bits or 64 bits. These options
+ are only available with the ELF object file format, and require
+ that the necessary BFD support has been included.
+
+`--dcti-couples-detect'
+ Warn if a DCTI (delayed control transfer instruction) couple is
+ found when generating code for a variant of the SPARC architecture
+ in which the execution of the couple is unpredictable, or very
+ slow. This is disabled by default.
+
+
+File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent
+
+9.43.2 Enforcing aligned data
+-----------------------------
+
+SPARC GAS normally permits data to be misaligned. For example, it
+permits the `.long' pseudo-op to be used on a byte boundary. However,
+the native SunOS assemblers issue an error when they see misaligned
+data.
+
+ You can use the `--enforce-aligned-data' option to make SPARC GAS
+also issue an error about misaligned data, just as the SunOS assemblers
+do.
+
+ The `--enforce-aligned-data' option is not the default because gcc
+issues misaligned data pseudo-ops when it initializes certain packed
+data structures (structures defined using the `packed' attribute). You
+may have to assemble with GAS in order to initialize packed data
+structures in your own code.
+
+
+File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
+
+9.43.3 Sparc Syntax
+-------------------
+
+The assembler syntax closely follows The Sparc Architecture Manual,
+versions 8 and 9, as well as most extensions defined by Sun for their
+UltraSPARC and Niagara line of processors.
+
+* Menu:
+
+* Sparc-Chars:: Special Characters
+* Sparc-Regs:: Register Names
+* Sparc-Constants:: Constant Names
+* Sparc-Relocs:: Relocations
+* Sparc-Size-Translations:: Size Translations
+
+
+File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax
+
+9.43.3.1 Special Characters
+...........................
+
+A `!' character appearing anywhere on a line indicates the start of a
+comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ `;' can be used instead of a newline to separate statements.
+
+
+File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax
+
+9.43.3.2 Register Names
+.......................
+
+The Sparc integer register file is broken down into global, outgoing,
+local, and incoming.
+
+ * The 8 global registers are referred to as `%gN'.
+
+ * The 8 outgoing registers are referred to as `%oN'.
+
+ * The 8 local registers are referred to as `%lN'.
+
+ * The 8 incoming registers are referred to as `%iN'.
+
+ * The frame pointer register `%i6' can be referenced using the alias
+ `%fp'.
+
+ * The stack pointer register `%o6' can be referenced using the alias
+ `%sp'.
+
+ Floating point registers are simply referred to as `%fN'. When
+assembling for pre-V9, only 32 floating point registers are available.
+For V9 and later there are 64, but there are restrictions when
+referencing the upper 32 registers. They can only be accessed as
+double or quad, and thus only even or quad numbered accesses are
+allowed. For example, `%f34' is a legal floating point register, but
+`%f35' is not.
+
+ Floating point registers accessed as double can also be referred
+using the `%dN' notation, where N is even. Similarly, floating point
+registers accessed as quad can be referred using the `%qN' notation,
+where N is a multiple of 4. For example, `%f4' can be denoted as both
+`%d4' and `%q4'. On the other hand, `%f2' can be denoted as `%d2' but
+not as `%q2'.
+
+ Certain V9 instructions allow access to ancillary state registers.
+Most simply they can be referred to as `%asrN' where N can be from 16
+to 31. However, there are some aliases defined to reference ASR
+registers defined for various UltraSPARC processors:
+
+ * The tick compare register is referred to as `%tick_cmpr'.
+
+ * The system tick register is referred to as `%stick'. An alias,
+ `%sys_tick', exists but is deprecated and should not be used by
+ new software.
+
+ * The system tick compare register is referred to as `%stick_cmpr'.
+ An alias, `%sys_tick_cmpr', exists but is deprecated and should
+ not be used by new software.
+
+ * The software interrupt register is referred to as `%softint'.
+
+ * The set software interrupt register is referred to as
+ `%set_softint'. The mnemonic `%softint_set' is provided as an
+ alias.
+
+ * The clear software interrupt register is referred to as
+ `%clear_softint'. The mnemonic `%softint_clear' is provided as an
+ alias.
+
+ * The performance instrumentation counters register is referred to as
+ `%pic'.
+
+ * The performance control register is referred to as `%pcr'.
+
+ * The graphics status register is referred to as `%gsr'.
+
+ * The V9 dispatch control register is referred to as `%dcr'.
+
+ Various V9 branch and conditional move instructions allow
+specification of which set of integer condition codes to test. These
+are referred to as `%xcc' and `%icc'.
+
+ Additionally, GAS supports the so-called "natural" condition codes;
+these are referred to as `%ncc' and reference to `%icc' if the word
+size is 32, `%xcc' if the word size is 64.
+
+ In V9, there are 4 sets of floating point condition codes which are
+referred to as `%fccN'.
+
+ Several special privileged and non-privileged registers exist:
+
+ * The V9 address space identifier register is referred to as `%asi'.
+
+ * The V9 restorable windows register is referred to as `%canrestore'.
+
+ * The V9 savable windows register is referred to as `%cansave'.
+
+ * The V9 clean windows register is referred to as `%cleanwin'.
+
+ * The V9 current window pointer register is referred to as `%cwp'.
+
+ * The floating-point queue register is referred to as `%fq'.
+
+ * The V8 co-processor queue register is referred to as `%cq'.
+
+ * The floating point status register is referred to as `%fsr'.
+
+ * The other windows register is referred to as `%otherwin'.
+
+ * The V9 program counter register is referred to as `%pc'.
+
+ * The V9 next program counter register is referred to as `%npc'.
+
+ * The V9 processor interrupt level register is referred to as `%pil'.
+
+ * The V9 processor state register is referred to as `%pstate'.
+
+ * The trap base address register is referred to as `%tba'.
+
+ * The V9 tick register is referred to as `%tick'.
+
+ * The V9 trap level is referred to as `%tl'.
+
+ * The V9 trap program counter is referred to as `%tpc'.
+
+ * The V9 trap next program counter is referred to as `%tnpc'.
+
+ * The V9 trap state is referred to as `%tstate'.
+
+ * The V9 trap type is referred to as `%tt'.
+
+ * The V9 condition codes is referred to as `%ccr'.
+
+ * The V9 floating-point registers state is referred to as `%fprs'.
+
+ * The V9 version register is referred to as `%ver'.
+
+ * The V9 window state register is referred to as `%wstate'.
+
+ * The Y register is referred to as `%y'.
+
+ * The V8 window invalid mask register is referred to as `%wim'.
+
+ * The V8 processor state register is referred to as `%psr'.
+
+ * The V9 global register level register is referred to as `%gl'.
+
+ Several special register names exist for hypervisor mode code:
+
+ * The hyperprivileged processor state register is referred to as
+ `%hpstate'.
+
+ * The hyperprivileged trap state register is referred to as
+ `%htstate'.
+
+ * The hyperprivileged interrupt pending register is referred to as
+ `%hintp'.
+
+ * The hyperprivileged trap base address register is referred to as
+ `%htba'.
+
+ * The hyperprivileged implementation version register is referred to
+ as `%hver'.
+
+ * The hyperprivileged system tick offset register is referred to as
+ `%hstick_offset'. Note that there is no `%hstick' register, the
+ normal `%stick' is used.
+
+ * The hyperprivileged system tick enable register is referred to as
+ `%hstick_enable'.
+
+ * The hyperprivileged system tick compare register is referred to as
+ `%hstick_cmpr'.
+
+
+File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax
+
+9.43.3.3 Constants
+..................
+
+Several Sparc instructions take an immediate operand field for which
+mnemonic names exist. Two such examples are `membar' and `prefetch'.
+Another example are the set of V9 memory access instruction that allow
+specification of an address space identifier.
+
+ The `membar' instruction specifies a memory barrier that is the
+defined by the operand which is a bitmask. The supported mask
+mnemonics are:
+
+ * `#Sync' requests that all operations (including nonmemory
+ reference operations) appearing prior to the `membar' must have
+ been performed and the effects of any exceptions become visible
+ before any instructions after the `membar' may be initiated. This
+ corresponds to `membar' cmask field bit 2.
+
+ * `#MemIssue' requests that all memory reference operations
+ appearing prior to the `membar' must have been performed before
+ any memory operation after the `membar' may be initiated. This
+ corresponds to `membar' cmask field bit 1.
+
+ * `#Lookaside' requests that a store appearing prior to the `membar'
+ must complete before any load following the `membar' referencing
+ the same address can be initiated. This corresponds to `membar'
+ cmask field bit 0.
+
+ * `#StoreStore' defines that the effects of all stores appearing
+ prior to the `membar' instruction must be visible to all
+ processors before the effect of any stores following the `membar'.
+ Equivalent to the deprecated `stbar' instruction. This
+ corresponds to `membar' mmask field bit 3.
+
+ * `#LoadStore' defines all loads appearing prior to the `membar'
+ instruction must have been performed before the effect of any
+ stores following the `membar' is visible to any other processor.
+ This corresponds to `membar' mmask field bit 2.
+
+ * `#StoreLoad' defines that the effects of all stores appearing
+ prior to the `membar' instruction must be visible to all
+ processors before loads following the `membar' may be performed.
+ This corresponds to `membar' mmask field bit 1.
+
+ * `#LoadLoad' defines that all loads appearing prior to the `membar'
+ instruction must have been performed before any loads following
+ the `membar' may be performed. This corresponds to `membar' mmask
+ field bit 0.
+
+
+ These values can be ored together, for example:
+
+ membar #Sync
+ membar #StoreLoad | #LoadLoad
+ membar #StoreLoad | #StoreStore
+
+ The `prefetch' and `prefetcha' instructions take a prefetch function
+code. The following prefetch function code constant mnemonics are
+available:
+
+ * `#n_reads' requests a prefetch for several reads, and corresponds
+ to a prefetch function code of 0.
+
+ `#one_read' requests a prefetch for one read, and corresponds to a
+ prefetch function code of 1.
+
+ `#n_writes' requests a prefetch for several writes (and possibly
+ reads), and corresponds to a prefetch function code of 2.
+
+ `#one_write' requests a prefetch for one write, and corresponds to
+ a prefetch function code of 3.
+
+ `#page' requests a prefetch page, and corresponds to a prefetch
+ function code of 4.
+
+ `#invalidate' requests a prefetch invalidate, and corresponds to a
+ prefetch function code of 16.
+
+ `#unified' requests a prefetch to the nearest unified cache, and
+ corresponds to a prefetch function code of 17.
+
+ `#n_reads_strong' requests a strong prefetch for several reads,
+ and corresponds to a prefetch function code of 20.
+
+ `#one_read_strong' requests a strong prefetch for one read, and
+ corresponds to a prefetch function code of 21.
+
+ `#n_writes_strong' requests a strong prefetch for several writes,
+ and corresponds to a prefetch function code of 22.
+
+ `#one_write_strong' requests a strong prefetch for one write, and
+ corresponds to a prefetch function code of 23.
+
+ Onle one prefetch code may be specified. Here are some examples:
+
+ prefetch [%l0 + %l2], #one_read
+ prefetch [%g2 + 8], #n_writes
+ prefetcha [%g1] 0x8, #unified
+ prefetcha [%o0 + 0x10] %asi, #n_reads
+
+ The actual behavior of a given prefetch function code is processor
+ specific. If a processor does not implement a given prefetch
+ function code, it will treat the prefetch instruction as a nop.
+
+ For instructions that accept an immediate address space identifier,
+ `as' provides many mnemonics corresponding to V9 defined as well
+ as UltraSPARC and Niagara extended values. For example, `#ASI_P'
+ and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor
+ specific manuals for details.
+
+
+
+File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax
+
+9.43.3.4 Relocations
+....................
+
+ELF relocations are available as defined in the 32-bit and 64-bit Sparc
+ELF specifications.
+
+ `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is
+obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix'
+and `R_SPARC_LOX10' is obtained using `%lox'. For example:
+
+ sethi %hi(symbol), %g1
+ or %g1, %lo(symbol), %g1
+
+ sethi %hix(symbol), %g1
+ xor %g1, %lox(symbol), %g1
+
+ These "high" mnemonics extract bits 31:10 of their operand, and the
+"low" mnemonics extract bits 9:0 of their operand.
+
+ V9 code model relocations can be requested as follows:
+
+ * `R_SPARC_HH22' is requested using `%hh'. It can also be generated
+ using `%uhi'.
+
+ * `R_SPARC_HM10' is requested using `%hm'. It can also be generated
+ using `%ulo'.
+
+ * `R_SPARC_LM22' is requested using `%lm'.
+
+ * `R_SPARC_H44' is requested using `%h44'.
+
+ * `R_SPARC_M44' is requested using `%m44'.
+
+ * `R_SPARC_L44' is requested using `%l44' or `%l34'.
+
+ * `R_SPARC_H34' is requested using `%h34'.
+
+ The `%l34' generates a `R_SPARC_L44' relocation because it
+calculates the necessary value, and therefore no explicit `R_SPARC_L34'
+relocation needed to be created for this purpose.
+
+ The `%h34' and `%l34' relocations are used for the abs34 code model.
+Here is an example abs34 address generation sequence:
+
+ sethi %h34(symbol), %g1
+ sllx %g1, 2, %g1
+ or %g1, %l34(symbol), %g1
+
+ The PC relative relocation `R_SPARC_PC22' can be obtained by
+enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10'
+relocation can be obtained using `%pc10'. These are mostly used when
+assembling PIC code. For example, the standard PIC sequence on Sparc
+to get the base of the global offset table, PC relative, into a
+register, can be performed as:
+
+ sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
+ add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
+
+ Several relocations exist to allow the link editor to potentially
+optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22'
+relocation can obtained by enclosing an operand inside of
+`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained
+by enclosing an operand inside of `%gdop_lox10'. Likewise,
+`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of
+`%gdop'. For example, assuming the GOT base is in register `%l7':
+
+ sethi %gdop_hix22(symbol), %l1
+ xor %l1, %gdop_lox10(symbol), %l1
+ ld [%l7 + %l1], %l2, %gdop(symbol)
+
+ There are many relocations that can be requested for access to
+thread local storage variables. All of the Sparc TLS mnemonics are
+supported:
+
+ * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'.
+
+ * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'.
+
+ * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'.
+
+ * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'.
+
+ * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'.
+
+ * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'.
+
+ * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'.
+
+ * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'.
+
+ * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'.
+
+ * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'.
+
+ * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'.
+
+ * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'.
+
+ * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'.
+
+ * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'.
+
+ * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'.
+
+ * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'.
+
+ * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'.
+
+ * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'.
+
+ Here are some example TLS model sequences.
+
+ First, General Dynamic:
+
+ sethi %tgd_hi22(symbol), %l1
+ add %l1, %tgd_lo10(symbol), %l1
+ add %l7, %l1, %o0, %tgd_add(symbol)
+ call __tls_get_addr, %tgd_call(symbol)
+ nop
+
+ Local Dynamic:
+
+ sethi %tldm_hi22(symbol), %l1
+ add %l1, %tldm_lo10(symbol), %l1
+ add %l7, %l1, %o0, %tldm_add(symbol)
+ call __tls_get_addr, %tldm_call(symbol)
+ nop
+
+ sethi %tldo_hix22(symbol), %l1
+ xor %l1, %tldo_lox10(symbol), %l1
+ add %o0, %l1, %l1, %tldo_add(symbol)
+
+ Initial Exec:
+
+ sethi %tie_hi22(symbol), %l1
+ add %l1, %tie_lo10(symbol), %l1
+ ld [%l7 + %l1], %o0, %tie_ld(symbol)
+ add %g7, %o0, %o0, %tie_add(symbol)
+
+ sethi %tie_hi22(symbol), %l1
+ add %l1, %tie_lo10(symbol), %l1
+ ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
+ add %g7, %o0, %o0, %tie_add(symbol)
+
+ And finally, Local Exec:
+
+ sethi %tle_hix22(symbol), %l1
+ add %l1, %tle_lox10(symbol), %l1
+ add %g7, %l1, %l1
+
+ When assembling for 64-bit, and a secondary constant addend is
+specified in an address expression that would normally generate an
+`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10'
+instead.
+
+
+File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax
+
+9.43.3.5 Size Translations
+..........................
+
+Often it is desirable to write code in an operand size agnostic manner.
+`as' provides support for this via operand size opcode translations.
+Translations are supported for loads, stores, shifts, compare-and-swap
+atomics, and the `clr' synthetic instruction.
+
+ If generating 32-bit code, `as' will generate the 32-bit opcode.
+Whereas if 64-bit code is being generated, the 64-bit opcode will be
+emitted. For example `ldn' will be transformed into `ld' for 32-bit
+code and `ldx' for 64-bit code.
+
+ Here is an example meant to demonstrate all the supported opcode
+translations:
+
+ ldn [%o0], %o1
+ ldna [%o0] %asi, %o2
+ stn %o1, [%o0]
+ stna %o2, [%o0] %asi
+ slln %o3, 3, %o3
+ srln %o4, 8, %o4
+ sran %o5, 12, %o5
+ casn [%o0], %o1, %o2
+ casna [%o0] %asi, %o1, %o2
+ clrn %g1
+
+ In 32-bit mode `as' will emit:
+
+ ld [%o0], %o1
+ lda [%o0] %asi, %o2
+ st %o1, [%o0]
+ sta %o2, [%o0] %asi
+ sll %o3, 3, %o3
+ srl %o4, 8, %o4
+ sra %o5, 12, %o5
+ cas [%o0], %o1, %o2
+ casa [%o0] %asi, %o1, %o2
+ clr %g1
+
+ And in 64-bit mode `as' will emit:
+
+ ldx [%o0], %o1
+ ldxa [%o0] %asi, %o2
+ stx %o1, [%o0]
+ stxa %o2, [%o0] %asi
+ sllx %o3, 3, %o3
+ srlx %o4, 8, %o4
+ srax %o5, 12, %o5
+ casx [%o0], %o1, %o2
+ casxa [%o0] %asi, %o1, %o2
+ clrx %g1
+
+ Finally, the `.nword' translating directive is supported as well.
+It is documented in the section on Sparc machine directives.
+
+
+File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent
+
+9.43.4 Floating Point
+---------------------
+
+The Sparc uses IEEE floating-point numbers.
+
+
+File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
+
+9.43.5 Sparc Machine Directives
+-------------------------------
+
+The Sparc version of `as' supports the following additional machine
+directives:
+
+`.align'
+ This must be followed by the desired alignment in bytes.
+
+`.common'
+ This must be followed by a symbol name, a positive number, and
+ `"bss"'. This behaves somewhat like `.comm', but the syntax is
+ different.
+
+`.half'
+ This is functionally identical to `.short'.
+
+`.nword'
+ On the Sparc, the `.nword' directive produces native word sized
+ value, ie. if assembling with -32 it is equivalent to `.word', if
+ assembling with -64 it is equivalent to `.xword'.
+
+`.proc'
+ This directive is ignored. Any text following it on the same line
+ is also ignored.
+
+`.register'
+ This directive declares use of a global application or system
+ register. It must be followed by a register name %g2, %g3, %g6 or
+ %g7, comma and the symbol name for that register. If symbol name
+ is `#scratch', it is a scratch register, if it is `#ignore', it
+ just suppresses any errors about using undeclared global register,
+ but does not emit any information about it into the object file.
+ This can be useful e.g. if you save the register before use and
+ restore it after.
+
+`.reserve'
+ This must be followed by a symbol name, a positive number, and
+ `"bss"'. This behaves somewhat like `.lcomm', but the syntax is
+ different.
+
+`.seg'
+ This must be followed by `"text"', `"data"', or `"data1"'. It
+ behaves like `.text', `.data', or `.data 1'.
+
+`.skip'
+ This is functionally identical to the `.space' directive.
+
+`.word'
+ On the Sparc, the `.word' directive produces 32 bit values,
+ instead of the 16 bit values it produces on many other machines.
+
+`.xword'
+ On the Sparc V9 processor, the `.xword' directive produces 64 bit
+ values.
+
+
+File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
+
+9.44 TIC54X Dependent Features
+==============================
+
+* Menu:
+
+* TIC54X-Opts:: Command-line Options
+* TIC54X-Block:: Blocking
+* TIC54X-Env:: Environment Settings
+* TIC54X-Constants:: Constants Syntax
+* TIC54X-Subsyms:: String Substitution
+* TIC54X-Locals:: Local Label Syntax
+* TIC54X-Builtins:: Builtin Assembler Math Functions
+* TIC54X-Ext:: Extended Addressing Support
+* TIC54X-Directives:: Directives
+* TIC54X-Macros:: Macro Features
+* TIC54X-MMRegs:: Memory-mapped Registers
+* TIC54X-Syntax:: Syntax
+
+
+File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent
+
+9.44.1 Options
+--------------
+
+The TMS320C54X version of `as' has a few machine-dependent options.
+
+ You can use the `-mfar-mode' option to enable extended addressing
+mode. All addresses will be assumed to be > 16 bits, and the
+appropriate relocation types will be used. This option is equivalent
+to using the `.far_mode' directive in the assembly code. If you do not
+use the `-mfar-mode' option, all references will be assumed to be 16
+bits. This option may be abbreviated to `-mf'.
+
+ You can use the `-mcpu' option to specify a particular CPU. This
+option is equivalent to using the `.version' directive in the assembly
+code. For recognized CPU codes, see *Note `.version':
+TIC54X-Directives. The default CPU version is `542'.
+
+ You can use the `-merrors-to-file' option to redirect error output
+to a file (this provided for those deficient environments which don't
+provide adequate output redirection). This option may be abbreviated to
+`-me'.
+
+
+File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent
+
+9.44.2 Blocking
+---------------
+
+A blocked section or memory block is guaranteed not to cross the
+blocking boundary (usually a page, or 128 words) if it is smaller than
+the blocking size, or to start on a page boundary if it is larger than
+the blocking size.
+
+
+File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent
+
+9.44.3 Environment Settings
+---------------------------
+
+`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
+to the list of directories normally searched for source and include
+files. `C54XDSP_DIR' will override `A_DIR'.
+
+
+File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent
+
+9.44.4 Constants Syntax
+-----------------------
+
+The TIC54X version of `as' allows the following additional constant
+formats, using a suffix to indicate the radix:
+
+ Binary `000000B, 011000b'
+ Octal `10Q, 224q'
+ Hexadecimal `45h, 0FH'
+
+
+File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent
+
+9.44.5 String Substitution
+--------------------------
+
+A subset of allowable symbols (which we'll call subsyms) may be assigned
+arbitrary string values. This is roughly equivalent to C preprocessor
+#define macros. When `as' encounters one of these symbols, the symbol
+is replaced in the input stream by its string value. Subsym names
+*must* begin with a letter.
+
+ Subsyms may be defined using the `.asg' and `.eval' directives
+(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives.
+
+ Expansion is recursive until a previously encountered symbol is
+seen, at which point substitution stops.
+
+ In this example, x is replaced with SYM2; SYM2 is replaced with
+SYM1, and SYM1 is replaced with x. At this point, x has already been
+encountered and the substitution stops.
+
+ .asg "x",SYM1
+ .asg "SYM1",SYM2
+ .asg "SYM2",x
+ add x,a ; final code assembled is "add x, a"
+
+ Macro parameters are converted to subsyms; a side effect of this is
+the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms
+defined within a macro will have global scope, unless the `.var'
+directive is used to identify the subsym as a local macro variable
+*note `.var': TIC54X-Directives.
+
+ Substitution may be forced in situations where replacement might be
+ambiguous by placing colons on either side of the subsym. The following
+code:
+
+ .eval "10",x
+ LAB:X: add #x, a
+
+ When assembled becomes:
+
+ LAB10 add #10, a
+
+ Smaller parts of the string assigned to a subsym may be accessed with
+the following syntax:
+
+``:SYMBOL(CHAR_INDEX):''
+ Evaluates to a single-character string, the character at
+ CHAR_INDEX.
+
+``:SYMBOL(START,LENGTH):''
+ Evaluates to a substring of SYMBOL beginning at START with length
+ LENGTH.
+
+
+File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent
+
+9.44.6 Local Labels
+-------------------
+
+Local labels may be defined in two ways:
+
+ * $N, where N is a decimal number between 0 and 9
+
+ * LABEL?, where LABEL is any legal symbol name.
+
+ Local labels thus defined may be redefined or automatically
+generated. The scope of a local label is based on when it may be
+undefined or reset. This happens when one of the following situations
+is encountered:
+
+ * .newblock directive *note `.newblock': TIC54X-Directives.
+
+ * The current section is changed (.sect, .text, or .data)
+
+ * Entering or leaving an included file
+
+ * The macro scope where the label was defined is exited
+
+
+File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent
+
+9.44.7 Math Builtins
+--------------------
+
+The following built-in functions may be used to generate a
+floating-point value. All return a floating-point value except `$cvi',
+`$int', and `$sgn', which return an integer value.
+
+``$acos(EXPR)''
+ Returns the floating point arccosine of EXPR.
+
+``$asin(EXPR)''
+ Returns the floating point arcsine of EXPR.
+
+``$atan(EXPR)''
+ Returns the floating point arctangent of EXPR.
+
+``$atan2(EXPR1,EXPR2)''
+ Returns the floating point arctangent of EXPR1 / EXPR2.
+
+``$ceil(EXPR)''
+ Returns the smallest integer not less than EXPR as floating point.
+
+``$cosh(EXPR)''
+ Returns the floating point hyperbolic cosine of EXPR.
+
+``$cos(EXPR)''
+ Returns the floating point cosine of EXPR.
+
+``$cvf(EXPR)''
+ Returns the integer value EXPR converted to floating-point.
+
+``$cvi(EXPR)''
+ Returns the floating point value EXPR converted to integer.
+
+``$exp(EXPR)''
+ Returns the floating point value e ^ EXPR.
+
+``$fabs(EXPR)''
+ Returns the floating point absolute value of EXPR.
+
+``$floor(EXPR)''
+ Returns the largest integer that is not greater than EXPR as
+ floating point.
+
+``$fmod(EXPR1,EXPR2)''
+ Returns the floating point remainder of EXPR1 / EXPR2.
+
+``$int(EXPR)''
+ Returns 1 if EXPR evaluates to an integer, zero otherwise.
+
+``$ldexp(EXPR1,EXPR2)''
+ Returns the floating point value EXPR1 * 2 ^ EXPR2.
+
+``$log10(EXPR)''
+ Returns the base 10 logarithm of EXPR.
+
+``$log(EXPR)''
+ Returns the natural logarithm of EXPR.
+
+``$max(EXPR1,EXPR2)''
+ Returns the floating point maximum of EXPR1 and EXPR2.
+
+``$min(EXPR1,EXPR2)''
+ Returns the floating point minimum of EXPR1 and EXPR2.
+
+``$pow(EXPR1,EXPR2)''
+ Returns the floating point value EXPR1 ^ EXPR2.
+
+``$round(EXPR)''
+ Returns the nearest integer to EXPR as a floating point number.
+
+``$sgn(EXPR)''
+ Returns -1, 0, or 1 based on the sign of EXPR.
+
+``$sin(EXPR)''
+ Returns the floating point sine of EXPR.
+
+``$sinh(EXPR)''
+ Returns the floating point hyperbolic sine of EXPR.
+
+``$sqrt(EXPR)''
+ Returns the floating point square root of EXPR.
+
+``$tan(EXPR)''
+ Returns the floating point tangent of EXPR.
+
+``$tanh(EXPR)''
+ Returns the floating point hyperbolic tangent of EXPR.
+
+``$trunc(EXPR)''
+ Returns the integer value of EXPR truncated towards zero as
+ floating point.
+
+
+
+File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent
+
+9.44.8 Extended Addressing
+--------------------------
+
+The `LDX' pseudo-op is provided for loading the extended addressing bits
+of a label or address. For example, if an address `_label' resides in
+extended program memory, the value of `_label' may be loaded as follows:
+ ldx #_label,16,a ; loads extended bits of _label
+ or #_label,a ; loads lower 16 bits of _label
+ bacc a ; full address is in accumulator A
+
+
+File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent
+
+9.44.9 Directives
+-----------------
+
+`.align [SIZE]'
+`.even'
+ Align the section program counter on the next boundary, based on
+ SIZE. SIZE may be any power of 2. `.even' is equivalent to
+ `.align' with a SIZE of 2.
+ `1'
+ Align SPC to word boundary
+
+ `2'
+ Align SPC to longword boundary (same as .even)
+
+ `128'
+ Align SPC to page boundary
+
+`.asg STRING, NAME'
+ Assign NAME the string STRING. String replacement is performed on
+ STRING before assignment.
+
+`.eval STRING, NAME'
+ Evaluate the contents of string STRING and assign the result as a
+ string to the subsym NAME. String replacement is performed on
+ STRING before assignment.
+
+`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
+ Reserve space for SYMBOL in the .bss section. SIZE is in words.
+ If present, BLOCKING_FLAG indicates the allocated space should be
+ aligned on a page boundary if it would otherwise cross a page
+ boundary. If present, ALIGNMENT_FLAG causes the assembler to
+ allocate SIZE on a long word boundary.
+
+`.byte VALUE [,...,VALUE_N]'
+`.ubyte VALUE [,...,VALUE_N]'
+`.char VALUE [,...,VALUE_N]'
+`.uchar VALUE [,...,VALUE_N]'
+ Place one or more bytes into consecutive words of the current
+ section. The upper 8 bits of each word is zero-filled. If a
+ label is used, it points to the word allocated for the first byte
+ encountered.
+
+`.clink ["SECTION_NAME"]'
+ Set STYP_CLINK flag for this section, which indicates to the
+ linker that if no symbols from this section are referenced, the
+ section should not be included in the link. If SECTION_NAME is
+ omitted, the current section is used.
+
+`.c_mode'
+ TBD.
+
+`.copy "FILENAME" | FILENAME'
+`.include "FILENAME" | FILENAME'
+ Read source statements from FILENAME. The normal include search
+ path is used. Normally .copy will cause statements from the
+ included file to be printed in the assembly listing and .include
+ will not, but this distinction is not currently implemented.
+
+`.data'
+ Begin assembling code into the .data section.
+
+`.double VALUE [,...,VALUE_N]'
+`.ldouble VALUE [,...,VALUE_N]'
+`.float VALUE [,...,VALUE_N]'
+`.xfloat VALUE [,...,VALUE_N]'
+ Place an IEEE single-precision floating-point representation of
+ one or more floating-point values into the current section. All
+ but `.xfloat' align the result on a longword boundary. Values are
+ stored most-significant word first.
+
+`.drlist'
+`.drnolist'
+ Control printing of directives to the listing file. Ignored.
+
+`.emsg STRING'
+`.mmsg STRING'
+`.wmsg STRING'
+ Emit a user-defined error, message, or warning, respectively.
+
+`.far_mode'
+ Use extended addressing when assembling statements. This should
+ appear only once per file, and is equivalent to the -mfar-mode
+ option *note `-mfar-mode': TIC54X-Opts.
+
+`.fclist'
+`.fcnolist'
+ Control printing of false conditional blocks to the listing file.
+
+`.field VALUE [,SIZE]'
+ Initialize a bitfield of SIZE bits in the current section. If
+ VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16
+ bits. If VALUE does not fit into SIZE bits, the value will be
+ truncated. Successive `.field' directives will pack starting at
+ the current word, filling the most significant bits first, and
+ aligning to the start of the next word if the field size does not
+ fit into the space remaining in the current word. A `.align'
+ directive with an operand of 1 will force the next `.field'
+ directive to begin packing into a new word. If a label is used, it
+ points to the word that contains the specified field.
+
+`.global SYMBOL [,...,SYMBOL_N]'
+`.def SYMBOL [,...,SYMBOL_N]'
+`.ref SYMBOL [,...,SYMBOL_N]'
+ `.def' nominally identifies a symbol defined in the current file
+ and available to other files. `.ref' identifies a symbol used in
+ the current file but defined elsewhere. Both map to the standard
+ `.global' directive.
+
+`.half VALUE [,...,VALUE_N]'
+`.uhalf VALUE [,...,VALUE_N]'
+`.short VALUE [,...,VALUE_N]'
+`.ushort VALUE [,...,VALUE_N]'
+`.int VALUE [,...,VALUE_N]'
+`.uint VALUE [,...,VALUE_N]'
+`.word VALUE [,...,VALUE_N]'
+`.uword VALUE [,...,VALUE_N]'
+ Place one or more values into consecutive words of the current
+ section. If a label is used, it points to the word allocated for
+ the first value encountered.
+
+`.label SYMBOL'
+ Define a special SYMBOL to refer to the load time address of the
+ current section program counter.
+
+`.length'
+`.width'
+ Set the page length and width of the output listing file. Ignored.
+
+`.list'
+`.nolist'
+ Control whether the source listing is printed. Ignored.
+
+`.long VALUE [,...,VALUE_N]'
+`.ulong VALUE [,...,VALUE_N]'
+`.xlong VALUE [,...,VALUE_N]'
+ Place one or more 32-bit values into consecutive words in the
+ current section. The most significant word is stored first.
+ `.long' and `.ulong' align the result on a longword boundary;
+ `xlong' does not.
+
+`.loop [COUNT]'
+`.break [CONDITION]'
+`.endloop'
+ Repeatedly assemble a block of code. `.loop' begins the block, and
+ `.endloop' marks its termination. COUNT defaults to 1024, and
+ indicates the number of times the block should be repeated.
+ `.break' terminates the loop so that assembly begins after the
+ `.endloop' directive. The optional CONDITION will cause the loop
+ to terminate only if it evaluates to zero.
+
+`MACRO_NAME .macro [PARAM1][,...PARAM_N]'
+`[.mexit]'
+`.endm'
+ See the section on macros for more explanation (*Note
+ TIC54X-Macros::.
+
+`.mlib "FILENAME" | FILENAME'
+ Load the macro library FILENAME. FILENAME must be an archived
+ library (BFD ar-compatible) of text files, expected to contain
+ only macro definitions. The standard include search path is used.
+
+`.mlist'
+`.mnolist'
+ Control whether to include macro and loop block expansions in the
+ listing output. Ignored.
+
+`.mmregs'
+ Define global symbolic names for the 'c54x registers. Supposedly
+ equivalent to executing `.set' directives for each register with
+ its memory-mapped value, but in reality is provided only for
+ compatibility and does nothing.
+
+`.newblock'
+ This directive resets any TIC54X local labels currently defined.
+ Normal `as' local labels are unaffected.
+
+`.option OPTION_LIST'
+ Set listing options. Ignored.
+
+`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
+ Designate SECTION_NAME for blocking. Blocking guarantees that a
+ section will start on a page boundary (128 words) if it would
+ otherwise cross a page boundary. Only initialized sections may be
+ designated with this directive. See also *Note TIC54X-Block::.
+
+`.sect "SECTION_NAME"'
+ Define a named initialized section and make it the current section.
+
+`SYMBOL .set "VALUE"'
+`SYMBOL .equ "VALUE"'
+ Equate a constant VALUE to a SYMBOL, which is placed in the symbol
+ table. SYMBOL may not be previously defined.
+
+`.space SIZE_IN_BITS'
+`.bes SIZE_IN_BITS'
+ Reserve the given number of bits in the current section and
+ zero-fill them. If a label is used with `.space', it points to the
+ *first* word reserved. With `.bes', the label points to the
+ *last* word reserved.
+
+`.sslist'
+`.ssnolist'
+ Controls the inclusion of subsym replacement in the listing
+ output. Ignored.
+
+`.string "STRING" [,...,"STRING_N"]'
+`.pstring "STRING" [,...,"STRING_N"]'
+ Place 8-bit characters from STRING into the current section.
+ `.string' zero-fills the upper 8 bits of each word, while
+ `.pstring' puts two characters into each word, filling the
+ most-significant bits first. Unused space is zero-filled. If a
+ label is used, it points to the first word initialized.
+
+`[STAG] .struct [OFFSET]'
+`[NAME_1] element [COUNT_1]'
+`[NAME_2] element [COUNT_2]'
+`[TNAME] .tag STAGX [TCOUNT]'
+`...'
+`[NAME_N] element [COUNT_N]'
+`[SSIZE] .endstruct'
+`LABEL .tag [STAG]'
+ Assign symbolic offsets to the elements of a structure. STAG
+ defines a symbol to use to reference the structure. OFFSET
+ indicates a starting value to use for the first element
+ encountered; otherwise it defaults to zero. Each element can have
+ a named offset, NAME, which is a symbol assigned the value of the
+ element's offset into the structure. If STAG is missing, these
+ become global symbols. COUNT adjusts the offset that many times,
+ as if `element' were an array. `element' may be one of `.byte',
+ `.word', `.long', `.float', or any equivalent of those, and the
+ structure offset is adjusted accordingly. `.field' and `.string'
+ are also allowed; the size of `.field' is one bit, and `.string'
+ is considered to be one word in size. Only element descriptors,
+ structure/union tags, `.align' and conditional assembly directives
+ are allowed within `.struct'/`.endstruct'. `.align' aligns member
+ offsets to word boundaries only. SSIZE, if provided, will always
+ be assigned the size of the structure.
+
+ The `.tag' directive, in addition to being used to define a
+ structure/union element within a structure, may be used to apply a
+ structure to a symbol. Once applied to LABEL, the individual
+ structure elements may be applied to LABEL to produce the desired
+ offsets using LABEL as the structure base.
+
+`.tab'
+ Set the tab size in the output listing. Ignored.
+
+`[UTAG] .union'
+`[NAME_1] element [COUNT_1]'
+`[NAME_2] element [COUNT_2]'
+`[TNAME] .tag UTAGX[,TCOUNT]'
+`...'
+`[NAME_N] element [COUNT_N]'
+`[USIZE] .endstruct'
+`LABEL .tag [UTAG]'
+ Similar to `.struct', but the offset after each element is reset to
+ zero, and the USIZE is set to the maximum of all defined elements.
+ Starting offset for the union is always zero.
+
+`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
+ Reserve space for variables in a named, uninitialized section
+ (similar to .bss). `.usect' allows definitions sections
+ independent of .bss. SYMBOL points to the first location reserved
+ by this allocation. The symbol may be used as a variable name.
+ SIZE is the allocated size in words. BLOCKING_FLAG indicates
+ whether to block this section on a page boundary (128 words)
+ (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the
+ section should be longword-aligned.
+
+`.var SYM[,..., SYM_N]'
+ Define a subsym to be a local variable within a macro. See *Note
+ TIC54X-Macros::.
+
+`.version VERSION'
+ Set which processor to build instructions for. Though the
+ following values are accepted, the op is ignored.
+ `541'
+ `542'
+ `543'
+ `545'
+ `545LP'
+ `546LP'
+ `548'
+ `549'
+
+
+File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent
+
+9.44.10 Macros
+--------------
+
+Macros do not require explicit dereferencing of arguments (i.e., \ARG).
+
+ During macro expansion, the macro parameters are converted to
+subsyms. If the number of arguments passed the macro invocation
+exceeds the number of parameters defined, the last parameter is
+assigned the string equivalent of all remaining arguments. If fewer
+arguments are given than parameters, the missing parameters are
+assigned empty strings. To include a comma in an argument, you must
+enclose the argument in quotes.
+
+ The following built-in subsym functions allow examination of the
+string value of subsyms (or ordinary strings). The arguments are
+strings unless otherwise indicated (subsyms passed as args will be
+replaced by the strings they represent).
+``$symlen(STR)''
+ Returns the length of STR.
+
+``$symcmp(STR1,STR2)''
+ Returns 0 if STR1 == STR2, non-zero otherwise.
+
+``$firstch(STR,CH)''
+ Returns index of the first occurrence of character constant CH in
+ STR.
+
+``$lastch(STR,CH)''
+ Returns index of the last occurrence of character constant CH in
+ STR.
+
+``$isdefed(SYMBOL)''
+ Returns zero if the symbol SYMBOL is not in the symbol table,
+ non-zero otherwise.
+
+``$ismember(SYMBOL,LIST)''
+ Assign the first member of comma-separated string LIST to SYMBOL;
+ LIST is reassigned the remainder of the list. Returns zero if
+ LIST is a null string. Both arguments must be subsyms.
+
+``$iscons(EXPR)''
+ Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal,
+ 4 if a character, 5 if decimal, and zero if not an integer.
+
+``$isname(NAME)''
+ Returns 1 if NAME is a valid symbol name, zero otherwise.
+
+``$isreg(REG)''
+ Returns 1 if REG is a valid predefined register name (AR0-AR7
+ only).
+
+``$structsz(STAG)''
+ Returns the size of the structure or union represented by STAG.
+
+``$structacc(STAG)''
+ Returns the reference point of the structure or union represented
+ by STAG. Always returns zero.
+
+
+
+File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent
+
+9.44.11 Memory-mapped Registers
+-------------------------------
+
+The following symbols are recognized as memory-mapped registers:
+
+
+
+File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent
+
+9.44.12 TIC54X Syntax
+---------------------
+
+* Menu:
+
+* TIC54X-Chars:: Special Characters
+
+
+File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax
+
+9.44.12.1 Special Characters
+............................
+
+The presence of a `;' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The presence of an asterisk (`*') at the start of a line also
+indicates a comment that extends to the end of that line.
+
+ The TIC54X assembler does not currently support a line separator
+character.
+
+
+File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies
+
+9.45 TIC6X Dependent Features
+=============================
+
+* Menu:
+
+* TIC6X Options:: Options
+* TIC6X Syntax:: Syntax
+* TIC6X Directives:: Directives
+
+
+File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent
+
+9.45.1 TIC6X Options
+--------------------
+
+`-march=ARCH'
+ Enable (only) instructions from architecture ARCH. By default,
+ all instructions are permitted.
+
+ The following values of ARCH are accepted: `c62x', `c64x',
+ `c64x+', `c67x', `c67x+', `c674x'.
+
+`-mdsbt'
+`-mno-dsbt'
+ The `-mdsbt' option causes the assembler to generate the
+ `Tag_ABI_DSBT' attribute with a value of 1, indicating that the
+ code is using DSBT addressing. The `-mno-dsbt' option, the
+ default, causes the tag to have a value of 0, indicating that the
+ code does not use DSBT addressing. The linker will emit a warning
+ if objects of different type (DSBT and non-DSBT) are linked
+ together.
+
+`-mpid=no'
+`-mpid=near'
+`-mpid=far'
+ The `-mpid=' option causes the assembler to generate the
+ `Tag_ABI_PID' attribute with a value indicating the form of data
+ addressing used by the code. `-mpid=no', the default, indicates
+ position-dependent data addressing, `-mpid=near' indicates
+ position-independent addressing with GOT accesses using near DP
+ addressing, and `-mpid=far' indicates position-independent
+ addressing with GOT accesses using far DP addressing. The linker
+ will emit a warning if objects built with different settings of
+ this option are linked together.
+
+`-mpic'
+`-mno-pic'
+ The `-mpic' option causes the assembler to generate the
+ `Tag_ABI_PIC' attribute with a value of 1, indicating that the
+ code is using position-independent code addressing, The
+ `-mno-pic' option, the default, causes the tag to have a value of
+ 0, indicating position-dependent code addressing. The linker will
+ emit a warning if objects of different type (position-dependent and
+ position-independent) are linked together.
+
+`-mbig-endian'
+`-mlittle-endian'
+ Generate code for the specified endianness. The default is
+ little-endian.
+
+
+
+File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent
+
+9.45.2 TIC6X Syntax
+-------------------
+
+The presence of a `;' on a line indicates the start of a comment that
+extends to the end of the current line. If a `#' or `*' appears as the
+first character of a line, the whole line is treated as a comment.
+Note that if a line starts with a `#' character then it can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `@' character can be used instead of a newline to separate
+statements.
+
+ Instruction, register and functional unit names are case-insensitive.
+`as' requires fully-specified functional unit names, such as `.S1',
+`.L1X' or `.D1T2', on all instructions using a functional unit.
+
+ For some instructions, there may be syntactic ambiguity between
+register or functional unit names and the names of labels or other
+symbols. To avoid this, enclose the ambiguous symbol name in
+parentheses; register and functional unit names may not be enclosed in
+parentheses.
+
+
+File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent
+
+9.45.3 TIC6X Directives
+-----------------------
+
+Directives controlling the set of instructions accepted by the
+assembler have effect for instructions between the directive and any
+subsequent directive overriding it.
+
+`.arch ARCH'
+ This has the same effect as `-march=ARCH'.
+
+`.cantunwind'
+ Prevents unwinding through the current function. No personality
+ routine or exception table data is required or permitted.
+
+ If this is not specified then frame unwinding information will be
+ constructed from CFI directives. *note CFI directives::.
+
+`.c6xabi_attribute TAG, VALUE'
+ Set the C6000 EABI build attribute TAG to VALUE.
+
+ The TAG is either an attribute number or one of `Tag_ISA',
+ `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed',
+ `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID',
+ `Tag_ABI_PIC', `TAG_ABI_array_object_alignment',
+ `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and
+ `Tag_ABI_conformance'. The VALUE is either a `number',
+ `"string"', or `number, "string"' depending on the tag.
+
+`.ehtype SYMBOL'
+ Output an exception type table reference to SYMBOL.
+
+`.endp'
+ Marks the end of and exception table or function. If preceeded by
+ a `.handlerdata' directive then this also switched back to the
+ previous text section.
+
+`.handlerdata'
+ Marks the end of the current function, and the start of the
+ exception table entry for that function. Anything between this
+ directive and the `.endp' directive will be added to the exception
+ table entry.
+
+ Must be preceded by a CFI block containing a `.cfi_lsda' directive.
+
+`.nocmp'
+ Disallow use of C64x+ compact instructions in the current text
+ section.
+
+`.personalityindex INDEX'
+ Sets the personality routine for the current function to the ABI
+ specified compact routine number INDEX
+
+`.personality NAME'
+ Sets the personality routine for the current function to NAME.
+
+`.scomm SYMBOL, SIZE, ALIGN'
+ Like `.comm', creating a common symbol SYMBOL with size SIZE and
+ alignment ALIGN, but unlike when using `.comm', this symbol will
+ be placed into the small BSS section by the linker.
+
+
+
+File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies
+
+9.46 TILE-Gx Dependent Features
+===============================
+
+* Menu:
+
+* TILE-Gx Options:: TILE-Gx Options
+* TILE-Gx Syntax:: TILE-Gx Syntax
+* TILE-Gx Directives:: TILE-Gx Directives
+
+
+File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent
+
+9.46.1 Options
+--------------
+
+The following table lists all available TILE-Gx specific options:
+
+`-m32 | -m64'
+ Select the word size, either 32 bits or 64 bits.
+
+`-EB | -EL'
+ Select the endianness, either big-endian (-EB) or little-endian
+ (-EL).
+
+
+
+File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent
+
+9.46.2 Syntax
+-------------
+
+Block comments are delimited by `/*' and `*/'. End of line comments
+may be introduced by `#'.
+
+ Instructions consist of a leading opcode or macro name followed by
+whitespace and an optional comma-separated list of operands:
+
+ OPCODE [OPERAND, ...]
+
+ Instructions must be separated by a newline or semicolon.
+
+ There are two ways to write code: either write naked instructions,
+which the assembler is free to combine into VLIW bundles, or specify
+the VLIW bundles explicitly.
+
+ Bundles are specified using curly braces:
+
+ { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
+
+ A bundle can span multiple lines. If you want to put multiple
+instructions on a line, whether in a bundle or not, you need to
+separate them with semicolons as in this example.
+
+ A bundle may contain one or more instructions, up to the limit
+specified by the ISA (currently three). If fewer instructions are
+specified than the hardware supports in a bundle, the assembler inserts
+`fnop' instructions automatically.
+
+ The assembler will prefer to preserve the ordering of instructions
+within the bundle, putting the first instruction in a lower-numbered
+pipeline than the next one, etc. This fact, combined with the optional
+use of explicit `fnop' or `nop' instructions, allows precise control
+over which pipeline executes each instruction.
+
+ If the instructions cannot be bundled in the listed order, the
+assembler will automatically try to find a valid pipeline assignment.
+If there is no way to bundle the instructions together, the assembler
+reports an error.
+
+ The assembler does not yet auto-bundle (automatically combine
+multiple instructions into one bundle), but it reserves the right to do
+so in the future. If you want to force an instruction to run by
+itself, put it in a bundle explicitly with curly braces and use `nop'
+instructions (not `fnop') to fill the remaining pipeline slots in that
+bundle.
+
+* Menu:
+
+* TILE-Gx Opcodes:: Opcode Naming Conventions.
+* TILE-Gx Registers:: Register Naming.
+* TILE-Gx Modifiers:: Symbolic Operand Modifiers.
+
+
+File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax
+
+9.46.2.1 Opcode Names
+.....................
+
+For a complete list of opcodes and descriptions of their semantics, see
+`TILE-Gx Instruction Set Architecture', available upon request at
+www.tilera.com.
+
+
+File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax
+
+9.46.2.2 Register Names
+.......................
+
+General-purpose registers are represented by predefined symbols of the
+form `rN', where N represents a number between `0' and `63'. However,
+the following registers have canonical names that must be used instead:
+
+`r54'
+ sp
+
+`r55'
+ lr
+
+`r56'
+ sn
+
+`r57'
+ idn0
+
+`r58'
+ idn1
+
+`r59'
+ udn0
+
+`r60'
+ udn1
+
+`r61'
+ udn2
+
+`r62'
+ udn3
+
+`r63'
+ zero
+
+
+ The assembler will emit a warning if a numeric name is used instead
+of the non-numeric name. The `.no_require_canonical_reg_names'
+assembler pseudo-op turns off this warning.
+`.require_canonical_reg_names' turns it back on.
+
+
+File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax
+
+9.46.2.3 Symbolic Operand Modifiers
+...................................
+
+The assembler supports several modifiers when using symbol addresses in
+TILE-Gx instruction operands. The general syntax is the following:
+
+ modifier(symbol)
+
+ The following modifiers are supported:
+
+`hw0'
+ This modifier is used to load bits 0-15 of the symbol's address.
+
+`hw1'
+ This modifier is used to load bits 16-31 of the symbol's address.
+
+`hw2'
+ This modifier is used to load bits 32-47 of the symbol's address.
+
+`hw3'
+ This modifier is used to load bits 48-63 of the symbol's address.
+
+`hw0_last'
+ This modifier yields the same value as `hw0', but it also checks
+ that the value does not overflow.
+
+`hw1_last'
+ This modifier yields the same value as `hw1', but it also checks
+ that the value does not overflow.
+
+`hw2_last'
+ This modifier yields the same value as `hw2', but it also checks
+ that the value does not overflow.
+
+ A 48-bit symbolic value is constructed by using the following
+ idiom:
+
+ moveli r0, hw2_last(sym)
+ shl16insli r0, r0, hw1(sym)
+ shl16insli r0, r0, hw0(sym)
+
+`hw0_got'
+ This modifier is used to load bits 0-15 of the symbol's offset in
+ the GOT entry corresponding to the symbol.
+
+`hw0_last_got'
+ This modifier yields the same value as `hw0_got', but it also
+ checks that the value does not overflow.
+
+`hw1_last_got'
+ This modifier is used to load bits 16-31 of the symbol's offset in
+ the GOT entry corresponding to the symbol, and it also checks that
+ the value does not overflow.
+
+`plt'
+ This modifier is used for function symbols. It causes a
+ _procedure linkage table_, an array of code stubs, to be created
+ at the time the shared object is created or linked against,
+ together with a global offset table entry. The value is a
+ pc-relative offset to the corresponding stub code in the procedure
+ linkage table. This arrangement causes the run-time symbol
+ resolver to be called to look up and set the value of the symbol
+ the first time the function is called (at latest; depending
+ environment variables). It is only safe to leave the symbol
+ unresolved this way if all references are function calls.
+
+`hw0_plt'
+ This modifier is used to load bits 0-15 of the pc-relative address
+ of a plt entry.
+
+`hw1_plt'
+ This modifier is used to load bits 16-31 of the pc-relative
+ address of a plt entry.
+
+`hw1_last_plt'
+ This modifier yields the same value as `hw1_plt', but it also
+ checks that the value does not overflow.
+
+`hw2_last_plt'
+ This modifier is used to load bits 32-47 of the pc-relative
+ address of a plt entry, and it also checks that the value does not
+ overflow.
+
+`hw0_tls_gd'
+ This modifier is used to load bits 0-15 of the offset of the GOT
+ entry of the symbol's TLS descriptor, to be used for
+ general-dynamic TLS accesses.
+
+`hw0_last_tls_gd'
+ This modifier yields the same value as `hw0_tls_gd', but it also
+ checks that the value does not overflow.
+
+`hw1_last_tls_gd'
+ This modifier is used to load bits 16-31 of the offset of the GOT
+ entry of the symbol's TLS descriptor, to be used for
+ general-dynamic TLS accesses. It also checks that the value does
+ not overflow.
+
+`hw0_tls_ie'
+ This modifier is used to load bits 0-15 of the offset of the GOT
+ entry containing the offset of the symbol's address from the TCB,
+ to be used for initial-exec TLS accesses.
+
+`hw0_last_tls_ie'
+ This modifier yields the same value as `hw0_tls_ie', but it also
+ checks that the value does not overflow.
+
+`hw1_last_tls_ie'
+ This modifier is used to load bits 16-31 of the offset of the GOT
+ entry containing the offset of the symbol's address from the TCB,
+ to be used for initial-exec TLS accesses. It also checks that the
+ value does not overflow.
+
+`hw0_tls_le'
+ This modifier is used to load bits 0-15 of the offset of the
+ symbol's address from the TCB, to be used for local-exec TLS
+ accesses.
+
+`hw0_last_tls_le'
+ This modifier yields the same value as `hw0_tls_le', but it also
+ checks that the value does not overflow.
+
+`hw1_last_tls_le'
+ This modifier is used to load bits 16-31 of the offset of the
+ symbol's address from the TCB, to be used for local-exec TLS
+ accesses. It also checks that the value does not overflow.
+
+`tls_gd_call'
+ This modifier is used to tag an instrution as the "call" part of a
+ calling sequence for a TLS GD reference of its operand.
+
+`tls_gd_add'
+ This modifier is used to tag an instruction as the "add" part of a
+ calling sequence for a TLS GD reference of its operand.
+
+`tls_ie_load'
+ This modifier is used to tag an instruction as the "load" part of a
+ calling sequence for a TLS IE reference of its operand.
+
+
+
+File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent
+
+9.46.3 TILE-Gx Directives
+-------------------------
+
+`.align EXPRESSION [, EXPRESSION]'
+ This is the generic .ALIGN directive. The first argument is the
+ requested alignment in bytes.
+
+`.allow_suspicious_bundles'
+ Turns on error checking for combinations of instructions in a
+ bundle that probably indicate a programming error. This is on by
+ default.
+
+`.no_allow_suspicious_bundles'
+ Turns off error checking for combinations of instructions in a
+ bundle that probably indicate a programming error.
+
+`.require_canonical_reg_names'
+ Require that canonical register names be used, and emit a warning
+ if the numeric names are used. This is on by default.
+
+`.no_require_canonical_reg_names'
+ Permit the use of numeric names for registers that have canonical
+ names.
+
+
+
+File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies
+
+9.47 TILEPro Dependent Features
+===============================
+
+* Menu:
+
+* TILEPro Options:: TILEPro Options
+* TILEPro Syntax:: TILEPro Syntax
+* TILEPro Directives:: TILEPro Directives
+
+
+File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent
+
+9.47.1 Options
+--------------
+
+`as' has no machine-dependent command-line options for TILEPro.
+
+
+File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent
+
+9.47.2 Syntax
+-------------
+
+Block comments are delimited by `/*' and `*/'. End of line comments
+may be introduced by `#'.
+
+ Instructions consist of a leading opcode or macro name followed by
+whitespace and an optional comma-separated list of operands:
+
+ OPCODE [OPERAND, ...]
+
+ Instructions must be separated by a newline or semicolon.
+
+ There are two ways to write code: either write naked instructions,
+which the assembler is free to combine into VLIW bundles, or specify
+the VLIW bundles explicitly.
+
+ Bundles are specified using curly braces:
+
+ { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
+
+ A bundle can span multiple lines. If you want to put multiple
+instructions on a line, whether in a bundle or not, you need to
+separate them with semicolons as in this example.
+
+ A bundle may contain one or more instructions, up to the limit
+specified by the ISA (currently three). If fewer instructions are
+specified than the hardware supports in a bundle, the assembler inserts
+`fnop' instructions automatically.
+
+ The assembler will prefer to preserve the ordering of instructions
+within the bundle, putting the first instruction in a lower-numbered
+pipeline than the next one, etc. This fact, combined with the optional
+use of explicit `fnop' or `nop' instructions, allows precise control
+over which pipeline executes each instruction.
+
+ If the instructions cannot be bundled in the listed order, the
+assembler will automatically try to find a valid pipeline assignment.
+If there is no way to bundle the instructions together, the assembler
+reports an error.
+
+ The assembler does not yet auto-bundle (automatically combine
+multiple instructions into one bundle), but it reserves the right to do
+so in the future. If you want to force an instruction to run by
+itself, put it in a bundle explicitly with curly braces and use `nop'
+instructions (not `fnop') to fill the remaining pipeline slots in that
+bundle.
+
+* Menu:
+
+* TILEPro Opcodes:: Opcode Naming Conventions.
+* TILEPro Registers:: Register Naming.
+* TILEPro Modifiers:: Symbolic Operand Modifiers.
+
+
+File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax
+
+9.47.2.1 Opcode Names
+.....................
+
+For a complete list of opcodes and descriptions of their semantics, see
+`TILE Processor User Architecture Manual', available upon request at
+www.tilera.com.
+
+
+File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax
+
+9.47.2.2 Register Names
+.......................
+
+General-purpose registers are represented by predefined symbols of the
+form `rN', where N represents a number between `0' and `63'. However,
+the following registers have canonical names that must be used instead:
+
+`r54'
+ sp
+
+`r55'
+ lr
+
+`r56'
+ sn
+
+`r57'
+ idn0
+
+`r58'
+ idn1
+
+`r59'
+ udn0
+
+`r60'
+ udn1
+
+`r61'
+ udn2
+
+`r62'
+ udn3
+
+`r63'
+ zero
+
+
+ The assembler will emit a warning if a numeric name is used instead
+of the canonical name. The `.no_require_canonical_reg_names' assembler
+pseudo-op turns off this warning. `.require_canonical_reg_names' turns
+it back on.
+
+
+File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax
+
+9.47.2.3 Symbolic Operand Modifiers
+...................................
+
+The assembler supports several modifiers when using symbol addresses in
+TILEPro instruction operands. The general syntax is the following:
+
+ modifier(symbol)
+
+ The following modifiers are supported:
+
+`lo16'
+ This modifier is used to load the low 16 bits of the symbol's
+ address, sign-extended to a 32-bit value (sign-extension allows it
+ to be range-checked against signed 16 bit immediate operands
+ without complaint).
+
+`hi16'
+ This modifier is used to load the high 16 bits of the symbol's
+ address, also sign-extended to a 32-bit value.
+
+`ha16'
+ `ha16(N)' is identical to `hi16(N)', except if `lo16(N)' is
+ negative it adds one to the `hi16(N)' value. This way `lo16' and
+ `ha16' can be added to create any 32-bit value using `auli'. For
+ example, here is how you move an arbitrary 32-bit address into r3:
+
+ moveli r3, lo16(sym)
+ auli r3, r3, ha16(sym)
+
+`got'
+ This modifier is used to load the offset of the GOT entry
+ corresponding to the symbol.
+
+`got_lo16'
+ This modifier is used to load the sign-extended low 16 bits of the
+ offset of the GOT entry corresponding to the symbol.
+
+`got_hi16'
+ This modifier is used to load the sign-extended high 16 bits of the
+ offset of the GOT entry corresponding to the symbol.
+
+`got_ha16'
+ This modifier is like `got_hi16', but it adds one if `got_lo16' of
+ the input value is negative.
+
+`plt'
+ This modifier is used for function symbols. It causes a
+ _procedure linkage table_, an array of code stubs, to be created
+ at the time the shared object is created or linked against,
+ together with a global offset table entry. The value is a
+ pc-relative offset to the corresponding stub code in the procedure
+ linkage table. This arrangement causes the run-time symbol
+ resolver to be called to look up and set the value of the symbol
+ the first time the function is called (at latest; depending
+ environment variables). It is only safe to leave the symbol
+ unresolved this way if all references are function calls.
+
+`tls_gd'
+ This modifier is used to load the offset of the GOT entry of the
+ symbol's TLS descriptor, to be used for general-dynamic TLS
+ accesses.
+
+`tls_gd_lo16'
+ This modifier is used to load the sign-extended low 16 bits of the
+ offset of the GOT entry of the symbol's TLS descriptor, to be used
+ for general dynamic TLS accesses.
+
+`tls_gd_hi16'
+ This modifier is used to load the sign-extended high 16 bits of the
+ offset of the GOT entry of the symbol's TLS descriptor, to be used
+ for general dynamic TLS accesses.
+
+`tls_gd_ha16'
+ This modifier is like `tls_gd_hi16', but it adds one to the value
+ if `tls_gd_lo16' of the input value is negative.
+
+`tls_ie'
+ This modifier is used to load the offset of the GOT entry
+ containing the offset of the symbol's address from the TCB, to be
+ used for initial-exec TLS accesses.
+
+`tls_ie_lo16'
+ This modifier is used to load the low 16 bits of the offset of the
+ GOT entry containing the offset of the symbol's address from the
+ TCB, to be used for initial-exec TLS accesses.
+
+`tls_ie_hi16'
+ This modifier is used to load the high 16 bits of the offset of the
+ GOT entry containing the offset of the symbol's address from the
+ TCB, to be used for initial-exec TLS accesses.
+
+`tls_ie_ha16'
+ This modifier is like `tls_ie_hi16', but it adds one to the value
+ if `tls_ie_lo16' of the input value is negative.
+
+`tls_le'
+ This modifier is used to load the offset of the symbol's address
+ from the TCB, to be used for local-exec TLS accesses.
+
+`tls_le_lo16'
+ This modifier is used to load the low 16 bits of the offset of the
+ symbol's address from the TCB, to be used for local-exec TLS
+ accesses.
+
+`tls_le_hi16'
+ This modifier is used to load the high 16 bits of the offset of the
+ symbol's address from the TCB, to be used for local-exec TLS
+ accesses.
+
+`tls_le_ha16'
+ This modifier is like `tls_le_hi16', but it adds one to the value
+ if `tls_le_lo16' of the input value is negative.
+
+`tls_gd_call'
+ This modifier is used to tag an instrution as the "call" part of a
+ calling sequence for a TLS GD reference of its operand.
+
+`tls_gd_add'
+ This modifier is used to tag an instruction as the "add" part of a
+ calling sequence for a TLS GD reference of its operand.
+
+`tls_ie_load'
+ This modifier is used to tag an instruction as the "load" part of a
+ calling sequence for a TLS IE reference of its operand.
+
+
+
+File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent
+
+9.47.3 TILEPro Directives
+-------------------------
+
+`.align EXPRESSION [, EXPRESSION]'
+ This is the generic .ALIGN directive. The first argument is the
+ requested alignment in bytes.
+
+`.allow_suspicious_bundles'
+ Turns on error checking for combinations of instructions in a
+ bundle that probably indicate a programming error. This is on by
+ default.
+
+`.no_allow_suspicious_bundles'
+ Turns off error checking for combinations of instructions in a
+ bundle that probably indicate a programming error.
+
+`.require_canonical_reg_names'
+ Require that canonical register names be used, and emit a warning
+ if the numeric names are used. This is on by default.
+
+`.no_require_canonical_reg_names'
+ Permit the use of numeric names for registers that have canonical
+ names.
+
+
+
+File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies
+
+9.48 v850 Dependent Features
+============================
+
+* Menu:
+
+* V850 Options:: Options
+* V850 Syntax:: Syntax
+* V850 Floating Point:: Floating Point
+* V850 Directives:: V850 Machine Directives
+* V850 Opcodes:: Opcodes
+
+
+File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
+
+9.48.1 Options
+--------------
+
+`as' supports the following additional command-line options for the
+V850 processor family:
+
+`-wsigned_overflow'
+ Causes warnings to be produced when signed immediate values
+ overflow the space available for then within their opcodes. By
+ default this option is disabled as it is possible to receive
+ spurious warnings due to using exact bit patterns as immediate
+ constants.
+
+`-wunsigned_overflow'
+ Causes warnings to be produced when unsigned immediate values
+ overflow the space available for then within their opcodes. By
+ default this option is disabled as it is possible to receive
+ spurious warnings due to using exact bit patterns as immediate
+ constants.
+
+`-mv850'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850 processor. This allows the linker to detect
+ attempts to link such code with code assembled for other
+ processors.
+
+`-mv850e'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E processor. This allows the linker to detect
+ attempts to link such code with code assembled for other
+ processors.
+
+`-mv850e1'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E1 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`-mv850any'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850 processor but support instructions that are
+ specific to the extended variants of the process. This allows the
+ production of binaries that contain target specific code, but
+ which are also intended to be used in a generic fashion. For
+ example libgcc.a contains generic routines used by the code
+ produced by GCC for all versions of the v850 architecture,
+ together with support routines only used by the V850E architecture.
+
+`-mv850e2'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E2 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`-mv850e2v3'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E2V3 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`-mv850e2v4'
+ This is an alias for `-mv850e3v5'.
+
+`-mv850e3v5'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E3V5 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`-mrelax'
+ Enables relaxation. This allows the .longcall and .longjump pseudo
+ ops to be used in the assembler source code. These ops label
+ sections of code which are either a long function call or a long
+ branch. The assembler will then flag these sections of code and
+ the linker will attempt to relax them.
+
+`-mgcc-abi'
+ Marks the generated object file as supporting the old GCC ABI.
+
+`-mrh850-abi'
+ Marks the generated object file as supporting the RH850 ABI. This
+ is the default.
+
+`-m8byte-align'
+ Marks the generated object file as supporting a maximum 64-bits of
+ alignment for variables defined in the source code.
+
+`-m4byte-align'
+ Marks the generated object file as supporting a maximum 32-bits of
+ alignment for variables defined in the source code. This is the
+ default.
+
+`-msoft-float'
+ Marks the generated object file as not using any floating point
+ instructions - and hence can be linked with other V850 binaries
+ that do or do not use floating point. This is the default for
+ binaries for architectures earlier than the `e2v3'.
+
+`-mhard-float'
+ Marks the generated object file as one that uses floating point
+ instructions - and hence can only be linked with other V850
+ binaries that use the same kind of floating point instructions, or
+ with binaries that do not use floating point at all. This is the
+ default for binaries the `e2v3' and later architectures.
+
+
+
+File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
+
+9.48.2 Syntax
+-------------
+
+* Menu:
+
+* V850-Chars:: Special Characters
+* V850-Regs:: Register Names
+
+
+File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
+
+9.48.2.1 Special Characters
+...........................
+
+`#' is the line comment character. If a `#' appears as the first
+character of a line, the whole line is treated as a comment, but in
+this case the line can also be a logical line number directive (*note
+Comments::) or a preprocessor control command (*note Preprocessing::).
+
+ Two dashes (`--') can also be used to start a line comment.
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
+
+9.48.2.2 Register Names
+.......................
+
+`as' supports the following names for registers:
+`general register 0'
+ r0, zero
+
+`general register 1'
+ r1
+
+`general register 2'
+ r2, hp
+
+`general register 3'
+ r3, sp
+
+`general register 4'
+ r4, gp
+
+`general register 5'
+ r5, tp
+
+`general register 6'
+ r6
+
+`general register 7'
+ r7
+
+`general register 8'
+ r8
+
+`general register 9'
+ r9
+
+`general register 10'
+ r10
+
+`general register 11'
+ r11
+
+`general register 12'
+ r12
+
+`general register 13'
+ r13
+
+`general register 14'
+ r14
+
+`general register 15'
+ r15
+
+`general register 16'
+ r16
+
+`general register 17'
+ r17
+
+`general register 18'
+ r18
+
+`general register 19'
+ r19
+
+`general register 20'
+ r20
+
+`general register 21'
+ r21
+
+`general register 22'
+ r22
+
+`general register 23'
+ r23
+
+`general register 24'
+ r24
+
+`general register 25'
+ r25
+
+`general register 26'
+ r26
+
+`general register 27'
+ r27
+
+`general register 28'
+ r28
+
+`general register 29'
+ r29
+
+`general register 30'
+ r30, ep
+
+`general register 31'
+ r31, lp
+
+`system register 0'
+ eipc
+
+`system register 1'
+ eipsw
+
+`system register 2'
+ fepc
+
+`system register 3'
+ fepsw
+
+`system register 4'
+ ecr
+
+`system register 5'
+ psw
+
+`system register 16'
+ ctpc
+
+`system register 17'
+ ctpsw
+
+`system register 18'
+ dbpc
+
+`system register 19'
+ dbpsw
+
+`system register 20'
+ ctbp
+
+
+File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
+
+9.48.3 Floating Point
+---------------------
+
+The V850 family uses IEEE floating-point numbers.
+
+
+File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
+
+9.48.4 V850 Machine Directives
+------------------------------
+
+`.offset <EXPRESSION>'
+ Moves the offset into the current section to the specified amount.
+
+`.section "name", <type>'
+ This is an extension to the standard .section directive. It sets
+ the current section to be <type> and creates an alias for this
+ section called "name".
+
+`.v850'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850 processor. This allows the linker to detect
+ attempts to link such code with code assembled for other
+ processors.
+
+`.v850e'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E processor. This allows the linker to detect
+ attempts to link such code with code assembled for other
+ processors.
+
+`.v850e1'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E1 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`.v850e2'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E2 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`.v850e2v3'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E2V3 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`.v850e2v4'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E3V5 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+`.v850e3v5'
+ Specifies that the assembled code should be marked as being
+ targeted at the V850E3V5 processor. This allows the linker to
+ detect attempts to link such code with code assembled for other
+ processors.
+
+
+
+File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
+
+9.48.5 Opcodes
+--------------
+
+`as' implements all the standard V850 opcodes.
+
+ `as' also implements the following pseudo ops:
+
+`hi0()'
+ Computes the higher 16 bits of the given expression and stores it
+ into the immediate operand field of the given instruction. For
+ example:
+
+ `mulhi hi0(here - there), r5, r6'
+
+ computes the difference between the address of labels 'here' and
+ 'there', takes the upper 16 bits of this difference, shifts it
+ down 16 bits and then multiplies it by the lower 16 bits in
+ register 5, putting the result into register 6.
+
+`lo()'
+ Computes the lower 16 bits of the given expression and stores it
+ into the immediate operand field of the given instruction. For
+ example:
+
+ `addi lo(here - there), r5, r6'
+
+ computes the difference between the address of labels 'here' and
+ 'there', takes the lower 16 bits of this difference and adds it to
+ register 5, putting the result into register 6.
+
+`hi()'
+ Computes the higher 16 bits of the given expression and then adds
+ the value of the most significant bit of the lower 16 bits of the
+ expression and stores the result into the immediate operand field
+ of the given instruction. For example the following code can be
+ used to compute the address of the label 'here' and store it into
+ register 6:
+
+ `movhi hi(here), r0, r6' `movea lo(here), r6, r6'
+
+ The reason for this special behaviour is that movea performs a sign
+ extension on its immediate operand. So for example if the address
+ of 'here' was 0xFFFFFFFF then without the special behaviour of the
+ hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
+ then the movea instruction would takes its immediate operand,
+ 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
+ into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
+ With the hi() pseudo op adding in the top bit of the lo() pseudo
+ op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
+ 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
+ the right value.
+
+`hilo()'
+ Computes the 32 bit value of the given expression and stores it
+ into the immediate operand field of the given instruction (which
+ must be a mov instruction). For example:
+
+ `mov hilo(here), r6'
+
+ computes the absolute address of label 'here' and puts the result
+ into register 6.
+
+`sdaoff()'
+ Computes the offset of the named variable from the start of the
+ Small Data Area (whoes address is held in register 4, the GP
+ register) and stores the result as a 16 bit signed value in the
+ immediate operand field of the given instruction. For example:
+
+ `ld.w sdaoff(_a_variable)[gp],r6'
+
+ loads the contents of the location pointed to by the label
+ '_a_variable' into register 6, provided that the label is located
+ somewhere within +/- 32K of the address held in the GP register.
+ [Note the linker assumes that the GP register contains a fixed
+ address set to the address of the label called '__gp'. This can
+ either be set up automatically by the linker, or specifically set
+ by using the `--defsym __gp=<value>' command line option].
+
+`tdaoff()'
+ Computes the offset of the named variable from the start of the
+ Tiny Data Area (whoes address is held in register 30, the EP
+ register) and stores the result as a 4,5, 7 or 8 bit unsigned
+ value in the immediate operand field of the given instruction.
+ For example:
+
+ `sld.w tdaoff(_a_variable)[ep],r6'
+
+ loads the contents of the location pointed to by the label
+ '_a_variable' into register 6, provided that the label is located
+ somewhere within +256 bytes of the address held in the EP
+ register. [Note the linker assumes that the EP register contains
+ a fixed address set to the address of the label called '__ep'.
+ This can either be set up automatically by the linker, or
+ specifically set by using the `--defsym __ep=<value>' command line
+ option].
+
+`zdaoff()'
+ Computes the offset of the named variable from address 0 and
+ stores the result as a 16 bit signed value in the immediate
+ operand field of the given instruction. For example:
+
+ `movea zdaoff(_a_variable),zero,r6'
+
+ puts the address of the label '_a_variable' into register 6,
+ assuming that the label is somewhere within the first 32K of
+ memory. (Strictly speaking it also possible to access the last
+ 32K of memory as well, as the offsets are signed).
+
+`ctoff()'
+ Computes the offset of the named variable from the start of the
+ Call Table Area (whoes address is helg in system register 20, the
+ CTBP register) and stores the result a 6 or 16 bit unsigned value
+ in the immediate field of then given instruction or piece of data.
+ For example:
+
+ `callt ctoff(table_func1)'
+
+ will put the call the function whoes address is held in the call
+ table at the location labeled 'table_func1'.
+
+`.longcall `name''
+ Indicates that the following sequence of instructions is a long
+ call to function `name'. The linker will attempt to shorten this
+ call sequence if `name' is within a 22bit offset of the call. Only
+ valid if the `-mrelax' command line switch has been enabled.
+
+`.longjump `name''
+ Indicates that the following sequence of instructions is a long
+ jump to label `name'. The linker will attempt to shorten this code
+ sequence if `name' is within a 22bit offset of the jump. Only
+ valid if the `-mrelax' command line switch has been enabled.
+
+
+ For information on the V850 instruction set, see `V850 Family
+32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
+Ltd.
+
+
+File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
+
+9.49 VAX Dependent Features
+===========================
+
+* Menu:
+
+* VAX-Opts:: VAX Command-Line Options
+* VAX-float:: VAX Floating Point
+* VAX-directives:: Vax Machine Directives
+* VAX-opcodes:: VAX Opcodes
+* VAX-branch:: VAX Branch Improvement
+* VAX-operands:: VAX Operands
+* VAX-no:: Not Supported on VAX
+* VAX-Syntax:: VAX Syntax
+
+
+File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
+
+9.49.1 VAX Command-Line Options
+-------------------------------
+
+The Vax version of `as' accepts any of the following options, gives a
+warning message that the option was ignored and proceeds. These
+options are for compatibility with scripts designed for other people's
+assemblers.
+
+``-D' (Debug)'
+``-S' (Symbol Table)'
+``-T' (Token Trace)'
+ These are obsolete options used to debug old assemblers.
+
+``-d' (Displacement size for JUMPs)'
+ This option expects a number following the `-d'. Like options
+ that expect filenames, the number may immediately follow the `-d'
+ (old standard) or constitute the whole of the command line
+ argument that follows `-d' (GNU standard).
+
+``-V' (Virtualize Interpass Temporary File)'
+ Some other assemblers use a temporary file. This option commanded
+ them to keep the information in active memory rather than in a
+ disk file. `as' always does this, so this option is redundant.
+
+``-J' (JUMPify Longer Branches)'
+ Many 32-bit computers permit a variety of branch instructions to
+ do the same job. Some of these instructions are short (and fast)
+ but have a limited range; others are long (and slow) but can
+ branch anywhere in virtual memory. Often there are 3 flavors of
+ branch: short, medium and long. Some other assemblers would emit
+ short and medium branches, unless told by this option to emit
+ short and long branches.
+
+``-t' (Temporary File Directory)'
+ Some other assemblers may use a temporary file, and this option
+ takes a filename being the directory to site the temporary file.
+ Since `as' does not use a temporary disk file, this option makes
+ no difference. `-t' needs exactly one filename.
+
+ The Vax version of the assembler accepts additional options when
+compiled for VMS:
+
+`-h N'
+ External symbol or section (used for global variables) names are
+ not case sensitive on VAX/VMS and always mapped to upper case.
+ This is contrary to the C language definition which explicitly
+ distinguishes upper and lower case. To implement a standard
+ conforming C compiler, names must be changed (mapped) to preserve
+ the case information. The default mapping is to convert all lower
+ case characters to uppercase and adding an underscore followed by
+ a 6 digit hex value, representing a 24 digit binary value. The
+ one digits in the binary value represent which characters are
+ uppercase in the original symbol name.
+
+ The `-h N' option determines how we map names. This takes several
+ values. No `-h' switch at all allows case hacking as described
+ above. A value of zero (`-h0') implies names should be upper
+ case, and inhibits the case hack. A value of 2 (`-h2') implies
+ names should be all lower case, with no case hack. A value of 3
+ (`-h3') implies that case should be preserved. The value 1 is
+ unused. The `-H' option directs `as' to display every mapped
+ symbol during assembly.
+
+ Symbols whose names include a dollar sign `$' are exceptions to the
+ general name mapping. These symbols are normally only used to
+ reference VMS library names. Such symbols are always mapped to
+ upper case.
+
+`-+'
+ The `-+' option causes `as' to truncate any symbol name larger
+ than 31 characters. The `-+' option also prevents some code
+ following the `_main' symbol normally added to make the object
+ file compatible with Vax-11 "C".
+
+`-1'
+ This option is ignored for backward compatibility with `as'
+ version 1.x.
+
+`-H'
+ The `-H' option causes `as' to print every symbol which was
+ changed by case mapping.
+
+
+File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
+
+9.49.2 VAX Floating Point
+-------------------------
+
+Conversion of flonums to floating point is correct, and compatible with
+previous assemblers. Rounding is towards zero if the remainder is
+exactly half the least significant bit.
+
+ `D', `F', `G' and `H' floating point formats are understood.
+
+ Immediate floating literals (_e.g._ `S`$6.9') are rendered
+correctly. Again, rounding is towards zero in the boundary case.
+
+ The `.float' directive produces `f' format numbers. The `.double'
+directive produces `d' format numbers.
+
+
+File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
+
+9.49.3 Vax Machine Directives
+-----------------------------
+
+The Vax version of the assembler supports four directives for
+generating Vax floating point constants. They are described in the
+table below.
+
+`.dfloat'
+ This expects zero or more flonums, separated by commas, and
+ assembles Vax `d' format 64-bit floating point constants.
+
+`.ffloat'
+ This expects zero or more flonums, separated by commas, and
+ assembles Vax `f' format 32-bit floating point constants.
+
+`.gfloat'
+ This expects zero or more flonums, separated by commas, and
+ assembles Vax `g' format 64-bit floating point constants.
+
+`.hfloat'
+ This expects zero or more flonums, separated by commas, and
+ assembles Vax `h' format 128-bit floating point constants.
+
+
+
+File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
+
+9.49.4 VAX Opcodes
+------------------
+
+All DEC mnemonics are supported. Beware that `case...' instructions
+have exactly 3 operands. The dispatch table that follows the `case...'
+instruction should be made with `.word' statements. This is compatible
+with all unix assemblers we know of.
+
+
+File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
+
+9.49.5 VAX Branch Improvement
+-----------------------------
+
+Certain pseudo opcodes are permitted. They are for branch
+instructions. They expand to the shortest branch instruction that
+reaches the target. Generally these mnemonics are made by substituting
+`j' for `b' at the start of a DEC mnemonic. This feature is included
+both for compatibility and to help compilers. If you do not need this
+feature, avoid these opcodes. Here are the mnemonics, and the code
+they can expand into.
+
+`jbsb'
+ `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
+ (byte displacement)
+ `bsbb ...'
+
+ (word displacement)
+ `bsbw ...'
+
+ (long displacement)
+ `jsb ...'
+
+`jbr'
+`jr'
+ Unconditional branch.
+ (byte displacement)
+ `brb ...'
+
+ (word displacement)
+ `brw ...'
+
+ (long displacement)
+ `jmp ...'
+
+`jCOND'
+ COND may be any one of the conditional branches `neq', `nequ',
+ `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
+ `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests
+ `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
+ `lbc'. NOTCOND is the opposite condition to COND.
+ (byte displacement)
+ `bCOND ...'
+
+ (word displacement)
+ `bNOTCOND foo ; brw ... ; foo:'
+
+ (long displacement)
+ `bNOTCOND foo ; jmp ... ; foo:'
+
+`jacbX'
+ X may be one of `b d f g h l w'.
+ (word displacement)
+ `OPCODE ...'
+
+ (long displacement)
+ OPCODE ..., foo ;
+ brb bar ;
+ foo: jmp ... ;
+ bar:
+
+`jaobYYY'
+ YYY may be one of `lss leq'.
+
+`jsobZZZ'
+ ZZZ may be one of `geq gtr'.
+ (byte displacement)
+ `OPCODE ...'
+
+ (word displacement)
+ OPCODE ..., foo ;
+ brb bar ;
+ foo: brw DESTINATION ;
+ bar:
+
+ (long displacement)
+ OPCODE ..., foo ;
+ brb bar ;
+ foo: jmp DESTINATION ;
+ bar:
+
+`aobleq'
+`aoblss'
+`sobgeq'
+`sobgtr'
+
+ (byte displacement)
+ `OPCODE ...'
+
+ (word displacement)
+ OPCODE ..., foo ;
+ brb bar ;
+ foo: brw DESTINATION ;
+ bar:
+
+ (long displacement)
+ OPCODE ..., foo ;
+ brb bar ;
+ foo: jmp DESTINATION ;
+ bar:
+
+
+File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
+
+9.49.6 VAX Operands
+-------------------
+
+The immediate character is `$' for Unix compatibility, not `#' as DEC
+writes it.
+
+ The indirect character is `*' for Unix compatibility, not `@' as DEC
+writes it.
+
+ The displacement sizing character is ``' (an accent grave) for Unix
+compatibility, not `^' as DEC writes it. The letter preceding ``' may
+have either case. `G' is not understood, but all other letters (`b i l
+s w') are understood.
+
+ Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper
+and lower case letters are equivalent.
+
+ For instance
+ tstb *w`$4(r5)
+
+ Any expression is permitted in an operand. Operands are comma
+separated.
+
+
+File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent
+
+9.49.7 Not Supported on VAX
+---------------------------
+
+Vax bit fields can not be assembled with `as'. Someone can add the
+required code if they really need it.
+
+
+File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent
+
+9.49.8 VAX Syntax
+-----------------
+
+* Menu:
+
+* VAX-Chars:: Special Characters
+
+
+File: as.info, Node: VAX-Chars, Up: VAX-Syntax
+
+9.49.8.1 Special Characters
+...........................
+
+The presence of a `#' appearing anywhere on a line indicates the start
+of a comment that extends to the end of that line.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line can also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The `;' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: Visium-Dependent, Next: XGATE-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies
+
+9.50 Visium Dependent Features
+==============================
+
+* Menu:
+
+* Visium Options:: Options
+* Visium Syntax:: Syntax
+* Visium Opcodes:: Opcodes
+
+
+File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent
+
+9.50.1 Options
+--------------
+
+The Visium assembler implements one machine-specific option:
+
+`-mtune=ARCH'
+ This option specifies the target architecture. If an attempt is
+ made to assemble an instruction that will not execute on the
+ target architecture, the assembler will issue an error message.
+
+ The following names are recognized: `mcm24' `mcm' `gr5' `gr6'
+
+
+File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent
+
+9.50.2 Syntax
+-------------
+
+* Menu:
+
+* Visium Characters:: Special Characters
+* Visium Registers:: Register Names
+
+
+File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax
+
+9.50.2.1 Special Characters
+...........................
+
+Line comments are introduced either by the `!' character or by the `;'
+character appearing anywhere on a line.
+
+ A hash character (`#') as the first character on a line also marks
+the start of a line comment, but in this case it could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The Visium assembler does not currently support a line separator
+character.
+
+
+File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax
+
+9.50.2.2 Register Names
+.......................
+
+Registers can be specified either by using their canonical mnemonic
+names or by using their alias if they have one, for example `sp'.
+
+
+File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent
+
+9.50.3 Opcodes
+--------------
+
+All the standard opcodes of the architecture are implemented, along
+with the following three pseudo-instructions: `cmp', `cmpc', `move'.
+
+ In addition, the following two illegal opcodes are implemented and
+used by the simulation:
+
+ stop 5-bit immediate, SourceA
+ trace 5-bit immediate, SourceA
+
+
+File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies
+
+9.51 XGATE Dependent Features
+=============================
+
+* Menu:
+
+* XGATE-Opts:: XGATE Options
+* XGATE-Syntax:: Syntax
+* XGATE-Directives:: Assembler Directives
+* XGATE-Float:: Floating Point
+* XGATE-opcodes:: Opcodes
+
+
+File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent
+
+9.51.1 XGATE Options
+--------------------
+
+The Freescale XGATE version of `as' has a few machine dependent options.
+
+`-mshort'
+ This option controls the ABI and indicates to use a 16-bit integer
+ ABI. It has no effect on the assembled instructions. This is the
+ default.
+
+`-mlong'
+ This option controls the ABI and indicates to use a 32-bit integer
+ ABI.
+
+`-mshort-double'
+ This option controls the ABI and indicates to use a 32-bit float
+ ABI. This is the default.
+
+`-mlong-double'
+ This option controls the ABI and indicates to use a 64-bit float
+ ABI.
+
+`--print-insn-syntax'
+ You can use the `--print-insn-syntax' option to obtain the syntax
+ description of the instruction when an error is detected.
+
+`--print-opcodes'
+ The `--print-opcodes' option prints the list of all the
+ instructions with their syntax. Once the list is printed `as'
+ exits.
+
+
+
+File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent
+
+9.51.2 Syntax
+-------------
+
+In XGATE RISC syntax, the instruction name comes first and it may be
+followed by up to three operands. Operands are separated by commas
+(`,'). `as' will complain if too many operands are specified for a
+given instruction. The same will happen if you specified too few
+operands.
+
+ nop
+ ldl #23
+ CMP R1, R2
+
+ The presence of a `;' character or a `!' character anywhere on a
+line indicates the start of a comment that extends to the end of that
+line.
+
+ A `*' or a `#' character at the start of a line also introduces a
+line comment, but these characters do not work elsewhere on the line.
+If the first character of the line is a `#' then as well as starting a
+comment, the line could also be logical line number directive (*note
+Comments::) or a preprocessor control command (*note Preprocessing::).
+
+ The XGATE assembler does not currently support a line separator
+character.
+
+ The following addressing modes are understood for XGATE:
+"Inherent"
+ `'
+
+"Immediate 3 Bit Wide"
+ `#NUMBER'
+
+"Immediate 4 Bit Wide"
+ `#NUMBER'
+
+"Immediate 8 Bit Wide"
+ `#NUMBER'
+
+"Monadic Addressing"
+ `REG'
+
+"Dyadic Addressing"
+ `REG, REG'
+
+"Triadic Addressing"
+ `REG, REG, REG'
+
+"Relative Addressing 9 Bit Wide"
+ `*SYMBOL'
+
+"Relative Addressing 10 Bit Wide"
+ `*SYMBOL'
+
+"Index Register plus Immediate Offset"
+ `REG, (REG, #NUMBER)'
+
+"Index Register plus Register Offset"
+ `REG, REG, REG'
+
+"Index Register plus Register Offset with Post-increment"
+ `REG, REG, REG+'
+
+"Index Register plus Register Offset with Pre-decrement"
+ `REG, REG, -REG'
+
+ The register can be either `R0', `R1', `R2', `R3', `R4', `R5',
+ `R6' or `R7'.
+
+
+ Convience macro opcodes to deal with 16-bit values have been added.
+
+"Immediate 16 Bit Wide"
+ `#NUMBER', or `*SYMBOL'
+
+ For example:
+
+ ldw R1, #1024
+ ldw R3, timer
+ ldw R1, (R1, #0)
+ COM R1
+ stw R2, (R1, #0)
+
+
+File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent
+
+9.51.3 Assembler Directives
+---------------------------
+
+The XGATE version of `as' have the following specific assembler
+directives:
+
+
+File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent
+
+9.51.4 Floating Point
+---------------------
+
+Packed decimal (P) format floating literals are not supported(yet).
+
+ The floating point formats generated by directives are these.
+
+`.float'
+ `Single' precision floating point constants.
+
+`.double'
+ `Double' precision floating point constants.
+
+`.extend'
+`.ldouble'
+ `Extended' precision (`long double') floating point constants.
+
+
+File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent
+
+9.51.5 Opcodes
+--------------
+
+
+File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies
+
+9.52 XStormy16 Dependent Features
+=================================
+
+* Menu:
+
+* XStormy16 Syntax:: Syntax
+* XStormy16 Directives:: Machine Directives
+* XStormy16 Opcodes:: Pseudo-Opcodes
+
+
+File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent
+
+9.52.1 Syntax
+-------------
+
+* Menu:
+
+* XStormy16-Chars:: Special Characters
+
+
+File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax
+
+9.52.1.1 Special Characters
+...........................
+
+`#' is the line comment character. If a `#' appears as the first
+character of a line, the whole line is treated as a comment, but in
+this case the line can also be a logical line number directive (*note
+Comments::) or a preprocessor control command (*note Preprocessing::).
+
+ A semicolon (`;') can be used to start a comment that extends from
+wherever the character appears on the line up to the end of the line.
+
+ The `|' character can be used to separate statements on the same
+line.
+
+
+File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent
+
+9.52.2 XStormy16 Machine Directives
+-----------------------------------
+
+`.16bit_pointers'
+ Like the `--16bit-pointers' command line option this directive
+ indicates that the assembly code makes use of 16-bit pointers.
+
+`.32bit_pointers'
+ Like the `--32bit-pointers' command line option this directive
+ indicates that the assembly code makes use of 32-bit pointers.
+
+`.no_pointers'
+ Like the `--no-pointers' command line option this directive
+ indicates that the assembly code does not makes use pointers.
+
+
+
+File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent
+
+9.52.3 XStormy16 Pseudo-Opcodes
+-------------------------------
+
+`as' implements all the standard XStormy16 opcodes.
+
+ `as' also implements the following pseudo ops:
+
+`@lo()'
+ Computes the lower 16 bits of the given expression and stores it
+ into the immediate operand field of the given instruction. For
+ example:
+
+ `add r6, @lo(here - there)'
+
+ computes the difference between the address of labels 'here' and
+ 'there', takes the lower 16 bits of this difference and adds it to
+ register 6.
+
+`@hi()'
+ Computes the higher 16 bits of the given expression and stores it
+ into the immediate operand field of the given instruction. For
+ example:
+
+ `addc r7, @hi(here - there)'
+
+ computes the difference between the address of labels 'here' and
+ 'there', takes the upper 16 bits of this difference, shifts it
+ down 16 bits and then adds it, along with the carry bit, to the
+ value in register 7.
+
+
+
+File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies
+
+9.53 Xtensa Dependent Features
+==============================
+
+ This chapter covers features of the GNU assembler that are specific
+to the Xtensa architecture. For details about the Xtensa instruction
+set, please consult the `Xtensa Instruction Set Architecture (ISA)
+Reference Manual'.
+
+* Menu:
+
+* Xtensa Options:: Command-line Options.
+* Xtensa Syntax:: Assembler Syntax for Xtensa Processors.
+* Xtensa Optimizations:: Assembler Optimizations.
+* Xtensa Relaxation:: Other Automatic Transformations.
+* Xtensa Directives:: Directives for Xtensa Processors.
+
+
+File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent
+
+9.53.1 Command Line Options
+---------------------------
+
+`--text-section-literals | --no-text-section-literals'
+ Control the treatment of literal pools. The default is
+ `--no-text-section-literals', which places literals in separate
+ sections in the output file. This allows the literal pool to be
+ placed in a data RAM/ROM. With `--text-section-literals', the
+ literals are interspersed in the text section in order to keep
+ them as close as possible to their references. This may be
+ necessary for large assembly files, where the literals would
+ otherwise be out of range of the `L32R' instructions in the text
+ section. Literals are grouped into pools following
+ `.literal_position' directives or preceding `ENTRY' instructions.
+ These options only affect literals referenced via PC-relative
+ `L32R' instructions; literals for absolute mode `L32R'
+ instructions are handled separately. *Note literal: Literal
+ Directive.
+
+`--auto-litpools | --no-auto-litpools'
+ Control the treatment of literal pools. The default is
+ `--no-auto-litpools', which in the absence of
+ `--text-section-literals' places literals in separate sections in
+ the output file. This allows the literal pool to be placed in a
+ data RAM/ROM. With `--auto-litpools', the literals are
+ interspersed in the text section in order to keep them as close as
+ possible to their references, explicit `.literal_position'
+ directives are not required. This may be necessary for very large
+ functions, where single literal pool at the beginning of the
+ function may not be reachable by `L32R' instructions at the end.
+ These options only affect literals referenced via PC-relative
+ `L32R' instructions; literals for absolute mode `L32R'
+ instructions are handled separately. When used together with
+ `--text-section-literals', `--auto-litpools' takes precedence.
+ *Note literal: Literal Directive.
+
+`--absolute-literals | --no-absolute-literals'
+ Indicate to the assembler whether `L32R' instructions use absolute
+ or PC-relative addressing. If the processor includes the absolute
+ addressing option, the default is to use absolute `L32R'
+ relocations. Otherwise, only the PC-relative `L32R' relocations
+ can be used.
+
+`--target-align | --no-target-align'
+ Enable or disable automatic alignment to reduce branch penalties
+ at some expense in code size. *Note Automatic Instruction
+ Alignment: Xtensa Automatic Alignment. This optimization is
+ enabled by default. Note that the assembler will always align
+ instructions like `LOOP' that have fixed alignment requirements.
+
+`--longcalls | --no-longcalls'
+ Enable or disable transformation of call instructions to allow
+ calls across a greater range of addresses. *Note Function Call
+ Relaxation: Xtensa Call Relaxation. This option should be used
+ when call targets can potentially be out of range. It may degrade
+ both code size and performance, but the linker can generally
+ optimize away the unnecessary overhead when a call ends up within
+ range. The default is `--no-longcalls'.
+
+`--transform | --no-transform'
+ Enable or disable all assembler transformations of Xtensa
+ instructions, including both relaxation and optimization. The
+ default is `--transform'; `--no-transform' should only be used in
+ the rare cases when the instructions must be exactly as specified
+ in the assembly source. Using `--no-transform' causes out of range
+ instruction operands to be errors.
+
+`--rename-section OLDNAME=NEWNAME'
+ Rename the OLDNAME section to NEWNAME. This option can be used
+ multiple times to rename multiple sections.
+
+`--trampolines | --no-trampolines'
+ Enable or disable transformation of jump instructions to allow
+ jumps across a greater range of addresses. *Note Jump
+ Trampolines: Xtensa Jump Relaxation. This option should be used
+ when jump targets can potentially be out of range. In the absence
+ of such jumps this option does not affect code size or
+ performance. The default is `--trampolines'.
+
+
+File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent
+
+9.53.2 Assembler Syntax
+-----------------------
+
+Block comments are delimited by `/*' and `*/'. End of line comments
+may be introduced with either `#' or `//'.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ Instructions consist of a leading opcode or macro name followed by
+whitespace and an optional comma-separated list of operands:
+
+ OPCODE [OPERAND, ...]
+
+ Instructions must be separated by a newline or semicolon (`;').
+
+ FLIX instructions, which bundle multiple opcodes together in a single
+instruction, are specified by enclosing the bundled opcodes inside
+braces:
+
+ {
+ [FORMAT]
+ OPCODE0 [OPERANDS]
+ OPCODE1 [OPERANDS]
+ OPCODE2 [OPERANDS]
+ ...
+ }
+
+ The opcodes in a FLIX instruction are listed in the same order as the
+corresponding instruction slots in the TIE format declaration.
+Directives and labels are not allowed inside the braces of a FLIX
+instruction. A particular TIE format name can optionally be specified
+immediately after the opening brace, but this is usually unnecessary.
+The assembler will automatically search for a format that can encode the
+specified opcodes, so the format name need only be specified in rare
+cases where there is more than one applicable format and where it
+matters which of those formats is used. A FLIX instruction can also be
+specified on a single line by separating the opcodes with semicolons:
+
+ { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
+
+ If an opcode can only be encoded in a FLIX instruction but is not
+specified as part of a FLIX bundle, the assembler will choose the
+smallest format where the opcode can be encoded and will fill unused
+instruction slots with no-ops.
+
+* Menu:
+
+* Xtensa Opcodes:: Opcode Naming Conventions.
+* Xtensa Registers:: Register Naming.
+
+
+File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax
+
+9.53.2.1 Opcode Names
+.....................
+
+See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
+for a complete list of opcodes and descriptions of their semantics.
+
+ If an opcode name is prefixed with an underscore character (`_'),
+`as' will not transform that instruction in any way. The underscore
+prefix disables both optimization (*note Xtensa Optimizations: Xtensa
+Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
+Relaxation.) for that particular instruction. Only use the underscore
+prefix when it is essential to select the exact opcode produced by the
+assembler. Using this feature unnecessarily makes the code less
+efficient by disabling assembler optimization and less flexible by
+disabling relaxation.
+
+ Note that this special handling of underscore prefixes only applies
+to Xtensa opcodes, not to either built-in macros or user-defined macros.
+When an underscore prefix is used with a macro (e.g., `_MOV'), it
+refers to a different macro. The assembler generally provides built-in
+macros both with and without the underscore prefix, where the underscore
+versions behave as if the underscore carries through to the instructions
+in the macros. For example, `_MOV' may expand to `_MOV.N'.
+
+ The underscore prefix only applies to individual instructions, not to
+series of instructions. For example, if a series of instructions have
+underscore prefixes, the assembler will not transform the individual
+instructions, but it may insert other instructions between them (e.g.,
+to align a `LOOP' instruction). To prevent the assembler from
+modifying a series of instructions as a whole, use the `no-transform'
+directive. *Note transform: Transform Directive.
+
+
+File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax
+
+9.53.2.2 Register Names
+.......................
+
+The assembly syntax for a register file entry is the "short" name for a
+TIE register file followed by the index into that register file. For
+example, the general-purpose `AR' register file has a short name of
+`a', so these registers are named `a0'...`a15'. As a special feature,
+`sp' is also supported as a synonym for `a1'. Additional registers may
+be added by processor configuration options and by designer-defined TIE
+extensions. An initial `$' character is optional in all register names.
+
+
+File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent
+
+9.53.3 Xtensa Optimizations
+---------------------------
+
+The optimizations currently supported by `as' are generation of density
+instructions where appropriate and automatic branch target alignment.
+
+* Menu:
+
+* Density Instructions:: Using Density Instructions.
+* Xtensa Automatic Alignment:: Automatic Instruction Alignment.
+
+
+File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations
+
+9.53.3.1 Using Density Instructions
+...................................
+
+The Xtensa instruction set has a code density option that provides
+16-bit versions of some of the most commonly used opcodes. Use of these
+opcodes can significantly reduce code size. When possible, the
+assembler automatically translates instructions from the core Xtensa
+instruction set into equivalent instructions from the Xtensa code
+density option. This translation can be disabled by using underscore
+prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
+`--no-transform' command-line option (*note Command Line Options:
+Xtensa Options.), or by using the `no-transform' directive (*note
+transform: Transform Directive.).
+
+ It is a good idea _not_ to use the density instructions directly.
+The assembler will automatically select dense instructions where
+possible. If you later need to use an Xtensa processor without the code
+density option, the same assembly code will then work without
+modification.
+
+
+File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations
+
+9.53.3.2 Automatic Instruction Alignment
+........................................
+
+The Xtensa assembler will automatically align certain instructions, both
+to optimize performance and to satisfy architectural requirements.
+
+ As an optimization to improve performance, the assembler attempts to
+align branch targets so they do not cross instruction fetch boundaries.
+(Xtensa processors can be configured with either 32-bit or 64-bit
+instruction fetch widths.) An instruction immediately following a call
+is treated as a branch target in this context, because it will be the
+target of a return from the call. This alignment has the potential to
+reduce branch penalties at some expense in code size. This
+optimization is enabled by default. You can disable it with the
+`--no-target-align' command-line option (*note Command Line Options:
+Xtensa Options.).
+
+ The target alignment optimization is done without adding instructions
+that could increase the execution time of the program. If there are
+density instructions in the code preceding a target, the assembler can
+change the target alignment by widening some of those instructions to
+the equivalent 24-bit instructions. Extra bytes of padding can be
+inserted immediately following unconditional jump and return
+instructions. This approach is usually successful in aligning many,
+but not all, branch targets.
+
+ The `LOOP' family of instructions must be aligned such that the
+first instruction in the loop body does not cross an instruction fetch
+boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be
+on either a 1 or 2 mod 4 byte boundary). The assembler knows about
+this restriction and inserts the minimal number of 2 or 3 byte no-op
+instructions to satisfy it. When no-op instructions are added, any
+label immediately preceding the original loop will be moved in order to
+refer to the loop instruction, not the newly generated no-op
+instruction. To preserve binary compatibility across processors with
+different fetch widths, the assembler conservatively assumes a 32-bit
+fetch width when aligning `LOOP' instructions (except if the first
+instruction in the loop is a 64-bit instruction).
+
+ Previous versions of the assembler automatically aligned `ENTRY'
+instructions to 4-byte boundaries, but that alignment is now the
+programmer's responsibility.
+
+
+File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent
+
+9.53.4 Xtensa Relaxation
+------------------------
+
+When an instruction operand is outside the range allowed for that
+particular instruction field, `as' can transform the code to use a
+functionally-equivalent instruction or sequence of instructions. This
+process is known as "relaxation". This is typically done for branch
+instructions because the distance of the branch targets is not known
+until assembly-time. The Xtensa assembler offers branch relaxation and
+also extends this concept to function calls, `MOVI' instructions and
+other instructions with immediate fields.
+
+* Menu:
+
+* Xtensa Branch Relaxation:: Relaxation of Branches.
+* Xtensa Call Relaxation:: Relaxation of Function Calls.
+* Xtensa Jump Relaxation:: Relaxation of Jumps.
+* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields.
+
+
+File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation
+
+9.53.4.1 Conditional Branch Relaxation
+......................................
+
+When the target of a branch is too far away from the branch itself,
+i.e., when the offset from the branch to the target is too large to fit
+in the immediate field of the branch instruction, it may be necessary to
+replace the branch with a branch around a jump. For example,
+
+ beqz a2, L
+
+ may result in:
+
+ bnez.n a2, M
+ j L
+ M:
+
+ (The `BNEZ.N' instruction would be used in this example only if the
+density option is available. Otherwise, `BNEZ' would be used.)
+
+ This relaxation works well because the unconditional jump instruction
+has a much larger offset range than the various conditional branches.
+However, an error will occur if a branch target is beyond the range of a
+jump instruction. `as' cannot relax unconditional jumps. Similarly,
+an error will occur if the original input contains an unconditional
+jump to a target that is out of range.
+
+ Branch relaxation is enabled by default. It can be disabled by using
+underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
+`--no-transform' command-line option (*note Command Line Options:
+Xtensa Options.), or the `no-transform' directive (*note transform:
+Transform Directive.).
+
+
+File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation
+
+9.53.4.2 Function Call Relaxation
+.................................
+
+Function calls may require relaxation because the Xtensa immediate call
+instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a
+PC-relative offset of only 512 Kbytes in either direction. For larger
+programs, it may be necessary to use indirect calls (`CALLX0',
+`CALLX4', `CALLX8' and `CALLX12') where the target address is specified
+in a register. The Xtensa assembler can automatically relax immediate
+call instructions into indirect call instructions. This relaxation is
+done by loading the address of the called function into the callee's
+return address register and then using a `CALLX' instruction. So, for
+example:
+
+ call8 func
+
+ might be relaxed to:
+
+ .literal .L1, func
+ l32r a8, .L1
+ callx8 a8
+
+ Because the addresses of targets of function calls are not generally
+known until link-time, the assembler must assume the worst and relax all
+the calls to functions in other source files, not just those that really
+will be out of range. The linker can recognize calls that were
+unnecessarily relaxed, and it will remove the overhead introduced by the
+assembler for those cases where direct calls are sufficient.
+
+ Call relaxation is disabled by default because it can have a negative
+effect on both code size and performance, although the linker can
+usually eliminate the unnecessary overhead. If a program is too large
+and some of the calls are out of range, function call relaxation can be
+enabled using the `--longcalls' command-line option or the `longcalls'
+directive (*note longcalls: Longcalls Directive.).
+
+
+File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation
+
+9.53.4.3 Jump Relaxation
+........................
+
+Jump instruction may require relaxation because the Xtensa jump
+instruction (`J') provide a PC-relative offset of only 128 Kbytes in
+either direction. One option is to use jump long (`J.L') instruction,
+which depending on jump distance may be assembled as jump (`J') or
+indirect jump (`JX'). However it needs a free register. When there's
+no spare register it is possible to plant intermediate jump sites
+(trampolines) between the jump instruction and its target. These sites
+may be located in areas unreachable by normal code execution flow, in
+that case they only contain intermediate jumps, or they may be inserted
+in the middle of code block, in which case there's an additional jump
+from the beginning of the trampoline to the instruction past its end.
+So, for example:
+
+ j 1f
+ ...
+ retw
+ ...
+ mov a10, a2
+ call8 func
+ ...
+ 1:
+ ...
+
+ might be relaxed to:
+
+ j .L0_TR_1
+ ...
+ retw
+ .L0_TR_1:
+ j 1f
+ ...
+ mov a10, a2
+ call8 func
+ ...
+ 1:
+ ...
+
+ or to:
+
+ j .L0_TR_1
+ ...
+ retw
+ ...
+ mov a10, a2
+ j .L0_TR_0
+ .L0_TR_1:
+ j 1f
+ .L0_TR_0:
+ call8 func
+ ...
+ 1:
+ ...
+
+ The Xtensa assempler uses trampolines with jump around only when it
+cannot find suitable unreachable trampoline. There may be multiple
+trampolines between the jump instruction and its target.
+
+ This relaxation does not apply to jumps to undefined symbols,
+assuming they will reach their targets once resolved.
+
+ Jump relaxation is enabled by default because it does not affect
+code size or performance while the code itself is small. This
+relaxation may be disabled completely with `--no-trampolines' or
+`--no-transform' command-line options (*note Command Line Options:
+Xtensa Options.).
+
+
+File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation
+
+9.53.4.4 Other Immediate Field Relaxation
+.........................................
+
+The assembler normally performs the following other relaxations. They
+can be disabled by using underscore prefixes (*note Opcode Names:
+Xtensa Opcodes.), the `--no-transform' command-line option (*note
+Command Line Options: Xtensa Options.), or the `no-transform' directive
+(*note transform: Transform Directive.).
+
+ The `MOVI' machine instruction can only materialize values in the
+range from -2048 to 2047. Values outside this range are best
+materialized with `L32R' instructions. Thus:
+
+ movi a0, 100000
+
+ is assembled into the following machine code:
+
+ .literal .L1, 100000
+ l32r a0, .L1
+
+ The `L8UI' machine instruction can only be used with immediate
+offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine
+instructions can only be used with offsets from 0 to 510. The `L32I'
+machine instruction can only be used with offsets from 0 to 1020. A
+load offset outside these ranges can be materialized with an `L32R'
+instruction if the destination register of the load is different than
+the source address register. For example:
+
+ l32i a1, a0, 2040
+
+ is translated to:
+
+ .literal .L1, 2040
+ l32r a1, .L1
+ add a1, a0, a1
+ l32i a1, a1, 0
+
+If the load destination and source address register are the same, an
+out-of-range offset causes an error.
+
+ The Xtensa `ADDI' instruction only allows immediate operands in the
+range from -128 to 127. There are a number of alternate instruction
+sequences for the `ADDI' operation. First, if the immediate is 0, the
+`ADDI' will be turned into a `MOV.N' instruction (or the equivalent
+`OR' instruction if the code density option is not available). If the
+`ADDI' immediate is outside of the range -128 to 127, but inside the
+range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI'
+sequence will be used. Finally, if the immediate is outside of this
+range and a free register is available, an `L32R'/`ADD' sequence will
+be used with a literal allocated from the literal pool.
+
+ For example:
+
+ addi a5, a6, 0
+ addi a5, a6, 512
+ addi a5, a6, 513
+ addi a5, a6, 50000
+
+ is assembled into the following:
+
+ .literal .L1, 50000
+ mov.n a5, a6
+ addmi a5, a6, 0x200
+ addmi a5, a6, 0x200
+ addi a5, a5, 1
+ l32r a5, .L1
+ add a5, a6, a5
+
+
+File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent
+
+9.53.5 Directives
+-----------------
+
+The Xtensa assembler supports a region-based directive syntax:
+
+ .begin DIRECTIVE [OPTIONS]
+ ...
+ .end DIRECTIVE
+
+ All the Xtensa-specific directives that apply to a region of code use
+this syntax.
+
+ The directive applies to code between the `.begin' and the `.end'.
+The state of the option after the `.end' reverts to what it was before
+the `.begin'. A nested `.begin'/`.end' region can further change the
+state of the directive without having to be aware of its outer state.
+For example, consider:
+
+ .begin no-transform
+ L: add a0, a1, a2
+ .begin transform
+ M: add a0, a1, a2
+ .end transform
+ N: add a0, a1, a2
+ .end no-transform
+
+ The `ADD' opcodes at `L' and `N' in the outer `no-transform' region
+both result in `ADD' machine instructions, but the assembler selects an
+`ADD.N' instruction for the `ADD' at `M' in the inner `transform'
+region.
+
+ The advantage of this style is that it works well inside macros
+which can preserve the context of their callers.
+
+ The following directives are available:
+
+* Menu:
+
+* Schedule Directive:: Enable instruction scheduling.
+* Longcalls Directive:: Use Indirect Calls for Greater Range.
+* Transform Directive:: Disable All Assembler Transformations.
+* Literal Directive:: Intermix Literals with Instructions.
+* Literal Position Directive:: Specify Inline Literal Pool Locations.
+* Literal Prefix Directive:: Specify Literal Section Name Prefix.
+* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
+
+
+File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives
+
+9.53.5.1 schedule
+.................
+
+The `schedule' directive is recognized only for compatibility with
+Tensilica's assembler.
+
+ .begin [no-]schedule
+ .end [no-]schedule
+
+ This directive is ignored and has no effect on `as'.
+
+
+File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives
+
+9.53.5.2 longcalls
+..................
+
+The `longcalls' directive enables or disables function call relaxation.
+*Note Function Call Relaxation: Xtensa Call Relaxation.
+
+ .begin [no-]longcalls
+ .end [no-]longcalls
+
+ Call relaxation is disabled by default unless the `--longcalls'
+command-line option is specified. The `longcalls' directive overrides
+the default determined by the command-line options.
+
+
+File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives
+
+9.53.5.3 transform
+..................
+
+This directive enables or disables all assembler transformation,
+including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
+optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
+
+ .begin [no-]transform
+ .end [no-]transform
+
+ Transformations are enabled by default unless the `--no-transform'
+option is used. The `transform' directive overrides the default
+determined by the command-line options. An underscore opcode prefix,
+disabling transformation of that opcode, always takes precedence over
+both directives and command-line flags.
+
+
+File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives
+
+9.53.5.4 literal
+................
+
+The `.literal' directive is used to define literal pool data, i.e.,
+read-only 32-bit data accessed via `L32R' instructions.
+
+ .literal LABEL, VALUE[, VALUE...]
+
+ This directive is similar to the standard `.word' directive, except
+that the actual location of the literal data is determined by the
+assembler and linker, not by the position of the `.literal' directive.
+Using this directive gives the assembler freedom to locate the literal
+data in the most appropriate place and possibly to combine identical
+literals. For example, the code:
+
+ entry sp, 40
+ .literal .L1, sym
+ l32r a4, .L1
+
+ can be used to load a pointer to the symbol `sym' into register
+`a4'. The value of `sym' will not be placed between the `ENTRY' and
+`L32R' instructions; instead, the assembler puts the data in a literal
+pool.
+
+ Literal pools are placed by default in separate literal sections;
+however, when using the `--text-section-literals' option (*note Command
+Line Options: Xtensa Options.), the literal pools for PC-relative mode
+`L32R' instructions are placed in the current section.(1) These text
+section literal pools are created automatically before `ENTRY'
+instructions and manually after `.literal_position' directives (*note
+literal_position: Literal Position Directive.). If there are no
+preceding `ENTRY' instructions, explicit `.literal_position' directives
+must be used to place the text section literal pools; otherwise, `as'
+will report an error.
+
+ When literals are placed in separate sections, the literal section
+names are derived from the names of the sections where the literals are
+defined. The base literal section names are `.literal' for PC-relative
+mode `L32R' instructions and `.lit4' for absolute mode `L32R'
+instructions (*note absolute-literals: Absolute Literals Directive.).
+These base names are used for literals defined in the default `.text'
+section. For literals defined in other sections or within the scope of
+a `literal_prefix' directive (*note literal_prefix: Literal Prefix
+Directive.), the following rules determine the literal section name:
+
+ 1. If the current section is a member of a section group, the literal
+ section name includes the group name as a suffix to the base
+ `.literal' or `.lit4' name, with a period to separate the base
+ name and group name. The literal section is also made a member of
+ the group.
+
+ 2. If the current section name (or `literal_prefix' value) begins with
+ "`.gnu.linkonce.KIND.'", the literal section name is formed by
+ replacing "`.KIND'" with the base `.literal' or `.lit4' name. For
+ example, for literals defined in a section named
+ `.gnu.linkonce.t.func', the literal section will be
+ `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'.
+
+ 3. If the current section name (or `literal_prefix' value) ends with
+ `.text', the literal section name is formed by replacing that
+ suffix with the base `.literal' or `.lit4' name. For example, for
+ literals defined in a section named `.iram0.text', the literal
+ section will be `.iram0.literal' or `.iram0.lit4'.
+
+ 4. If none of the preceding conditions apply, the literal section
+ name is formed by adding the base `.literal' or `.lit4' name as a
+ suffix to the current section name (or `literal_prefix' value).
+
+ ---------- Footnotes ----------
+
+ (1) Literals for the `.init' and `.fini' sections are always placed
+in separate sections, even when `--text-section-literals' is enabled.
+
+
+File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives
+
+9.53.5.5 literal_position
+.........................
+
+When using `--text-section-literals' to place literals inline in the
+section being assembled, the `.literal_position' directive can be used
+to mark a potential location for a literal pool.
+
+ .literal_position
+
+ The `.literal_position' directive is ignored when the
+`--text-section-literals' option is not used or when `L32R'
+instructions use the absolute addressing mode.
+
+ The assembler will automatically place text section literal pools
+before `ENTRY' instructions, so the `.literal_position' directive is
+only needed to specify some other location for a literal pool. You may
+need to add an explicit jump instruction to skip over an inline literal
+pool.
+
+ For example, an interrupt vector does not begin with an `ENTRY'
+instruction so the assembler will be unable to automatically find a good
+place to put a literal pool. Moreover, the code for the interrupt
+vector must be at a specific starting address, so the literal pool
+cannot come before the start of the code. The literal pool for the
+vector must be explicitly positioned in the middle of the vector (before
+any uses of the literals, due to the negative offsets used by
+PC-relative `L32R' instructions). The `.literal_position' directive
+can be used to do this. In the following code, the literal for `M'
+will automatically be aligned correctly and is placed after the
+unconditional jump.
+
+ .global M
+ code_start:
+ j continue
+ .literal_position
+ .align 4
+ continue:
+ movi a4, M
+
+
+File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives
+
+9.53.5.6 literal_prefix
+.......................
+
+The `literal_prefix' directive allows you to override the default
+literal section names, which are derived from the names of the sections
+where the literals are defined.
+
+ .begin literal_prefix [NAME]
+ .end literal_prefix
+
+ For literals defined within the delimited region, the literal section
+names are derived from the NAME argument instead of the name of the
+current section. The rules used to derive the literal section names do
+not change. *Note literal: Literal Directive. If the NAME argument is
+omitted, the literal sections revert to the defaults. This directive
+has no effect when using the `--text-section-literals' option (*note
+Command Line Options: Xtensa Options.).
+
+
+File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives
+
+9.53.5.7 absolute-literals
+..........................
+
+The `absolute-literals' and `no-absolute-literals' directives control
+the absolute vs. PC-relative mode for `L32R' instructions. These are
+relevant only for Xtensa configurations that include the absolute
+addressing option for `L32R' instructions.
+
+ .begin [no-]absolute-literals
+ .end [no-]absolute-literals
+
+ These directives do not change the `L32R' mode--they only cause the
+assembler to emit the appropriate kind of relocation for `L32R'
+instructions and to place the literal values in the appropriate section.
+To change the `L32R' mode, the program must write the `LITBASE' special
+register. It is the programmer's responsibility to keep track of the
+mode and indicate to the assembler which mode is used in each region of
+code.
+
+ If the Xtensa configuration includes the absolute `L32R' addressing
+option, the default is to assume absolute `L32R' addressing unless the
+`--no-absolute-literals' command-line option is specified. Otherwise,
+the default is to assume PC-relative `L32R' addressing. The
+`absolute-literals' directive can then be used to override the default
+determined by the command-line options.
+
+
+File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies
+
+9.54 Z80 Dependent Features
+===========================
+
+* Menu:
+
+* Z80 Options:: Options
+* Z80 Syntax:: Syntax
+* Z80 Floating Point:: Floating Point
+* Z80 Directives:: Z80 Machine Directives
+* Z80 Opcodes:: Opcodes
+
+
+File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent
+
+9.54.1 Options
+--------------
+
+The Zilog Z80 and Ascii R800 version of `as' have a few machine
+dependent options.
+`-z80'
+ Produce code for the Z80 processor. There are additional options to
+ request warnings and error messages for undocumented instructions.
+
+`-ignore-undocumented-instructions'
+`-Wnud'
+ Silently assemble undocumented Z80-instructions that have been
+ adopted as documented R800-instructions.
+
+`-ignore-unportable-instructions'
+`-Wnup'
+ Silently assemble all undocumented Z80-instructions.
+
+`-warn-undocumented-instructions'
+`-Wud'
+ Issue warnings for undocumented Z80-instructions that work on
+ R800, do not assemble other undocumented instructions without
+ warning.
+
+`-warn-unportable-instructions'
+`-Wup'
+ Issue warnings for other undocumented Z80-instructions, do not
+ treat any undocumented instructions as errors.
+
+`-forbid-undocumented-instructions'
+`-Fud'
+ Treat all undocumented z80-instructions as errors.
+
+`-forbid-unportable-instructions'
+`-Fup'
+ Treat undocumented z80-instructions that do not work on R800 as
+ errors.
+
+`-r800'
+ Produce code for the R800 processor. The assembler does not support
+ undocumented instructions for the R800. In line with common
+ practice, `as' uses Z80 instruction names for the R800 processor,
+ as far as they exist.
+
+
+File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent
+
+9.54.2 Syntax
+-------------
+
+The assembler syntax closely follows the 'Z80 family CPU User Manual' by
+Zilog. In expressions a single `=' may be used as "is equal to"
+comparison operator.
+
+ Suffices can be used to indicate the radix of integer constants; `H'
+or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o'
+for octal, and `B' for binary.
+
+ The suffix `b' denotes a backreference to local label.
+
+* Menu:
+
+* Z80-Chars:: Special Characters
+* Z80-Regs:: Register Names
+* Z80-Case:: Case Sensitivity
+
+
+File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax
+
+9.54.2.1 Special Characters
+...........................
+
+The semicolon `;' is the line comment character;
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ The Z80 assembler does not support a line separator character.
+
+ The dollar sign `$' can be used as a prefix for hexadecimal numbers
+and as a symbol denoting the current location counter.
+
+ A backslash `\' is an ordinary character for the Z80 assembler.
+
+ The single quote `'' must be followed by a closing quote. If there
+is one character in between, it is a character constant, otherwise it is
+a string constant.
+
+
+File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax
+
+9.54.2.2 Register Names
+.......................
+
+The registers are referred to with the letters assigned to them by
+Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and
+most significant octet in `ix', and similarly `iyl' and `iyh' as parts
+of `iy'.
+
+
+File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax
+
+9.54.2.3 Case Sensitivity
+.........................
+
+Upper and lower case are equivalent in register names, opcodes,
+condition codes and assembler directives. The case of letters is
+significant in labels and symbol names. The case is also important to
+distinguish the suffix `b' for a backward reference to a local label
+from the suffix `B' for a number in binary notation.
+
+
+File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent
+
+9.54.3 Floating Point
+---------------------
+
+Floating-point numbers are not supported.
+
+
+File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent
+
+9.54.4 Z80 Assembler Directives
+-------------------------------
+
+`as' for the Z80 supports some additional directives for compatibility
+with other assemblers.
+
+ These are the additional directives in `as' for the Z80:
+
+`db EXPRESSION|STRING[,EXPRESSION|STRING...]'
+`defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
+ For each STRING the characters are copied to the object file, for
+ each other EXPRESSION the value is stored in one byte. A warning
+ is issued in case of an overflow.
+
+`dw EXPRESSION[,EXPRESSION...]'
+`defw EXPRESSION[,EXPRESSION...]'
+ For each EXPRESSION the value is stored in two bytes, ignoring
+ overflow.
+
+`d24 EXPRESSION[,EXPRESSION...]'
+`def24 EXPRESSION[,EXPRESSION...]'
+ For each EXPRESSION the value is stored in three bytes, ignoring
+ overflow.
+
+`d32 EXPRESSION[,EXPRESSION...]'
+`def32 EXPRESSION[,EXPRESSION...]'
+ For each EXPRESSION the value is stored in four bytes, ignoring
+ overflow.
+
+`ds COUNT[, VALUE]'
+`defs COUNT[, VALUE]'
+ Fill COUNT bytes in the object file with VALUE, if VALUE is
+ omitted it defaults to zero.
+
+`SYMBOL equ EXPRESSION'
+`SYMBOL defl EXPRESSION'
+ These directives set the value of SYMBOL to EXPRESSION. If `equ'
+ is used, it is an error if SYMBOL is already defined. Symbols
+ defined with `equ' are not protected from redefinition.
+
+`set'
+ This is a normal instruction on Z80, and not an assembler
+ directive.
+
+`psect NAME'
+ A synonym for *Note Section::, no second argument should be given.
+
+
+
+File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent
+
+9.54.5 Opcodes
+--------------
+
+In line with common practice, Z80 mnemonics are used for both the Z80
+and the R800.
+
+ In many instructions it is possible to use one of the half index
+registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general
+purpose register. This yields instructions that are documented on the
+R800 and undocumented on the Z80. Similarly `in f,(c)' is documented
+on the R800 and undocumented on the Z80.
+
+ The assembler also supports the following undocumented
+Z80-instructions, that have not been adopted in the R800 instruction
+set:
+`out (c),0'
+ Sends zero to the port pointed to by register c.
+
+`sli M'
+ Equivalent to `M = (M<<1)+1', the operand M can be any operand
+ that is valid for `sla'. One can use `sll' as a synonym for `sli'.
+
+`OP (ix+D), R'
+ This is equivalent to
+
+ ld R, (ix+D)
+ OPC R
+ ld (ix+D), R
+
+ The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc',
+ `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R'
+ may be any of `a', `b', `c', `d', `e', `h' and `l'.
+
+`OPC (iy+D), R'
+ As above, but with `iy' instead of `ix'.
+
+ The web site at `http://www.z80.info' is a good starting place to
+find more information on programming the Z80.
+
+
+File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies
+
+9.55 Z8000 Dependent Features
+=============================
+
+ The Z8000 as supports both members of the Z8000 family: the
+unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
+24 bit addresses.
+
+ When the assembler is in unsegmented mode (specified with the
+`unsegm' directive), an address takes up one word (16 bit) sized
+register. When the assembler is in segmented mode (specified with the
+`segm' directive), a 24-bit address takes up a long (32 bit) register.
+*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
+of other Z8000 specific assembler directives.
+
+* Menu:
+
+* Z8000 Options:: Command-line options for the Z8000
+* Z8000 Syntax:: Assembler syntax for the Z8000
+* Z8000 Directives:: Special directives for the Z8000
+* Z8000 Opcodes:: Opcodes
+
+
+File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
+
+9.55.1 Options
+--------------
+
+`-z8001'
+ Generate segmented code by default.
+
+`-z8002'
+ Generate unsegmented code by default.
+
+
+File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
+
+9.55.2 Syntax
+-------------
+
+* Menu:
+
+* Z8000-Chars:: Special Characters
+* Z8000-Regs:: Register Names
+* Z8000-Addressing:: Addressing Modes
+
+
+File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
+
+9.55.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+ If a `#' appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be a
+logical line number directive (*note Comments::) or a preprocessor
+control command (*note Preprocessing::).
+
+ You can use `;' instead of a newline to separate statements.
+
+
+File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
+
+9.55.2.2 Register Names
+.......................
+
+The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
+to different sized groups of registers by register number, with the
+prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
+64 bit registers. You can also refer to the contents of the first
+eight (of the sixteen 16 bit registers) by bytes. They are named `rlN'
+and `rhN'.
+
+_byte registers_
+ rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
+ rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
+
+_word registers_
+ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
+
+_long word registers_
+ rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
+
+_quad word registers_
+ rq0 rq4 rq8 rq12
+
+
+File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
+
+9.55.2.3 Addressing Modes
+.........................
+
+as understands the following addressing modes for the Z8000:
+
+`rlN'
+`rhN'
+`rN'
+`rrN'
+`rqN'
+ Register direct: 8bit, 16bit, 32bit, and 64bit registers.
+
+`@rN'
+`@rrN'
+ Indirect register: @rrN in segmented mode, @rN in unsegmented
+ mode.
+
+`ADDR'
+ Direct: the 16 bit or 24 bit address (depending on whether the
+ assembler is in segmented or unsegmented mode) of the operand is
+ in the instruction.
+
+`address(rN)'
+ Indexed: the 16 or 24 bit address is added to the 16 bit register
+ to produce the final address in memory of the operand.
+
+`rN(#IMM)'
+`rrN(#IMM)'
+ Base Address: the 16 or 24 bit register is added to the 16 bit sign
+ extended immediate displacement to produce the final address in
+ memory of the operand.
+
+`rN(rM)'
+`rrN(rM)'
+ Base Index: the 16 or 24 bit register rN or rrN is added to the
+ sign extended 16 bit index register rM to produce the final
+ address in memory of the operand.
+
+`#XX'
+ Immediate data XX.
+
+
+File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
+
+9.55.3 Assembler Directives for the Z8000
+-----------------------------------------
+
+The Z8000 port of as includes additional assembler directives, for
+compatibility with other Z8000 assemblers. These do not begin with `.'
+(unlike the ordinary as directives).
+
+`segm'
+`.z8001'
+ Generate code for the segmented Z8001.
+
+`unsegm'
+`.z8002'
+ Generate code for the unsegmented Z8002.
+
+`name'
+ Synonym for `.file'
+
+`global'
+ Synonym for `.global'
+
+`wval'
+ Synonym for `.word'
+
+`lval'
+ Synonym for `.long'
+
+`bval'
+ Synonym for `.byte'
+
+`sval'
+ Assemble a string. `sval' expects one string literal, delimited by
+ single quotes. It assembles each byte of the string into
+ consecutive addresses. You can use the escape sequence `%XX'
+ (where XX represents a two-digit hexadecimal number) to represent
+ the character whose ASCII value is XX. Use this feature to
+ describe single quote and other characters that may not appear in
+ string literals as themselves. For example, the C statement
+ `char *a = "he said \"it's 50% off\"";' is represented in Z8000
+ assembly language (shown with the assembler output in hex at the
+ left) as
+
+ 68652073 sval 'he said %22it%27s 50%25 off%22%00'
+ 61696420
+ 22697427
+ 73203530
+ 25206F66
+ 662200
+
+`rsect'
+ synonym for `.section'
+
+`block'
+ synonym for `.space'
+
+`even'
+ special case of `.align'; aligns output to even byte boundary.
+
+
+File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
+
+9.55.4 Opcodes
+--------------
+
+For detailed information on the Z8000 machine instruction set, see
+`Z8000 Technical Manual'.
+
+ The following table summarizes the opcodes and their arguments:
+
+ rs 16 bit source register
+ rd 16 bit destination register
+ rbs 8 bit source register
+ rbd 8 bit destination register
+ rrs 32 bit source register
+ rrd 32 bit destination register
+ rqs 64 bit source register
+ rqd 64 bit destination register
+ addr 16/24 bit address
+ imm immediate data
+
+ adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
+ adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
+ add rd,@rs clrb rbd dab rbd
+ add rd,addr com @rd dbjnz rbd,disp7
+ add rd,addr(rs) com addr dec @rd,imm4m1
+ add rd,imm16 com addr(rd) dec addr(rd),imm4m1
+ add rd,rs com rd dec addr,imm4m1
+ addb rbd,@rs comb @rd dec rd,imm4m1
+ addb rbd,addr comb addr decb @rd,imm4m1
+ addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
+ addb rbd,imm8 comb rbd decb addr,imm4m1
+ addb rbd,rbs comflg flags decb rbd,imm4m1
+ addl rrd,@rs cp @rd,imm16 di i2
+ addl rrd,addr cp addr(rd),imm16 div rrd,@rs
+ addl rrd,addr(rs) cp addr,imm16 div rrd,addr
+ addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
+ addl rrd,rrs cp rd,addr div rrd,imm16
+ and rd,@rs cp rd,addr(rs) div rrd,rs
+ and rd,addr cp rd,imm16 divl rqd,@rs
+ and rd,addr(rs) cp rd,rs divl rqd,addr
+ and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
+ and rd,rs cpb addr(rd),imm8 divl rqd,imm32
+ andb rbd,@rs cpb addr,imm8 divl rqd,rrs
+ andb rbd,addr cpb rbd,@rs djnz rd,disp7
+ andb rbd,addr(rs) cpb rbd,addr ei i2
+ andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
+ andb rbd,rbs cpb rbd,imm8 ex rd,addr
+ bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
+ bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
+ bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
+ bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
+ bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
+ bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
+ bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
+ bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
+ bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
+ bitb rbd,rs cpl rrd,@rs ext8f imm8
+ bpt cpl rrd,addr exts rrd
+ call @rd cpl rrd,addr(rs) extsb rd
+ call addr cpl rrd,imm32 extsl rqd
+ call addr(rd) cpl rrd,rrs halt
+ calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
+ clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
+ clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
+ clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
+ clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
+ clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
+ inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
+ inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
+ incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
+ incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
+ incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
+ incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
+ ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
+ indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
+ inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
+ inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
+ iret ldib @rd,@rs,rr neg addr(rd)
+ jp cc,@rd ldir @rd,@rs,rr neg rd
+ jp cc,addr ldirb @rd,@rs,rr negb @rd
+ jp cc,addr(rd) ldk rd,imm4 negb addr
+ jr cc,disp8 ldl @rd,rrs negb addr(rd)
+ ld @rd,imm16 ldl addr(rd),rrs negb rbd
+ ld @rd,rs ldl addr,rrs nop
+ ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
+ ld addr(rd),rs ldl rd(rx),rrs or rd,addr
+ ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
+ ld addr,rs ldl rrd,addr or rd,imm16
+ ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
+ ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
+ ld rd,@rs ldl rrd,rrs orb rbd,addr
+ ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
+ ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
+ ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
+ ld rd,rs ldm addr(rd),rs,n out @rd,rs
+ ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
+ ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
+ lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
+ lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
+ lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
+ lda rd,rs(rx) ldps addr outib @rd,@rs,ra
+ ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
+ ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
+ ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
+ ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
+ ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
+ ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
+ ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
+ ldb rbd,@rs mbit popl addr,@rs
+ ldb rbd,addr mreq rd popl rrd,@rs
+ ldb rbd,addr(rs) mres push @rd,@rs
+ ldb rbd,imm8 mset push @rd,addr
+ ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
+ ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
+ push @rd,rs set addr,imm4 subl rrd,imm32
+ pushl @rd,@rs set rd,imm4 subl rrd,rrs
+ pushl @rd,addr set rd,rs tcc cc,rd
+ pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
+ pushl @rd,rrs setb addr(rd),imm4 test @rd
+ res @rd,imm4 setb addr,imm4 test addr
+ res addr(rd),imm4 setb rbd,imm4 test addr(rd)
+ res addr,imm4 setb rbd,rs test rd
+ res rd,imm4 setflg imm4 testb @rd
+ res rd,rs sinb rbd,imm16 testb addr
+ resb @rd,imm4 sinb rd,imm16 testb addr(rd)
+ resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
+ resb addr,imm4 sindb @rd,@rs,rba testl @rd
+ resb rbd,imm4 sinib @rd,@rs,ra testl addr
+ resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
+ resflg imm4 sla rd,imm8 testl rrd
+ ret cc slab rbd,imm8 trdb @rd,@rs,rba
+ rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
+ rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
+ rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
+ rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
+ rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
+ rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
+ rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
+ rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
+ rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
+ rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
+ rsvd36 sra rd,imm8 tset rd
+ rsvd38 srab rbd,imm8 tsetb @rd
+ rsvd78 sral rrd,imm8 tsetb addr
+ rsvd7e srl rd,imm8 tsetb addr(rd)
+ rsvd9d srlb rbd,imm8 tsetb rbd
+ rsvd9f srll rrd,imm8 xor rd,@rs
+ rsvdb9 sub rd,@rs xor rd,addr
+ rsvdbf sub rd,addr xor rd,addr(rs)
+ sbc rd,rs sub rd,addr(rs) xor rd,imm16
+ sbcb rbd,rbs sub rd,imm16 xor rd,rs
+ sc imm8 sub rd,rs xorb rbd,@rs
+ sda rd,rs subb rbd,@rs xorb rbd,addr
+ sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
+ sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
+ sdl rd,rs subb rbd,imm8 xorb rbd,rbs
+ sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
+ sdll rrd,rs subl rrd,@rs
+ set @rd,imm4 subl rrd,addr
+ set addr(rd),imm4 subl rrd,addr(rs)
+
+
+File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
+
+10 Reporting Bugs
+*****************
+
+Your bug reports play an essential role in making `as' reliable.
+
+ Reporting a bug may help you by bringing a solution to your problem,
+or it may not. But in any case the principal function of a bug report
+is to help the entire community by making the next version of `as' work
+better. Bug reports are your contribution to the maintenance of `as'.
+
+ In order for a bug report to serve its purpose, you must include the
+information that enables us to fix the bug.
+
+* Menu:
+
+* Bug Criteria:: Have you found a bug?
+* Bug Reporting:: How to report bugs
+
+
+File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
+
+10.1 Have You Found a Bug?
+==========================
+
+If you are not sure whether you have found a bug, here are some
+guidelines:
+
+ * If the assembler gets a fatal signal, for any input whatever, that
+ is a `as' bug. Reliable assemblers never crash.
+
+ * If `as' produces an error message for valid input, that is a bug.
+
+ * If `as' does not produce an error message for invalid input, that
+ is a bug. However, you should note that your idea of "invalid
+ input" might be our idea of "an extension" or "support for
+ traditional practice".
+
+ * If you are an experienced user of assemblers, your suggestions for
+ improvement of `as' are welcome in any case.
+
+
+File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs
+
+10.2 How to Report Bugs
+=======================
+
+A number of companies and individuals offer support for GNU products.
+If you obtained `as' from a support organization, we recommend you
+contact that organization first.
+
+ You can find contact information for many support companies and
+individuals in the file `etc/SERVICE' in the GNU Emacs distribution.
+
+ In any event, we also recommend that you send bug reports for `as'
+to `http://www.sourceware.org/bugzilla/'.
+
+ The fundamental principle of reporting bugs usefully is this:
+*report all the facts*. If you are not sure whether to state a fact or
+leave it out, state it!
+
+ Often people omit facts because they think they know what causes the
+problem and assume that some details do not matter. Thus, you might
+assume that the name of a symbol you use in an example does not matter.
+Well, probably it does not, but one cannot be sure. Perhaps the bug
+is a stray memory reference which happens to fetch from the location
+where that name is stored in memory; perhaps, if the name were
+different, the contents of that location would fool the assembler into
+doing the right thing despite the bug. Play it safe and give a
+specific, complete example. That is the easiest thing for you to do,
+and the most helpful.
+
+ Keep in mind that the purpose of a bug report is to enable us to fix
+the bug if it is new to us. Therefore, always write your bug reports
+on the assumption that the bug has not been reported previously.
+
+ Sometimes people give a few sketchy facts and ask, "Does this ring a
+bell?" This cannot help us fix a bug, so it is basically useless. We
+respond by asking for enough details to enable us to investigate. You
+might as well expedite matters by sending them to begin with.
+
+ To enable us to fix the bug, you should include all these things:
+
+ * The version of `as'. `as' announces it if you start it with the
+ `--version' argument.
+
+ Without this, we will not know whether there is any point in
+ looking for the bug in the current version of `as'.
+
+ * Any patches you may have applied to the `as' source.
+
+ * The type of machine you are using, and the operating system name
+ and version number.
+
+ * What compiler (and its version) was used to compile `as'--e.g.
+ "`gcc-2.7'".
+
+ * The command arguments you gave the assembler to assemble your
+ example and observe the bug. To guarantee you will not omit
+ something important, list them all. A copy of the Makefile (or
+ the output from make) is sufficient.
+
+ If we were to try to guess the arguments, we would probably guess
+ wrong and then we might not encounter the bug.
+
+ * A complete input file that will reproduce the bug. If the bug is
+ observed when the assembler is invoked via a compiler, send the
+ assembler source, not the high level language source. Most
+ compilers will produce the assembler source when run with the `-S'
+ option. If you are using `gcc', use the options `-v
+ --save-temps'; this will save the assembler source in a file with
+ an extension of `.s', and also show you exactly how `as' is being
+ run.
+
+ * A description of what behavior you observe that you believe is
+ incorrect. For example, "It gets a fatal signal."
+
+ Of course, if the bug is that `as' gets a fatal signal, then we
+ will certainly notice it. But if the bug is incorrect output, we
+ might not notice unless it is glaringly wrong. You might as well
+ not give us a chance to make a mistake.
+
+ Even if the problem you experience is a fatal signal, you should
+ still say so explicitly. Suppose something strange is going on,
+ such as, your copy of `as' is out of sync, or you have encountered
+ a bug in the C library on your system. (This has happened!) Your
+ copy might crash and ours would not. If you told us to expect a
+ crash, then when ours fails to crash, we would know that the bug
+ was not happening for us. If you had not told us to expect a
+ crash, then we would not be able to draw any conclusion from our
+ observations.
+
+ * If you wish to suggest changes to the `as' source, send us context
+ diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
+ Always send diffs from the old file to the new file. If you even
+ discuss something in the `as' source, refer to it by context, not
+ by line number.
+
+ The line numbers in our development sources will not match those
+ in your sources. Your line numbers would convey no useful
+ information to us.
+
+ Here are some things that are not necessary:
+
+ * A description of the envelope of the bug.
+
+ Often people who encounter a bug spend a lot of time investigating
+ which changes to the input file will make the bug go away and which
+ changes will not affect it.
+
+ This is often time consuming and not very useful, because the way
+ we will find the bug is by running a single example under the
+ debugger with breakpoints, not by pure deduction from a series of
+ examples. We recommend that you save your time for something else.
+
+ Of course, if you can find a simpler example to report _instead_
+ of the original one, that is a convenience for us. Errors in the
+ output will be easier to spot, running under the debugger will take
+ less time, and so on.
+
+ However, simplification is not vital; if you do not want to do
+ this, report the bug anyway and send us the entire test case you
+ used.
+
+ * A patch for the bug.
+
+ A patch for the bug does help us if it is a good one. But do not
+ omit the necessary information, such as the test case, on the
+ assumption that a patch is all we need. We might see problems
+ with your patch and decide to fix the problem another way, or we
+ might not understand it at all.
+
+ Sometimes with a program as complicated as `as' it is very hard to
+ construct an example that will make the program follow a certain
+ path through the code. If you do not send us the example, we will
+ not be able to construct one, so we will not be able to verify
+ that the bug is fixed.
+
+ And if we cannot understand what bug you are trying to fix, or why
+ your patch should be an improvement, we will not install it. A
+ test case will help us to understand.
+
+ * A guess about what the bug is or what it depends on.
+
+ Such guesses are usually wrong. Even we cannot guess right about
+ such things without first using the debugger to find the facts.
+
+
+File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top
+
+11 Acknowledgements
+*******************
+
+If you have contributed to GAS and your name isn't listed here, it is
+not meant as a slight. We just don't know about it. Send mail to the
+maintainer, and we'll correct the situation. Currently the maintainer
+is Nick Clifton (email address `nickc@redhat.com').
+
+ Dean Elsner wrote the original GNU assembler for the VAX.(1)
+
+ Jay Fenlason maintained GAS for a while, adding support for
+GDB-specific debug information and the 68k series machines, most of the
+preprocessing pass, and extensive changes in `messages.c',
+`input-file.c', `write.c'.
+
+ K. Richard Pixley maintained GAS for a while, adding various
+enhancements and many bug fixes, including merging support for several
+processors, breaking GAS up to handle multiple object file format back
+ends (including heavy rewrite, testing, an integration of the coff and
+b.out back ends), adding configuration including heavy testing and
+verification of cross assemblers and file splits and renaming,
+converted GAS to strictly ANSI C including full prototypes, added
+support for m680[34]0 and cpu32, did considerable work on i960
+including a COFF port (including considerable amounts of reverse
+engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
+hp300hpux host ports, updated "know" assertions and made them work,
+much other reorganization, cleanup, and lint.
+
+ Ken Raeburn wrote the high-level BFD interface code to replace most
+of the code in format-specific I/O modules.
+
+ The original VMS support was contributed by David L. Kashtan. Eric
+Youngdale has done much work with it since.
+
+ The Intel 80386 machine description was written by Eliot Dresselhaus.
+
+ Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
+
+ The Motorola 88k machine description was contributed by Devon Bowen
+of Buffalo University and Torbjorn Granlund of the Swedish Institute of
+Computer Science.
+
+ Keith Knowles at the Open Software Foundation wrote the original
+MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
+support (which hasn't been merged in yet). Ralph Campbell worked with
+the MIPS code to support a.out format.
+
+ Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
+tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
+Steve Chamberlain of Cygnus Support. Steve also modified the COFF back
+end to use BFD for some low-level operations, for use with the H8/300
+and AMD 29k targets.
+
+ John Gilmore built the AMD 29000 support, added `.include' support,
+and simplified the configuration of which versions accept which
+directives. He updated the 68k machine description so that Motorola's
+opcodes always produced fixed-size instructions (e.g., `jsr'), while
+synthetic instructions remained shrinkable (`jbsr'). John fixed many
+bugs, including true tested cross-compilation support, and one bug in
+relaxation that took a week and required the proverbial one-bit fix.
+
+ Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
+syntax for the 68k, completed support for some COFF targets (68k, i386
+SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
+wrote the initial RS/6000 and PowerPC assembler, and made a few other
+minor patches.
+
+ Steve Chamberlain made GAS able to generate listings.
+
+ Hewlett-Packard contributed support for the HP9000/300.
+
+ Jeff Law wrote GAS and BFD support for the native HPPA object format
+(SOM) along with a fairly extensive HPPA testsuite (for both SOM and
+ELF object formats). This work was supported by both the Center for
+Software Science at the University of Utah and Cygnus Support.
+
+ Support for ELF format files has been worked on by Mark Eichin of
+Cygnus Support (original, incomplete implementation for SPARC), Pete
+Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
+Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
+Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
+
+ Linas Vepstas added GAS support for the ESA/390 "IBM 370"
+architecture.
+
+ Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
+GAS and BFD support for openVMS/Alpha.
+
+ Timothy Wall, Michael Hayes, and Greg Smart contributed to the
+various tic* flavors.
+
+ David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
+Tensilica, Inc. added support for Xtensa processors.
+
+ Several engineers at Cygnus Support have also provided many small
+bug fixes and configuration enhancements.
+
+ Jon Beniston added support for the Lattice Mico32 architecture.
+
+ Many others have contributed large or small bugfixes and
+enhancements. If you have contributed significant work and are not
+mentioned on this list, and want to be, let us know. Some of the
+history has been lost; we are not intentionally leaving anyone out.
+
+ ---------- Footnotes ----------
+
+ (1) Any more details?
+
+
+File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top
+
+Appendix A GNU Free Documentation License
+*****************************************
+
+ Version 1.3, 3 November 2008
+
+ Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
+ `http://fsf.org/'
+
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ 0. PREAMBLE
+
+ The purpose of this License is to make a manual, textbook, or other
+ functional and useful document "free" in the sense of freedom: to
+ assure everyone the effective freedom to copy and redistribute it,
+ with or without modifying it, either commercially or
+ noncommercially. Secondarily, this License preserves for the
+ author and publisher a way to get credit for their work, while not
+ being considered responsible for modifications made by others.
+
+ This License is a kind of "copyleft", which means that derivative
+ works of the document must themselves be free in the same sense.
+ It complements the GNU General Public License, which is a copyleft
+ license designed for free software.
+
+ We have designed this License in order to use it for manuals for
+ free software, because free software needs free documentation: a
+ free program should come with manuals providing the same freedoms
+ that the software does. But this License is not limited to
+ software manuals; it can be used for any textual work, regardless
+ of subject matter or whether it is published as a printed book.
+ We recommend this License principally for works whose purpose is
+ instruction or reference.
+
+ 1. APPLICABILITY AND DEFINITIONS
+
+ This License applies to any manual or other work, in any medium,
+ that contains a notice placed by the copyright holder saying it
+ can be distributed under the terms of this License. Such a notice
+ grants a world-wide, royalty-free license, unlimited in duration,
+ to use that work under the conditions stated herein. The
+ "Document", below, refers to any such manual or work. Any member
+ of the public is a licensee, and is addressed as "you". You
+ accept the license if you copy, modify or distribute the work in a
+ way requiring permission under copyright law.
+
+ A "Modified Version" of the Document means any work containing the
+ Document or a portion of it, either copied verbatim, or with
+ modifications and/or translated into another language.
+
+ A "Secondary Section" is a named appendix or a front-matter section
+ of the Document that deals exclusively with the relationship of the
+ publishers or authors of the Document to the Document's overall
+ subject (or to related matters) and contains nothing that could
+ fall directly within that overall subject. (Thus, if the Document
+ is in part a textbook of mathematics, a Secondary Section may not
+ explain any mathematics.) The relationship could be a matter of
+ historical connection with the subject or with related matters, or
+ of legal, commercial, philosophical, ethical or political position
+ regarding them.
+
+ The "Invariant Sections" are certain Secondary Sections whose
+ titles are designated, as being those of Invariant Sections, in
+ the notice that says that the Document is released under this
+ License. If a section does not fit the above definition of
+ Secondary then it is not allowed to be designated as Invariant.
+ The Document may contain zero Invariant Sections. If the Document
+ does not identify any Invariant Sections then there are none.
+
+ The "Cover Texts" are certain short passages of text that are
+ listed, as Front-Cover Texts or Back-Cover Texts, in the notice
+ that says that the Document is released under this License. A
+ Front-Cover Text may be at most 5 words, and a Back-Cover Text may
+ be at most 25 words.
+
+ A "Transparent" copy of the Document means a machine-readable copy,
+ represented in a format whose specification is available to the
+ general public, that is suitable for revising the document
+ straightforwardly with generic text editors or (for images
+ composed of pixels) generic paint programs or (for drawings) some
+ widely available drawing editor, and that is suitable for input to
+ text formatters or for automatic translation to a variety of
+ formats suitable for input to text formatters. A copy made in an
+ otherwise Transparent file format whose markup, or absence of
+ markup, has been arranged to thwart or discourage subsequent
+ modification by readers is not Transparent. An image format is
+ not Transparent if used for any substantial amount of text. A
+ copy that is not "Transparent" is called "Opaque".
+
+ Examples of suitable formats for Transparent copies include plain
+ ASCII without markup, Texinfo input format, LaTeX input format,
+ SGML or XML using a publicly available DTD, and
+ standard-conforming simple HTML, PostScript or PDF designed for
+ human modification. Examples of transparent image formats include
+ PNG, XCF and JPG. Opaque formats include proprietary formats that
+ can be read and edited only by proprietary word processors, SGML or
+ XML for which the DTD and/or processing tools are not generally
+ available, and the machine-generated HTML, PostScript or PDF
+ produced by some word processors for output purposes only.
+
+ The "Title Page" means, for a printed book, the title page itself,
+ plus such following pages as are needed to hold, legibly, the
+ material this License requires to appear in the title page. For
+ works in formats which do not have any title page as such, "Title
+ Page" means the text near the most prominent appearance of the
+ work's title, preceding the beginning of the body of the text.
+
+ The "publisher" means any person or entity that distributes copies
+ of the Document to the public.
+
+ A section "Entitled XYZ" means a named subunit of the Document
+ whose title either is precisely XYZ or contains XYZ in parentheses
+ following text that translates XYZ in another language. (Here XYZ
+ stands for a specific section name mentioned below, such as
+ "Acknowledgements", "Dedications", "Endorsements", or "History".)
+ To "Preserve the Title" of such a section when you modify the
+ Document means that it remains a section "Entitled XYZ" according
+ to this definition.
+
+ The Document may include Warranty Disclaimers next to the notice
+ which states that this License applies to the Document. These
+ Warranty Disclaimers are considered to be included by reference in
+ this License, but only as regards disclaiming warranties: any other
+ implication that these Warranty Disclaimers may have is void and
+ has no effect on the meaning of this License.
+
+ 2. VERBATIM COPYING
+
+ You may copy and distribute the Document in any medium, either
+ commercially or noncommercially, provided that this License, the
+ copyright notices, and the license notice saying this License
+ applies to the Document are reproduced in all copies, and that you
+ add no other conditions whatsoever to those of this License. You
+ may not use technical measures to obstruct or control the reading
+ or further copying of the copies you make or distribute. However,
+ you may accept compensation in exchange for copies. If you
+ distribute a large enough number of copies you must also follow
+ the conditions in section 3.
+
+ You may also lend copies, under the same conditions stated above,
+ and you may publicly display copies.
+
+ 3. COPYING IN QUANTITY
+
+ If you publish printed copies (or copies in media that commonly
+ have printed covers) of the Document, numbering more than 100, and
+ the Document's license notice requires Cover Texts, you must
+ enclose the copies in covers that carry, clearly and legibly, all
+ these Cover Texts: Front-Cover Texts on the front cover, and
+ Back-Cover Texts on the back cover. Both covers must also clearly
+ and legibly identify you as the publisher of these copies. The
+ front cover must present the full title with all words of the
+ title equally prominent and visible. You may add other material
+ on the covers in addition. Copying with changes limited to the
+ covers, as long as they preserve the title of the Document and
+ satisfy these conditions, can be treated as verbatim copying in
+ other respects.
+
+ If the required texts for either cover are too voluminous to fit
+ legibly, you should put the first ones listed (as many as fit
+ reasonably) on the actual cover, and continue the rest onto
+ adjacent pages.
+
+ If you publish or distribute Opaque copies of the Document
+ numbering more than 100, you must either include a
+ machine-readable Transparent copy along with each Opaque copy, or
+ state in or with each Opaque copy a computer-network location from
+ which the general network-using public has access to download
+ using public-standard network protocols a complete Transparent
+ copy of the Document, free of added material. If you use the
+ latter option, you must take reasonably prudent steps, when you
+ begin distribution of Opaque copies in quantity, to ensure that
+ this Transparent copy will remain thus accessible at the stated
+ location until at least one year after the last time you
+ distribute an Opaque copy (directly or through your agents or
+ retailers) of that edition to the public.
+
+ It is requested, but not required, that you contact the authors of
+ the Document well before redistributing any large number of
+ copies, to give them a chance to provide you with an updated
+ version of the Document.
+
+ 4. MODIFICATIONS
+
+ You may copy and distribute a Modified Version of the Document
+ under the conditions of sections 2 and 3 above, provided that you
+ release the Modified Version under precisely this License, with
+ the Modified Version filling the role of the Document, thus
+ licensing distribution and modification of the Modified Version to
+ whoever possesses a copy of it. In addition, you must do these
+ things in the Modified Version:
+
+ A. Use in the Title Page (and on the covers, if any) a title
+ distinct from that of the Document, and from those of
+ previous versions (which should, if there were any, be listed
+ in the History section of the Document). You may use the
+ same title as a previous version if the original publisher of
+ that version gives permission.
+
+ B. List on the Title Page, as authors, one or more persons or
+ entities responsible for authorship of the modifications in
+ the Modified Version, together with at least five of the
+ principal authors of the Document (all of its principal
+ authors, if it has fewer than five), unless they release you
+ from this requirement.
+
+ C. State on the Title page the name of the publisher of the
+ Modified Version, as the publisher.
+
+ D. Preserve all the copyright notices of the Document.
+
+ E. Add an appropriate copyright notice for your modifications
+ adjacent to the other copyright notices.
+
+ F. Include, immediately after the copyright notices, a license
+ notice giving the public permission to use the Modified
+ Version under the terms of this License, in the form shown in
+ the Addendum below.
+
+ G. Preserve in that license notice the full lists of Invariant
+ Sections and required Cover Texts given in the Document's
+ license notice.
+
+ H. Include an unaltered copy of this License.
+
+ I. Preserve the section Entitled "History", Preserve its Title,
+ and add to it an item stating at least the title, year, new
+ authors, and publisher of the Modified Version as given on
+ the Title Page. If there is no section Entitled "History" in
+ the Document, create one stating the title, year, authors,
+ and publisher of the Document as given on its Title Page,
+ then add an item describing the Modified Version as stated in
+ the previous sentence.
+
+ J. Preserve the network location, if any, given in the Document
+ for public access to a Transparent copy of the Document, and
+ likewise the network locations given in the Document for
+ previous versions it was based on. These may be placed in
+ the "History" section. You may omit a network location for a
+ work that was published at least four years before the
+ Document itself, or if the original publisher of the version
+ it refers to gives permission.
+
+ K. For any section Entitled "Acknowledgements" or "Dedications",
+ Preserve the Title of the section, and preserve in the
+ section all the substance and tone of each of the contributor
+ acknowledgements and/or dedications given therein.
+
+ L. Preserve all the Invariant Sections of the Document,
+ unaltered in their text and in their titles. Section numbers
+ or the equivalent are not considered part of the section
+ titles.
+
+ M. Delete any section Entitled "Endorsements". Such a section
+ may not be included in the Modified Version.
+
+ N. Do not retitle any existing section to be Entitled
+ "Endorsements" or to conflict in title with any Invariant
+ Section.
+
+ O. Preserve any Warranty Disclaimers.
+
+ If the Modified Version includes new front-matter sections or
+ appendices that qualify as Secondary Sections and contain no
+ material copied from the Document, you may at your option
+ designate some or all of these sections as invariant. To do this,
+ add their titles to the list of Invariant Sections in the Modified
+ Version's license notice. These titles must be distinct from any
+ other section titles.
+
+ You may add a section Entitled "Endorsements", provided it contains
+ nothing but endorsements of your Modified Version by various
+ parties--for example, statements of peer review or that the text
+ has been approved by an organization as the authoritative
+ definition of a standard.
+
+ You may add a passage of up to five words as a Front-Cover Text,
+ and a passage of up to 25 words as a Back-Cover Text, to the end
+ of the list of Cover Texts in the Modified Version. Only one
+ passage of Front-Cover Text and one of Back-Cover Text may be
+ added by (or through arrangements made by) any one entity. If the
+ Document already includes a cover text for the same cover,
+ previously added by you or by arrangement made by the same entity
+ you are acting on behalf of, you may not add another; but you may
+ replace the old one, on explicit permission from the previous
+ publisher that added the old one.
+
+ The author(s) and publisher(s) of the Document do not by this
+ License give permission to use their names for publicity for or to
+ assert or imply endorsement of any Modified Version.
+
+ 5. COMBINING DOCUMENTS
+
+ You may combine the Document with other documents released under
+ this License, under the terms defined in section 4 above for
+ modified versions, provided that you include in the combination
+ all of the Invariant Sections of all of the original documents,
+ unmodified, and list them all as Invariant Sections of your
+ combined work in its license notice, and that you preserve all
+ their Warranty Disclaimers.
+
+ The combined work need only contain one copy of this License, and
+ multiple identical Invariant Sections may be replaced with a single
+ copy. If there are multiple Invariant Sections with the same name
+ but different contents, make the title of each such section unique
+ by adding at the end of it, in parentheses, the name of the
+ original author or publisher of that section if known, or else a
+ unique number. Make the same adjustment to the section titles in
+ the list of Invariant Sections in the license notice of the
+ combined work.
+
+ In the combination, you must combine any sections Entitled
+ "History" in the various original documents, forming one section
+ Entitled "History"; likewise combine any sections Entitled
+ "Acknowledgements", and any sections Entitled "Dedications". You
+ must delete all sections Entitled "Endorsements."
+
+ 6. COLLECTIONS OF DOCUMENTS
+
+ You may make a collection consisting of the Document and other
+ documents released under this License, and replace the individual
+ copies of this License in the various documents with a single copy
+ that is included in the collection, provided that you follow the
+ rules of this License for verbatim copying of each of the
+ documents in all other respects.
+
+ You may extract a single document from such a collection, and
+ distribute it individually under this License, provided you insert
+ a copy of this License into the extracted document, and follow
+ this License in all other respects regarding verbatim copying of
+ that document.
+
+ 7. AGGREGATION WITH INDEPENDENT WORKS
+
+ A compilation of the Document or its derivatives with other
+ separate and independent documents or works, in or on a volume of
+ a storage or distribution medium, is called an "aggregate" if the
+ copyright resulting from the compilation is not used to limit the
+ legal rights of the compilation's users beyond what the individual
+ works permit. When the Document is included in an aggregate, this
+ License does not apply to the other works in the aggregate which
+ are not themselves derivative works of the Document.
+
+ If the Cover Text requirement of section 3 is applicable to these
+ copies of the Document, then if the Document is less than one half
+ of the entire aggregate, the Document's Cover Texts may be placed
+ on covers that bracket the Document within the aggregate, or the
+ electronic equivalent of covers if the Document is in electronic
+ form. Otherwise they must appear on printed covers that bracket
+ the whole aggregate.
+
+ 8. TRANSLATION
+
+ Translation is considered a kind of modification, so you may
+ distribute translations of the Document under the terms of section
+ 4. Replacing Invariant Sections with translations requires special
+ permission from their copyright holders, but you may include
+ translations of some or all Invariant Sections in addition to the
+ original versions of these Invariant Sections. You may include a
+ translation of this License, and all the license notices in the
+ Document, and any Warranty Disclaimers, provided that you also
+ include the original English version of this License and the
+ original versions of those notices and disclaimers. In case of a
+ disagreement between the translation and the original version of
+ this License or a notice or disclaimer, the original version will
+ prevail.
+
+ If a section in the Document is Entitled "Acknowledgements",
+ "Dedications", or "History", the requirement (section 4) to
+ Preserve its Title (section 1) will typically require changing the
+ actual title.
+
+ 9. TERMINATION
+
+ You may not copy, modify, sublicense, or distribute the Document
+ except as expressly provided under this License. Any attempt
+ otherwise to copy, modify, sublicense, or distribute it is void,
+ and will automatically terminate your rights under this License.
+
+ However, if you cease all violation of this License, then your
+ license from a particular copyright holder is reinstated (a)
+ provisionally, unless and until the copyright holder explicitly
+ and finally terminates your license, and (b) permanently, if the
+ copyright holder fails to notify you of the violation by some
+ reasonable means prior to 60 days after the cessation.
+
+ Moreover, your license from a particular copyright holder is
+ reinstated permanently if the copyright holder notifies you of the
+ violation by some reasonable means, this is the first time you have
+ received notice of violation of this License (for any work) from
+ that copyright holder, and you cure the violation prior to 30 days
+ after your receipt of the notice.
+
+ Termination of your rights under this section does not terminate
+ the licenses of parties who have received copies or rights from
+ you under this License. If your rights have been terminated and
+ not permanently reinstated, receipt of a copy of some or all of
+ the same material does not give you any rights to use it.
+
+ 10. FUTURE REVISIONS OF THIS LICENSE
+
+ The Free Software Foundation may publish new, revised versions of
+ the GNU Free Documentation License from time to time. Such new
+ versions will be similar in spirit to the present version, but may
+ differ in detail to address new problems or concerns. See
+ `http://www.gnu.org/copyleft/'.
+
+ Each version of the License is given a distinguishing version
+ number. If the Document specifies that a particular numbered
+ version of this License "or any later version" applies to it, you
+ have the option of following the terms and conditions either of
+ that specified version or of any later version that has been
+ published (not as a draft) by the Free Software Foundation. If
+ the Document does not specify a version number of this License,
+ you may choose any version ever published (not as a draft) by the
+ Free Software Foundation. If the Document specifies that a proxy
+ can decide which future versions of this License can be used, that
+ proxy's public statement of acceptance of a version permanently
+ authorizes you to choose that version for the Document.
+
+ 11. RELICENSING
+
+ "Massive Multiauthor Collaboration Site" (or "MMC Site") means any
+ World Wide Web server that publishes copyrightable works and also
+ provides prominent facilities for anybody to edit those works. A
+ public wiki that anybody can edit is an example of such a server.
+ A "Massive Multiauthor Collaboration" (or "MMC") contained in the
+ site means any set of copyrightable works thus published on the MMC
+ site.
+
+ "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
+ license published by Creative Commons Corporation, a not-for-profit
+ corporation with a principal place of business in San Francisco,
+ California, as well as future copyleft versions of that license
+ published by that same organization.
+
+ "Incorporate" means to publish or republish a Document, in whole or
+ in part, as part of another Document.
+
+ An MMC is "eligible for relicensing" if it is licensed under this
+ License, and if all works that were first published under this
+ License somewhere other than this MMC, and subsequently
+ incorporated in whole or in part into the MMC, (1) had no cover
+ texts or invariant sections, and (2) were thus incorporated prior
+ to November 1, 2008.
+
+ The operator of an MMC Site may republish an MMC contained in the
+ site under CC-BY-SA on the same site at any time before August 1,
+ 2009, provided the MMC is eligible for relicensing.
+
+
+ADDENDUM: How to use this License for your documents
+====================================================
+
+To use this License in a document you have written, include a copy of
+the License in the document and put the following copyright and license
+notices just after the title page:
+
+ Copyright (C) YEAR YOUR NAME.
+ Permission is granted to copy, distribute and/or modify this document
+ under the terms of the GNU Free Documentation License, Version 1.3
+ or any later version published by the Free Software Foundation;
+ with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
+ Texts. A copy of the license is included in the section entitled ``GNU
+ Free Documentation License''.
+
+ If you have Invariant Sections, Front-Cover Texts and Back-Cover
+Texts, replace the "with...Texts." line with this:
+
+ with the Invariant Sections being LIST THEIR TITLES, with
+ the Front-Cover Texts being LIST, and with the Back-Cover Texts
+ being LIST.
+
+ If you have Invariant Sections without Cover Texts, or some other
+combination of the three, merge those two alternatives to suit the
+situation.
+
+ If your document contains nontrivial examples of program code, we
+recommend releasing these examples in parallel under your choice of
+free software license, such as the GNU General Public License, to
+permit their use in free software.
+
+
+File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top
+
+AS Index
+********
+
+
+* Menu:
+
+* \" (doublequote character): Strings. (line 43)
+* \\ (\ character): Strings. (line 40)
+* \b (backspace character): Strings. (line 15)
+* \DDD (octal character code): Strings. (line 30)
+* \f (formfeed character): Strings. (line 18)
+* \n (newline character): Strings. (line 21)
+* \r (carriage return character): Strings. (line 24)
+* \t (tab): Strings. (line 27)
+* \XD... (hex character code): Strings. (line 36)
+* #: Comments. (line 33)
+* #APP: Preprocessing. (line 27)
+* #NO_APP: Preprocessing. (line 27)
+* $ in symbol names <1>: SH-Chars. (line 15)
+* $ in symbol names <2>: Meta-Chars. (line 10)
+* $ in symbol names <3>: D30V-Chars. (line 70)
+* $ in symbol names <4>: D10V-Chars. (line 53)
+* $ in symbol names: SH64-Chars. (line 15)
+* $a: ARM Mapping Symbols.
+ (line 9)
+* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10)
+* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13)
+* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16)
+* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19)
+* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22)
+* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28)
+* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25)
+* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31)
+* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34)
+* $d <1>: AArch64 Mapping Symbols.
+ (line 12)
+* $d: ARM Mapping Symbols.
+ (line 15)
+* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37)
+* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40)
+* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26)
+* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43)
+* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47)
+* $int math builtin, TIC54X: TIC54X-Builtins. (line 50)
+* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43)
+* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34)
+* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38)
+* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47)
+* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50)
+* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30)
+* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53)
+* $log math builtin, TIC54X: TIC54X-Builtins. (line 59)
+* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56)
+* $max math builtin, TIC54X: TIC54X-Builtins. (line 62)
+* $min math builtin, TIC54X: TIC54X-Builtins. (line 65)
+* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68)
+* $round math builtin, TIC54X: TIC54X-Builtins. (line 71)
+* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74)
+* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77)
+* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80)
+* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83)
+* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57)
+* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54)
+* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23)
+* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20)
+* $t: ARM Mapping Symbols.
+ (line 12)
+* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86)
+* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89)
+* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92)
+* $x: AArch64 Mapping Symbols.
+ (line 9)
+* %gp: RX-Modifiers. (line 6)
+* %gpreg: RX-Modifiers. (line 22)
+* %pidreg: RX-Modifiers. (line 25)
+* -+ option, VAX/VMS: VAX-Opts. (line 71)
+* --: Command Line. (line 10)
+* --32 option, i386: i386-Options. (line 8)
+* --32 option, x86-64: i386-Options. (line 8)
+* --64 option, i386: i386-Options. (line 8)
+* --64 option, x86-64: i386-Options. (line 8)
+* --absolute-literals: Xtensa Options. (line 40)
+* --allow-reg-prefix: SH Options. (line 9)
+* --alternate: alternate. (line 6)
+* --auto-litpools: Xtensa Options. (line 23)
+* --base-size-default-16: M68K-Opts. (line 65)
+* --base-size-default-32: M68K-Opts. (line 65)
+* --big: SH Options. (line 9)
+* --bitwise-or option, M680x0: M68K-Opts. (line 58)
+* --compress-debug-sections= option: Overview. (line 345)
+* --disp-size-default-16: M68K-Opts. (line 74)
+* --disp-size-default-32: M68K-Opts. (line 74)
+* --divide option, i386: i386-Options. (line 24)
+* --dsp: SH Options. (line 9)
+* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9)
+* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9)
+* --enforce-aligned-data: Sparc-Aligned-Data. (line 11)
+* --fatal-warnings: W. (line 16)
+* --fdpic: SH Options. (line 31)
+* --fix-v4bx command line option, ARM: ARM Options. (line 190)
+* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
+ (line 8)
+* --force-long-branches: M68HC11-Opts. (line 82)
+* --generate-example: M68HC11-Opts. (line 99)
+* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12)
+* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16)
+* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
+ (line 67)
+* --listing-cont-lines: listing. (line 34)
+* --listing-lhs-width: listing. (line 16)
+* --listing-lhs-width2: listing. (line 21)
+* --listing-rhs-width: listing. (line 28)
+* --little: SH Options. (line 9)
+* --longcalls: Xtensa Options. (line 54)
+* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34)
+* --MD: MD. (line 6)
+* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62)
+* --no-absolute-literals: Xtensa Options. (line 40)
+* --no-auto-litpools: Xtensa Options. (line 23)
+* --no-expand command line option, MMIX: MMIX-Opts. (line 31)
+* --no-longcalls: Xtensa Options. (line 54)
+* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36)
+* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62)
+* --no-pad-sections: no-pad-sections. (line 6)
+* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22)
+* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54)
+* --no-stubs command line option, MMIX: MMIX-Opts. (line 54)
+* --no-target-align: Xtensa Options. (line 47)
+* --no-text-section-literals: Xtensa Options. (line 7)
+* --no-trampolines: Xtensa Options. (line 75)
+* --no-transform: Xtensa Options. (line 63)
+* --no-underscore command line option, CRIS: CRIS-Opts. (line 15)
+* --no-warn: W. (line 11)
+* --pcrel: M68K-Opts. (line 86)
+* --pic command line option, CRIS: CRIS-Opts. (line 27)
+* --print-insn-syntax <1>: M68HC11-Opts. (line 88)
+* --print-insn-syntax: XGATE-Opts. (line 25)
+* --print-opcodes <1>: XGATE-Opts. (line 29)
+* --print-opcodes: M68HC11-Opts. (line 92)
+* --register-prefix-optional option, M680x0: M68K-Opts. (line 45)
+* --relax: SH Options. (line 9)
+* --relax command line option, MMIX: MMIX-Opts. (line 19)
+* --rename-section: Xtensa Options. (line 71)
+* --renesas: SH Options. (line 9)
+* --sectname-subst: Section. (line 81)
+* --short-branches: M68HC11-Opts. (line 67)
+* --small: SH Options. (line 9)
+* --statistics: statistics. (line 6)
+* --strict-direct-mode: M68HC11-Opts. (line 57)
+* --target-align: Xtensa Options. (line 47)
+* --text-section-literals: Xtensa Options. (line 7)
+* --traditional-format: traditional-format. (line 6)
+* --trampolines: Xtensa Options. (line 75)
+* --transform: Xtensa Options. (line 63)
+* --underscore command line option, CRIS: CRIS-Opts. (line 15)
+* --warn: W. (line 19)
+* --x32 option, i386: i386-Options. (line 8)
+* --x32 option, x86-64: i386-Options. (line 8)
+* --xgate-ramoffset: M68HC11-Opts. (line 36)
+* -1 option, VAX/VMS: VAX-Opts. (line 77)
+* -32addr command line option, Alpha: Alpha Options. (line 57)
+* -a: a. (line 6)
+* -A options, i960: Options-i960. (line 6)
+* -ac: a. (line 6)
+* -ad: a. (line 6)
+* -ag: a. (line 6)
+* -ah: a. (line 6)
+* -al: a. (line 6)
+* -Aleon: Sparc-Opts. (line 25)
+* -an: a. (line 6)
+* -as: a. (line 6)
+* -Asparc: Sparc-Opts. (line 25)
+* -Asparcfmaf: Sparc-Opts. (line 25)
+* -Asparcima: Sparc-Opts. (line 25)
+* -Asparclet: Sparc-Opts. (line 25)
+* -Asparclite: Sparc-Opts. (line 25)
+* -Asparcvis: Sparc-Opts. (line 25)
+* -Asparcvis2: Sparc-Opts. (line 25)
+* -Asparcvis3: Sparc-Opts. (line 25)
+* -Asparcvis3r: Sparc-Opts. (line 25)
+* -Av6: Sparc-Opts. (line 25)
+* -Av7: Sparc-Opts. (line 25)
+* -Av8: Sparc-Opts. (line 25)
+* -Av9: Sparc-Opts. (line 25)
+* -Av9a: Sparc-Opts. (line 25)
+* -Av9b: Sparc-Opts. (line 25)
+* -Av9c: Sparc-Opts. (line 25)
+* -Av9d: Sparc-Opts. (line 25)
+* -Av9e: Sparc-Opts. (line 25)
+* -Av9m: Sparc-Opts. (line 25)
+* -Av9v: Sparc-Opts. (line 25)
+* -b option, i960: Options-i960. (line 22)
+* -big option, M32R: M32R-Opts. (line 35)
+* -D: D. (line 6)
+* -D, ignored on VAX: VAX-Opts. (line 11)
+* -d, VAX option: VAX-Opts. (line 16)
+* -eabi= command line option, ARM: ARM Options. (line 166)
+* -EB command line option, AArch64: AArch64 Options. (line 6)
+* -EB command line option, ARC: ARC Options. (line 85)
+* -EB command line option, ARM: ARM Options. (line 171)
+* -EB option (MIPS): MIPS Options. (line 13)
+* -EB option, M32R: M32R-Opts. (line 39)
+* -EB option, TILE-Gx: TILE-Gx Options. (line 11)
+* -EL command line option, AArch64: AArch64 Options. (line 10)
+* -EL command line option, ARC: ARC Options. (line 89)
+* -EL command line option, ARM: ARM Options. (line 182)
+* -EL option (MIPS): MIPS Options. (line 13)
+* -EL option, M32R: M32R-Opts. (line 32)
+* -EL option, TILE-Gx: TILE-Gx Options. (line 11)
+* -f: f. (line 6)
+* -F command line option, Alpha: Alpha Options. (line 57)
+* -G command line option, Alpha: Alpha Options. (line 53)
+* -g command line option, Alpha: Alpha Options. (line 47)
+* -G option (MIPS): MIPS Options. (line 8)
+* -h option, VAX/VMS: VAX-Opts. (line 45)
+* -H option, VAX/VMS: VAX-Opts. (line 81)
+* -I PATH: I. (line 6)
+* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87)
+* -Ip option, M32RX: M32R-Opts. (line 97)
+* -J, ignored on VAX: VAX-Opts. (line 27)
+* -K: K. (line 6)
+* -k command line option, ARM: ARM Options. (line 186)
+* -KPIC option, M32R: M32R-Opts. (line 42)
+* -KPIC option, MIPS: MIPS Options. (line 21)
+* -L: L. (line 6)
+* -l option, M680x0: M68K-Opts. (line 33)
+* -little option, M32R: M32R-Opts. (line 27)
+* -M: M. (line 6)
+* -m11/03: PDP-11-Options. (line 140)
+* -m11/04: PDP-11-Options. (line 143)
+* -m11/05: PDP-11-Options. (line 146)
+* -m11/10: PDP-11-Options. (line 146)
+* -m11/15: PDP-11-Options. (line 149)
+* -m11/20: PDP-11-Options. (line 149)
+* -m11/21: PDP-11-Options. (line 152)
+* -m11/23: PDP-11-Options. (line 155)
+* -m11/24: PDP-11-Options. (line 155)
+* -m11/34: PDP-11-Options. (line 158)
+* -m11/34a: PDP-11-Options. (line 161)
+* -m11/35: PDP-11-Options. (line 164)
+* -m11/40: PDP-11-Options. (line 164)
+* -m11/44: PDP-11-Options. (line 167)
+* -m11/45: PDP-11-Options. (line 170)
+* -m11/50: PDP-11-Options. (line 170)
+* -m11/53: PDP-11-Options. (line 173)
+* -m11/55: PDP-11-Options. (line 170)
+* -m11/60: PDP-11-Options. (line 176)
+* -m11/70: PDP-11-Options. (line 170)
+* -m11/73: PDP-11-Options. (line 173)
+* -m11/83: PDP-11-Options. (line 173)
+* -m11/84: PDP-11-Options. (line 173)
+* -m11/93: PDP-11-Options. (line 173)
+* -m11/94: PDP-11-Options. (line 173)
+* -m16c option, M16C: M32C-Opts. (line 12)
+* -m31 option, s390: s390 Options. (line 8)
+* -m32 option, TILE-Gx: TILE-Gx Options. (line 8)
+* -m32bit-doubles: RX-Opts. (line 9)
+* -m32c option, M32C: M32C-Opts. (line 9)
+* -m32r option, M32R: M32R-Opts. (line 21)
+* -m32rx option, M32R2: M32R-Opts. (line 17)
+* -m32rx option, M32RX: M32R-Opts. (line 9)
+* -m4byte-align command line option, V850: V850 Options. (line 90)
+* -m64 option, s390: s390 Options. (line 8)
+* -m64 option, TILE-Gx: TILE-Gx Options. (line 8)
+* -m64bit-doubles: RX-Opts. (line 15)
+* -m68000 and related options: M68K-Opts. (line 98)
+* -m68hc11: M68HC11-Opts. (line 9)
+* -m68hc12: M68HC11-Opts. (line 14)
+* -m68hcs12: M68HC11-Opts. (line 21)
+* -m8byte-align command line option, V850: V850 Options. (line 86)
+* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]div command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]float command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21)
+* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21)
+* -mabi= command line option, AArch64: AArch64 Options. (line 14)
+* -mabi=ABI option, RISC-V: RISC-V-Opts. (line 12)
+* -madd-bnd-prefix option, i386: i386-Options. (line 134)
+* -madd-bnd-prefix option, x86-64: i386-Options. (line 134)
+* -mall: PDP-11-Options. (line 26)
+* -mall-enabled command line option, LM32: LM32 Options. (line 30)
+* -mall-extensions: PDP-11-Options. (line 26)
+* -mall-opcodes command line option, AVR: AVR Options. (line 109)
+* -mamd64 option, x86-64: i386-Options. (line 190)
+* -mapcs-26 command line option, ARM: ARM Options. (line 138)
+* -mapcs-32 command line option, ARM: ARM Options. (line 138)
+* -mapcs-float command line option, ARM: ARM Options. (line 152)
+* -mapcs-reentrant command line option, ARM: ARM Options. (line 157)
+* -march= command line option, AArch64: AArch64 Options. (line 39)
+* -march= command line option, ARM: ARM Options. (line 73)
+* -march= command line option, M680x0: M68K-Opts. (line 8)
+* -march= command line option, TIC6X: TIC6X Options. (line 6)
+* -march= option, i386: i386-Options. (line 31)
+* -march= option, s390: s390 Options. (line 25)
+* -march= option, x86-64: i386-Options. (line 31)
+* -march=ISA option, RISC-V: RISC-V-Opts. (line 8)
+* -matpcs command line option, ARM: ARM Options. (line 144)
+* -mavxscalar= option, i386: i386-Options. (line 92)
+* -mavxscalar= option, x86-64: i386-Options. (line 92)
+* -mbarrel-shift-enabled command line option, LM32: LM32 Options.
+ (line 12)
+* -mbig-endian: RX-Opts. (line 20)
+* -mbig-obj option, x86-64: i386-Options. (line 148)
+* -mbreak-enabled command line option, LM32: LM32 Options. (line 27)
+* -mccs command line option, ARM: ARM Options. (line 199)
+* -mcis: PDP-11-Options. (line 32)
+* -mcode-density command line option, ARC: ARC Options. (line 94)
+* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6)
+* -mCPU command line option, Alpha: Alpha Options. (line 6)
+* -mcpu option, cpu: TIC54X-Opts. (line 15)
+* -mcpu=: RX-Opts. (line 75)
+* -mcpu= command line option, AArch64: AArch64 Options. (line 19)
+* -mcpu= command line option, ARM: ARM Options. (line 6)
+* -mcpu= command line option, Blackfin: Blackfin Options. (line 6)
+* -mcpu= command line option, M680x0: M68K-Opts. (line 14)
+* -mcpu=CPU command line option, ARC: ARC Options. (line 10)
+* -mcsm: PDP-11-Options. (line 43)
+* -mdcache-enabled command line option, LM32: LM32 Options. (line 24)
+* -mdebug command line option, Alpha: Alpha Options. (line 25)
+* -mdivide-enabled command line option, LM32: LM32 Options. (line 9)
+* -mdpfp command line option, ARC: ARC Options. (line 109)
+* -mdsbt command line option, TIC6X: TIC6X Options. (line 13)
+* -me option, stderr redirect: TIC54X-Opts. (line 20)
+* -meis: PDP-11-Options. (line 46)
+* -mepiphany command line option, Epiphany: Epiphany Options.
+ (line 9)
+* -mepiphany16 command line option, Epiphany: Epiphany Options.
+ (line 13)
+* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20)
+* -mesa option, s390: s390 Options. (line 17)
+* -mevexlig= option, i386: i386-Options. (line 100)
+* -mevexlig= option, x86-64: i386-Options. (line 100)
+* -mevexrcig= option, i386: i386-Options. (line 180)
+* -mevexrcig= option, x86-64: i386-Options. (line 180)
+* -mevexwig= option, i386: i386-Options. (line 110)
+* -mevexwig= option, x86-64: i386-Options. (line 110)
+* -mf option, far-mode: TIC54X-Opts. (line 8)
+* -mf11: PDP-11-Options. (line 122)
+* -mfar-mode option, far-mode: TIC54X-Opts. (line 8)
+* -mfdpic command line option, Blackfin: Blackfin Options. (line 19)
+* -mfence-as-lock-add= option, i386: i386-Options. (line 161)
+* -mfence-as-lock-add= option, x86-64: i386-Options. (line 161)
+* -mfis: PDP-11-Options. (line 51)
+* -mfloat-abi= command line option, ARM: ARM Options. (line 161)
+* -mfp-11: PDP-11-Options. (line 56)
+* -mfpp: PDP-11-Options. (line 56)
+* -mfpu: PDP-11-Options. (line 56)
+* -mfpu= command line option, ARM: ARM Options. (line 90)
+* -mfpuda command line option, ARC: ARC Options. (line 112)
+* -mgcc-abi: RX-Opts. (line 63)
+* -mgcc-abi command line option, V850: V850 Options. (line 79)
+* -mhard-float command line option, V850: V850 Options. (line 101)
+* -micache-enabled command line option, LM32: LM32 Options. (line 21)
+* -mimplicit-it command line option, ARM: ARM Options. (line 122)
+* -mint-register: RX-Opts. (line 57)
+* -mintel64 option, x86-64: i386-Options. (line 190)
+* -mip2022 option, IP2K: IP2K-Opts. (line 14)
+* -mip2022ext option, IP2022: IP2K-Opts. (line 9)
+* -mj11: PDP-11-Options. (line 126)
+* -mka11: PDP-11-Options. (line 92)
+* -mkb11: PDP-11-Options. (line 95)
+* -mkd11a: PDP-11-Options. (line 98)
+* -mkd11b: PDP-11-Options. (line 101)
+* -mkd11d: PDP-11-Options. (line 104)
+* -mkd11e: PDP-11-Options. (line 107)
+* -mkd11f: PDP-11-Options. (line 110)
+* -mkd11h: PDP-11-Options. (line 110)
+* -mkd11k: PDP-11-Options. (line 114)
+* -mkd11q: PDP-11-Options. (line 110)
+* -mkd11z: PDP-11-Options. (line 118)
+* -mkev11: PDP-11-Options. (line 51)
+* -mlimited-eis: PDP-11-Options. (line 64)
+* -mlink-relax command line option, AVR: AVR Options. (line 121)
+* -mlittle-endian: RX-Opts. (line 26)
+* -mlong <1>: M68HC11-Opts. (line 45)
+* -mlong: XGATE-Opts. (line 13)
+* -mlong-double <1>: XGATE-Opts. (line 21)
+* -mlong-double: M68HC11-Opts. (line 53)
+* -mm9s12x: M68HC11-Opts. (line 27)
+* -mm9s12xg: M68HC11-Opts. (line 32)
+* -mmcu= command line option, AVR: AVR Options. (line 6)
+* -mmfpt: PDP-11-Options. (line 70)
+* -mmicrocode: PDP-11-Options. (line 83)
+* -mmnemonic= option, i386: i386-Options. (line 117)
+* -mmnemonic= option, x86-64: i386-Options. (line 117)
+* -mmultiply-enabled command line option, LM32: LM32 Options.
+ (line 6)
+* -mmutiproc: PDP-11-Options. (line 73)
+* -mmxps: PDP-11-Options. (line 77)
+* -mnaked-reg option, i386: i386-Options. (line 129)
+* -mnaked-reg option, x86-64: i386-Options. (line 129)
+* -mnan= command line option, MIPS: MIPS Options. (line 380)
+* -mno-allow-string-insns: RX-Opts. (line 82)
+* -mno-cis: PDP-11-Options. (line 32)
+* -mno-csm: PDP-11-Options. (line 43)
+* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13)
+* -mno-eis: PDP-11-Options. (line 46)
+* -mno-extensions: PDP-11-Options. (line 29)
+* -mno-fdpic command line option, Blackfin: Blackfin Options.
+ (line 22)
+* -mno-fis: PDP-11-Options. (line 51)
+* -mno-fp-11: PDP-11-Options. (line 56)
+* -mno-fpp: PDP-11-Options. (line 56)
+* -mno-fpu: PDP-11-Options. (line 56)
+* -mno-kev11: PDP-11-Options. (line 51)
+* -mno-limited-eis: PDP-11-Options. (line 64)
+* -mno-link-relax command line option, AVR: AVR Options. (line 125)
+* -mno-mfpt: PDP-11-Options. (line 70)
+* -mno-microcode: PDP-11-Options. (line 83)
+* -mno-mutiproc: PDP-11-Options. (line 73)
+* -mno-mxps: PDP-11-Options. (line 77)
+* -mno-pic: PDP-11-Options. (line 11)
+* -mno-pic command line option, TIC6X: TIC6X Options. (line 36)
+* -mno-regnames option, s390: s390 Options. (line 50)
+* -mno-skip-bug command line option, AVR: AVR Options. (line 112)
+* -mno-spl: PDP-11-Options. (line 80)
+* -mno-sym32: MIPS Options. (line 288)
+* -mno-verbose-error command line option, AArch64: AArch64 Options.
+ (line 59)
+* -mno-wrap command line option, AVR: AVR Options. (line 115)
+* -mnopic command line option, Blackfin: Blackfin Options. (line 22)
+* -mnps400 command line option, ARC: ARC Options. (line 103)
+* -momit-lock-prefix= option, i386: i386-Options. (line 152)
+* -momit-lock-prefix= option, x86-64: i386-Options. (line 152)
+* -mpic: PDP-11-Options. (line 11)
+* -mpic command line option, TIC6X: TIC6X Options. (line 36)
+* -mpid: RX-Opts. (line 50)
+* -mpid= command line option, TIC6X: TIC6X Options. (line 23)
+* -mregnames option, s390: s390 Options. (line 47)
+* -mrelax command line option, ARC: ARC Options. (line 98)
+* -mrelax command line option, V850: V850 Options. (line 72)
+* -mrelax-relocations= option, i386: i386-Options. (line 170)
+* -mrelax-relocations= option, x86-64: i386-Options. (line 170)
+* -mrh850-abi command line option, V850: V850 Options. (line 82)
+* -mrmw command line option, AVR: AVR Options. (line 118)
+* -mrx-abi: RX-Opts. (line 69)
+* -mshared option, i386: i386-Options. (line 139)
+* -mshared option, x86-64: i386-Options. (line 139)
+* -mshort <1>: M68HC11-Opts. (line 40)
+* -mshort: XGATE-Opts. (line 8)
+* -mshort-double <1>: M68HC11-Opts. (line 49)
+* -mshort-double: XGATE-Opts. (line 17)
+* -msign-extend-enabled command line option, LM32: LM32 Options.
+ (line 15)
+* -msmall-data-limit: RX-Opts. (line 42)
+* -msoft-float command line option, V850: V850 Options. (line 95)
+* -mspfp command line option, ARC: ARC Options. (line 106)
+* -mspl: PDP-11-Options. (line 80)
+* -msse-check= option, i386: i386-Options. (line 82)
+* -msse-check= option, x86-64: i386-Options. (line 82)
+* -msse2avx option, i386: i386-Options. (line 78)
+* -msse2avx option, x86-64: i386-Options. (line 78)
+* -msym32: MIPS Options. (line 288)
+* -msyntax= option, i386: i386-Options. (line 123)
+* -msyntax= option, x86-64: i386-Options. (line 123)
+* -mt11: PDP-11-Options. (line 130)
+* -mthumb command line option, ARM: ARM Options. (line 113)
+* -mthumb-interwork command line option, ARM: ARM Options. (line 118)
+* -mtune= option, i386: i386-Options. (line 70)
+* -mtune= option, x86-64: i386-Options. (line 70)
+* -mtune=ARCH command line option, Visium: Visium Options. (line 8)
+* -muse-conventional-section-names: RX-Opts. (line 33)
+* -muse-renesas-section-names: RX-Opts. (line 37)
+* -muser-enabled command line option, LM32: LM32 Options. (line 18)
+* -mv850 command line option, V850: V850 Options. (line 23)
+* -mv850any command line option, V850: V850 Options. (line 41)
+* -mv850e command line option, V850: V850 Options. (line 29)
+* -mv850e1 command line option, V850: V850 Options. (line 35)
+* -mv850e2 command line option, V850: V850 Options. (line 51)
+* -mv850e2v3 command line option, V850: V850 Options. (line 57)
+* -mv850e2v4 command line option, V850: V850 Options. (line 63)
+* -mv850e3v5 command line option, V850: V850 Options. (line 66)
+* -mverbose-error command line option, AArch64: AArch64 Options.
+ (line 55)
+* -mvxworks-pic option, MIPS: MIPS Options. (line 26)
+* -mwarn-areg-zero option, s390: s390 Options. (line 53)
+* -mwarn-deprecated command line option, ARM: ARM Options. (line 194)
+* -mwarn-syms command line option, ARM: ARM Options. (line 202)
+* -mzarch option, s390: s390 Options. (line 17)
+* -N command line option, CRIS: CRIS-Opts. (line 58)
+* -nIp option, M32RX: M32R-Opts. (line 101)
+* -no-bitinst, M32R2: M32R-Opts. (line 54)
+* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93)
+* -no-mdebug command line option, Alpha: Alpha Options. (line 25)
+* -no-parallel option, M32RX: M32R-Opts. (line 51)
+* -no-relax option, i960: Options-i960. (line 66)
+* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
+ (line 79)
+* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111)
+* -nocpp ignored (MIPS): MIPS Options. (line 291)
+* -noreplace command line option, Alpha: Alpha Options. (line 40)
+* -o: o. (line 6)
+* -O option, M32RX: M32R-Opts. (line 59)
+* -parallel option, M32RX: M32R-Opts. (line 46)
+* -R: R. (line 6)
+* -r800 command line option, Z80: Z80 Options. (line 41)
+* -relax command line option, Alpha: Alpha Options. (line 32)
+* -replace command line option, Alpha: Alpha Options. (line 40)
+* -S, ignored on VAX: VAX-Opts. (line 11)
+* -T, ignored on VAX: VAX-Opts. (line 11)
+* -t, ignored on VAX: VAX-Opts. (line 36)
+* -v: v. (line 6)
+* -V, redundant on VAX: VAX-Opts. (line 22)
+* -version: v. (line 6)
+* -W: W. (line 11)
+* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
+ (line 65)
+* -warn-unmatched-high option, M32R: M32R-Opts. (line 105)
+* -Wnp option, M32RX: M32R-Opts. (line 83)
+* -Wnuh option, M32RX: M32R-Opts. (line 117)
+* -Wp option, M32RX: M32R-Opts. (line 75)
+* -wsigned_overflow command line option, V850: V850 Options. (line 9)
+* -Wuh option, M32RX: M32R-Opts. (line 114)
+* -wunsigned_overflow command line option, V850: V850 Options.
+ (line 16)
+* -x command line option, MMIX: MMIX-Opts. (line 44)
+* -z80 command line option, Z80: Z80 Options. (line 8)
+* -z8001 command line option, Z8000: Z8000 Options. (line 6)
+* -z8002 command line option, Z8000: Z8000 Options. (line 9)
+* . (symbol): Dot. (line 6)
+* .2byte directive, ARM: ARM Directives. (line 6)
+* .4byte directive, ARM: ARM Directives. (line 6)
+* .8byte directive, ARM: ARM Directives. (line 6)
+* .align directive, ARM: ARM Directives. (line 11)
+* .align directive, TILE-Gx: TILE-Gx Directives. (line 6)
+* .align directive, TILEPro: TILEPro Directives. (line 6)
+* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives.
+ (line 10)
+* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives.
+ (line 10)
+* .arch directive, AArch64: AArch64 Directives. (line 6)
+* .arch directive, ARM: ARM Directives. (line 18)
+* .arch directive, TIC6X: TIC6X Directives. (line 10)
+* .arch_extension directive, AArch64: AArch64 Directives. (line 13)
+* .arch_extension directive, ARM: ARM Directives. (line 25)
+* .arm directive, ARM: ARM Directives. (line 34)
+* .big directive, M32RX: M32R-Directives. (line 88)
+* .bss directive, AArch64: AArch64 Directives. (line 22)
+* .bss directive, ARM: ARM Directives. (line 37)
+* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20)
+* .cantunwind directive, ARM: ARM Directives. (line 40)
+* .cantunwind directive, TIC6X: TIC6X Directives. (line 13)
+* .code directive, ARM: ARM Directives. (line 44)
+* .cpu directive, AArch64: AArch64 Directives. (line 25)
+* .cpu directive, ARM: ARM Directives. (line 48)
+* .dn and .qn directives, ARM: ARM Directives. (line 55)
+* .dword directive, AArch64: AArch64 Directives. (line 29)
+* .eabi_attribute directive, ARM: ARM Directives. (line 78)
+* .ehtype directive, TIC6X: TIC6X Directives. (line 31)
+* .endp directive, TIC6X: TIC6X Directives. (line 34)
+* .even directive, AArch64: AArch64 Directives. (line 32)
+* .even directive, ARM: ARM Directives. (line 106)
+* .extend directive, ARM: ARM Directives. (line 109)
+* .fnend directive, ARM: ARM Directives. (line 115)
+* .fnstart directive, ARM: ARM Directives. (line 124)
+* .force_thumb directive, ARM: ARM Directives. (line 127)
+* .fpu directive, ARM: ARM Directives. (line 131)
+* .global: MIPS insn. (line 12)
+* .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History.
+ (line 6)
+* .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History.
+ (line 6)
+* .handlerdata directive, ARM: ARM Directives. (line 135)
+* .handlerdata directive, TIC6X: TIC6X Directives. (line 39)
+* .insn: MIPS insn. (line 6)
+* .insn directive, s390: s390 Directives. (line 11)
+* .inst directive, AArch64: AArch64 Directives. (line 36)
+* .inst directive, ARM: ARM Directives. (line 144)
+* .ldouble directive, ARM: ARM Directives. (line 109)
+* .little directive, M32RX: M32R-Directives. (line 82)
+* .long directive, s390: s390 Directives. (line 16)
+* .ltorg directive, AArch64: AArch64 Directives. (line 40)
+* .ltorg directive, ARM: ARM Directives. (line 154)
+* .ltorg directive, s390: s390 Directives. (line 88)
+* .m32r directive, M32R: M32R-Directives. (line 66)
+* .m32r2 directive, M32R2: M32R-Directives. (line 77)
+* .m32rx directive, M32RX: M32R-Directives. (line 72)
+* .machine directive, s390: s390 Directives. (line 93)
+* .machinemode directive, s390: s390 Directives. (line 109)
+* .module: MIPS assembly options.
+ (line 6)
+* .module fp=NN directive, MIPS: MIPS FP ABI Selection.
+ (line 6)
+* .movsp directive, ARM: ARM Directives. (line 168)
+* .nan directive, MIPS: MIPS NaN Encodings. (line 6)
+* .no_pointers directive, XStormy16: XStormy16 Directives.
+ (line 14)
+* .nocmp directive, TIC6X: TIC6X Directives. (line 47)
+* .o: Object. (line 6)
+* .object_arch directive, ARM: ARM Directives. (line 173)
+* .packed directive, ARM: ARM Directives. (line 179)
+* .pad directive, ARM: ARM Directives. (line 184)
+* .param on HPPA: HPPA Directives. (line 19)
+* .personality directive, ARM: ARM Directives. (line 189)
+* .personality directive, TIC6X: TIC6X Directives. (line 55)
+* .personalityindex directive, ARM: ARM Directives. (line 192)
+* .personalityindex directive, TIC6X: TIC6X Directives. (line 51)
+* .pool directive, AArch64: AArch64 Directives. (line 54)
+* .pool directive, ARM: ARM Directives. (line 196)
+* .quad directive, s390: s390 Directives. (line 16)
+* .req directive, AArch64: AArch64 Directives. (line 57)
+* .req directive, ARM: ARM Directives. (line 199)
+* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives.
+ (line 19)
+* .require_canonical_reg_names directive, TILEPro: TILEPro Directives.
+ (line 19)
+* .save directive, ARM: ARM Directives. (line 204)
+* .scomm directive, TIC6X: TIC6X Directives. (line 58)
+* .secrel32 directive, ARM: ARM Directives. (line 242)
+* .set arch=CPU: MIPS ISA. (line 19)
+* .set at: MIPS Macros. (line 42)
+* .set at=REG: MIPS Macros. (line 36)
+* .set autoextend: MIPS autoextend. (line 6)
+* .set doublefloat: MIPS Floating-Point.
+ (line 12)
+* .set dsp: MIPS ASE Instruction Generation Overrides.
+ (line 21)
+* .set dspr2: MIPS ASE Instruction Generation Overrides.
+ (line 26)
+* .set dspr3: MIPS ASE Instruction Generation Overrides.
+ (line 32)
+* .set hardfloat: MIPS Floating-Point.
+ (line 6)
+* .set insn32: MIPS assembly options.
+ (line 18)
+* .set macro: MIPS Macros. (line 31)
+* .set mcu: MIPS ASE Instruction Generation Overrides.
+ (line 43)
+* .set mdmx: MIPS ASE Instruction Generation Overrides.
+ (line 16)
+* .set mips3d: MIPS ASE Instruction Generation Overrides.
+ (line 6)
+* .set mipsN: MIPS ISA. (line 6)
+* .set msa: MIPS ASE Instruction Generation Overrides.
+ (line 48)
+* .set mt: MIPS ASE Instruction Generation Overrides.
+ (line 38)
+* .set noat: MIPS Macros. (line 42)
+* .set noautoextend: MIPS autoextend. (line 6)
+* .set nodsp: MIPS ASE Instruction Generation Overrides.
+ (line 21)
+* .set nodspr2: MIPS ASE Instruction Generation Overrides.
+ (line 26)
+* .set nodspr3: MIPS ASE Instruction Generation Overrides.
+ (line 32)
+* .set noinsn32: MIPS assembly options.
+ (line 18)
+* .set nomacro: MIPS Macros. (line 31)
+* .set nomcu: MIPS ASE Instruction Generation Overrides.
+ (line 43)
+* .set nomdmx: MIPS ASE Instruction Generation Overrides.
+ (line 16)
+* .set nomips3d: MIPS ASE Instruction Generation Overrides.
+ (line 6)
+* .set nomsa: MIPS ASE Instruction Generation Overrides.
+ (line 48)
+* .set nomt: MIPS ASE Instruction Generation Overrides.
+ (line 38)
+* .set nosmartmips: MIPS ASE Instruction Generation Overrides.
+ (line 11)
+* .set nosym32: MIPS Symbol Sizes. (line 6)
+* .set novirt: MIPS ASE Instruction Generation Overrides.
+ (line 53)
+* .set noxpa: MIPS ASE Instruction Generation Overrides.
+ (line 58)
+* .set pop: MIPS Option Stack. (line 6)
+* .set push: MIPS Option Stack. (line 6)
+* .set singlefloat: MIPS Floating-Point.
+ (line 12)
+* .set smartmips: MIPS ASE Instruction Generation Overrides.
+ (line 11)
+* .set softfloat: MIPS Floating-Point.
+ (line 6)
+* .set sym32: MIPS Symbol Sizes. (line 6)
+* .set virt: MIPS ASE Instruction Generation Overrides.
+ (line 53)
+* .set xpa: MIPS ASE Instruction Generation Overrides.
+ (line 58)
+* .setfp directive, ARM: ARM Directives. (line 228)
+* .short directive, s390: s390 Directives. (line 16)
+* .syntax directive, ARM: ARM Directives. (line 247)
+* .thumb directive, ARM: ARM Directives. (line 251)
+* .thumb_func directive, ARM: ARM Directives. (line 254)
+* .thumb_set directive, ARM: ARM Directives. (line 265)
+* .tlsdescadd directive, AArch64: AArch64 Directives. (line 62)
+* .tlsdesccall directive, AArch64: AArch64 Directives. (line 65)
+* .tlsdescldr directive, AArch64: AArch64 Directives. (line 68)
+* .tlsdescseq directive, ARM: ARM Directives. (line 272)
+* .unreq directive, AArch64: AArch64 Directives. (line 71)
+* .unreq directive, ARM: ARM Directives. (line 277)
+* .unwind_raw directive, ARM: ARM Directives. (line 288)
+* .v850 directive, V850: V850 Directives. (line 14)
+* .v850e directive, V850: V850 Directives. (line 20)
+* .v850e1 directive, V850: V850 Directives. (line 26)
+* .v850e2 directive, V850: V850 Directives. (line 32)
+* .v850e2v3 directive, V850: V850 Directives. (line 38)
+* .v850e2v4 directive, V850: V850 Directives. (line 44)
+* .v850e3v5 directive, V850: V850 Directives. (line 50)
+* .vsave directive, ARM: ARM Directives. (line 295)
+* .xword directive, AArch64: AArch64 Directives. (line 82)
+* .z8001: Z8000 Directives. (line 11)
+* .z8002: Z8000 Directives. (line 15)
+* 16-bit code, i386: i386-16bit. (line 6)
+* 16bit_pointers directive, XStormy16: XStormy16 Directives.
+ (line 6)
+* 16byte directive, Nios II: Nios II Directives. (line 28)
+* 2byte directive, Nios II: Nios II Directives. (line 19)
+* 32bit_pointers directive, XStormy16: XStormy16 Directives.
+ (line 10)
+* 3DNow!, i386: i386-SIMD. (line 6)
+* 3DNow!, x86-64: i386-SIMD. (line 6)
+* 430 support: MSP430-Dependent. (line 6)
+* 4byte directive, Nios II: Nios II Directives. (line 22)
+* 8byte directive, Nios II: Nios II Directives. (line 25)
+* : (label): Statements. (line 31)
+* @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20)
+* @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16)
+* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21)
+* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10)
+* @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12)
+* @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23)
+* @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28)
+* @word modifier, D10V: D10V-Word. (line 6)
+* _ opcode prefix: Xtensa Opcodes. (line 9)
+* __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14)
+* __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols.
+ (line 11)
+* a.out: Object. (line 6)
+* a.out symbol attributes: a.out Symbols. (line 6)
+* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
+* AArch64 floating point (IEEE): AArch64 Floating Point.
+ (line 6)
+* AArch64 immediate character: AArch64-Chars. (line 13)
+* AArch64 line comment character: AArch64-Chars. (line 6)
+* AArch64 line separator: AArch64-Chars. (line 10)
+* AArch64 machine directives: AArch64 Directives. (line 6)
+* AArch64 opcodes: AArch64 Opcodes. (line 6)
+* AArch64 options (none): AArch64 Options. (line 6)
+* AArch64 register names: AArch64-Regs. (line 6)
+* AArch64 relocations: AArch64-Relocations.
+ (line 6)
+* AArch64 support: AArch64-Dependent. (line 6)
+* ABI options, SH64: SH64 Options. (line 29)
+* abort directive: Abort. (line 6)
+* ABORT directive: ABORT (COFF). (line 6)
+* absolute section: Ld Sections. (line 29)
+* absolute-literals directive: Absolute Literals Directive.
+ (line 6)
+* ADDI instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 43)
+* addition, permitted arguments: Infix Ops. (line 44)
+* addresses: Expressions. (line 6)
+* addresses, format of: Secs Background. (line 68)
+* addressing modes, D10V: D10V-Addressing. (line 6)
+* addressing modes, D30V: D30V-Addressing. (line 6)
+* addressing modes, H8/300: H8/300-Addressing. (line 6)
+* addressing modes, M680x0: M68K-Syntax. (line 21)
+* addressing modes, M68HC11: M68HC11-Syntax. (line 30)
+* addressing modes, SH: SH-Addressing. (line 6)
+* addressing modes, SH64: SH64-Addressing. (line 6)
+* addressing modes, XGATE: XGATE-Syntax. (line 29)
+* addressing modes, Z8000: Z8000-Addressing. (line 6)
+* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25)
+* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35)
+* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations.
+ (line 14)
+* advancing location counter: Org. (line 6)
+* align directive: Align. (line 6)
+* align directive, Nios II: Nios II Directives. (line 6)
+* align directive, SPARC: Sparc-Directives. (line 9)
+* align directive, TIC54X: TIC54X-Directives. (line 6)
+* aligned instruction bundle: Bundle directives. (line 9)
+* alignment for NEON instructions: ARM-Neon-Alignment. (line 6)
+* alignment of branch targets: Xtensa Automatic Alignment.
+ (line 6)
+* alignment of LOOP instructions: Xtensa Automatic Alignment.
+ (line 6)
+* Alpha floating point (IEEE): Alpha Floating Point.
+ (line 6)
+* Alpha line comment character: Alpha-Chars. (line 6)
+* Alpha line separator: Alpha-Chars. (line 11)
+* Alpha notes: Alpha Notes. (line 6)
+* Alpha options: Alpha Options. (line 6)
+* Alpha registers: Alpha-Regs. (line 6)
+* Alpha relocations: Alpha-Relocs. (line 6)
+* Alpha support: Alpha-Dependent. (line 6)
+* Alpha Syntax: Alpha Options. (line 61)
+* Alpha-only directives: Alpha Directives. (line 10)
+* Altera Nios II support: NiosII-Dependent. (line 6)
+* altered difference tables: Word. (line 12)
+* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6)
+* ARC Branch Target Address: ARC-Regs. (line 61)
+* ARC BTA saved on exception entry: ARC-Regs. (line 80)
+* ARC Build configuration for: BTA Registers: ARC-Regs. (line 90)
+* ARC Build configuration for: Core Registers: ARC-Regs. (line 98)
+* ARC Build configuration for: Interrupts: ARC-Regs. (line 94)
+* ARC Build Configuration Registers Version: ARC-Regs. (line 86)
+* ARC C preprocessor macro separator: ARC-Chars. (line 31)
+* ARC core general registers: ARC-Regs. (line 10)
+* ARC DCCM RAM Configuration Register: ARC-Regs. (line 102)
+* ARC Exception Cause Register: ARC-Regs. (line 64)
+* ARC Exception Return Address: ARC-Regs. (line 77)
+* ARC extension core registers: ARC-Regs. (line 38)
+* ARC frame pointer: ARC-Regs. (line 17)
+* ARC global pointer: ARC-Regs. (line 14)
+* ARC interrupt link register: ARC-Regs. (line 27)
+* ARC Interrupt Vector Base address: ARC-Regs. (line 67)
+* ARC level 1 interrupt link register: ARC-Regs. (line 23)
+* ARC level 2 interrupt link register: ARC-Regs. (line 31)
+* ARC line comment character: ARC-Chars. (line 11)
+* ARC line separator: ARC-Chars. (line 27)
+* ARC link register: ARC-Regs. (line 35)
+* ARC loop counter: ARC-Regs. (line 41)
+* ARC machine directives: ARC Directives. (line 6)
+* ARC opcodes: ARC Opcodes. (line 6)
+* ARC options: ARC Options. (line 6)
+* ARC Processor Identification register: ARC-Regs. (line 52)
+* ARC Program Counter: ARC-Regs. (line 55)
+* ARC register name prefix character: ARC-Chars. (line 7)
+* ARC register names: ARC-Regs. (line 6)
+* ARC Saved User Stack Pointer: ARC-Regs. (line 74)
+* ARC stack pointer: ARC-Regs. (line 20)
+* ARC Status register: ARC-Regs. (line 58)
+* ARC STATUS32 saved on exception: ARC-Regs. (line 83)
+* ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs.
+ (line 70)
+* ARC support: ARC-Dependent. (line 6)
+* ARC symbol prefix character: ARC-Chars. (line 20)
+* ARC word aligned program counter: ARC-Regs. (line 44)
+* arch directive, i386: i386-Arch. (line 6)
+* arch directive, M680x0: M68K-Directives. (line 22)
+* arch directive, MSP 430: MSP430 Directives. (line 18)
+* arch directive, x86-64: i386-Arch. (line 6)
+* architecture options, i960: Options-i960. (line 6)
+* architecture options, IP2022: IP2K-Opts. (line 9)
+* architecture options, IP2K: IP2K-Opts. (line 14)
+* architecture options, M16C: M32C-Opts. (line 12)
+* architecture options, M32C: M32C-Opts. (line 9)
+* architecture options, M32R: M32R-Opts. (line 21)
+* architecture options, M32R2: M32R-Opts. (line 17)
+* architecture options, M32RX: M32R-Opts. (line 9)
+* architecture options, M680x0: M68K-Opts. (line 98)
+* Architecture variant option, CRIS: CRIS-Opts. (line 34)
+* architectures, Meta: Meta Options. (line 6)
+* architectures, PowerPC: PowerPC-Opts. (line 6)
+* architectures, SCORE: SCORE-Opts. (line 6)
+* architectures, SPARC: Sparc-Opts. (line 6)
+* arguments for addition: Infix Ops. (line 44)
+* arguments for subtraction: Infix Ops. (line 49)
+* arguments in expressions: Arguments. (line 6)
+* arithmetic functions: Operators. (line 6)
+* arithmetic operands: Arguments. (line 6)
+* ARM data relocations: ARM-Relocations. (line 6)
+* ARM floating point (IEEE): ARM Floating Point. (line 6)
+* ARM identifiers: ARM-Chars. (line 19)
+* ARM immediate character: ARM-Chars. (line 17)
+* ARM line comment character: ARM-Chars. (line 6)
+* ARM line separator: ARM-Chars. (line 14)
+* ARM machine directives: ARM Directives. (line 6)
+* ARM opcodes: ARM Opcodes. (line 6)
+* ARM options (none): ARM Options. (line 6)
+* ARM register names: ARM-Regs. (line 6)
+* ARM support: ARM-Dependent. (line 6)
+* ascii directive: Ascii. (line 6)
+* asciz directive: Asciz. (line 6)
+* asg directive, TIC54X: TIC54X-Directives. (line 20)
+* assembler bugs, reporting: Bug Reporting. (line 6)
+* assembler crash: Bug Criteria. (line 9)
+* assembler directive .3byte, RX: RX-Directives. (line 9)
+* assembler directive .arch, CRIS: CRIS-Pseudos. (line 45)
+* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12)
+* assembler directive .far, M68HC11: M68HC11-Directives. (line 20)
+* assembler directive .fetchalign, RX: RX-Directives. (line 13)
+* assembler directive .interrupt, M68HC11: M68HC11-Directives.
+ (line 26)
+* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16)
+* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10)
+* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17)
+* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31)
+* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131)
+* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97)
+* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131)
+* assembler directive GREG, MMIX: MMIX-Pseudos. (line 50)
+* assembler directive IS, MMIX: MMIX-Pseudos. (line 42)
+* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7)
+* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28)
+* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108)
+* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120)
+* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108)
+* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108)
+* assembler directives, CRIS: CRIS-Pseudos. (line 6)
+* assembler directives, M68HC11: M68HC11-Directives. (line 6)
+* assembler directives, M68HC12: M68HC11-Directives. (line 6)
+* assembler directives, MMIX: MMIX-Pseudos. (line 6)
+* assembler directives, RL78: RL78-Directives. (line 6)
+* assembler directives, RX: RX-Directives. (line 6)
+* assembler directives, XGATE: XGATE-Directives. (line 6)
+* assembler internal logic error: As Sections. (line 13)
+* assembler version: v. (line 6)
+* assembler, and linker: Secs Background. (line 10)
+* assembly listings, enabling: a. (line 6)
+* assigning values to symbols <1>: Setting Symbols. (line 6)
+* assigning values to symbols: Equ. (line 6)
+* at register, MIPS: MIPS Macros. (line 36)
+* atmp directive, i860: Directives-i860. (line 16)
+* att_syntax pseudo op, i386: i386-Variations. (line 6)
+* att_syntax pseudo op, x86-64: i386-Variations. (line 6)
+* attributes, symbol: Symbol Attributes. (line 6)
+* auxiliary attributes, COFF symbols: COFF Symbols. (line 19)
+* auxiliary symbol information, COFF: Dim. (line 6)
+* AVR line comment character: AVR-Chars. (line 6)
+* AVR line separator: AVR-Chars. (line 14)
+* AVR modifiers: AVR-Modifiers. (line 6)
+* AVR opcode summary: AVR Opcodes. (line 6)
+* AVR options (none): AVR Options. (line 6)
+* AVR register names: AVR-Regs. (line 6)
+* AVR support: AVR-Dependent. (line 6)
+* backslash (\\): Strings. (line 40)
+* backspace (\b): Strings. (line 15)
+* balign directive: Balign. (line 6)
+* balignl directive: Balign. (line 27)
+* balignw directive: Balign. (line 27)
+* bes directive, TIC54X: TIC54X-Directives. (line 196)
+* big endian output, MIPS: Overview. (line 828)
+* big endian output, PJ: Overview. (line 731)
+* big-endian output, MIPS: MIPS Options. (line 13)
+* big-endian output, TIC6X: TIC6X Options. (line 46)
+* bignums: Bignums. (line 6)
+* binary constants, TIC54X: TIC54X-Constants. (line 8)
+* binary files, including: Incbin. (line 6)
+* binary integers: Integers. (line 6)
+* bit names, IA-64: IA-64-Bits. (line 6)
+* bitfields, not supported on VAX: VAX-no. (line 6)
+* Blackfin directives: Blackfin Directives.
+ (line 6)
+* Blackfin options (none): Blackfin Options. (line 6)
+* Blackfin support: Blackfin-Dependent. (line 6)
+* Blackfin syntax: Blackfin Syntax. (line 6)
+* block: Z8000 Directives. (line 55)
+* BMI, i386: i386-BMI. (line 6)
+* BMI, x86-64: i386-BMI. (line 6)
+* branch improvement, M680x0: M68K-Branch. (line 6)
+* branch improvement, M68HC11: M68HC11-Branch. (line 6)
+* branch improvement, VAX: VAX-branch. (line 6)
+* branch instructions, relaxation: Xtensa Branch Relaxation.
+ (line 6)
+* branch recording, i960: Options-i960. (line 22)
+* branch statistics table, i960: Options-i960. (line 40)
+* Branch Target Address, ARC: ARC-Regs. (line 61)
+* branch target alignment: Xtensa Automatic Alignment.
+ (line 6)
+* break directive, TIC54X: TIC54X-Directives. (line 143)
+* BSD syntax: PDP-11-Syntax. (line 6)
+* bss directive, i960: Directives-i960. (line 6)
+* bss directive, TIC54X: TIC54X-Directives. (line 29)
+* bss section <1>: bss. (line 6)
+* bss section: Ld Sections. (line 20)
+* BTA saved on exception entry, ARC: ARC-Regs. (line 80)
+* bug criteria: Bug Criteria. (line 6)
+* bug reports: Bug Reporting. (line 6)
+* bugs in assembler: Reporting Bugs. (line 6)
+* Build configuration for: BTA Registers, ARC: ARC-Regs. (line 90)
+* Build configuration for: Core Registers, ARC: ARC-Regs. (line 98)
+* Build configuration for: Interrupts, ARC: ARC-Regs. (line 94)
+* Build Configuration Registers Version, ARC: ARC-Regs. (line 86)
+* Built-in symbols, CRIS: CRIS-Symbols. (line 6)
+* builtin math functions, TIC54X: TIC54X-Builtins. (line 6)
+* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16)
+* bundle: Bundle directives. (line 9)
+* bundle-locked: Bundle directives. (line 38)
+* bundle_align_mode directive: Bundle directives. (line 9)
+* bundle_lock directive: Bundle directives. (line 31)
+* bundle_unlock directive: Bundle directives. (line 31)
+* bus lock prefixes, i386: i386-Prefixes. (line 36)
+* bval: Z8000 Directives. (line 30)
+* byte directive: Byte. (line 6)
+* byte directive, TIC54X: TIC54X-Directives. (line 36)
+* C preprocessor macro separator, ARC: ARC-Chars. (line 31)
+* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6)
+* c_mode directive, TIC54X: TIC54X-Directives. (line 51)
+* call directive, Nios II: Nios II Relocations.
+ (line 38)
+* call instructions, i386: i386-Mnemonics. (line 59)
+* call instructions, relaxation: Xtensa Call Relaxation.
+ (line 6)
+* call instructions, x86-64: i386-Mnemonics. (line 59)
+* call_hiadj directive, Nios II: Nios II Relocations.
+ (line 38)
+* call_lo directive, Nios II: Nios II Relocations.
+ (line 38)
+* callj, i960 pseudo-opcode: callj-i960. (line 6)
+* carriage return (backslash-r): Strings. (line 24)
+* case sensitivity, Z80: Z80-Case. (line 6)
+* cfi_endproc directive: CFI directives. (line 40)
+* cfi_fde_data directive: CFI directives. (line 66)
+* cfi_personality directive: CFI directives. (line 47)
+* cfi_personality_id directive: CFI directives. (line 59)
+* cfi_sections directive: CFI directives. (line 9)
+* cfi_startproc directive: CFI directives. (line 30)
+* char directive, TIC54X: TIC54X-Directives. (line 36)
+* character constant, Z80: Z80-Chars. (line 20)
+* character constants: Characters. (line 6)
+* character escape codes: Strings. (line 15)
+* character escapes, Z80: Z80-Chars. (line 18)
+* character, single: Chars. (line 6)
+* characters used in symbols: Symbol Intro. (line 6)
+* clink directive, TIC54X: TIC54X-Directives. (line 45)
+* code16 directive, i386: i386-16bit. (line 6)
+* code16gcc directive, i386: i386-16bit. (line 6)
+* code32 directive, i386: i386-16bit. (line 6)
+* code64 directive, i386: i386-16bit. (line 6)
+* code64 directive, x86-64: i386-16bit. (line 6)
+* COFF auxiliary symbol information: Dim. (line 6)
+* COFF structure debugging: Tag. (line 6)
+* COFF symbol attributes: COFF Symbols. (line 6)
+* COFF symbol descriptor: Desc. (line 6)
+* COFF symbol storage class: Scl. (line 6)
+* COFF symbol type: Type. (line 11)
+* COFF symbols, debugging: Def. (line 6)
+* COFF value attribute: Val. (line 6)
+* COMDAT: Linkonce. (line 6)
+* comm directive: Comm. (line 6)
+* command line conventions: Command Line. (line 6)
+* command line options, V850: V850 Options. (line 9)
+* command-line options ignored, VAX: VAX-Opts. (line 6)
+* comment character, XStormy16: XStormy16-Chars. (line 11)
+* comments: Comments. (line 6)
+* comments, M680x0: M68K-Chars. (line 6)
+* comments, removed by preprocessor: Preprocessing. (line 11)
+* common directive, SPARC: Sparc-Directives. (line 12)
+* common sections: Linkonce. (line 6)
+* common variable storage: bss. (line 6)
+* compare and jump expansions, i960: Compare-and-branch-i960.
+ (line 13)
+* compare/branch instructions, i960: Compare-and-branch-i960.
+ (line 6)
+* comparison expressions: Infix Ops. (line 55)
+* conditional assembly: If. (line 6)
+* constant, single character: Chars. (line 6)
+* constants: Constants. (line 6)
+* constants, bignum: Bignums. (line 6)
+* constants, character: Characters. (line 6)
+* constants, converted by preprocessor: Preprocessing. (line 14)
+* constants, floating point: Flonums. (line 6)
+* constants, integer: Integers. (line 6)
+* constants, number: Numbers. (line 6)
+* constants, Sparc: Sparc-Constants. (line 6)
+* constants, string: Strings. (line 6)
+* constants, TIC54X: TIC54X-Constants. (line 6)
+* conversion instructions, i386: i386-Mnemonics. (line 40)
+* conversion instructions, x86-64: i386-Mnemonics. (line 40)
+* coprocessor wait, i386: i386-Prefixes. (line 40)
+* copy directive, TIC54X: TIC54X-Directives. (line 54)
+* core general registers, ARC: ARC-Regs. (line 10)
+* cpu directive, ARC: ARC Directives. (line 27)
+* cpu directive, M680x0: M68K-Directives. (line 30)
+* cpu directive, MSP 430: MSP430 Directives. (line 22)
+* CR16 line comment character: CR16-Chars. (line 6)
+* CR16 line separator: CR16-Chars. (line 13)
+* CR16 Operand Qualifiers: CR16 Operand Qualifiers.
+ (line 6)
+* CR16 support: CR16-Dependent. (line 6)
+* crash of assembler: Bug Criteria. (line 9)
+* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9)
+* CRIS --emulation=criself command line option: CRIS-Opts. (line 9)
+* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34)
+* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 62)
+* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 62)
+* CRIS --no-underscore command line option: CRIS-Opts. (line 15)
+* CRIS --pic command line option: CRIS-Opts. (line 27)
+* CRIS --underscore command line option: CRIS-Opts. (line 15)
+* CRIS -N command line option: CRIS-Opts. (line 58)
+* CRIS architecture variant option: CRIS-Opts. (line 34)
+* CRIS assembler directive .arch: CRIS-Pseudos. (line 45)
+* CRIS assembler directive .dword: CRIS-Pseudos. (line 12)
+* CRIS assembler directive .syntax: CRIS-Pseudos. (line 17)
+* CRIS assembler directives: CRIS-Pseudos. (line 6)
+* CRIS built-in symbols: CRIS-Symbols. (line 6)
+* CRIS instruction expansion: CRIS-Expand. (line 6)
+* CRIS line comment characters: CRIS-Chars. (line 6)
+* CRIS options: CRIS-Opts. (line 6)
+* CRIS position-independent code: CRIS-Opts. (line 27)
+* CRIS pseudo-op .arch: CRIS-Pseudos. (line 45)
+* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12)
+* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17)
+* CRIS pseudo-ops: CRIS-Pseudos. (line 6)
+* CRIS register names: CRIS-Regs. (line 6)
+* CRIS support: CRIS-Dependent. (line 6)
+* CRIS symbols in position-independent code: CRIS-Pic. (line 6)
+* ctbp register, V850: V850-Regs. (line 131)
+* ctoff pseudo-op, V850: V850 Opcodes. (line 111)
+* ctpc register, V850: V850-Regs. (line 119)
+* ctpsw register, V850: V850-Regs. (line 122)
+* current address: Dot. (line 6)
+* current address, advancing: Org. (line 6)
+* D10V @word modifier: D10V-Word. (line 6)
+* D10V addressing modes: D10V-Addressing. (line 6)
+* D10V floating point: D10V-Float. (line 6)
+* D10V line comment character: D10V-Chars. (line 6)
+* D10V opcode summary: D10V-Opcodes. (line 6)
+* D10V optimization: Overview. (line 591)
+* D10V options: D10V-Opts. (line 6)
+* D10V registers: D10V-Regs. (line 6)
+* D10V size modifiers: D10V-Size. (line 6)
+* D10V sub-instruction ordering: D10V-Chars. (line 14)
+* D10V sub-instructions: D10V-Subs. (line 6)
+* D10V support: D10V-Dependent. (line 6)
+* D10V syntax: D10V-Syntax. (line 6)
+* D30V addressing modes: D30V-Addressing. (line 6)
+* D30V floating point: D30V-Float. (line 6)
+* D30V Guarded Execution: D30V-Guarded. (line 6)
+* D30V line comment character: D30V-Chars. (line 6)
+* D30V nops: Overview. (line 599)
+* D30V nops after 32-bit multiply: Overview. (line 602)
+* D30V opcode summary: D30V-Opcodes. (line 6)
+* D30V optimization: Overview. (line 596)
+* D30V options: D30V-Opts. (line 6)
+* D30V registers: D30V-Regs. (line 6)
+* D30V size modifiers: D30V-Size. (line 6)
+* D30V sub-instruction ordering: D30V-Chars. (line 14)
+* D30V sub-instructions: D30V-Subs. (line 6)
+* D30V support: D30V-Dependent. (line 6)
+* D30V syntax: D30V-Syntax. (line 6)
+* data alignment on SPARC: Sparc-Aligned-Data. (line 6)
+* data and text sections, joining: R. (line 6)
+* data directive: Data. (line 6)
+* data directive, TIC54X: TIC54X-Directives. (line 61)
+* data relocations, ARM: ARM-Relocations. (line 6)
+* data section: Ld Sections. (line 9)
+* data1 directive, M680x0: M68K-Directives. (line 9)
+* data2 directive, M680x0: M68K-Directives. (line 12)
+* datalabel, SH64: SH64-Addressing. (line 16)
+* dbpc register, V850: V850-Regs. (line 125)
+* dbpsw register, V850: V850-Regs. (line 128)
+* DCCM RAM Configuration Register, ARC: ARC-Regs. (line 102)
+* debuggers, and symbol order: Symbols. (line 10)
+* debugging COFF symbols: Def. (line 6)
+* DEC syntax: PDP-11-Syntax. (line 6)
+* decimal integers: Integers. (line 12)
+* def directive: Def. (line 6)
+* def directive, TIC54X: TIC54X-Directives. (line 103)
+* density instructions: Density Instructions.
+ (line 6)
+* dependency tracking: MD. (line 6)
+* deprecated directives: Deprecated. (line 6)
+* desc directive: Desc. (line 6)
+* descriptor, of a.out symbol: Symbol Desc. (line 6)
+* dfloat directive, VAX: VAX-directives. (line 10)
+* difference tables altered: Word. (line 12)
+* difference tables, warning: K. (line 6)
+* differences, mmixal: MMIX-mmixal. (line 6)
+* dim directive: Dim. (line 6)
+* directives and instructions: Statements. (line 20)
+* directives for PowerPC: PowerPC-Pseudo. (line 6)
+* directives for SCORE: SCORE-Pseudo. (line 6)
+* directives, Blackfin: Blackfin Directives.
+ (line 6)
+* directives, M32R: M32R-Directives. (line 6)
+* directives, M680x0: M68K-Directives. (line 6)
+* directives, machine independent: Pseudo Ops. (line 6)
+* directives, Xtensa: Xtensa Directives. (line 6)
+* directives, Z8000: Z8000 Directives. (line 6)
+* Disable floating-point instructions: MIPS Floating-Point.
+ (line 6)
+* Disable single-precision floating-point operations: MIPS Floating-Point.
+ (line 12)
+* displacement sizing character, VAX: VAX-operands. (line 12)
+* dollar local symbols: Symbol Names. (line 114)
+* dot (symbol): Dot. (line 6)
+* double directive: Double. (line 6)
+* double directive, i386: i386-Float. (line 14)
+* double directive, M680x0: M68K-Float. (line 14)
+* double directive, M68HC11: M68HC11-Float. (line 14)
+* double directive, RX: RX-Float. (line 11)
+* double directive, TIC54X: TIC54X-Directives. (line 64)
+* double directive, VAX: VAX-float. (line 15)
+* double directive, x86-64: i386-Float. (line 14)
+* double directive, XGATE: XGATE-Float. (line 13)
+* doublequote (\"): Strings. (line 43)
+* drlist directive, TIC54X: TIC54X-Directives. (line 73)
+* drnolist directive, TIC54X: TIC54X-Directives. (line 73)
+* dual directive, i860: Directives-i860. (line 6)
+* dword directive, Nios II: Nios II Directives. (line 16)
+* EB command line option, Nios II: Nios II Options. (line 23)
+* ecr register, V850: V850-Regs. (line 113)
+* eight-byte integer: Quad. (line 9)
+* eipc register, V850: V850-Regs. (line 101)
+* eipsw register, V850: V850-Regs. (line 104)
+* eject directive: Eject. (line 6)
+* EL command line option, Nios II: Nios II Options. (line 26)
+* ELF symbol type: Type. (line 22)
+* else directive: Else. (line 6)
+* elseif directive: Elseif. (line 6)
+* empty expressions: Empty Exprs. (line 6)
+* emsg directive, TIC54X: TIC54X-Directives. (line 77)
+* emulation: Overview. (line 1029)
+* encoding options, i386: i386-Mnemonics. (line 35)
+* encoding options, x86-64: i386-Mnemonics. (line 35)
+* end directive: End. (line 6)
+* enddual directive, i860: Directives-i860. (line 11)
+* endef directive: Endef. (line 6)
+* endfunc directive: Endfunc. (line 6)
+* endianness, MIPS: Overview. (line 828)
+* endianness, PJ: Overview. (line 731)
+* endif directive: Endif. (line 6)
+* endloop directive, TIC54X: TIC54X-Directives. (line 143)
+* endm directive: Macro. (line 138)
+* endm directive, TIC54X: TIC54X-Directives. (line 153)
+* endstruct directive, TIC54X: TIC54X-Directives. (line 216)
+* endunion directive, TIC54X: TIC54X-Directives. (line 250)
+* environment settings, TIC54X: TIC54X-Env. (line 6)
+* EOF, newline must precede: Statements. (line 14)
+* ep register, V850: V850-Regs. (line 95)
+* Epiphany line comment character: Epiphany-Chars. (line 6)
+* Epiphany line separator: Epiphany-Chars. (line 14)
+* Epiphany options: Epiphany Options. (line 6)
+* Epiphany support: Epiphany-Dependent. (line 6)
+* equ directive: Equ. (line 6)
+* equ directive, TIC54X: TIC54X-Directives. (line 191)
+* equiv directive: Equiv. (line 6)
+* eqv directive: Eqv. (line 6)
+* err directive: Err. (line 6)
+* error directive: Error. (line 6)
+* error messages: Errors. (line 6)
+* error on valid input: Bug Criteria. (line 12)
+* errors, caused by warnings: W. (line 16)
+* errors, continuing after: Z. (line 6)
+* ESA/390 floating point (IEEE): ESA/390 Floating Point.
+ (line 6)
+* ESA/390 support: ESA/390-Dependent. (line 6)
+* ESA/390 Syntax: ESA/390 Options. (line 8)
+* ESA/390-only directives: ESA/390 Directives. (line 12)
+* escape codes, character: Strings. (line 15)
+* eval directive, TIC54X: TIC54X-Directives. (line 24)
+* even: Z8000 Directives. (line 58)
+* even directive, M680x0: M68K-Directives. (line 15)
+* even directive, TIC54X: TIC54X-Directives. (line 6)
+* Exception Cause Register, ARC: ARC-Regs. (line 64)
+* Exception Return Address, ARC: ARC-Regs. (line 77)
+* exitm directive: Macro. (line 141)
+* expr (internal section): As Sections. (line 17)
+* expression arguments: Arguments. (line 6)
+* expressions: Expressions. (line 6)
+* expressions, comparison: Infix Ops. (line 55)
+* expressions, empty: Empty Exprs. (line 6)
+* expressions, integer: Integer Exprs. (line 6)
+* extAuxRegister directive, ARC: ARC Directives. (line 106)
+* extCondCode directive, ARC: ARC Directives. (line 128)
+* extCoreRegister directive, ARC: ARC Directives. (line 139)
+* extend directive M680x0: M68K-Float. (line 17)
+* extend directive M68HC11: M68HC11-Float. (line 17)
+* extend directive XGATE: XGATE-Float. (line 16)
+* extended directive, i960: Directives-i960. (line 13)
+* extension core registers, ARC: ARC-Regs. (line 38)
+* extern directive: Extern. (line 6)
+* extInstruction directive, ARC: ARC Directives. (line 167)
+* fail directive: Fail. (line 6)
+* far_mode directive, TIC54X: TIC54X-Directives. (line 82)
+* faster processing (-f): f. (line 6)
+* fatal signal: Bug Criteria. (line 9)
+* fclist directive, TIC54X: TIC54X-Directives. (line 87)
+* fcnolist directive, TIC54X: TIC54X-Directives. (line 87)
+* fepc register, V850: V850-Regs. (line 107)
+* fepsw register, V850: V850-Regs. (line 110)
+* ffloat directive, VAX: VAX-directives. (line 14)
+* field directive, TIC54X: TIC54X-Directives. (line 91)
+* file directive: File. (line 6)
+* file directive, MSP 430: MSP430 Directives. (line 6)
+* file name, logical: File. (line 13)
+* file names and line numbers, in warnings/errors: Errors. (line 16)
+* files, including: Include. (line 6)
+* files, input: Input Files. (line 6)
+* fill directive: Fill. (line 6)
+* filling memory <1>: Skip. (line 6)
+* filling memory: Space. (line 6)
+* filling memory with zero bytes: Zero. (line 6)
+* FLIX syntax: Xtensa Syntax. (line 6)
+* float directive: Float. (line 6)
+* float directive, i386: i386-Float. (line 14)
+* float directive, M680x0: M68K-Float. (line 11)
+* float directive, M68HC11: M68HC11-Float. (line 11)
+* float directive, RX: RX-Float. (line 8)
+* float directive, TIC54X: TIC54X-Directives. (line 64)
+* float directive, VAX: VAX-float. (line 15)
+* float directive, x86-64: i386-Float. (line 14)
+* float directive, XGATE: XGATE-Float. (line 10)
+* floating point numbers: Flonums. (line 6)
+* floating point numbers (double): Double. (line 6)
+* floating point numbers (single) <1>: Single. (line 6)
+* floating point numbers (single): Float. (line 6)
+* floating point, AArch64 (IEEE): AArch64 Floating Point.
+ (line 6)
+* floating point, Alpha (IEEE): Alpha Floating Point.
+ (line 6)
+* floating point, ARM (IEEE): ARM Floating Point. (line 6)
+* floating point, D10V: D10V-Float. (line 6)
+* floating point, D30V: D30V-Float. (line 6)
+* floating point, ESA/390 (IEEE): ESA/390 Floating Point.
+ (line 6)
+* floating point, H8/300 (IEEE): H8/300 Floating Point.
+ (line 6)
+* floating point, HPPA (IEEE): HPPA Floating Point.
+ (line 6)
+* floating point, i386: i386-Float. (line 6)
+* floating point, i960 (IEEE): Floating Point-i960.
+ (line 6)
+* floating point, M680x0: M68K-Float. (line 6)
+* floating point, M68HC11: M68HC11-Float. (line 6)
+* floating point, MSP 430 (IEEE): MSP430 Floating Point.
+ (line 6)
+* floating point, RX: RX-Float. (line 6)
+* floating point, s390: s390 Floating Point.
+ (line 6)
+* floating point, SH (IEEE): SH Floating Point. (line 6)
+* floating point, SPARC (IEEE): Sparc-Float. (line 6)
+* floating point, V850 (IEEE): V850 Floating Point.
+ (line 6)
+* floating point, VAX: VAX-float. (line 6)
+* floating point, x86-64: i386-Float. (line 6)
+* floating point, XGATE: XGATE-Float. (line 6)
+* floating point, Z80: Z80 Floating Point. (line 6)
+* flonums: Flonums. (line 6)
+* format of error messages: Errors. (line 38)
+* format of warning messages: Errors. (line 12)
+* formfeed (\f): Strings. (line 18)
+* frame pointer, ARC: ARC-Regs. (line 17)
+* func directive: Func. (line 6)
+* functions, in expressions: Operators. (line 6)
+* gbr960, i960 postprocessor: Options-i960. (line 40)
+* gfloat directive, VAX: VAX-directives. (line 18)
+* global: Z8000 Directives. (line 21)
+* global directive: Global. (line 6)
+* global directive, TIC54X: TIC54X-Directives. (line 103)
+* global pointer, ARC: ARC-Regs. (line 14)
+* got directive, Nios II: Nios II Relocations.
+ (line 38)
+* got_hiadj directive, Nios II: Nios II Relocations.
+ (line 38)
+* got_lo directive, Nios II: Nios II Relocations.
+ (line 38)
+* gotoff directive, Nios II: Nios II Relocations.
+ (line 38)
+* gotoff_hiadj directive, Nios II: Nios II Relocations.
+ (line 38)
+* gotoff_lo directive, Nios II: Nios II Relocations.
+ (line 38)
+* gp register, MIPS: MIPS Small Data. (line 6)
+* gp register, V850: V850-Regs. (line 17)
+* gprel directive, Nios II: Nios II Relocations.
+ (line 26)
+* grouping data: Sub-Sections. (line 6)
+* H8/300 addressing modes: H8/300-Addressing. (line 6)
+* H8/300 floating point (IEEE): H8/300 Floating Point.
+ (line 6)
+* H8/300 line comment character: H8/300-Chars. (line 6)
+* H8/300 line separator: H8/300-Chars. (line 8)
+* H8/300 machine directives (none): H8/300 Directives. (line 6)
+* H8/300 opcode summary: H8/300 Opcodes. (line 6)
+* H8/300 options: H8/300 Options. (line 6)
+* H8/300 registers: H8/300-Regs. (line 6)
+* H8/300 size suffixes: H8/300 Opcodes. (line 163)
+* H8/300 support: H8/300-Dependent. (line 6)
+* H8/300H, assembling for: H8/300 Directives. (line 8)
+* half directive, Nios II: Nios II Directives. (line 10)
+* half directive, SPARC: Sparc-Directives. (line 17)
+* half directive, TIC54X: TIC54X-Directives. (line 111)
+* hex character code (\XD...): Strings. (line 36)
+* hexadecimal integers: Integers. (line 15)
+* hexadecimal prefix, Z80: Z80-Chars. (line 15)
+* hfloat directive, VAX: VAX-directives. (line 22)
+* hi directive, Nios II: Nios II Relocations.
+ (line 20)
+* hi pseudo-op, V850: V850 Opcodes. (line 33)
+* hi0 pseudo-op, V850: V850 Opcodes. (line 10)
+* hiadj directive, Nios II: Nios II Relocations.
+ (line 6)
+* hidden directive: Hidden. (line 6)
+* high directive, M32R: M32R-Directives. (line 18)
+* hilo pseudo-op, V850: V850 Opcodes. (line 55)
+* HPPA directives not supported: HPPA Directives. (line 11)
+* HPPA floating point (IEEE): HPPA Floating Point.
+ (line 6)
+* HPPA Syntax: HPPA Options. (line 8)
+* HPPA-only directives: HPPA Directives. (line 24)
+* hword directive: hword. (line 6)
+* i370 support: ESA/390-Dependent. (line 6)
+* i386 16-bit code: i386-16bit. (line 6)
+* i386 arch directive: i386-Arch. (line 6)
+* i386 att_syntax pseudo op: i386-Variations. (line 6)
+* i386 conversion instructions: i386-Mnemonics. (line 40)
+* i386 floating point: i386-Float. (line 6)
+* i386 immediate operands: i386-Variations. (line 15)
+* i386 instruction naming: i386-Mnemonics. (line 9)
+* i386 instruction prefixes: i386-Prefixes. (line 6)
+* i386 intel_syntax pseudo op: i386-Variations. (line 6)
+* i386 jump optimization: i386-Jumps. (line 6)
+* i386 jump, call, return: i386-Variations. (line 41)
+* i386 jump/call operands: i386-Variations. (line 15)
+* i386 line comment character: i386-Chars. (line 6)
+* i386 line separator: i386-Chars. (line 18)
+* i386 memory references: i386-Memory. (line 6)
+* i386 mnemonic compatibility: i386-Mnemonics. (line 65)
+* i386 mul, imul instructions: i386-Notes. (line 6)
+* i386 options: i386-Options. (line 6)
+* i386 register operands: i386-Variations. (line 15)
+* i386 registers: i386-Regs. (line 6)
+* i386 sections: i386-Variations. (line 47)
+* i386 size suffixes: i386-Variations. (line 29)
+* i386 source, destination operands: i386-Variations. (line 22)
+* i386 support: i386-Dependent. (line 6)
+* i386 syntax compatibility: i386-Variations. (line 6)
+* i80386 support: i386-Dependent. (line 6)
+* i860 line comment character: i860-Chars. (line 6)
+* i860 line separator: i860-Chars. (line 14)
+* i860 machine directives: Directives-i860. (line 6)
+* i860 opcodes: Opcodes for i860. (line 6)
+* i860 support: i860-Dependent. (line 6)
+* i960 architecture options: Options-i960. (line 6)
+* i960 branch recording: Options-i960. (line 22)
+* i960 callj pseudo-opcode: callj-i960. (line 6)
+* i960 compare and jump expansions: Compare-and-branch-i960.
+ (line 13)
+* i960 compare/branch instructions: Compare-and-branch-i960.
+ (line 6)
+* i960 floating point (IEEE): Floating Point-i960.
+ (line 6)
+* i960 line comment character: i960-Chars. (line 6)
+* i960 line separator: i960-Chars. (line 14)
+* i960 machine directives: Directives-i960. (line 6)
+* i960 opcodes: Opcodes for i960. (line 6)
+* i960 options: Options-i960. (line 6)
+* i960 support: i960-Dependent. (line 6)
+* IA-64 line comment character: IA-64-Chars. (line 6)
+* IA-64 line separator: IA-64-Chars. (line 8)
+* IA-64 options: IA-64 Options. (line 6)
+* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6)
+* IA-64 registers: IA-64-Regs. (line 6)
+* IA-64 relocations: IA-64-Relocs. (line 6)
+* IA-64 support: IA-64-Dependent. (line 6)
+* IA-64 Syntax: IA-64 Options. (line 87)
+* ident directive: Ident. (line 6)
+* identifiers, ARM: ARM-Chars. (line 19)
+* identifiers, MSP 430: MSP430-Chars. (line 17)
+* if directive: If. (line 6)
+* ifb directive: If. (line 21)
+* ifc directive: If. (line 25)
+* ifdef directive: If. (line 16)
+* ifeq directive: If. (line 33)
+* ifeqs directive: If. (line 36)
+* ifge directive: If. (line 40)
+* ifgt directive: If. (line 44)
+* ifle directive: If. (line 48)
+* iflt directive: If. (line 52)
+* ifnb directive: If. (line 56)
+* ifnc directive: If. (line 61)
+* ifndef directive: If. (line 65)
+* ifne directive: If. (line 72)
+* ifnes directive: If. (line 76)
+* ifnotdef directive: If. (line 65)
+* immediate character, AArch64: AArch64-Chars. (line 13)
+* immediate character, ARM: ARM-Chars. (line 17)
+* immediate character, M680x0: M68K-Chars. (line 13)
+* immediate character, VAX: VAX-operands. (line 6)
+* immediate fields, relaxation: Xtensa Immediate Relaxation.
+ (line 6)
+* immediate operands, i386: i386-Variations. (line 15)
+* immediate operands, x86-64: i386-Variations. (line 15)
+* imul instruction, i386: i386-Notes. (line 6)
+* imul instruction, x86-64: i386-Notes. (line 6)
+* incbin directive: Incbin. (line 6)
+* include directive: Include. (line 6)
+* include directive search path: I. (line 6)
+* indirect character, VAX: VAX-operands. (line 9)
+* infix operators: Infix Ops. (line 6)
+* inhibiting interrupts, i386: i386-Prefixes. (line 36)
+* input: Input Files. (line 6)
+* input file linenumbers: Input Files. (line 35)
+* instruction aliases, s390: s390 Aliases. (line 6)
+* instruction bundle: Bundle directives. (line 9)
+* instruction expansion, CRIS: CRIS-Expand. (line 6)
+* instruction expansion, MMIX: MMIX-Expand. (line 6)
+* instruction formats, s390: s390 Formats. (line 6)
+* instruction marker, s390: s390 Instruction Marker.
+ (line 6)
+* instruction mnemonics, s390: s390 Mnemonics. (line 6)
+* instruction naming, i386: i386-Mnemonics. (line 9)
+* instruction naming, x86-64: i386-Mnemonics. (line 9)
+* instruction operand modifier, s390: s390 Operand Modifier.
+ (line 6)
+* instruction operands, s390: s390 Operands. (line 6)
+* instruction prefixes, i386: i386-Prefixes. (line 6)
+* instruction set, M680x0: M68K-opcodes. (line 6)
+* instruction set, M68HC11: M68HC11-opcodes. (line 6)
+* instruction set, XGATE: XGATE-opcodes. (line 6)
+* instruction summary, AVR: AVR Opcodes. (line 6)
+* instruction summary, D10V: D10V-Opcodes. (line 6)
+* instruction summary, D30V: D30V-Opcodes. (line 6)
+* instruction summary, H8/300: H8/300 Opcodes. (line 6)
+* instruction summary, LM32: LM32 Opcodes. (line 6)
+* instruction summary, SH: SH Opcodes. (line 6)
+* instruction summary, SH64: SH64 Opcodes. (line 6)
+* instruction summary, Z8000: Z8000 Opcodes. (line 6)
+* instruction syntax, s390: s390 Syntax. (line 6)
+* instructions and directives: Statements. (line 20)
+* int directive: Int. (line 6)
+* int directive, H8/300: H8/300 Directives. (line 6)
+* int directive, i386: i386-Float. (line 21)
+* int directive, TIC54X: TIC54X-Directives. (line 111)
+* int directive, x86-64: i386-Float. (line 21)
+* integer expressions: Integer Exprs. (line 6)
+* integer, 16-byte: Octa. (line 6)
+* integer, 8-byte: Quad. (line 9)
+* integers: Integers. (line 6)
+* integers, 16-bit: hword. (line 6)
+* integers, 32-bit: Int. (line 6)
+* integers, binary: Integers. (line 6)
+* integers, decimal: Integers. (line 12)
+* integers, hexadecimal: Integers. (line 15)
+* integers, octal: Integers. (line 9)
+* integers, one byte: Byte. (line 6)
+* intel_syntax pseudo op, i386: i386-Variations. (line 6)
+* intel_syntax pseudo op, x86-64: i386-Variations. (line 6)
+* internal assembler sections: As Sections. (line 6)
+* internal directive: Internal. (line 6)
+* interrupt link register, ARC: ARC-Regs. (line 27)
+* Interrupt Vector Base address, ARC: ARC-Regs. (line 67)
+* invalid input: Bug Criteria. (line 14)
+* invocation summary: Overview. (line 6)
+* IP2K architecture options: IP2K-Opts. (line 9)
+* IP2K line comment character: IP2K-Chars. (line 6)
+* IP2K line separator: IP2K-Chars. (line 14)
+* IP2K options: IP2K-Opts. (line 6)
+* IP2K support: IP2K-Dependent. (line 6)
+* irp directive: Irp. (line 6)
+* irpc directive: Irpc. (line 6)
+* ISA options, SH64: SH64 Options. (line 6)
+* joining text and data sections: R. (line 6)
+* jump instructions, i386: i386-Mnemonics. (line 59)
+* jump instructions, relaxation: Xtensa Jump Relaxation.
+ (line 6)
+* jump instructions, x86-64: i386-Mnemonics. (line 59)
+* jump optimization, i386: i386-Jumps. (line 6)
+* jump optimization, x86-64: i386-Jumps. (line 6)
+* jump/call operands, i386: i386-Variations. (line 15)
+* jump/call operands, x86-64: i386-Variations. (line 15)
+* L16SI instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 23)
+* L16UI instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 23)
+* L32I instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 23)
+* L8UI instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 23)
+* label (:): Statements. (line 31)
+* label directive, TIC54X: TIC54X-Directives. (line 123)
+* labels: Labels. (line 6)
+* lcomm directive <1>: ARC Directives. (line 9)
+* lcomm directive: Lcomm. (line 6)
+* lcomm directive, COFF: i386-Directives. (line 6)
+* lcommon directive, ARC: ARC Directives. (line 24)
+* ld: Object. (line 15)
+* ldouble directive M680x0: M68K-Float. (line 17)
+* ldouble directive M68HC11: M68HC11-Float. (line 17)
+* ldouble directive XGATE: XGATE-Float. (line 16)
+* ldouble directive, TIC54X: TIC54X-Directives. (line 64)
+* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9)
+* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15)
+* leafproc directive, i960: Directives-i960. (line 18)
+* length directive, TIC54X: TIC54X-Directives. (line 127)
+* length of symbols: Symbol Intro. (line 19)
+* level 1 interrupt link register, ARC: ARC-Regs. (line 23)
+* level 2 interrupt link register, ARC: ARC-Regs. (line 31)
+* lflags directive (ignored): Lflags. (line 6)
+* line: ARC-Chars. (line 30)
+* line comment character: Comments. (line 19)
+* line comment character, AArch64: AArch64-Chars. (line 6)
+* line comment character, Alpha: Alpha-Chars. (line 6)
+* line comment character, ARC: ARC-Chars. (line 11)
+* line comment character, ARM: ARM-Chars. (line 6)
+* line comment character, AVR: AVR-Chars. (line 6)
+* line comment character, CR16: CR16-Chars. (line 6)
+* line comment character, D10V: D10V-Chars. (line 6)
+* line comment character, D30V: D30V-Chars. (line 6)
+* line comment character, Epiphany: Epiphany-Chars. (line 6)
+* line comment character, H8/300: H8/300-Chars. (line 6)
+* line comment character, i386: i386-Chars. (line 6)
+* line comment character, i860: i860-Chars. (line 6)
+* line comment character, i960: i960-Chars. (line 6)
+* line comment character, IA-64: IA-64-Chars. (line 6)
+* line comment character, IP2K: IP2K-Chars. (line 6)
+* line comment character, LM32: LM32-Chars. (line 6)
+* line comment character, M32C: M32C-Chars. (line 6)
+* line comment character, M680x0: M68K-Chars. (line 6)
+* line comment character, M68HC11: M68HC11-Syntax. (line 17)
+* line comment character, Meta: Meta-Chars. (line 6)
+* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6)
+* line comment character, MIPS: MIPS-Chars. (line 6)
+* line comment character, MSP 430: MSP430-Chars. (line 6)
+* line comment character, Nios II: Nios II Chars. (line 6)
+* line comment character, NS32K: NS32K-Chars. (line 6)
+* line comment character, PJ: PJ-Chars. (line 6)
+* line comment character, PowerPC: PowerPC-Chars. (line 6)
+* line comment character, RL78: RL78-Chars. (line 6)
+* line comment character, RX: RX-Chars. (line 6)
+* line comment character, s390: s390 Characters. (line 6)
+* line comment character, SCORE: SCORE-Chars. (line 6)
+* line comment character, SH: SH-Chars. (line 6)
+* line comment character, SH64: SH64-Chars. (line 6)
+* line comment character, Sparc: Sparc-Chars. (line 6)
+* line comment character, TIC54X: TIC54X-Chars. (line 6)
+* line comment character, TIC6X: TIC6X Syntax. (line 6)
+* line comment character, V850: V850-Chars. (line 6)
+* line comment character, VAX: VAX-Chars. (line 6)
+* line comment character, Visium: Visium Characters. (line 6)
+* line comment character, XGATE: XGATE-Syntax. (line 16)
+* line comment character, XStormy16: XStormy16-Chars. (line 6)
+* line comment character, Z80: Z80-Chars. (line 6)
+* line comment character, Z8000: Z8000-Chars. (line 6)
+* line comment characters, CRIS: CRIS-Chars. (line 6)
+* line comment characters, MMIX: MMIX-Chars. (line 6)
+* line directive: Line. (line 6)
+* line directive, MSP 430: MSP430 Directives. (line 14)
+* line numbers, in input files: Input Files. (line 35)
+* line separator character: Statements. (line 6)
+* line separator character, Nios II: Nios II Chars. (line 6)
+* line separator, AArch64: AArch64-Chars. (line 10)
+* line separator, Alpha: Alpha-Chars. (line 11)
+* line separator, ARC: ARC-Chars. (line 27)
+* line separator, ARM: ARM-Chars. (line 14)
+* line separator, AVR: AVR-Chars. (line 14)
+* line separator, CR16: CR16-Chars. (line 13)
+* line separator, Epiphany: Epiphany-Chars. (line 14)
+* line separator, H8/300: H8/300-Chars. (line 8)
+* line separator, i386: i386-Chars. (line 18)
+* line separator, i860: i860-Chars. (line 14)
+* line separator, i960: i960-Chars. (line 14)
+* line separator, IA-64: IA-64-Chars. (line 8)
+* line separator, IP2K: IP2K-Chars. (line 14)
+* line separator, LM32: LM32-Chars. (line 12)
+* line separator, M32C: M32C-Chars. (line 14)
+* line separator, M680x0: M68K-Chars. (line 20)
+* line separator, M68HC11: M68HC11-Syntax. (line 27)
+* line separator, Meta: Meta-Chars. (line 8)
+* line separator, MicroBlaze: MicroBlaze-Chars. (line 14)
+* line separator, MIPS: MIPS-Chars. (line 14)
+* line separator, MSP 430: MSP430-Chars. (line 14)
+* line separator, NS32K: NS32K-Chars. (line 18)
+* line separator, PJ: PJ-Chars. (line 14)
+* line separator, PowerPC: PowerPC-Chars. (line 18)
+* line separator, RL78: RL78-Chars. (line 14)
+* line separator, RX: RX-Chars. (line 14)
+* line separator, s390: s390 Characters. (line 13)
+* line separator, SCORE: SCORE-Chars. (line 14)
+* line separator, SH: SH-Chars. (line 8)
+* line separator, SH64: SH64-Chars. (line 13)
+* line separator, Sparc: Sparc-Chars. (line 14)
+* line separator, TIC54X: TIC54X-Chars. (line 17)
+* line separator, TIC6X: TIC6X Syntax. (line 13)
+* line separator, V850: V850-Chars. (line 13)
+* line separator, VAX: VAX-Chars. (line 14)
+* line separator, Visium: Visium Characters. (line 14)
+* line separator, XGATE: XGATE-Syntax. (line 26)
+* line separator, XStormy16: XStormy16-Chars. (line 14)
+* line separator, Z80: Z80-Chars. (line 13)
+* line separator, Z8000: Z8000-Chars. (line 13)
+* lines starting with #: Comments. (line 33)
+* link register, ARC: ARC-Regs. (line 35)
+* linker: Object. (line 15)
+* linker, and assembler: Secs Background. (line 10)
+* linkonce directive: Linkonce. (line 6)
+* list directive: List. (line 6)
+* list directive, TIC54X: TIC54X-Directives. (line 131)
+* listing control, turning off: Nolist. (line 6)
+* listing control, turning on: List. (line 6)
+* listing control: new page: Eject. (line 6)
+* listing control: paper size: Psize. (line 6)
+* listing control: subtitle: Sbttl. (line 6)
+* listing control: title line: Title. (line 6)
+* listings, enabling: a. (line 6)
+* literal directive: Literal Directive. (line 6)
+* literal pool entries, s390: s390 Literal Pool Entries.
+ (line 6)
+* literal_position directive: Literal Position Directive.
+ (line 6)
+* literal_prefix directive: Literal Prefix Directive.
+ (line 6)
+* little endian output, MIPS: Overview. (line 831)
+* little endian output, PJ: Overview. (line 734)
+* little-endian output, MIPS: MIPS Options. (line 13)
+* little-endian output, TIC6X: TIC6X Options. (line 46)
+* LM32 line comment character: LM32-Chars. (line 6)
+* LM32 line separator: LM32-Chars. (line 12)
+* LM32 modifiers: LM32-Modifiers. (line 6)
+* LM32 opcode summary: LM32 Opcodes. (line 6)
+* LM32 options (none): LM32 Options. (line 6)
+* LM32 register names: LM32-Regs. (line 6)
+* LM32 support: LM32-Dependent. (line 6)
+* ln directive: Ln. (line 6)
+* lo directive, Nios II: Nios II Relocations.
+ (line 23)
+* lo pseudo-op, V850: V850 Opcodes. (line 22)
+* loc directive: Loc. (line 6)
+* loc_mark_labels directive: Loc_mark_labels. (line 6)
+* local common symbols: Lcomm. (line 6)
+* local directive: Local. (line 6)
+* local labels: Symbol Names. (line 43)
+* local symbol names: Symbol Names. (line 30)
+* local symbols, retaining in output: L. (line 6)
+* location counter: Dot. (line 6)
+* location counter, advancing: Org. (line 6)
+* location counter, Z80: Z80-Chars. (line 15)
+* logical file name: File. (line 13)
+* logical line number: Line. (line 6)
+* logical line numbers: Comments. (line 33)
+* long directive: Long. (line 6)
+* long directive, i386: i386-Float. (line 21)
+* long directive, TIC54X: TIC54X-Directives. (line 135)
+* long directive, x86-64: i386-Float. (line 21)
+* longcall pseudo-op, V850: V850 Opcodes. (line 123)
+* longcalls directive: Longcalls Directive.
+ (line 6)
+* longjump pseudo-op, V850: V850 Opcodes. (line 129)
+* loop counter, ARC: ARC-Regs. (line 41)
+* loop directive, TIC54X: TIC54X-Directives. (line 143)
+* LOOP instructions, alignment: Xtensa Automatic Alignment.
+ (line 6)
+* low directive, M32R: M32R-Directives. (line 9)
+* lp register, V850: V850-Regs. (line 98)
+* lval: Z8000 Directives. (line 27)
+* LWP, i386: i386-LWP. (line 6)
+* LWP, x86-64: i386-LWP. (line 6)
+* M16C architecture option: M32C-Opts. (line 12)
+* M32C architecture option: M32C-Opts. (line 9)
+* M32C line comment character: M32C-Chars. (line 6)
+* M32C line separator: M32C-Chars. (line 14)
+* M32C modifiers: M32C-Modifiers. (line 6)
+* M32C options: M32C-Opts. (line 6)
+* M32C support: M32C-Dependent. (line 6)
+* M32R architecture options: M32R-Opts. (line 9)
+* M32R directives: M32R-Directives. (line 6)
+* M32R options: M32R-Opts. (line 6)
+* M32R support: M32R-Dependent. (line 6)
+* M32R warnings: M32R-Warnings. (line 6)
+* M680x0 addressing modes: M68K-Syntax. (line 21)
+* M680x0 architecture options: M68K-Opts. (line 98)
+* M680x0 branch improvement: M68K-Branch. (line 6)
+* M680x0 directives: M68K-Directives. (line 6)
+* M680x0 floating point: M68K-Float. (line 6)
+* M680x0 immediate character: M68K-Chars. (line 13)
+* M680x0 line comment character: M68K-Chars. (line 6)
+* M680x0 line separator: M68K-Chars. (line 20)
+* M680x0 opcodes: M68K-opcodes. (line 6)
+* M680x0 options: M68K-Opts. (line 6)
+* M680x0 pseudo-opcodes: M68K-Branch. (line 6)
+* M680x0 size modifiers: M68K-Syntax. (line 8)
+* M680x0 support: M68K-Dependent. (line 6)
+* M680x0 syntax: M68K-Syntax. (line 8)
+* M68HC11 addressing modes: M68HC11-Syntax. (line 30)
+* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6)
+* M68HC11 assembler directive .far: M68HC11-Directives. (line 20)
+* M68HC11 assembler directive .interrupt: M68HC11-Directives.
+ (line 26)
+* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16)
+* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10)
+* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31)
+* M68HC11 assembler directives: M68HC11-Directives. (line 6)
+* M68HC11 branch improvement: M68HC11-Branch. (line 6)
+* M68HC11 floating point: M68HC11-Float. (line 6)
+* M68HC11 line comment character: M68HC11-Syntax. (line 17)
+* M68HC11 line separator: M68HC11-Syntax. (line 27)
+* M68HC11 modifiers: M68HC11-Modifiers. (line 6)
+* M68HC11 opcodes: M68HC11-opcodes. (line 6)
+* M68HC11 options: M68HC11-Opts. (line 6)
+* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6)
+* M68HC11 syntax: M68HC11-Syntax. (line 6)
+* M68HC12 assembler directives: M68HC11-Directives. (line 6)
+* mA6 command line option, ARC: ARC Options. (line 14)
+* mA7 command line option, ARC: ARC Options. (line 39)
+* machine dependencies: Machine Dependencies.
+ (line 6)
+* machine directives, AArch64: AArch64 Directives. (line 6)
+* machine directives, ARC: ARC Directives. (line 6)
+* machine directives, ARM: ARM Directives. (line 6)
+* machine directives, H8/300 (none): H8/300 Directives. (line 6)
+* machine directives, i860: Directives-i860. (line 6)
+* machine directives, i960: Directives-i960. (line 6)
+* machine directives, MSP 430: MSP430 Directives. (line 6)
+* machine directives, Nios II: Nios II Directives. (line 6)
+* machine directives, SH: SH Directives. (line 6)
+* machine directives, SH64: SH64 Directives. (line 9)
+* machine directives, SPARC: Sparc-Directives. (line 6)
+* machine directives, TIC54X: TIC54X-Directives. (line 6)
+* machine directives, TIC6X: TIC6X Directives. (line 6)
+* machine directives, TILE-Gx: TILE-Gx Directives. (line 6)
+* machine directives, TILEPro: TILEPro Directives. (line 6)
+* machine directives, V850: V850 Directives. (line 6)
+* machine directives, VAX: VAX-directives. (line 6)
+* machine directives, x86: i386-Directives. (line 6)
+* machine directives, XStormy16: XStormy16 Directives.
+ (line 6)
+* machine independent directives: Pseudo Ops. (line 6)
+* machine instructions (not covered): Manual. (line 14)
+* machine relocations, Nios II: Nios II Relocations.
+ (line 6)
+* machine-independent syntax: Syntax. (line 6)
+* macro directive: Macro. (line 28)
+* macro directive, TIC54X: TIC54X-Directives. (line 153)
+* macros: Macro. (line 6)
+* macros, count executed: Macro. (line 143)
+* Macros, MSP 430: MSP430-Macros. (line 6)
+* macros, TIC54X: TIC54X-Macros. (line 6)
+* make rules: MD. (line 6)
+* manual, structure and purpose: Manual. (line 6)
+* marc600 command line option, ARC: ARC Options. (line 14)
+* mARC601 command line option, ARC: ARC Options. (line 27)
+* mARC700 command line option, ARC: ARC Options. (line 39)
+* march command line option, Nios II: Nios II Options. (line 29)
+* math builtins, TIC54X: TIC54X-Builtins. (line 6)
+* Maximum number of continuation lines: listing. (line 34)
+* mEM command line option, ARC: ARC Options. (line 42)
+* memory references, i386: i386-Memory. (line 6)
+* memory references, x86-64: i386-Memory. (line 6)
+* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6)
+* merging text and data sections: R. (line 6)
+* messages from assembler: Errors. (line 6)
+* Meta architectures: Meta Options. (line 6)
+* Meta line comment character: Meta-Chars. (line 6)
+* Meta line separator: Meta-Chars. (line 8)
+* Meta options: Meta Options. (line 6)
+* Meta registers: Meta-Regs. (line 6)
+* Meta support: Meta-Dependent. (line 6)
+* mHS command line option, ARC: ARC Options. (line 64)
+* MicroBlaze architectures: MicroBlaze-Dependent.
+ (line 6)
+* MicroBlaze directives: MicroBlaze Directives.
+ (line 6)
+* MicroBlaze line comment character: MicroBlaze-Chars. (line 6)
+* MicroBlaze line separator: MicroBlaze-Chars. (line 14)
+* MicroBlaze support: MicroBlaze-Dependent.
+ (line 13)
+* minus, permitted arguments: Infix Ops. (line 49)
+* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options.
+ (line 18)
+* MIPS architecture options: MIPS Options. (line 29)
+* MIPS big-endian output: MIPS Options. (line 13)
+* MIPS CPU override: MIPS ISA. (line 19)
+* MIPS directives to override command line options: MIPS assembly options.
+ (line 6)
+* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 21)
+* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 26)
+* MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 32)
+* MIPS endianness: Overview. (line 828)
+* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 58)
+* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings.
+ (line 6)
+* MIPS ISA: Overview. (line 834)
+* MIPS ISA override: MIPS ISA. (line 6)
+* MIPS line comment character: MIPS-Chars. (line 6)
+* MIPS line separator: MIPS-Chars. (line 14)
+* MIPS little-endian output: MIPS Options. (line 13)
+* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 43)
+* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 16)
+* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 6)
+* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 38)
+* MIPS option stack: MIPS Option Stack. (line 6)
+* MIPS processor: MIPS-Dependent. (line 6)
+* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 48)
+* MIT: M68K-Syntax. (line 6)
+* mlib directive, TIC54X: TIC54X-Directives. (line 159)
+* mlist directive, TIC54X: TIC54X-Directives. (line 164)
+* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131)
+* MMIX assembler directive BYTE: MMIX-Pseudos. (line 97)
+* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131)
+* MMIX assembler directive GREG: MMIX-Pseudos. (line 50)
+* MMIX assembler directive IS: MMIX-Pseudos. (line 42)
+* MMIX assembler directive LOC: MMIX-Pseudos. (line 7)
+* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28)
+* MMIX assembler directive OCTA: MMIX-Pseudos. (line 108)
+* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120)
+* MMIX assembler directive TETRA: MMIX-Pseudos. (line 108)
+* MMIX assembler directive WYDE: MMIX-Pseudos. (line 108)
+* MMIX assembler directives: MMIX-Pseudos. (line 6)
+* MMIX line comment characters: MMIX-Chars. (line 6)
+* MMIX options: MMIX-Opts. (line 6)
+* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131)
+* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97)
+* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131)
+* MMIX pseudo-op GREG: MMIX-Pseudos. (line 50)
+* MMIX pseudo-op IS: MMIX-Pseudos. (line 42)
+* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7)
+* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28)
+* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108)
+* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120)
+* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108)
+* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108)
+* MMIX pseudo-ops: MMIX-Pseudos. (line 6)
+* MMIX register names: MMIX-Regs. (line 6)
+* MMIX support: MMIX-Dependent. (line 6)
+* mmixal differences: MMIX-mmixal. (line 6)
+* mmregs directive, TIC54X: TIC54X-Directives. (line 169)
+* mmsg directive, TIC54X: TIC54X-Directives. (line 77)
+* MMX, i386: i386-SIMD. (line 6)
+* MMX, x86-64: i386-SIMD. (line 6)
+* mnemonic compatibility, i386: i386-Mnemonics. (line 65)
+* mnemonic suffixes, i386: i386-Variations. (line 29)
+* mnemonic suffixes, x86-64: i386-Variations. (line 29)
+* mnemonics for opcodes, VAX: VAX-opcodes. (line 6)
+* mnemonics, AVR: AVR Opcodes. (line 6)
+* mnemonics, D10V: D10V-Opcodes. (line 6)
+* mnemonics, D30V: D30V-Opcodes. (line 6)
+* mnemonics, H8/300: H8/300 Opcodes. (line 6)
+* mnemonics, LM32: LM32 Opcodes. (line 6)
+* mnemonics, SH: SH Opcodes. (line 6)
+* mnemonics, SH64: SH64 Opcodes. (line 6)
+* mnemonics, Z8000: Z8000 Opcodes. (line 6)
+* mnolist directive, TIC54X: TIC54X-Directives. (line 164)
+* mnps400 command line option, ARC: ARC Options. (line 79)
+* modifiers, M32C: M32C-Modifiers. (line 6)
+* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6)
+* MOVI instructions, relaxation: Xtensa Immediate Relaxation.
+ (line 12)
+* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations.
+ (line 6)
+* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21)
+* MRI compatibility mode: M. (line 6)
+* mri directive: MRI. (line 6)
+* MRI mode, temporarily: MRI. (line 6)
+* MSP 430 floating point (IEEE): MSP430 Floating Point.
+ (line 6)
+* MSP 430 identifiers: MSP430-Chars. (line 17)
+* MSP 430 line comment character: MSP430-Chars. (line 6)
+* MSP 430 line separator: MSP430-Chars. (line 14)
+* MSP 430 machine directives: MSP430 Directives. (line 6)
+* MSP 430 macros: MSP430-Macros. (line 6)
+* MSP 430 opcodes: MSP430 Opcodes. (line 6)
+* MSP 430 options (none): MSP430 Options. (line 6)
+* MSP 430 profiling capability: MSP430 Profiling Capability.
+ (line 6)
+* MSP 430 register names: MSP430-Regs. (line 6)
+* MSP 430 support: MSP430-Dependent. (line 6)
+* MSP430 Assembler Extensions: MSP430-Ext. (line 6)
+* mul instruction, i386: i386-Notes. (line 6)
+* mul instruction, x86-64: i386-Notes. (line 6)
+* N32K support: NS32K-Dependent. (line 6)
+* name: Z8000 Directives. (line 18)
+* named section: Section. (line 6)
+* named sections: Ld Sections. (line 8)
+* names, symbol: Symbol Names. (line 6)
+* naming object file: o. (line 6)
+* NDS32 options: NDS32 Options. (line 6)
+* NDS32 processor: NDS32-Dependent. (line 6)
+* new page, in listings: Eject. (line 6)
+* newblock directive, TIC54X: TIC54X-Directives. (line 175)
+* newline (\n): Strings. (line 21)
+* newline, required at file end: Statements. (line 14)
+* Nios II line comment character: Nios II Chars. (line 6)
+* Nios II line separator character: Nios II Chars. (line 6)
+* Nios II machine directives: Nios II Directives. (line 6)
+* Nios II machine relocations: Nios II Relocations.
+ (line 6)
+* Nios II opcodes: Nios II Opcodes. (line 6)
+* Nios II options: Nios II Options. (line 6)
+* Nios II support: NiosII-Dependent. (line 6)
+* Nios support: NiosII-Dependent. (line 6)
+* no-absolute-literals directive: Absolute Literals Directive.
+ (line 6)
+* no-longcalls directive: Longcalls Directive.
+ (line 6)
+* no-relax command line option, Nios II: Nios II Options. (line 20)
+* no-schedule directive: Schedule Directive. (line 6)
+* no-transform directive: Transform Directive.
+ (line 6)
+* nolist directive: Nolist. (line 6)
+* nolist directive, TIC54X: TIC54X-Directives. (line 131)
+* NOP pseudo op, ARM: ARM Opcodes. (line 9)
+* notes for Alpha: Alpha Notes. (line 6)
+* NS32K line comment character: NS32K-Chars. (line 6)
+* NS32K line separator: NS32K-Chars. (line 18)
+* null-terminated strings: Asciz. (line 6)
+* number constants: Numbers. (line 6)
+* number of macros executed: Macro. (line 143)
+* numbered subsections: Sub-Sections. (line 6)
+* numbers, 16-bit: hword. (line 6)
+* numeric values: Expressions. (line 6)
+* nword directive, SPARC: Sparc-Directives. (line 20)
+* object attributes: Object Attributes. (line 6)
+* object file: Object. (line 6)
+* object file format: Object Formats. (line 6)
+* object file name: o. (line 6)
+* object file, after errors: Z. (line 6)
+* obsolescent directives: Deprecated. (line 6)
+* octa directive: Octa. (line 6)
+* octal character code (\DDD): Strings. (line 30)
+* octal integers: Integers. (line 9)
+* offset directive: Offset. (line 6)
+* offset directive, V850: V850 Directives. (line 6)
+* opcode mnemonics, VAX: VAX-opcodes. (line 6)
+* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6)
+* opcode names, TILEPro: TILEPro Opcodes. (line 6)
+* opcode names, Xtensa: Xtensa Opcodes. (line 6)
+* opcode summary, AVR: AVR Opcodes. (line 6)
+* opcode summary, D10V: D10V-Opcodes. (line 6)
+* opcode summary, D30V: D30V-Opcodes. (line 6)
+* opcode summary, H8/300: H8/300 Opcodes. (line 6)
+* opcode summary, LM32: LM32 Opcodes. (line 6)
+* opcode summary, SH: SH Opcodes. (line 6)
+* opcode summary, SH64: SH64 Opcodes. (line 6)
+* opcode summary, Z8000: Z8000 Opcodes. (line 6)
+* opcodes for AArch64: AArch64 Opcodes. (line 6)
+* opcodes for ARC: ARC Opcodes. (line 6)
+* opcodes for ARM: ARM Opcodes. (line 6)
+* opcodes for MSP 430: MSP430 Opcodes. (line 6)
+* opcodes for Nios II: Nios II Opcodes. (line 6)
+* opcodes for V850: V850 Opcodes. (line 6)
+* opcodes, i860: Opcodes for i860. (line 6)
+* opcodes, i960: Opcodes for i960. (line 6)
+* opcodes, M680x0: M68K-opcodes. (line 6)
+* opcodes, M68HC11: M68HC11-opcodes. (line 6)
+* operand delimiters, i386: i386-Variations. (line 15)
+* operand delimiters, x86-64: i386-Variations. (line 15)
+* operand notation, VAX: VAX-operands. (line 6)
+* operands in expressions: Arguments. (line 6)
+* operator precedence: Infix Ops. (line 11)
+* operators, in expressions: Operators. (line 6)
+* operators, permitted arguments: Infix Ops. (line 6)
+* optimization, D10V: Overview. (line 591)
+* optimization, D30V: Overview. (line 596)
+* optimizations: Xtensa Optimizations.
+ (line 6)
+* option directive, TIC54X: TIC54X-Directives. (line 179)
+* option summary: Overview. (line 6)
+* options for AArch64 (none): AArch64 Options. (line 6)
+* options for Alpha: Alpha Options. (line 6)
+* options for ARC: ARC Options. (line 6)
+* options for ARM (none): ARM Options. (line 6)
+* options for AVR (none): AVR Options. (line 6)
+* options for Blackfin (none): Blackfin Options. (line 6)
+* options for i386: i386-Options. (line 6)
+* options for IA-64: IA-64 Options. (line 6)
+* options for LM32 (none): LM32 Options. (line 6)
+* options for Meta: Meta Options. (line 6)
+* options for MSP430 (none): MSP430 Options. (line 6)
+* options for NDS32: NDS32 Options. (line 6)
+* options for Nios II: Nios II Options. (line 6)
+* options for PDP-11: PDP-11-Options. (line 6)
+* options for PowerPC: PowerPC-Opts. (line 6)
+* options for s390: s390 Options. (line 6)
+* options for SCORE: SCORE-Opts. (line 6)
+* options for SPARC: Sparc-Opts. (line 6)
+* options for TIC6X: TIC6X Options. (line 6)
+* options for V850 (none): V850 Options. (line 6)
+* options for VAX/VMS: VAX-Opts. (line 42)
+* options for Visium: Visium Options. (line 6)
+* options for x86-64: i386-Options. (line 6)
+* options for Z80: Z80 Options. (line 6)
+* options, all versions of assembler: Invoking. (line 6)
+* options, command line: Command Line. (line 13)
+* options, CRIS: CRIS-Opts. (line 6)
+* options, D10V: D10V-Opts. (line 6)
+* options, D30V: D30V-Opts. (line 6)
+* options, Epiphany: Epiphany Options. (line 6)
+* options, H8/300: H8/300 Options. (line 6)
+* options, i960: Options-i960. (line 6)
+* options, IP2K: IP2K-Opts. (line 6)
+* options, M32C: M32C-Opts. (line 6)
+* options, M32R: M32R-Opts. (line 6)
+* options, M680x0: M68K-Opts. (line 6)
+* options, M68HC11: M68HC11-Opts. (line 6)
+* options, MMIX: MMIX-Opts. (line 6)
+* options, PJ: PJ Options. (line 6)
+* options, RL78: RL78-Opts. (line 6)
+* options, RX: RX-Opts. (line 6)
+* options, SH: SH Options. (line 6)
+* options, SH64: SH64 Options. (line 6)
+* options, TIC54X: TIC54X-Opts. (line 6)
+* options, XGATE: XGATE-Opts. (line 6)
+* options, Z8000: Z8000 Options. (line 6)
+* org directive: Org. (line 6)
+* other attribute, of a.out symbol: Symbol Other. (line 6)
+* output file: Object. (line 6)
+* output section padding: no-pad-sections. (line 6)
+* p2align directive: P2align. (line 6)
+* p2alignl directive: P2align. (line 28)
+* p2alignw directive: P2align. (line 28)
+* padding the location counter: Align. (line 6)
+* padding the location counter given a power of two: P2align.
+ (line 6)
+* padding the location counter given number of bytes: Balign.
+ (line 6)
+* page, in listings: Eject. (line 6)
+* paper size, for listings: Psize. (line 6)
+* paths for .include: I. (line 6)
+* patterns, writing in memory: Fill. (line 6)
+* PDP-11 comments: PDP-11-Syntax. (line 16)
+* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13)
+* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10)
+* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6)
+* PDP-11 line separator: PDP-11-Syntax. (line 19)
+* PDP-11 support: PDP-11-Dependent. (line 6)
+* PDP-11 syntax: PDP-11-Syntax. (line 6)
+* PIC code generation for ARM: ARM Options. (line 186)
+* PIC code generation for M32R: M32R-Opts. (line 42)
+* PIC selection, MIPS: MIPS Options. (line 21)
+* PJ endianness: Overview. (line 731)
+* PJ line comment character: PJ-Chars. (line 6)
+* PJ line separator: PJ-Chars. (line 14)
+* PJ options: PJ Options. (line 6)
+* PJ support: PJ-Dependent. (line 6)
+* plus, permitted arguments: Infix Ops. (line 44)
+* popsection directive: PopSection. (line 6)
+* Position-independent code, CRIS: CRIS-Opts. (line 27)
+* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6)
+* PowerPC architectures: PowerPC-Opts. (line 6)
+* PowerPC directives: PowerPC-Pseudo. (line 6)
+* PowerPC line comment character: PowerPC-Chars. (line 6)
+* PowerPC line separator: PowerPC-Chars. (line 18)
+* PowerPC options: PowerPC-Opts. (line 6)
+* PowerPC support: PPC-Dependent. (line 6)
+* precedence of operators: Infix Ops. (line 11)
+* precision, floating point: Flonums. (line 6)
+* prefix operators: Prefix Ops. (line 6)
+* prefixes, i386: i386-Prefixes. (line 6)
+* preprocessing: Preprocessing. (line 6)
+* preprocessing, turning on and off: Preprocessing. (line 27)
+* previous directive: Previous. (line 6)
+* primary attributes, COFF symbols: COFF Symbols. (line 13)
+* print directive: Print. (line 6)
+* proc directive, SPARC: Sparc-Directives. (line 25)
+* Processor Identification register, ARC: ARC-Regs. (line 52)
+* profiler directive, MSP 430: MSP430 Directives. (line 26)
+* profiling capability for MSP 430: MSP430 Profiling Capability.
+ (line 6)
+* Program Counter, ARC: ARC-Regs. (line 55)
+* protected directive: Protected. (line 6)
+* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45)
+* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12)
+* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17)
+* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131)
+* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97)
+* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131)
+* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50)
+* pseudo-op IS, MMIX: MMIX-Pseudos. (line 42)
+* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7)
+* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28)
+* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108)
+* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120)
+* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108)
+* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108)
+* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6)
+* pseudo-opcodes, M680x0: M68K-Branch. (line 6)
+* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6)
+* pseudo-ops for branch, VAX: VAX-branch. (line 6)
+* pseudo-ops, CRIS: CRIS-Pseudos. (line 6)
+* pseudo-ops, machine independent: Pseudo Ops. (line 6)
+* pseudo-ops, MMIX: MMIX-Pseudos. (line 6)
+* psize directive: Psize. (line 6)
+* PSR bits: IA-64-Bits. (line 6)
+* pstring directive, TIC54X: TIC54X-Directives. (line 208)
+* psw register, V850: V850-Regs. (line 116)
+* purgem directive: Purgem. (line 6)
+* purpose of GNU assembler: GNU Assembler. (line 12)
+* pushsection directive: PushSection. (line 6)
+* quad directive: Quad. (line 6)
+* quad directive, i386: i386-Float. (line 21)
+* quad directive, x86-64: i386-Float. (line 21)
+* real-mode code, i386: i386-16bit. (line 6)
+* ref directive, TIC54X: TIC54X-Directives. (line 103)
+* refsym directive, MSP 430: MSP430 Directives. (line 30)
+* register directive, SPARC: Sparc-Directives. (line 29)
+* register name prefix character, ARC: ARC-Chars. (line 7)
+* register names, AArch64: AArch64-Regs. (line 6)
+* register names, Alpha: Alpha-Regs. (line 6)
+* register names, ARC: ARC-Regs. (line 6)
+* register names, ARM: ARM-Regs. (line 6)
+* register names, AVR: AVR-Regs. (line 6)
+* register names, CRIS: CRIS-Regs. (line 6)
+* register names, H8/300: H8/300-Regs. (line 6)
+* register names, IA-64: IA-64-Regs. (line 6)
+* register names, LM32: LM32-Regs. (line 6)
+* register names, MMIX: MMIX-Regs. (line 6)
+* register names, MSP 430: MSP430-Regs. (line 6)
+* register names, Sparc: Sparc-Regs. (line 6)
+* register names, TILE-Gx: TILE-Gx Registers. (line 6)
+* register names, TILEPro: TILEPro Registers. (line 6)
+* register names, V850: V850-Regs. (line 6)
+* register names, VAX: VAX-operands. (line 17)
+* register names, Visium: Visium Registers. (line 6)
+* register names, Xtensa: Xtensa Registers. (line 6)
+* register names, Z80: Z80-Regs. (line 6)
+* register naming, s390: s390 Register. (line 6)
+* register operands, i386: i386-Variations. (line 15)
+* register operands, x86-64: i386-Variations. (line 15)
+* registers, D10V: D10V-Regs. (line 6)
+* registers, D30V: D30V-Regs. (line 6)
+* registers, i386: i386-Regs. (line 6)
+* registers, Meta: Meta-Regs. (line 6)
+* registers, SH: SH-Regs. (line 6)
+* registers, SH64: SH64-Regs. (line 6)
+* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6)
+* registers, x86-64: i386-Regs. (line 6)
+* registers, Z8000: Z8000-Regs. (line 6)
+* relax-all command line option, Nios II: Nios II Options. (line 13)
+* relax-section command line option, Nios II: Nios II Options.
+ (line 6)
+* relaxation: Xtensa Relaxation. (line 6)
+* relaxation of ADDI instructions: Xtensa Immediate Relaxation.
+ (line 43)
+* relaxation of branch instructions: Xtensa Branch Relaxation.
+ (line 6)
+* relaxation of call instructions: Xtensa Call Relaxation.
+ (line 6)
+* relaxation of immediate fields: Xtensa Immediate Relaxation.
+ (line 6)
+* relaxation of jump instructions: Xtensa Jump Relaxation.
+ (line 6)
+* relaxation of L16SI instructions: Xtensa Immediate Relaxation.
+ (line 23)
+* relaxation of L16UI instructions: Xtensa Immediate Relaxation.
+ (line 23)
+* relaxation of L32I instructions: Xtensa Immediate Relaxation.
+ (line 23)
+* relaxation of L8UI instructions: Xtensa Immediate Relaxation.
+ (line 23)
+* relaxation of MOVI instructions: Xtensa Immediate Relaxation.
+ (line 12)
+* reloc directive: Reloc. (line 6)
+* relocation: Sections. (line 6)
+* relocation example: Ld Sections. (line 40)
+* relocations, AArch64: AArch64-Relocations.
+ (line 6)
+* relocations, Alpha: Alpha-Relocs. (line 6)
+* relocations, Sparc: Sparc-Relocs. (line 6)
+* repeat prefixes, i386: i386-Prefixes. (line 44)
+* reporting bugs in assembler: Reporting Bugs. (line 6)
+* rept directive: Rept. (line 6)
+* reserve directive, SPARC: Sparc-Directives. (line 39)
+* return instructions, i386: i386-Variations. (line 41)
+* return instructions, x86-64: i386-Variations. (line 41)
+* REX prefixes, i386: i386-Prefixes. (line 46)
+* RISC-V support: RISC-V-Dependent. (line 6)
+* RL78 assembler directives: RL78-Directives. (line 6)
+* RL78 line comment character: RL78-Chars. (line 6)
+* RL78 line separator: RL78-Chars. (line 14)
+* RL78 modifiers: RL78-Modifiers. (line 6)
+* RL78 options: RL78-Opts. (line 6)
+* RL78 support: RL78-Dependent. (line 6)
+* rsect: Z8000 Directives. (line 52)
+* RX assembler directive .3byte: RX-Directives. (line 9)
+* RX assembler directive .fetchalign: RX-Directives. (line 13)
+* RX assembler directives: RX-Directives. (line 6)
+* RX floating point: RX-Float. (line 6)
+* RX line comment character: RX-Chars. (line 6)
+* RX line separator: RX-Chars. (line 14)
+* RX modifiers: RX-Modifiers. (line 6)
+* RX options: RX-Opts. (line 6)
+* RX support: RX-Dependent. (line 6)
+* s390 floating point: s390 Floating Point.
+ (line 6)
+* s390 instruction aliases: s390 Aliases. (line 6)
+* s390 instruction formats: s390 Formats. (line 6)
+* s390 instruction marker: s390 Instruction Marker.
+ (line 6)
+* s390 instruction mnemonics: s390 Mnemonics. (line 6)
+* s390 instruction operand modifier: s390 Operand Modifier.
+ (line 6)
+* s390 instruction operands: s390 Operands. (line 6)
+* s390 instruction syntax: s390 Syntax. (line 6)
+* s390 line comment character: s390 Characters. (line 6)
+* s390 line separator: s390 Characters. (line 13)
+* s390 literal pool entries: s390 Literal Pool Entries.
+ (line 6)
+* s390 options: s390 Options. (line 6)
+* s390 register naming: s390 Register. (line 6)
+* s390 support: S/390-Dependent. (line 6)
+* Saved User Stack Pointer, ARC: ARC-Regs. (line 74)
+* sblock directive, TIC54X: TIC54X-Directives. (line 182)
+* sbttl directive: Sbttl. (line 6)
+* schedule directive: Schedule Directive. (line 6)
+* scl directive: Scl. (line 6)
+* SCORE architectures: SCORE-Opts. (line 6)
+* SCORE directives: SCORE-Pseudo. (line 6)
+* SCORE line comment character: SCORE-Chars. (line 6)
+* SCORE line separator: SCORE-Chars. (line 14)
+* SCORE options: SCORE-Opts. (line 6)
+* SCORE processor: SCORE-Dependent. (line 6)
+* sdaoff pseudo-op, V850: V850 Opcodes. (line 65)
+* search path for .include: I. (line 6)
+* sect directive, TIC54X: TIC54X-Directives. (line 188)
+* section directive (COFF version): Section. (line 16)
+* section directive (ELF version): Section. (line 77)
+* section directive, V850: V850 Directives. (line 9)
+* section name substitution: Section. (line 81)
+* section override prefixes, i386: i386-Prefixes. (line 23)
+* Section Stack <1>: PopSection. (line 6)
+* Section Stack <2>: SubSection. (line 6)
+* Section Stack <3>: Section. (line 72)
+* Section Stack <4>: PushSection. (line 6)
+* Section Stack: Previous. (line 6)
+* section-relative addressing: Secs Background. (line 68)
+* sections: Sections. (line 6)
+* sections in messages, internal: As Sections. (line 6)
+* sections, i386: i386-Variations. (line 47)
+* sections, named: Ld Sections. (line 8)
+* sections, x86-64: i386-Variations. (line 47)
+* seg directive, SPARC: Sparc-Directives. (line 44)
+* segm: Z8000 Directives. (line 10)
+* set at directive, Nios II: Nios II Directives. (line 35)
+* set break directive, Nios II: Nios II Directives. (line 43)
+* set directive: Set. (line 6)
+* set directive, Nios II: Nios II Directives. (line 57)
+* set directive, TIC54X: TIC54X-Directives. (line 191)
+* set noat directive, Nios II: Nios II Directives. (line 31)
+* set nobreak directive, Nios II: Nios II Directives. (line 39)
+* set norelax directive, Nios II: Nios II Directives. (line 46)
+* set relaxall directive, Nios II: Nios II Directives. (line 53)
+* set relaxsection directive, Nios II: Nios II Directives. (line 49)
+* SH addressing modes: SH-Addressing. (line 6)
+* SH floating point (IEEE): SH Floating Point. (line 6)
+* SH line comment character: SH-Chars. (line 6)
+* SH line separator: SH-Chars. (line 8)
+* SH machine directives: SH Directives. (line 6)
+* SH opcode summary: SH Opcodes. (line 6)
+* SH options: SH Options. (line 6)
+* SH registers: SH-Regs. (line 6)
+* SH support: SH-Dependent. (line 6)
+* SH64 ABI options: SH64 Options. (line 29)
+* SH64 addressing modes: SH64-Addressing. (line 6)
+* SH64 ISA options: SH64 Options. (line 6)
+* SH64 line comment character: SH64-Chars. (line 6)
+* SH64 line separator: SH64-Chars. (line 13)
+* SH64 machine directives: SH64 Directives. (line 9)
+* SH64 opcode summary: SH64 Opcodes. (line 6)
+* SH64 options: SH64 Options. (line 6)
+* SH64 registers: SH64-Regs. (line 6)
+* SH64 support: SH64-Dependent. (line 6)
+* shigh directive, M32R: M32R-Directives. (line 26)
+* short directive: Short. (line 6)
+* short directive, TIC54X: TIC54X-Directives. (line 111)
+* SIMD, i386: i386-SIMD. (line 6)
+* SIMD, x86-64: i386-SIMD. (line 6)
+* single character constant: Chars. (line 6)
+* single directive: Single. (line 6)
+* single directive, i386: i386-Float. (line 14)
+* single directive, x86-64: i386-Float. (line 14)
+* single quote, Z80: Z80-Chars. (line 20)
+* sixteen bit integers: hword. (line 6)
+* sixteen byte integer: Octa. (line 6)
+* size directive (COFF version): Size. (line 11)
+* size directive (ELF version): Size. (line 19)
+* size modifiers, D10V: D10V-Size. (line 6)
+* size modifiers, D30V: D30V-Size. (line 6)
+* size modifiers, M680x0: M68K-Syntax. (line 8)
+* size prefixes, i386: i386-Prefixes. (line 27)
+* size suffixes, H8/300: H8/300 Opcodes. (line 163)
+* size, translations, Sparc: Sparc-Size-Translations.
+ (line 6)
+* sizes operands, i386: i386-Variations. (line 29)
+* sizes operands, x86-64: i386-Variations. (line 29)
+* skip directive: Skip. (line 6)
+* skip directive, M680x0: M68K-Directives. (line 19)
+* skip directive, SPARC: Sparc-Directives. (line 48)
+* sleb128 directive: Sleb128. (line 6)
+* small data, MIPS: MIPS Small Data. (line 6)
+* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 11)
+* SOM symbol attributes: SOM Symbols. (line 6)
+* source program: Input Files. (line 6)
+* source, destination operands; i386: i386-Variations. (line 22)
+* source, destination operands; x86-64: i386-Variations. (line 22)
+* sp register: Xtensa Registers. (line 6)
+* sp register, V850: V850-Regs. (line 14)
+* space directive: Space. (line 6)
+* space directive, TIC54X: TIC54X-Directives. (line 196)
+* space used, maximum for assembly: statistics. (line 6)
+* SPARC architectures: Sparc-Opts. (line 6)
+* Sparc constants: Sparc-Constants. (line 6)
+* SPARC data alignment: Sparc-Aligned-Data. (line 6)
+* SPARC floating point (IEEE): Sparc-Float. (line 6)
+* Sparc line comment character: Sparc-Chars. (line 6)
+* Sparc line separator: Sparc-Chars. (line 14)
+* SPARC machine directives: Sparc-Directives. (line 6)
+* SPARC options: Sparc-Opts. (line 6)
+* Sparc registers: Sparc-Regs. (line 6)
+* Sparc relocations: Sparc-Relocs. (line 6)
+* Sparc size translations: Sparc-Size-Translations.
+ (line 6)
+* SPARC support: Sparc-Dependent. (line 6)
+* SPARC syntax: Sparc-Aligned-Data. (line 21)
+* special characters, M680x0: M68K-Chars. (line 6)
+* special purpose registers, MSP 430: MSP430-Regs. (line 11)
+* sslist directive, TIC54X: TIC54X-Directives. (line 203)
+* ssnolist directive, TIC54X: TIC54X-Directives. (line 203)
+* stabd directive: Stab. (line 38)
+* stabn directive: Stab. (line 48)
+* stabs directive: Stab. (line 51)
+* stabX directives: Stab. (line 6)
+* stack pointer, ARC: ARC-Regs. (line 20)
+* standard assembler sections: Secs Background. (line 27)
+* standard input, as input file: Command Line. (line 10)
+* statement separator character: Statements. (line 6)
+* statement separator, AArch64: AArch64-Chars. (line 10)
+* statement separator, Alpha: Alpha-Chars. (line 11)
+* statement separator, ARC: ARC-Chars. (line 27)
+* statement separator, ARM: ARM-Chars. (line 14)
+* statement separator, AVR: AVR-Chars. (line 14)
+* statement separator, CR16: CR16-Chars. (line 13)
+* statement separator, Epiphany: Epiphany-Chars. (line 14)
+* statement separator, H8/300: H8/300-Chars. (line 8)
+* statement separator, i386: i386-Chars. (line 18)
+* statement separator, i860: i860-Chars. (line 14)
+* statement separator, i960: i960-Chars. (line 14)
+* statement separator, IA-64: IA-64-Chars. (line 8)
+* statement separator, IP2K: IP2K-Chars. (line 14)
+* statement separator, LM32: LM32-Chars. (line 12)
+* statement separator, M32C: M32C-Chars. (line 14)
+* statement separator, M68HC11: M68HC11-Syntax. (line 27)
+* statement separator, Meta: Meta-Chars. (line 8)
+* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14)
+* statement separator, MIPS: MIPS-Chars. (line 14)
+* statement separator, MSP 430: MSP430-Chars. (line 14)
+* statement separator, NS32K: NS32K-Chars. (line 18)
+* statement separator, PJ: PJ-Chars. (line 14)
+* statement separator, PowerPC: PowerPC-Chars. (line 18)
+* statement separator, RL78: RL78-Chars. (line 14)
+* statement separator, RX: RX-Chars. (line 14)
+* statement separator, s390: s390 Characters. (line 13)
+* statement separator, SCORE: SCORE-Chars. (line 14)
+* statement separator, SH: SH-Chars. (line 8)
+* statement separator, SH64: SH64-Chars. (line 13)
+* statement separator, Sparc: Sparc-Chars. (line 14)
+* statement separator, TIC54X: TIC54X-Chars. (line 17)
+* statement separator, TIC6X: TIC6X Syntax. (line 13)
+* statement separator, V850: V850-Chars. (line 13)
+* statement separator, VAX: VAX-Chars. (line 14)
+* statement separator, Visium: Visium Characters. (line 14)
+* statement separator, XGATE: XGATE-Syntax. (line 26)
+* statement separator, XStormy16: XStormy16-Chars. (line 14)
+* statement separator, Z80: Z80-Chars. (line 13)
+* statement separator, Z8000: Z8000-Chars. (line 13)
+* statements, structure of: Statements. (line 6)
+* statistics, about assembly: statistics. (line 6)
+* Status register, ARC: ARC-Regs. (line 58)
+* STATUS32 saved on exception, ARC: ARC-Regs. (line 83)
+* stopping the assembly: Abort. (line 6)
+* Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs.
+ (line 70)
+* string constants: Strings. (line 6)
+* string directive: String. (line 8)
+* string directive on HPPA: HPPA Directives. (line 137)
+* string directive, TIC54X: TIC54X-Directives. (line 208)
+* string literals: Ascii. (line 6)
+* string, copying to object file: String. (line 8)
+* string16 directive: String. (line 8)
+* string16, copying to object file: String. (line 8)
+* string32 directive: String. (line 8)
+* string32, copying to object file: String. (line 8)
+* string64 directive: String. (line 8)
+* string64, copying to object file: String. (line 8)
+* string8 directive: String. (line 8)
+* string8, copying to object file: String. (line 8)
+* struct directive: Struct. (line 6)
+* struct directive, TIC54X: TIC54X-Directives. (line 216)
+* structure debugging, COFF: Tag. (line 6)
+* sub-instruction ordering, D10V: D10V-Chars. (line 14)
+* sub-instruction ordering, D30V: D30V-Chars. (line 14)
+* sub-instructions, D10V: D10V-Subs. (line 6)
+* sub-instructions, D30V: D30V-Subs. (line 6)
+* subexpressions: Arguments. (line 24)
+* subsection directive: SubSection. (line 6)
+* subsym builtins, TIC54X: TIC54X-Macros. (line 16)
+* subtitles for listings: Sbttl. (line 6)
+* subtraction, permitted arguments: Infix Ops. (line 49)
+* summary of options: Overview. (line 6)
+* support: HPPA-Dependent. (line 6)
+* supporting files, including: Include. (line 6)
+* suppressing warnings: W. (line 11)
+* sval: Z8000 Directives. (line 33)
+* symbol attributes: Symbol Attributes. (line 6)
+* symbol attributes, a.out: a.out Symbols. (line 6)
+* symbol attributes, COFF: COFF Symbols. (line 6)
+* symbol attributes, SOM: SOM Symbols. (line 6)
+* symbol descriptor, COFF: Desc. (line 6)
+* symbol modifiers <1>: LM32-Modifiers. (line 12)
+* symbol modifiers <2>: M32C-Modifiers. (line 11)
+* symbol modifiers <3>: AVR-Modifiers. (line 12)
+* symbol modifiers: M68HC11-Modifiers. (line 12)
+* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6)
+* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6)
+* symbol names: Symbol Names. (line 6)
+* symbol names, $ in <1>: D30V-Chars. (line 70)
+* symbol names, $ in <2>: D10V-Chars. (line 53)
+* symbol names, $ in <3>: Meta-Chars. (line 10)
+* symbol names, $ in <4>: SH-Chars. (line 15)
+* symbol names, $ in: SH64-Chars. (line 15)
+* symbol names, local: Symbol Names. (line 30)
+* symbol names, temporary: Symbol Names. (line 43)
+* symbol prefix character, ARC: ARC-Chars. (line 20)
+* symbol storage class (COFF): Scl. (line 6)
+* symbol type: Symbol Type. (line 6)
+* symbol type, COFF: Type. (line 11)
+* symbol type, ELF: Type. (line 22)
+* symbol value: Symbol Value. (line 6)
+* symbol value, setting: Set. (line 6)
+* symbol values, assigning: Setting Symbols. (line 6)
+* symbol versioning: Symver. (line 6)
+* symbol, common: Comm. (line 6)
+* symbol, making visible to linker: Global. (line 6)
+* symbolic debuggers, information for: Stab. (line 6)
+* symbols: Symbols. (line 6)
+* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6)
+* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42)
+* symbols, assigning values to: Equ. (line 6)
+* Symbols, built-in, CRIS: CRIS-Symbols. (line 6)
+* Symbols, CRIS, built-in: CRIS-Symbols. (line 6)
+* symbols, local common: Lcomm. (line 6)
+* symver directive: Symver. (line 6)
+* syntax compatibility, i386: i386-Variations. (line 6)
+* syntax compatibility, x86-64: i386-Variations. (line 6)
+* syntax, AVR: AVR-Modifiers. (line 6)
+* syntax, Blackfin: Blackfin Syntax. (line 6)
+* syntax, D10V: D10V-Syntax. (line 6)
+* syntax, D30V: D30V-Syntax. (line 6)
+* syntax, LM32: LM32-Modifiers. (line 6)
+* syntax, M680x0: M68K-Syntax. (line 8)
+* syntax, M68HC11 <1>: M68HC11-Syntax. (line 6)
+* syntax, M68HC11: M68HC11-Modifiers. (line 6)
+* syntax, machine-independent: Syntax. (line 6)
+* syntax, RL78: RL78-Modifiers. (line 6)
+* syntax, RX: RX-Modifiers. (line 6)
+* syntax, SPARC: Sparc-Aligned-Data. (line 21)
+* syntax, TILE-Gx: TILE-Gx Syntax. (line 6)
+* syntax, TILEPro: TILEPro Syntax. (line 6)
+* syntax, XGATE: XGATE-Syntax. (line 6)
+* syntax, Xtensa assembler: Xtensa Syntax. (line 6)
+* sysproc directive, i960: Directives-i960. (line 37)
+* tab (\t): Strings. (line 27)
+* tab directive, TIC54X: TIC54X-Directives. (line 247)
+* tag directive: Tag. (line 6)
+* tag directive, TIC54X: TIC54X-Directives. (line 250)
+* TBM, i386: i386-TBM. (line 6)
+* TBM, x86-64: i386-TBM. (line 6)
+* tdaoff pseudo-op, V850: V850 Opcodes. (line 81)
+* temporary symbol names: Symbol Names. (line 43)
+* text and data sections, joining: R. (line 6)
+* text directive: Text. (line 6)
+* text section: Ld Sections. (line 9)
+* tfloat directive, i386: i386-Float. (line 14)
+* tfloat directive, x86-64: i386-Float. (line 14)
+* Thumb support: ARM-Dependent. (line 6)
+* TIC54X builtin math functions: TIC54X-Builtins. (line 6)
+* TIC54X line comment character: TIC54X-Chars. (line 6)
+* TIC54X line separator: TIC54X-Chars. (line 17)
+* TIC54X machine directives: TIC54X-Directives. (line 6)
+* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6)
+* TIC54X options: TIC54X-Opts. (line 6)
+* TIC54X subsym builtins: TIC54X-Macros. (line 16)
+* TIC54X support: TIC54X-Dependent. (line 6)
+* TIC54X-specific macros: TIC54X-Macros. (line 6)
+* TIC6X big-endian output: TIC6X Options. (line 46)
+* TIC6X line comment character: TIC6X Syntax. (line 6)
+* TIC6X line separator: TIC6X Syntax. (line 13)
+* TIC6X little-endian output: TIC6X Options. (line 46)
+* TIC6X machine directives: TIC6X Directives. (line 6)
+* TIC6X options: TIC6X Options. (line 6)
+* TIC6X support: TIC6X-Dependent. (line 6)
+* TILE-Gx machine directives: TILE-Gx Directives. (line 6)
+* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6)
+* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6)
+* TILE-Gx register names: TILE-Gx Registers. (line 6)
+* TILE-Gx support: TILE-Gx-Dependent. (line 6)
+* TILE-Gx syntax: TILE-Gx Syntax. (line 6)
+* TILEPro machine directives: TILEPro Directives. (line 6)
+* TILEPro modifiers: TILEPro Modifiers. (line 6)
+* TILEPro opcode names: TILEPro Opcodes. (line 6)
+* TILEPro register names: TILEPro Registers. (line 6)
+* TILEPro support: TILEPro-Dependent. (line 6)
+* TILEPro syntax: TILEPro Syntax. (line 6)
+* time, total for assembly: statistics. (line 6)
+* title directive: Title. (line 6)
+* tls_gd directive, Nios II: Nios II Relocations.
+ (line 38)
+* tls_ie directive, Nios II: Nios II Relocations.
+ (line 38)
+* tls_ldm directive, Nios II: Nios II Relocations.
+ (line 38)
+* tls_ldo directive, Nios II: Nios II Relocations.
+ (line 38)
+* tls_le directive, Nios II: Nios II Relocations.
+ (line 38)
+* TMS320C6X support: TIC6X-Dependent. (line 6)
+* tp register, V850: V850-Regs. (line 20)
+* transform directive: Transform Directive.
+ (line 6)
+* trusted compiler: f. (line 6)
+* turning preprocessing on and off: Preprocessing. (line 27)
+* type directive (COFF version): Type. (line 11)
+* type directive (ELF version): Type. (line 22)
+* type of a symbol: Symbol Type. (line 6)
+* ualong directive, SH: SH Directives. (line 6)
+* uaquad directive, SH: SH Directives. (line 6)
+* uaword directive, SH: SH Directives. (line 6)
+* ubyte directive, TIC54X: TIC54X-Directives. (line 36)
+* uchar directive, TIC54X: TIC54X-Directives. (line 36)
+* uhalf directive, TIC54X: TIC54X-Directives. (line 111)
+* uint directive, TIC54X: TIC54X-Directives. (line 111)
+* uleb128 directive: Uleb128. (line 6)
+* ulong directive, TIC54X: TIC54X-Directives. (line 135)
+* undefined section: Ld Sections. (line 36)
+* union directive, TIC54X: TIC54X-Directives. (line 250)
+* unsegm: Z8000 Directives. (line 14)
+* usect directive, TIC54X: TIC54X-Directives. (line 262)
+* ushort directive, TIC54X: TIC54X-Directives. (line 111)
+* uword directive, TIC54X: TIC54X-Directives. (line 111)
+* V850 command line options: V850 Options. (line 9)
+* V850 floating point (IEEE): V850 Floating Point.
+ (line 6)
+* V850 line comment character: V850-Chars. (line 6)
+* V850 line separator: V850-Chars. (line 13)
+* V850 machine directives: V850 Directives. (line 6)
+* V850 opcodes: V850 Opcodes. (line 6)
+* V850 options (none): V850 Options. (line 6)
+* V850 register names: V850-Regs. (line 6)
+* V850 support: V850-Dependent. (line 6)
+* val directive: Val. (line 6)
+* value attribute, COFF: Val. (line 6)
+* value of a symbol: Symbol Value. (line 6)
+* var directive, TIC54X: TIC54X-Directives. (line 272)
+* VAX bitfields not supported: VAX-no. (line 6)
+* VAX branch improvement: VAX-branch. (line 6)
+* VAX command-line options ignored: VAX-Opts. (line 6)
+* VAX displacement sizing character: VAX-operands. (line 12)
+* VAX floating point: VAX-float. (line 6)
+* VAX immediate character: VAX-operands. (line 6)
+* VAX indirect character: VAX-operands. (line 9)
+* VAX line comment character: VAX-Chars. (line 6)
+* VAX line separator: VAX-Chars. (line 14)
+* VAX machine directives: VAX-directives. (line 6)
+* VAX opcode mnemonics: VAX-opcodes. (line 6)
+* VAX operand notation: VAX-operands. (line 6)
+* VAX register names: VAX-operands. (line 17)
+* VAX support: Vax-Dependent. (line 6)
+* Vax-11 C compatibility: VAX-Opts. (line 42)
+* VAX/VMS options: VAX-Opts. (line 42)
+* version directive: Version. (line 6)
+* version directive, TIC54X: TIC54X-Directives. (line 276)
+* version of assembler: v. (line 6)
+* versions of symbols: Symver. (line 6)
+* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides.
+ (line 53)
+* visibility <1>: Protected. (line 6)
+* visibility <2>: Internal. (line 6)
+* visibility: Hidden. (line 6)
+* Visium line comment character: Visium Characters. (line 6)
+* Visium line separator: Visium Characters. (line 14)
+* Visium options: Visium Options. (line 6)
+* Visium registers: Visium Registers. (line 6)
+* Visium support: Visium-Dependent. (line 6)
+* VMS (VAX) options: VAX-Opts. (line 42)
+* vtable_entry directive: VTableEntry. (line 6)
+* vtable_inherit directive: VTableInherit. (line 6)
+* warning directive: Warning. (line 6)
+* warning for altered difference tables: K. (line 6)
+* warning messages: Errors. (line 6)
+* warnings, causing error: W. (line 16)
+* warnings, M32R: M32R-Warnings. (line 6)
+* warnings, suppressing: W. (line 11)
+* warnings, switching on: W. (line 19)
+* weak directive: Weak. (line 6)
+* weakref directive: Weakref. (line 6)
+* whitespace: Whitespace. (line 6)
+* whitespace, removed by preprocessor: Preprocessing. (line 7)
+* wide floating point directives, VAX: VAX-directives. (line 10)
+* width directive, TIC54X: TIC54X-Directives. (line 127)
+* Width of continuation lines of disassembly output: listing.
+ (line 21)
+* Width of first line disassembly output: listing. (line 16)
+* Width of source line output: listing. (line 28)
+* wmsg directive, TIC54X: TIC54X-Directives. (line 77)
+* word aligned program counter, ARC: ARC-Regs. (line 44)
+* word directive: Word. (line 6)
+* word directive, H8/300: H8/300 Directives. (line 6)
+* word directive, i386: i386-Float. (line 21)
+* word directive, Nios II: Nios II Directives. (line 13)
+* word directive, SPARC: Sparc-Directives. (line 51)
+* word directive, TIC54X: TIC54X-Directives. (line 111)
+* word directive, x86-64: i386-Float. (line 21)
+* writing patterns in memory: Fill. (line 6)
+* wval: Z8000 Directives. (line 24)
+* x86 machine directives: i386-Directives. (line 6)
+* x86-64 arch directive: i386-Arch. (line 6)
+* x86-64 att_syntax pseudo op: i386-Variations. (line 6)
+* x86-64 conversion instructions: i386-Mnemonics. (line 40)
+* x86-64 floating point: i386-Float. (line 6)
+* x86-64 immediate operands: i386-Variations. (line 15)
+* x86-64 instruction naming: i386-Mnemonics. (line 9)
+* x86-64 intel_syntax pseudo op: i386-Variations. (line 6)
+* x86-64 jump optimization: i386-Jumps. (line 6)
+* x86-64 jump, call, return: i386-Variations. (line 41)
+* x86-64 jump/call operands: i386-Variations. (line 15)
+* x86-64 memory references: i386-Memory. (line 6)
+* x86-64 options: i386-Options. (line 6)
+* x86-64 register operands: i386-Variations. (line 15)
+* x86-64 registers: i386-Regs. (line 6)
+* x86-64 sections: i386-Variations. (line 47)
+* x86-64 size suffixes: i386-Variations. (line 29)
+* x86-64 source, destination operands: i386-Variations. (line 22)
+* x86-64 support: i386-Dependent. (line 6)
+* x86-64 syntax compatibility: i386-Variations. (line 6)
+* xfloat directive, TIC54X: TIC54X-Directives. (line 64)
+* XGATE addressing modes: XGATE-Syntax. (line 29)
+* XGATE assembler directives: XGATE-Directives. (line 6)
+* XGATE floating point: XGATE-Float. (line 6)
+* XGATE line comment character: XGATE-Syntax. (line 16)
+* XGATE line separator: XGATE-Syntax. (line 26)
+* XGATE opcodes: XGATE-opcodes. (line 6)
+* XGATE options: XGATE-Opts. (line 6)
+* XGATE support: XGATE-Dependent. (line 6)
+* XGATE syntax: XGATE-Syntax. (line 6)
+* xlong directive, TIC54X: TIC54X-Directives. (line 135)
+* XStormy16 comment character: XStormy16-Chars. (line 11)
+* XStormy16 line comment character: XStormy16-Chars. (line 6)
+* XStormy16 line separator: XStormy16-Chars. (line 14)
+* XStormy16 machine directives: XStormy16 Directives.
+ (line 6)
+* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6)
+* XStormy16 support: XSTORMY16-Dependent.
+ (line 6)
+* Xtensa architecture: Xtensa-Dependent. (line 6)
+* Xtensa assembler syntax: Xtensa Syntax. (line 6)
+* Xtensa directives: Xtensa Directives. (line 6)
+* Xtensa opcode names: Xtensa Opcodes. (line 6)
+* Xtensa register names: Xtensa Registers. (line 6)
+* xword directive, SPARC: Sparc-Directives. (line 55)
+* Z80 $: Z80-Chars. (line 15)
+* Z80 ': Z80-Chars. (line 20)
+* Z80 floating point: Z80 Floating Point. (line 6)
+* Z80 line comment character: Z80-Chars. (line 6)
+* Z80 line separator: Z80-Chars. (line 13)
+* Z80 options: Z80 Options. (line 6)
+* Z80 registers: Z80-Regs. (line 6)
+* Z80 support: Z80-Dependent. (line 6)
+* Z80 Syntax: Z80 Options. (line 47)
+* Z80, \: Z80-Chars. (line 18)
+* Z80, case sensitivity: Z80-Case. (line 6)
+* Z80-only directives: Z80 Directives. (line 9)
+* Z800 addressing modes: Z8000-Addressing. (line 6)
+* Z8000 directives: Z8000 Directives. (line 6)
+* Z8000 line comment character: Z8000-Chars. (line 6)
+* Z8000 line separator: Z8000-Chars. (line 13)
+* Z8000 opcode summary: Z8000 Opcodes. (line 6)
+* Z8000 options: Z8000 Options. (line 6)
+* Z8000 registers: Z8000-Regs. (line 6)
+* Z8000 support: Z8000-Dependent. (line 6)
+* zdaoff pseudo-op, V850: V850 Opcodes. (line 99)
+* zero directive: Zero. (line 6)
+* zero register, V850: V850-Regs. (line 7)
+* zero-terminated strings: Asciz. (line 6)
+
+
+
+Tag Table:
+Node: Top739
+Node: Overview1725
+Node: Manual40121
+Node: GNU Assembler41065
+Node: Object Formats42236
+Node: Command Line42688
+Node: Input Files43775
+Node: Object45756
+Node: Errors46652
+Node: Invoking48216
+Node: a50233
+Node: alternate52144
+Node: D52316
+Node: f52549
+Node: I53057
+Node: K53601
+Node: L53905
+Node: listing54644
+Node: M56303
+Node: MD60704
+Node: no-pad-sections61144
+Node: o61519
+Node: R61987
+Node: statistics63017
+Node: traditional-format63424
+Node: v63897
+Node: W64172
+Node: Z65079
+Node: Syntax65601
+Node: Preprocessing66193
+Node: Whitespace67756
+Node: Comments68152
+Node: Symbol Intro70163
+Node: Statements71146
+Node: Constants73135
+Node: Characters73766
+Node: Strings74268
+Node: Chars76443
+Node: Numbers77296
+Node: Integers77836
+Node: Bignums78492
+Node: Flonums78848
+Node: Sections80595
+Node: Secs Background80973
+Node: Ld Sections86012
+Node: As Sections88396
+Node: Sub-Sections89306
+Node: bss92451
+Node: Symbols93401
+Node: Labels94049
+Node: Setting Symbols94780
+Node: Symbol Names95334
+Node: Dot100799
+Node: Symbol Attributes101246
+Node: Symbol Value101983
+Node: Symbol Type103028
+Node: a.out Symbols103416
+Node: Symbol Desc103678
+Node: Symbol Other103973
+Node: COFF Symbols104142
+Node: SOM Symbols104815
+Node: Expressions105257
+Node: Empty Exprs106006
+Node: Integer Exprs106353
+Node: Arguments106748
+Node: Operators107854
+Node: Prefix Ops108189
+Node: Infix Ops108517
+Node: Pseudo Ops110907
+Node: Abort116576
+Node: ABORT (COFF)116988
+Node: Align117196
+Node: Altmacro119478
+Node: Ascii120807
+Node: Asciz121116
+Node: Balign121361
+Node: Bundle directives123237
+Node: Byte126219
+Node: CFI directives126478
+Node: Comm135787
+Ref: Comm-Footnote-1137388
+Node: Data137750
+Node: Def138067
+Node: Desc138299
+Node: Dim138799
+Node: Double139056
+Node: Eject139394
+Node: Else139569
+Node: Elseif139869
+Node: End140163
+Node: Endef140378
+Node: Endfunc140555
+Node: Endif140730
+Node: Equ140991
+Node: Equiv141505
+Node: Eqv142061
+Node: Err142425
+Node: Error142736
+Node: Exitm143181
+Node: Extern143350
+Node: Fail143611
+Node: File144056
+Node: Fill145385
+Node: Float146349
+Node: Func146691
+Node: Global147281
+Node: Gnu_attribute148038
+Node: Hidden148263
+Node: hword148849
+Node: Ident149177
+Node: If149751
+Node: Incbin152810
+Node: Include153505
+Node: Int154056
+Node: Internal154437
+Node: Irp155085
+Node: Irpc155964
+Node: Lcomm156881
+Node: Lflags157629
+Node: Line157823
+Node: Linkonce158736
+Node: List159965
+Node: Ln160573
+Node: Loc160723
+Node: Loc_mark_labels162109
+Node: Local162593
+Node: Long163205
+Node: Macro163383
+Node: MRI169305
+Node: Noaltmacro169643
+Node: Nolist169812
+Node: Octa170242
+Node: Offset170579
+Node: Org170906
+Node: P2align172191
+Node: PopSection174119
+Node: Previous174627
+Node: Print176040
+Node: Protected176269
+Node: Psize176916
+Node: Purgem177600
+Node: PushSection177821
+Node: Quad178564
+Node: Reloc179020
+Node: Rept179781
+Node: Sbttl180195
+Node: Scl180560
+Node: Section180901
+Ref: Section Name Substitutions182975
+Node: Set189070
+Node: Short190152
+Node: Single190473
+Node: Size190818
+Node: Skip191490
+Node: Sleb128191812
+Node: Space192134
+Node: Stab192773
+Node: String194775
+Node: Struct195767
+Node: SubSection196490
+Node: Symver197051
+Node: Tag199442
+Node: Text199822
+Node: Title200141
+Node: Type200520
+Node: Uleb128202831
+Node: Val203153
+Node: Version203401
+Node: VTableEntry203674
+Node: VTableInherit203962
+Node: Warning204410
+Node: Weak204644
+Node: Weakref205313
+Node: Word206278
+Node: Zero208118
+Node: Deprecated208530
+Node: Object Attributes208765
+Node: GNU Object Attributes210485
+Node: Defining New Object Attributes214025
+Node: Machine Dependencies214822
+Node: AArch64-Dependent218833
+Node: AArch64 Options219315
+Node: AArch64 Extensions221950
+Node: AArch64 Syntax224692
+Node: AArch64-Chars224992
+Node: AArch64-Regs225478
+Node: AArch64-Relocations225772
+Node: AArch64 Floating Point226846
+Node: AArch64 Directives227071
+Node: AArch64 Opcodes229970
+Node: AArch64 Mapping Symbols230648
+Node: Alpha-Dependent231030
+Node: Alpha Notes231470
+Node: Alpha Options231751
+Node: Alpha Syntax234226
+Node: Alpha-Chars234695
+Node: Alpha-Regs235107
+Node: Alpha-Relocs235494
+Node: Alpha Floating Point241752
+Node: Alpha Directives241974
+Node: Alpha Opcodes247497
+Node: ARC-Dependent247792
+Node: ARC Options248237
+Node: ARC Syntax251345
+Node: ARC-Chars251573
+Node: ARC-Regs252696
+Node: ARC Directives255466
+Node: ARC Modifiers263479
+Node: ARC Symbols264490
+Node: ARC Opcodes265051
+Node: ARM-Dependent265297
+Node: ARM Options265762
+Node: ARM Syntax275855
+Node: ARM-Instruction-Set276223
+Node: ARM-Chars277443
+Node: ARM-Regs278154
+Node: ARM-Relocations278363
+Node: ARM-Neon-Alignment280048
+Node: ARM Floating Point280512
+Node: ARM Directives280711
+Ref: arm_fnend285159
+Ref: arm_fnstart285483
+Ref: arm_pad287891
+Ref: arm_save288493
+Ref: arm_setfp289194
+Node: ARM Opcodes292486
+Node: ARM Mapping Symbols294574
+Node: ARM Unwinding Tutorial295384
+Node: AVR-Dependent301586
+Node: AVR Options301876
+Node: AVR Syntax307919
+Node: AVR-Chars308206
+Node: AVR-Regs308765
+Node: AVR-Modifiers309344
+Node: AVR Opcodes311404
+Node: Blackfin-Dependent316650
+Node: Blackfin Options316962
+Node: Blackfin Syntax317936
+Node: Blackfin Directives324143
+Node: CR16-Dependent324889
+Node: CR16 Operand Qualifiers325189
+Node: CR16 Syntax327918
+Node: CR16-Chars328104
+Node: CRIS-Dependent328641
+Node: CRIS-Opts328987
+Ref: march-option330673
+Node: CRIS-Expand332490
+Node: CRIS-Symbols333673
+Node: CRIS-Syntax334842
+Node: CRIS-Chars335178
+Node: CRIS-Pic335729
+Ref: crispic335925
+Node: CRIS-Regs339465
+Node: CRIS-Pseudos339882
+Ref: crisnous340658
+Node: D10V-Dependent341940
+Node: D10V-Opts342291
+Node: D10V-Syntax343253
+Node: D10V-Size343782
+Node: D10V-Subs344755
+Node: D10V-Chars345790
+Node: D10V-Regs347702
+Node: D10V-Addressing348747
+Node: D10V-Word349433
+Node: D10V-Float349948
+Node: D10V-Opcodes350259
+Node: D30V-Dependent350652
+Node: D30V-Opts351009
+Node: D30V-Syntax351686
+Node: D30V-Size352220
+Node: D30V-Subs353193
+Node: D30V-Chars354230
+Node: D30V-Guarded356838
+Node: D30V-Regs357520
+Node: D30V-Addressing358661
+Node: D30V-Float359331
+Node: D30V-Opcodes359644
+Node: Epiphany-Dependent360039
+Node: Epiphany Options360327
+Node: Epiphany Syntax360726
+Node: Epiphany-Chars360927
+Node: H8/300-Dependent361481
+Node: H8/300 Options361897
+Node: H8/300 Syntax362338
+Node: H8/300-Chars362639
+Node: H8/300-Regs362938
+Node: H8/300-Addressing363857
+Node: H8/300 Floating Point364898
+Node: H8/300 Directives365225
+Node: H8/300 Opcodes366353
+Node: HPPA-Dependent374675
+Node: HPPA Notes375110
+Node: HPPA Options375868
+Node: HPPA Syntax376063
+Node: HPPA Floating Point377333
+Node: HPPA Directives377539
+Node: HPPA Opcodes386225
+Node: ESA/390-Dependent386484
+Node: ESA/390 Notes386944
+Node: ESA/390 Options387735
+Node: ESA/390 Syntax387945
+Node: ESA/390 Floating Point390118
+Node: ESA/390 Directives390397
+Node: ESA/390 Opcodes393686
+Node: i386-Dependent393948
+Node: i386-Options395278
+Node: i386-Directives403887
+Node: i386-Syntax404625
+Node: i386-Variations404930
+Node: i386-Chars407471
+Node: i386-Mnemonics408200
+Node: i386-Regs411564
+Node: i386-Prefixes414402
+Node: i386-Memory417162
+Node: i386-Jumps420099
+Node: i386-Float421220
+Node: i386-SIMD423049
+Node: i386-LWP424158
+Node: i386-BMI424992
+Node: i386-TBM425370
+Node: i386-16bit425900
+Node: i386-Arch427971
+Node: i386-Bugs431151
+Node: i386-Notes431905
+Node: i860-Dependent432763
+Node: Notes-i860433203
+Node: Options-i860434108
+Node: Directives-i860435471
+Node: Opcodes for i860436540
+Node: Syntax of i860438730
+Node: i860-Chars438914
+Node: i960-Dependent439473
+Node: Options-i960439920
+Node: Floating Point-i960443805
+Node: Directives-i960444073
+Node: Opcodes for i960446107
+Node: callj-i960446747
+Node: Compare-and-branch-i960447236
+Node: Syntax of i960449140
+Node: i960-Chars449340
+Node: IA-64-Dependent449883
+Node: IA-64 Options450184
+Node: IA-64 Syntax453335
+Node: IA-64-Chars453741
+Node: IA-64-Regs453971
+Node: IA-64-Bits454897
+Node: IA-64-Relocs455427
+Node: IA-64 Opcodes455899
+Node: IP2K-Dependent456171
+Node: IP2K-Opts456443
+Node: IP2K-Syntax456943
+Node: IP2K-Chars457117
+Node: LM32-Dependent457660
+Node: LM32 Options457955
+Node: LM32 Syntax458589
+Node: LM32-Regs458885
+Node: LM32-Modifiers459844
+Node: LM32-Chars461219
+Node: LM32 Opcodes461727
+Node: M32C-Dependent462031
+Node: M32C-Opts462540
+Node: M32C-Syntax462960
+Node: M32C-Modifiers463195
+Node: M32C-Chars464984
+Node: M32R-Dependent465550
+Node: M32R-Opts465871
+Node: M32R-Directives470034
+Node: M32R-Warnings474009
+Node: M68K-Dependent477015
+Node: M68K-Opts477482
+Node: M68K-Syntax484855
+Node: M68K-Moto-Syntax486695
+Node: M68K-Float489285
+Node: M68K-Directives489805
+Node: M68K-opcodes491133
+Node: M68K-Branch491359
+Node: M68K-Chars495557
+Node: M68HC11-Dependent496420
+Node: M68HC11-Opts496951
+Node: M68HC11-Syntax501256
+Node: M68HC11-Modifiers504047
+Node: M68HC11-Directives505875
+Node: M68HC11-Float507251
+Node: M68HC11-opcodes507779
+Node: M68HC11-Branch507961
+Node: Meta-Dependent510410
+Node: Meta Options510695
+Node: Meta Syntax511357
+Node: Meta-Chars511569
+Node: Meta-Regs511869
+Node: MicroBlaze-Dependent512145
+Node: MicroBlaze Directives512834
+Node: MicroBlaze Syntax514217
+Node: MicroBlaze-Chars514449
+Node: MIPS-Dependent515001
+Node: MIPS Options516438
+Node: MIPS Macros533133
+Ref: MIPS Macros-Footnote-1535847
+Node: MIPS Symbol Sizes535990
+Node: MIPS Small Data537662
+Node: MIPS ISA539825
+Node: MIPS assembly options541610
+Node: MIPS autoextend542743
+Node: MIPS insn543477
+Node: MIPS FP ABIs544757
+Node: MIPS FP ABI History545209
+Node: MIPS FP ABI Variants545969
+Node: MIPS FP ABI Selection548523
+Node: MIPS FP ABI Compatibility549587
+Node: MIPS NaN Encodings550397
+Node: MIPS Option Stack552360
+Node: MIPS ASE Instruction Generation Overrides553145
+Node: MIPS Floating-Point556160
+Node: MIPS Syntax557066
+Node: MIPS-Chars557328
+Node: MMIX-Dependent557870
+Node: MMIX-Opts558250
+Node: MMIX-Expand561854
+Node: MMIX-Syntax563169
+Ref: mmixsite563526
+Node: MMIX-Chars564367
+Node: MMIX-Symbols565241
+Node: MMIX-Regs567309
+Node: MMIX-Pseudos568334
+Ref: MMIX-loc568475
+Ref: MMIX-local569555
+Ref: MMIX-is570087
+Ref: MMIX-greg570358
+Ref: GREG-base571277
+Ref: MMIX-byte572594
+Ref: MMIX-constants573065
+Ref: MMIX-prefix573711
+Ref: MMIX-spec574085
+Node: MMIX-mmixal574419
+Node: MSP430-Dependent577917
+Node: MSP430 Options578386
+Node: MSP430 Syntax581565
+Node: MSP430-Macros581881
+Node: MSP430-Chars582612
+Node: MSP430-Regs583327
+Node: MSP430-Ext583887
+Node: MSP430 Floating Point585708
+Node: MSP430 Directives585932
+Node: MSP430 Opcodes587253
+Node: MSP430 Profiling Capability587648
+Node: NDS32-Dependent589977
+Node: NDS32 Options590589
+Node: NDS32 Syntax592490
+Node: NDS32-Chars592758
+Node: NDS32-Regs593225
+Node: NDS32-Ops594079
+Node: NiosII-Dependent597674
+Node: Nios II Options598093
+Node: Nios II Syntax599331
+Node: Nios II Chars599537
+Node: Nios II Relocations599728
+Node: Nios II Directives601300
+Node: Nios II Opcodes602863
+Node: NS32K-Dependent603138
+Node: NS32K Syntax603365
+Node: NS32K-Chars603514
+Node: PDP-11-Dependent604254
+Node: PDP-11-Options604644
+Node: PDP-11-Pseudos609715
+Node: PDP-11-Syntax610060
+Node: PDP-11-Mnemonics610892
+Node: PDP-11-Synthetic611194
+Node: PJ-Dependent611412
+Node: PJ Options611675
+Node: PJ Syntax611970
+Node: PJ-Chars612135
+Node: PPC-Dependent612684
+Node: PowerPC-Opts613017
+Node: PowerPC-Pseudo616644
+Node: PowerPC-Syntax617266
+Node: PowerPC-Chars617456
+Node: RL78-Dependent618207
+Node: RL78-Opts618609
+Node: RL78-Modifiers619444
+Node: RL78-Directives620220
+Node: RL78-Syntax620825
+Node: RL78-Chars621021
+Node: RISC-V-Dependent621577
+Node: RISC-V-Opts621799
+Node: RX-Dependent622333
+Node: RX-Opts622766
+Node: RX-Modifiers627014
+Node: RX-Directives628118
+Node: RX-Float628858
+Node: RX-Syntax629499
+Node: RX-Chars629678
+Node: S/390-Dependent630230
+Node: s390 Options631050
+Node: s390 Characters633165
+Node: s390 Syntax633686
+Node: s390 Register634587
+Node: s390 Mnemonics635400
+Node: s390 Operands638420
+Node: s390 Formats641039
+Node: s390 Aliases648910
+Node: s390 Operand Modifier652807
+Node: s390 Instruction Marker656608
+Node: s390 Literal Pool Entries657624
+Node: s390 Directives659547
+Node: s390 Floating Point664990
+Node: SCORE-Dependent665436
+Node: SCORE-Opts665738
+Node: SCORE-Pseudo667026
+Node: SCORE-Syntax669103
+Node: SCORE-Chars669285
+Node: SH-Dependent669843
+Node: SH Options670254
+Node: SH Syntax671309
+Node: SH-Chars671582
+Node: SH-Regs672125
+Node: SH-Addressing672739
+Node: SH Floating Point673648
+Node: SH Directives674742
+Node: SH Opcodes675143
+Node: SH64-Dependent679465
+Node: SH64 Options679827
+Node: SH64 Syntax681624
+Node: SH64-Chars681907
+Node: SH64-Regs682456
+Node: SH64-Addressing683552
+Node: SH64 Directives684735
+Node: SH64 Opcodes685720
+Node: Sparc-Dependent686436
+Node: Sparc-Opts686847
+Node: Sparc-Aligned-Data692187
+Node: Sparc-Syntax693019
+Node: Sparc-Chars693593
+Node: Sparc-Regs694156
+Node: Sparc-Constants700004
+Node: Sparc-Relocs704764
+Node: Sparc-Size-Translations709900
+Node: Sparc-Float711549
+Node: Sparc-Directives711744
+Node: TIC54X-Dependent713704
+Node: TIC54X-Opts714467
+Node: TIC54X-Block715510
+Node: TIC54X-Env715870
+Node: TIC54X-Constants716218
+Node: TIC54X-Subsyms716620
+Node: TIC54X-Locals718529
+Node: TIC54X-Builtins719273
+Node: TIC54X-Ext721744
+Node: TIC54X-Directives722315
+Node: TIC54X-Macros733216
+Node: TIC54X-MMRegs735327
+Node: TIC54X-Syntax735565
+Node: TIC54X-Chars735755
+Node: TIC6X-Dependent736446
+Node: TIC6X Options736749
+Node: TIC6X Syntax738750
+Node: TIC6X Directives739852
+Node: TILE-Gx-Dependent742137
+Node: TILE-Gx Options742447
+Node: TILE-Gx Syntax742797
+Node: TILE-Gx Opcodes745031
+Node: TILE-Gx Registers745319
+Node: TILE-Gx Modifiers746091
+Node: TILE-Gx Directives751063
+Node: TILEPro-Dependent751967
+Node: TILEPro Options752276
+Node: TILEPro Syntax752460
+Node: TILEPro Opcodes754694
+Node: TILEPro Registers754985
+Node: TILEPro Modifiers755755
+Node: TILEPro Directives760520
+Node: V850-Dependent761424
+Node: V850 Options761820
+Node: V850 Syntax766100
+Node: V850-Chars766340
+Node: V850-Regs766884
+Node: V850 Floating Point768452
+Node: V850 Directives768658
+Node: V850 Opcodes770725
+Node: Vax-Dependent776617
+Node: VAX-Opts777201
+Node: VAX-float780936
+Node: VAX-directives781568
+Node: VAX-opcodes782429
+Node: VAX-branch782818
+Node: VAX-operands785325
+Node: VAX-no786088
+Node: VAX-Syntax786344
+Node: VAX-Chars786510
+Node: Visium-Dependent787064
+Node: Visium Options787371
+Node: Visium Syntax787837
+Node: Visium Characters788082
+Node: Visium Registers788663
+Node: Visium Opcodes788935
+Node: XGATE-Dependent789361
+Node: XGATE-Opts789783
+Node: XGATE-Syntax790774
+Node: XGATE-Directives792853
+Node: XGATE-Float793092
+Node: XGATE-opcodes793589
+Node: XSTORMY16-Dependent793701
+Node: XStormy16 Syntax794047
+Node: XStormy16-Chars794237
+Node: XStormy16 Directives794850
+Node: XStormy16 Opcodes795505
+Node: Xtensa-Dependent796561
+Node: Xtensa Options797295
+Node: Xtensa Syntax801566
+Node: Xtensa Opcodes803710
+Node: Xtensa Registers805504
+Node: Xtensa Optimizations806137
+Node: Density Instructions806589
+Node: Xtensa Automatic Alignment807691
+Node: Xtensa Relaxation810138
+Node: Xtensa Branch Relaxation811103
+Node: Xtensa Call Relaxation812475
+Node: Xtensa Jump Relaxation814256
+Node: Xtensa Immediate Relaxation816356
+Node: Xtensa Directives818930
+Node: Schedule Directive820639
+Node: Longcalls Directive820979
+Node: Transform Directive821523
+Node: Literal Directive822265
+Ref: Literal Directive-Footnote-1825804
+Node: Literal Position Directive825946
+Node: Literal Prefix Directive827645
+Node: Absolute Literals Directive828543
+Node: Z80-Dependent829850
+Node: Z80 Options830238
+Node: Z80 Syntax831661
+Node: Z80-Chars832333
+Node: Z80-Regs833183
+Node: Z80-Case833535
+Node: Z80 Floating Point833980
+Node: Z80 Directives834174
+Node: Z80 Opcodes835799
+Node: Z8000-Dependent837143
+Node: Z8000 Options838082
+Node: Z8000 Syntax838299
+Node: Z8000-Chars838589
+Node: Z8000-Regs839071
+Node: Z8000-Addressing839861
+Node: Z8000 Directives840978
+Node: Z8000 Opcodes842587
+Node: Reporting Bugs852529
+Node: Bug Criteria853255
+Node: Bug Reporting854022
+Node: Acknowledgements860671
+Ref: Acknowledgements-Footnote-1865636
+Node: GNU Free Documentation License865662
+Node: AS Index890831
+
+End Tag Table
diff --git a/gas/doc/asconfig.texi b/gas/doc/asconfig.texi
new file mode 100644
index 0000000..24ec477
--- /dev/null
+++ b/gas/doc/asconfig.texi
@@ -0,0 +1,108 @@
+@c Copyright (C) 1992-2017 Free Software Foundation, Inc.
+@c This file is part of the documentation for the GAS manual
+
+@c Configuration settings for all-inclusive version of manual
+
+@c switches:------------------------------------------------------------
+@c Properties of the manual
+@c ========================
+@c Discuss all architectures?
+@set ALL-ARCH
+@c A generic form of manual (not tailored to specific target)?
+@set GENERIC
+@c Include text on assembler internals?
+@clear INTERNALS
+@c Many object formats supported in this config?
+@set MULTI-OBJ
+
+@c Object formats of interest
+@c ==========================
+@set AOUT
+@set COFF
+@set ELF
+@set SOM
+
+@c CPUs of interest
+@c ================
+@set AARCH64
+@set ALPHA
+@set ARC
+@set ARM
+@set AVR
+@set Blackfin
+@set CR16
+@set CRIS
+@set D10V
+@set D30V
+@set EPIPHANY
+@set H8/300
+@set HPPA
+@set I370
+@set I80386
+@set I860
+@set I960
+@set IA64
+@set IP2K
+@set LM32
+@set M32C
+@set M32R
+@set xc16x
+@set M68HC11
+@set M680X0
+@set MCORE
+@set METAG
+@set MICROBLAZE
+@set MIPS
+@set MMIX
+@set MS1
+@set MSP430
+@set NIOSII
+@set NDS32
+@set NS32K
+@set PDP11
+@set PJ
+@set PPC
+@set RL78
+@set RISCV
+@set RX
+@set S390
+@set SCORE
+@set SH
+@set SPARC
+@set TIC54X
+@set TIC6X
+@set TILEGX
+@set TILEPRO
+@set V850
+@set VAX
+@set VISIUM
+@set XGATE
+@set XSTORMY16
+@set XTENSA
+@set Z80
+@set Z8000
+
+@c Does this version of the assembler use the difference-table kludge?
+@set DIFF-TBL-KLUGE
+
+@c Do all machines described use IEEE floating point?
+@clear IEEEFLOAT
+
+@c Is a word 32 bits, or 16?
+@clear W32
+@set W16
+
+@c Do symbols have different characters than usual?
+@clear SPECIAL-SYMS
+
+@c strings:------------------------------------------------------------
+@c Name of the assembler:
+@set AS as
+@c Name of C compiler:
+@set GCC gcc
+@c Name of linker:
+@set LD ld
+@c Text for target machine (best not used in generic case; but just in case...)
+@set TARGET machine specific
+@c Name of object format NOT SET in generic version
+@clear OBJ-NAME
diff --git a/gas/itbl-lex.c b/gas/itbl-lex.c
new file mode 100644
index 0000000..dc2d5e4
--- /dev/null
+++ b/gas/itbl-lex.c
@@ -0,0 +1,1919 @@
+
+#line 3 "itbl-lex.c"
+
+#define YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types.
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+typedef uint64_t flex_uint64_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t;
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else /* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif /* defined (__STDC__) */
+#endif /* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index. If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition. This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state. The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart(yyin )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+extern yy_size_t yyleng;
+
+extern FILE *yyin, *yyout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+ #define YY_LESS_LINENO(n)
+
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ *yy_cp = (yy_hold_char); \
+ YY_RESTORE_YY_MORE_OFFSET \
+ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+ YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+ } \
+ while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr) )
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+ {
+ FILE *yy_input_file;
+
+ char *yy_ch_buf; /* input buffer */
+ char *yy_buf_pos; /* current position in input buffer */
+
+ /* Size of input buffer in bytes, not including room for EOB
+ * characters.
+ */
+ yy_size_t yy_buf_size;
+
+ /* Number of characters read into yy_ch_buf, not including EOB
+ * characters.
+ */
+ yy_size_t yy_n_chars;
+
+ /* Whether we "own" the buffer - i.e., we know we created it,
+ * and can realloc() it to grow it, and should free() it to
+ * delete it.
+ */
+ int yy_is_our_buffer;
+
+ /* Whether this is an "interactive" input source; if so, and
+ * if we're using stdio for input, then we want to use getc()
+ * instead of fread(), to make sure we stop fetching input after
+ * each newline.
+ */
+ int yy_is_interactive;
+
+ /* Whether we're considered to be at the beginning of a line.
+ * If so, '^' rules will be active on the next match, otherwise
+ * not.
+ */
+ int yy_at_bol;
+
+ int yy_bs_lineno; /**< The line count. */
+ int yy_bs_column; /**< The column count. */
+
+ /* Whether to try to fill the input buffer when we reach the
+ * end of it.
+ */
+ int yy_fill_buffer;
+
+ int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+ /* When an EOF's been seen but there's still some text to process
+ * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+ * shouldn't try reading from the input source any more. We might
+ * still have a bunch of tokens to match, though, because of
+ * possible backing-up.
+ *
+ * When we actually see the EOF, we change the status to "new"
+ * (via yyrestart()), so that the user can continue scanning by
+ * just pointing yyin at a new input file.
+ */
+#define YY_BUFFER_EOF_PENDING 2
+
+ };
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+ : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */
+yy_size_t yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0; /* whether we need to initialize */
+static int yy_start = 0; /* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin. A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void yyrestart (FILE *input_file );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size );
+void yy_delete_buffer (YY_BUFFER_STATE b );
+void yy_flush_buffer (YY_BUFFER_STATE b );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer );
+void yypop_buffer_state (void );
+
+static void yyensure_buffer_stack (void );
+static void yy_load_buffer_state (void );
+static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file );
+
+#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,yy_size_t len );
+
+void *yyalloc (yy_size_t );
+void *yyrealloc (void *,yy_size_t );
+void yyfree (void * );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){ \
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+ }
+
+#define yy_set_bol(at_bol) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){\
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+ }
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+#define yywrap(n) 1
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int yylineno;
+
+int yylineno = 1;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[] );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+ (yytext_ptr) = yy_bp; \
+ yyleng = (yy_size_t) (yy_cp - yy_bp); \
+ (yy_hold_char) = *yy_cp; \
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 15
+#define YY_END_OF_BUFFER 16
+/* This struct is not used in this scanner,
+ but its presence is necessary. */
+struct yy_trans_info
+ {
+ flex_int32_t yy_verify;
+ flex_int32_t yy_nxt;
+ };
+static yyconst flex_int16_t yy_accept[60] =
+ { 0,
+ 0, 0, 16, 14, 13, 12, 11, 8, 8, 10,
+ 10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
+ 10, 8, 0, 10, 10, 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10, 10, 7, 9, 10, 10,
+ 10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
+ 5, 1, 2, 3, 10, 6, 10, 4, 0
+ } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 4, 1, 1, 5, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 6, 7, 7,
+ 7, 7, 7, 7, 7, 7, 7, 1, 8, 1,
+ 1, 1, 1, 1, 9, 10, 11, 12, 13, 10,
+ 14, 15, 16, 15, 15, 15, 17, 18, 15, 15,
+ 15, 19, 20, 15, 15, 15, 15, 15, 15, 15,
+ 1, 1, 1, 1, 15, 1, 21, 10, 22, 23,
+
+ 24, 10, 25, 15, 26, 15, 15, 15, 27, 28,
+ 15, 29, 15, 30, 31, 15, 15, 15, 15, 32,
+ 15, 15, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1
+ } ;
+
+static yyconst flex_int32_t yy_meta[33] =
+ { 0,
+ 1, 1, 1, 1, 1, 2, 2, 1, 2, 2,
+ 2, 2, 2, 3, 3, 3, 3, 3, 3, 3,
+ 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
+ 3, 3
+ } ;
+
+static yyconst flex_int16_t yy_base[62] =
+ { 0,
+ 0, 0, 83, 84, 84, 84, 84, 27, 29, 70,
+ 0, 62, 61, 60, 20, 55, 47, 46, 45, 12,
+ 35, 37, 0, 0, 62, 60, 59, 58, 53, 49,
+ 45, 43, 42, 41, 37, 32, 0, 0, 43, 44,
+ 43, 42, 42, 36, 23, 27, 26, 25, 25, 20,
+ 0, 0, 0, 0, 35, 0, 23, 0, 84, 58,
+ 43
+ } ;
+
+static yyconst flex_int16_t yy_def[62] =
+ { 0,
+ 59, 1, 59, 59, 59, 59, 59, 59, 59, 60,
+ 60, 60, 60, 60, 60, 60, 60, 60, 60, 60,
+ 60, 59, 61, 60, 60, 60, 60, 60, 60, 60,
+ 60, 60, 60, 60, 60, 60, 60, 61, 60, 60,
+ 60, 60, 60, 60, 60, 60, 60, 60, 60, 60,
+ 60, 60, 60, 60, 60, 60, 60, 60, 0, 59,
+ 59
+ } ;
+
+static yyconst flex_int16_t yy_nxt[117] =
+ { 0,
+ 4, 5, 6, 5, 7, 8, 9, 7, 10, 11,
+ 12, 13, 11, 14, 11, 15, 11, 11, 11, 11,
+ 16, 17, 18, 11, 19, 20, 11, 11, 21, 11,
+ 11, 11, 22, 22, 22, 22, 29, 30, 35, 36,
+ 37, 37, 22, 22, 38, 58, 58, 56, 57, 54,
+ 53, 52, 51, 56, 55, 54, 53, 52, 23, 24,
+ 24, 51, 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 40, 39, 34, 33, 32, 31, 28, 27,
+ 26, 25, 59, 3, 59, 59, 59, 59, 59, 59,
+ 59, 59, 59, 59, 59, 59, 59, 59, 59, 59,
+
+ 59, 59, 59, 59, 59, 59, 59, 59, 59, 59,
+ 59, 59, 59, 59, 59, 59
+ } ;
+
+static yyconst flex_int16_t yy_chk[117] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 8, 8, 9, 9, 15, 15, 20, 20,
+ 21, 21, 22, 22, 61, 57, 55, 50, 49, 48,
+ 47, 46, 45, 44, 43, 42, 41, 40, 8, 60,
+ 60, 39, 36, 35, 34, 33, 32, 31, 30, 29,
+ 28, 27, 26, 25, 19, 18, 17, 16, 14, 13,
+ 12, 10, 3, 59, 59, 59, 59, 59, 59, 59,
+ 59, 59, 59, 59, 59, 59, 59, 59, 59, 59,
+
+ 59, 59, 59, 59, 59, 59, 59, 59, 59, 59,
+ 59, 59, 59, 59, 59, 59
+ } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int yy_flex_debug;
+int yy_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "itbl-lex.l"
+/* itbl-lex.l
+ Copyright (C) 1997-2017 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+#line 24 "itbl-lex.l"
+#include "as.h"
+#include "itbl-lex.h"
+#include <itbl-parse.h>
+
+#ifdef DEBUG
+#define DBG(x) printf x
+#define MDBG(x) printf x
+#else
+#define DBG(x)
+#define MDBG(x)
+#endif
+
+int insntbl_line = 1;
+#line 530 "itbl-lex.c"
+
+#define INITIAL 0
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Accessor methods to globals.
+ These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined );
+
+FILE *yyget_in (void );
+
+void yyset_in (FILE * in_str );
+
+FILE *yyget_out (void );
+
+void yyset_out (FILE * out_str );
+
+yy_size_t yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+ static void yyunput (int c,char *buf_ptr );
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO fwrite( yytext, yyleng, 1, yyout )
+#endif
+
+/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+ { \
+ int c = '*'; \
+ yy_size_t n; \
+ for ( n = 0; n < max_size && \
+ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+ buf[n] = (char) c; \
+ if ( c == '\n' ) \
+ buf[n++] = (char) c; \
+ if ( c == EOF && ferror( yyin ) ) \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ result = n; \
+ } \
+ else \
+ { \
+ errno=0; \
+ while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+ { \
+ if( errno != EINTR) \
+ { \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ break; \
+ } \
+ errno=0; \
+ clearerr(yyin); \
+ } \
+ }\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+ YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp, *yy_bp;
+ register int yy_act;
+
+#line 44 "itbl-lex.l"
+
+
+#line 715 "itbl-lex.c"
+
+ if ( !(yy_init) )
+ {
+ (yy_init) = 1;
+
+#ifdef YY_USER_INIT
+ YY_USER_INIT;
+#endif
+
+ if ( ! (yy_start) )
+ (yy_start) = 1; /* first start state */
+
+ if ( ! yyin )
+ yyin = stdin;
+
+ if ( ! yyout )
+ yyout = stdout;
+
+ if ( ! YY_CURRENT_BUFFER ) {
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer(yyin,YY_BUF_SIZE );
+ }
+
+ yy_load_buffer_state( );
+ }
+
+ while ( 1 ) /* loops until end-of-file is reached */
+ {
+ yy_cp = (yy_c_buf_p);
+
+ /* Support of yytext. */
+ *yy_cp = (yy_hold_char);
+
+ /* yy_bp points to the position in yy_ch_buf of the start of
+ * the current run.
+ */
+ yy_bp = yy_cp;
+
+ yy_current_state = (yy_start);
+yy_match:
+ do
+ {
+ register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 60 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ ++yy_cp;
+ }
+ while ( yy_base[yy_current_state] != 84 );
+
+yy_find_action:
+ yy_act = yy_accept[yy_current_state];
+ if ( yy_act == 0 )
+ { /* have to back up */
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ yy_act = yy_accept[yy_current_state];
+ }
+
+ YY_DO_BEFORE_ACTION;
+
+do_action: /* This label is used only to access EOF actions. */
+
+ switch ( yy_act )
+ { /* beginning of action switch */
+ case 0: /* must back up */
+ /* undo the effects of YY_DO_BEFORE_ACTION */
+ *yy_cp = (yy_hold_char);
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 46 "itbl-lex.l"
+{
+ return CREG;
+ }
+ YY_BREAK
+case 2:
+YY_RULE_SETUP
+#line 49 "itbl-lex.l"
+{
+ return DREG;
+ }
+ YY_BREAK
+case 3:
+YY_RULE_SETUP
+#line 52 "itbl-lex.l"
+{
+ return GREG;
+ }
+ YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 55 "itbl-lex.l"
+{
+ return IMMED;
+ }
+ YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 58 "itbl-lex.l"
+{
+ return ADDR;
+ }
+ YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 61 "itbl-lex.l"
+{
+ return INSN;
+ }
+ YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 64 "itbl-lex.l"
+{
+ yytext[yyleng] = 0;
+ yylval.processor = strtoul (yytext+1, 0, 0);
+ return PNUM;
+ }
+ YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 69 "itbl-lex.l"
+{
+ yytext[yyleng] = 0;
+ yylval.num = strtoul (yytext, 0, 0);
+ return NUM;
+ }
+ YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 74 "itbl-lex.l"
+{
+ yytext[yyleng] = 0;
+ yylval.num = strtoul (yytext, 0, 0);
+ return NUM;
+ }
+ YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 79 "itbl-lex.l"
+{
+ yytext[yyleng] = 0;
+ yylval.str = strdup (yytext);
+ return ID;
+ }
+ YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 84 "itbl-lex.l"
+{
+ int c;
+ while ((c = input ()) != EOF)
+ {
+ if (c == '\n')
+ {
+ unput (c);
+ break;
+ }
+ }
+ }
+ YY_BREAK
+case 12:
+/* rule 12 can match eol */
+YY_RULE_SETUP
+#line 95 "itbl-lex.l"
+{
+ insntbl_line++;
+ MDBG (("in lex, NL = %d (x%x)\n", NL, NL));
+ return NL;
+ }
+ YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 100 "itbl-lex.l"
+{
+ }
+ YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 102 "itbl-lex.l"
+{
+ MDBG (("char = %x, %d\n", yytext[0], yytext[0]));
+ return yytext[0];
+ }
+ YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 106 "itbl-lex.l"
+ECHO;
+ YY_BREAK
+#line 920 "itbl-lex.c"
+case YY_STATE_EOF(INITIAL):
+ yyterminate();
+
+ case YY_END_OF_BUFFER:
+ {
+ /* Amount of text matched not including the EOB char. */
+ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+ /* Undo the effects of YY_DO_BEFORE_ACTION. */
+ *yy_cp = (yy_hold_char);
+ YY_RESTORE_YY_MORE_OFFSET
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+ {
+ /* We're scanning a new file or input source. It's
+ * possible that this happened because the user
+ * just pointed yyin at a new source and called
+ * yylex(). If so, then we have to assure
+ * consistency between YY_CURRENT_BUFFER and our
+ * globals. Here is the right place to do so, because
+ * this is the first action (other than possibly a
+ * back-up) that will match for the new input source.
+ */
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+ }
+
+ /* Note that here we test for yy_c_buf_p "<=" to the position
+ * of the first EOB in the buffer, since yy_c_buf_p will
+ * already have been incremented past the NUL character
+ * (since all states make transitions on EOB to the
+ * end-of-buffer state). Contrast this with the test
+ * in input().
+ */
+ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ { /* This was really a NUL. */
+ yy_state_type yy_next_state;
+
+ (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ /* Okay, we're now positioned to make the NUL
+ * transition. We couldn't have
+ * yy_get_previous_state() go ahead and do it
+ * for us because it doesn't know how to deal
+ * with the possibility of jamming (and we don't
+ * want to build jamming into it because then it
+ * will run more slowly).
+ */
+
+ yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+ if ( yy_next_state )
+ {
+ /* Consume the NUL. */
+ yy_cp = ++(yy_c_buf_p);
+ yy_current_state = yy_next_state;
+ goto yy_match;
+ }
+
+ else
+ {
+ yy_cp = (yy_c_buf_p);
+ goto yy_find_action;
+ }
+ }
+
+ else switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_END_OF_FILE:
+ {
+ (yy_did_buffer_switch_on_eof) = 0;
+
+ if ( yywrap( ) )
+ {
+ /* Note: because we've taken care in
+ * yy_get_next_buffer() to have set up
+ * yytext, we can now set up
+ * yy_c_buf_p so that if some total
+ * hoser (like flex itself) wants to
+ * call the scanner after we return the
+ * YY_NULL, it'll still work - another
+ * YY_NULL will get returned.
+ */
+ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+ yy_act = YY_STATE_EOF(YY_START);
+ goto do_action;
+ }
+
+ else
+ {
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+ }
+ break;
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) =
+ (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_match;
+
+ case EOB_ACT_LAST_MATCH:
+ (yy_c_buf_p) =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_find_action;
+ }
+ break;
+ }
+
+ default:
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--no action found" );
+ } /* end of action switch */
+ } /* end of scanning one token */
+} /* end of yylex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ * EOB_ACT_LAST_MATCH -
+ * EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ * EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+ register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+ register char *source = (yytext_ptr);
+ register int number_to_move, i;
+ int ret_val;
+
+ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--end of buffer missed" );
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+ { /* Don't try to fill the buffer, so this is an EOF. */
+ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+ {
+ /* We matched a single character, the EOB, so
+ * treat this as a final EOF.
+ */
+ return EOB_ACT_END_OF_FILE;
+ }
+
+ else
+ {
+ /* We matched some text prior to the EOB, first
+ * process it.
+ */
+ return EOB_ACT_LAST_MATCH;
+ }
+ }
+
+ /* Try to read more data. */
+
+ /* First move last chars to start of buffer. */
+ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+ for ( i = 0; i < number_to_move; ++i )
+ *(dest++) = *(source++);
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+ /* don't do the read, it's not guaranteed to return an EOF,
+ * just force an EOF
+ */
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+ else
+ {
+ yy_size_t num_to_read =
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+ while ( num_to_read <= 0 )
+ { /* Not enough room in the buffer - grow it. */
+
+ /* just a shorter name for the current buffer */
+ YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+ int yy_c_buf_p_offset =
+ (int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+ if ( b->yy_is_our_buffer )
+ {
+ yy_size_t new_size = b->yy_buf_size * 2;
+
+ if ( new_size <= 0 )
+ b->yy_buf_size += b->yy_buf_size / 8;
+ else
+ b->yy_buf_size *= 2;
+
+ b->yy_ch_buf = (char *)
+ /* Include room in for 2 EOB chars. */
+ yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
+ }
+ else
+ /* Can't grow it, we don't own it. */
+ b->yy_ch_buf = 0;
+
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR(
+ "fatal error - scanner input buffer overflow" );
+
+ (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+ num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+ number_to_move - 1;
+
+ }
+
+ if ( num_to_read > YY_READ_BUF_SIZE )
+ num_to_read = YY_READ_BUF_SIZE;
+
+ /* Read in more data. */
+ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+ (yy_n_chars), num_to_read );
+
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ if ( (yy_n_chars) == 0 )
+ {
+ if ( number_to_move == YY_MORE_ADJ )
+ {
+ ret_val = EOB_ACT_END_OF_FILE;
+ yyrestart(yyin );
+ }
+
+ else
+ {
+ ret_val = EOB_ACT_LAST_MATCH;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+ YY_BUFFER_EOF_PENDING;
+ }
+ }
+
+ else
+ ret_val = EOB_ACT_CONTINUE_SCAN;
+
+ if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+ /* Extend the array by 50%, plus the number we really need. */
+ yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size );
+ if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+ }
+
+ (yy_n_chars) += number_to_move;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+ (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+ return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+ static yy_state_type yy_get_previous_state (void)
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp;
+
+ yy_current_state = (yy_start);
+
+ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+ {
+ register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 60 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ }
+
+ return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ * next_state = yy_try_NUL_trans( current_state );
+ */
+ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
+{
+ register int yy_is_jam;
+ register char *yy_cp = (yy_c_buf_p);
+
+ register YY_CHAR yy_c = 1;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 60 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ yy_is_jam = (yy_current_state == 59);
+
+ return yy_is_jam ? 0 : yy_current_state;
+}
+
+ static void yyunput (int c, register char * yy_bp )
+{
+ register char *yy_cp;
+
+ yy_cp = (yy_c_buf_p);
+
+ /* undo effects of setting up yytext */
+ *yy_cp = (yy_hold_char);
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ { /* need to shift things up to make room */
+ /* +2 for EOB chars. */
+ register yy_size_t number_to_move = (yy_n_chars) + 2;
+ register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+ register char *source =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+ while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ *--dest = *--source;
+
+ yy_cp += (int) (dest - source);
+ yy_bp += (int) (dest - source);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ YY_FATAL_ERROR( "flex scanner push-back overflow" );
+ }
+
+ *--yy_cp = (char) c;
+
+ (yytext_ptr) = yy_bp;
+ (yy_hold_char) = *yy_cp;
+ (yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+ static int yyinput (void)
+#else
+ static int input (void)
+#endif
+
+{
+ int c;
+
+ *(yy_c_buf_p) = (yy_hold_char);
+
+ if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+ {
+ /* yy_c_buf_p now points to the character we want to return.
+ * If this occurs *before* the EOB characters, then it's a
+ * valid NUL; if not, then we've hit the end of the buffer.
+ */
+ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ /* This was really a NUL. */
+ *(yy_c_buf_p) = '\0';
+
+ else
+ { /* need more input */
+ yy_size_t offset = (yy_c_buf_p) - (yytext_ptr);
+ ++(yy_c_buf_p);
+
+ switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_LAST_MATCH:
+ /* This happens because yy_g_n_b()
+ * sees that we've accumulated a
+ * token and flags that we need to
+ * try matching the token before
+ * proceeding. But for input(),
+ * there's no matching to consider.
+ * So convert the EOB_ACT_LAST_MATCH
+ * to EOB_ACT_END_OF_FILE.
+ */
+
+ /* Reset buffer status. */
+ yyrestart(yyin );
+
+ /*FALLTHROUGH*/
+
+ case EOB_ACT_END_OF_FILE:
+ {
+ if ( yywrap( ) )
+ return 0;
+
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+#ifdef __cplusplus
+ return yyinput();
+#else
+ return input();
+#endif
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) = (yytext_ptr) + offset;
+ break;
+ }
+ }
+ }
+
+ c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
+ *(yy_c_buf_p) = '\0'; /* preserve yytext */
+ (yy_hold_char) = *++(yy_c_buf_p);
+
+ return c;
+}
+#endif /* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ *
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+ void yyrestart (FILE * input_file )
+{
+
+ if ( ! YY_CURRENT_BUFFER ){
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer(yyin,YY_BUF_SIZE );
+ }
+
+ yy_init_buffer(YY_CURRENT_BUFFER,input_file );
+ yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ *
+ */
+ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer )
+{
+
+ /* TODO. We should be able to replace this entire function body
+ * with
+ * yypop_buffer_state();
+ * yypush_buffer_state(new_buffer);
+ */
+ yyensure_buffer_stack ();
+ if ( YY_CURRENT_BUFFER == new_buffer )
+ return;
+
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+ yy_load_buffer_state( );
+
+ /* We don't actually know whether we did this switch during
+ * EOF (yywrap()) processing, but the only time this flag
+ * is looked at is after yywrap() is called, so it's safe
+ * to go ahead and always set it.
+ */
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void yy_load_buffer_state (void)
+{
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+ yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+ (yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ *
+ * @return the allocated buffer state.
+ */
+ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size )
+{
+ YY_BUFFER_STATE b;
+
+ b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_buf_size = size;
+
+ /* yy_ch_buf has to be 2 characters longer than the size given because
+ * we need to put in 2 end-of-buffer characters.
+ */
+ b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 );
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_is_our_buffer = 1;
+
+ yy_init_buffer(b,file );
+
+ return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ *
+ */
+ void yy_delete_buffer (YY_BUFFER_STATE b )
+{
+
+ if ( ! b )
+ return;
+
+ if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+ if ( b->yy_is_our_buffer )
+ yyfree((void *) b->yy_ch_buf );
+
+ yyfree((void *) b );
+}
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+ static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file )
+
+{
+ int oerrno = errno;
+
+ yy_flush_buffer(b );
+
+ b->yy_input_file = file;
+ b->yy_fill_buffer = 1;
+
+ /* If b is the current buffer, then yy_init_buffer was _probably_
+ * called from yyrestart() or through yy_get_next_buffer.
+ * In that case, we don't want to reset the lineno or column.
+ */
+ if (b != YY_CURRENT_BUFFER){
+ b->yy_bs_lineno = 1;
+ b->yy_bs_column = 0;
+ }
+
+ b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+
+ errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ *
+ */
+ void yy_flush_buffer (YY_BUFFER_STATE b )
+{
+ if ( ! b )
+ return;
+
+ b->yy_n_chars = 0;
+
+ /* We always need two end-of-buffer characters. The first causes
+ * a transition to the end-of-buffer state. The second causes
+ * a jam in that state.
+ */
+ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+ b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+ b->yy_buf_pos = &b->yy_ch_buf[0];
+
+ b->yy_at_bol = 1;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ if ( b == YY_CURRENT_BUFFER )
+ yy_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ * the current state. This function will allocate the stack
+ * if necessary.
+ * @param new_buffer The new state.
+ *
+ */
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+ if (new_buffer == NULL)
+ return;
+
+ yyensure_buffer_stack();
+
+ /* This block is copied from yy_switch_to_buffer. */
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ /* Only push if top exists. Otherwise, replace top. */
+ if (YY_CURRENT_BUFFER)
+ (yy_buffer_stack_top)++;
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+ /* copied from yy_switch_to_buffer. */
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ * The next element becomes the new top.
+ *
+ */
+void yypop_buffer_state (void)
+{
+ if (!YY_CURRENT_BUFFER)
+ return;
+
+ yy_delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ if ((yy_buffer_stack_top) > 0)
+ --(yy_buffer_stack_top);
+
+ if (YY_CURRENT_BUFFER) {
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+ }
+}
+
+/* Allocates the stack if it does not exist.
+ * Guarantees space for at least one push.
+ */
+static void yyensure_buffer_stack (void)
+{
+ yy_size_t num_to_alloc;
+
+ if (!(yy_buffer_stack)) {
+
+ /* First allocation is just for 2 elements, since we don't know if this
+ * scanner will even need a stack. We use 2 instead of 1 to avoid an
+ * immediate realloc on the next call.
+ */
+ num_to_alloc = 1;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+ (num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+
+ (yy_buffer_stack_max) = num_to_alloc;
+ (yy_buffer_stack_top) = 0;
+ return;
+ }
+
+ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+ /* Increase the buffer to prepare for a possible push. */
+ int grow_size = 8 /* arbitrary grow size */;
+
+ num_to_alloc = (yy_buffer_stack_max) + grow_size;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+ ((yy_buffer_stack),
+ num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ /* zero only the new slots.*/
+ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+ (yy_buffer_stack_max) = num_to_alloc;
+ }
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size )
+{
+ YY_BUFFER_STATE b;
+
+ if ( size < 2 ||
+ base[size-2] != YY_END_OF_BUFFER_CHAR ||
+ base[size-1] != YY_END_OF_BUFFER_CHAR )
+ /* They forgot to leave room for the EOB's. */
+ return 0;
+
+ b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+ b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
+ b->yy_buf_pos = b->yy_ch_buf = base;
+ b->yy_is_our_buffer = 0;
+ b->yy_input_file = 0;
+ b->yy_n_chars = b->yy_buf_size;
+ b->yy_is_interactive = 0;
+ b->yy_at_bol = 1;
+ b->yy_fill_buffer = 0;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ yy_switch_to_buffer(b );
+
+ return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to yylex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ *
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ * yy_scan_bytes() instead.
+ */
+YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+{
+
+ return yy_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len )
+{
+ YY_BUFFER_STATE b;
+ char *buf;
+ yy_size_t n, i;
+
+ /* Get memory for full buffer, including space for trailing EOB's. */
+ n = _yybytes_len + 2;
+ buf = (char *) yyalloc(n );
+ if ( ! buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+ for ( i = 0; i < _yybytes_len; ++i )
+ buf[i] = yybytes[i];
+
+ buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+ b = yy_scan_buffer(buf,n );
+ if ( ! b )
+ YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+ /* It's okay to grow etc. this buffer, and we should throw it
+ * away when we're done.
+ */
+ b->yy_is_our_buffer = 1;
+
+ return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+ (void) fprintf( stderr, "%s\n", msg );
+ exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ yytext[yyleng] = (yy_hold_char); \
+ (yy_c_buf_p) = yytext + yyless_macro_arg; \
+ (yy_hold_char) = *(yy_c_buf_p); \
+ *(yy_c_buf_p) = '\0'; \
+ yyleng = yyless_macro_arg; \
+ } \
+ while ( 0 )
+
+/* Accessor methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ *
+ */
+int yyget_lineno (void)
+{
+
+ return yylineno;
+}
+
+/** Get the input stream.
+ *
+ */
+FILE *yyget_in (void)
+{
+ return yyin;
+}
+
+/** Get the output stream.
+ *
+ */
+FILE *yyget_out (void)
+{
+ return yyout;
+}
+
+/** Get the length of the current token.
+ *
+ */
+yy_size_t yyget_leng (void)
+{
+ return yyleng;
+}
+
+/** Get the current token.
+ *
+ */
+
+char *yyget_text (void)
+{
+ return yytext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ *
+ */
+void yyset_lineno (int line_number )
+{
+
+ yylineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ *
+ * @see yy_switch_to_buffer
+ */
+void yyset_in (FILE * in_str )
+{
+ yyin = in_str ;
+}
+
+void yyset_out (FILE * out_str )
+{
+ yyout = out_str ;
+}
+
+int yyget_debug (void)
+{
+ return yy_flex_debug;
+}
+
+void yyset_debug (int bdebug )
+{
+ yy_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+ /* Initialization is the same as for the non-reentrant scanner.
+ * This function is called from yylex_destroy(), so don't allocate here.
+ */
+
+ (yy_buffer_stack) = 0;
+ (yy_buffer_stack_top) = 0;
+ (yy_buffer_stack_max) = 0;
+ (yy_c_buf_p) = (char *) 0;
+ (yy_init) = 0;
+ (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+ yyin = stdin;
+ yyout = stdout;
+#else
+ yyin = (FILE *) 0;
+ yyout = (FILE *) 0;
+#endif
+
+ /* For future reference: Set errno on error, since we are called by
+ * yylex_init()
+ */
+ return 0;
+}
+
+/* yylex_destroy is for both reentrant and non-reentrant scanners. */
+int yylex_destroy (void)
+{
+
+ /* Pop the buffer stack, destroying each element. */
+ while(YY_CURRENT_BUFFER){
+ yy_delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ yypop_buffer_state();
+ }
+
+ /* Destroy the stack itself. */
+ yyfree((yy_buffer_stack) );
+ (yy_buffer_stack) = NULL;
+
+ /* Reset the globals. This is important in a non-reentrant scanner so the next time
+ * yylex() is called, initialization will occur. */
+ yy_init_globals( );
+
+ return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+ register int i;
+ for ( i = 0; i < n; ++i )
+ s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+ register int n;
+ for ( n = 0; s[n]; ++n )
+ ;
+
+ return n;
+}
+#endif
+
+void *yyalloc (yy_size_t size )
+{
+ return (void *) malloc( size );
+}
+
+void *yyrealloc (void * ptr, yy_size_t size )
+{
+ /* The cast to (char *) in the following accommodates both
+ * implementations that use char* generic pointers, and those
+ * that use void* generic pointers. It works with the latter
+ * because both ANSI C and C++ allow castless assignment from
+ * any pointer type to void*, and deal with argument conversions
+ * as though doing an assignment.
+ */
+ return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+ free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 106 "itbl-lex.l"
+
+
+
diff --git a/gas/itbl-parse.c b/gas/itbl-parse.c
new file mode 100644
index 0000000..b1b1ace
--- /dev/null
+++ b/gas/itbl-parse.c
@@ -0,0 +1,1906 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison implementation for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "3.0"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Push parsers. */
+#define YYPUSH 0
+
+/* Pull parsers. */
+#define YYPULL 1
+
+
+
+
+/* Copy the first part of user declarations. */
+#line 21 "./itbl-parse.y" /* yacc.c:339 */
+
+
+/*
+
+Yacc grammar for instruction table entries.
+
+=======================================================================
+Original Instruction table specification document:
+
+ MIPS Coprocessor Table Specification
+ ====================================
+
+This document describes the format of the MIPS coprocessor table. The
+table specifies a list of valid functions, data registers and control
+registers that can be used in coprocessor instructions. This list,
+together with the coprocessor instruction classes listed below,
+specifies the complete list of coprocessor instructions that will
+be recognized and assembled by the GNU assembler. In effect,
+this makes the GNU assembler table-driven, where the table is
+specified by the programmer.
+
+The table is an ordinary text file that the GNU assembler reads when
+it starts. Using the information in the table, the assembler
+generates an internal list of valid coprocessor registers and
+functions. The assembler uses this internal list in addition to the
+standard MIPS registers and instructions which are built-in to the
+assembler during code generation.
+
+To specify the coprocessor table when invoking the GNU assembler, use
+the command line option "--itbl file", where file is the
+complete name of the table, including path and extension.
+
+Examples:
+
+ gas -t cop.tbl test.s -o test.o
+ gas -t /usr/local/lib/cop.tbl test.s -o test.o
+ gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
+
+Only one table may be supplied during a single invocation of
+the assembler.
+
+
+Instruction classes
+===================
+
+Below is a list of the valid coprocessor instruction classes for
+any given coprocessor "z". These instructions are already recognized
+by the assembler, and are listed here only for reference.
+
+Class format instructions
+-------------------------------------------------
+Class1:
+ op base rt offset
+ LWCz rt,offset (base)
+ SWCz rt,offset (base)
+Class2:
+ COPz sub rt rd 0
+ MTCz rt,rd
+ MFCz rt,rd
+ CTCz rt,rd
+ CFCz rt,rd
+Class3:
+ COPz CO cofun
+ COPz cofun
+Class4:
+ COPz BC br offset
+ BCzT offset
+ BCzF offset
+Class5:
+ COPz sub rt rd 0
+ DMFCz rt,rd
+ DMTCz rt,rd
+Class6:
+ op base rt offset
+ LDCz rt,offset (base)
+ SDCz rt,offset (base)
+Class7:
+ COPz BC br offset
+ BCzTL offset
+ BCzFL offset
+
+The coprocessor table defines coprocessor-specific registers that can
+be used with all of the above classes of instructions, where
+appropriate. It also defines additional coprocessor-specific
+functions for Class3 (COPz cofun) instructions, Thus, the table allows
+the programmer to use convenient mnemonics and operands for these
+functions, instead of the COPz mmenmonic and cofun operand.
+
+The names of the MIPS general registers and their aliases are defined
+by the assembler and will be recognized as valid register names by the
+assembler when used (where allowed) in coprocessor instructions.
+However, the names and values of all coprocessor data and control
+register mnemonics must be specified in the coprocessor table.
+
+
+Table Grammar
+=============
+
+Here is the grammar for the coprocessor table:
+
+ table -> entry*
+
+ entry -> [z entrydef] [comment] '\n'
+
+ entrydef -> type name val
+ entrydef -> 'insn' name val funcdef ; type of entry (instruction)
+
+ z -> 'p'['0'..'3'] ; processor number
+ type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
+ ; 'dreg', 'creg' or 'greg' specifies a data, control, or general
+ ; register mnemonic, respectively
+ name -> [ltr|dec]* ; mnemonic of register/function
+ val -> [dec|hex] ; register/function number (integer constant)
+
+ funcdef -> frange flags fields
+ ; bitfield range for opcode
+ ; list of fields' formats
+ fields -> field*
+ field -> [','] ftype frange flags
+ flags -> ['*' flagexpr]
+ flagexpr -> '[' flagexpr ']'
+ flagexpr -> val '|' flagexpr
+ ftype -> [ type | 'immed' | 'addr' ]
+ ; 'immed' specifies an immediate value; see grammar for "val" above
+ ; 'addr' specifies a C identifier; name of symbol to be resolved at
+ ; link time
+ frange -> ':' val '-' val ; starting to ending bit positions, where
+ ; where 0 is least significant bit
+ frange -> (null) ; default range of 31-0 will be assumed
+
+ comment -> [';'|'#'] [char]*
+ char -> any printable character
+ ltr -> ['a'..'z'|'A'..'Z']
+ dec -> ['0'..'9']* ; value in decimal
+ hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexadecimal
+
+
+Examples
+========
+
+Example 1:
+
+The table:
+
+ p1 dreg d1 1 ; data register "d1" for COP1 has value 1
+ p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
+ p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
+ ; no fields
+
+will allow the assembler to accept the following coprocessor instructions:
+
+ LWC1 d1,0x100 ($2)
+ fill
+
+Here, the general purpose register "$2", and instruction "LWC1", are standard
+mnemonics built-in to the MIPS assembler.
+
+
+Example 2:
+
+The table:
+
+ p3 dreg d3 3 ; data register "d3" for COP3 has value 3
+ p3 creg c2 22 ; control register "c2" for COP3 has value 22
+ p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
+ ; function "fee" for COP3 has value 31, and 3 fields
+ ; consisting of a data register, a control register,
+ ; and an immediate value.
+
+will allow the assembler to accept the following coprocessor instruction:
+
+ fee d3,c2,0x1
+
+and will emit the object code:
+
+ 31-26 25 24-20 19-18 17-13 12-8 7-0
+ COPz CO fun dreg creg immed
+ 010011 1 11111 00 00011 10110 00000001
+
+ 0x4ff07601
+
+
+Example 3:
+
+The table:
+
+ p3 dreg d3 3 ; data register "d3" for COP3 has value 3
+ p3 creg c2 22 ; control register "c2" for COP3 has value 22
+ p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
+
+will allow the assembler to accept the following coprocessor
+instruction:
+
+ fuu d3,c2
+
+and will emit the object code:
+
+ 31-26 25 24-20 19-18 17-13 12-8 7-0
+ COPz CO fun dreg creg
+ 010011 1 11111 00 00011 10110 00000001
+
+ 0x4ff07601
+
+In this way, the programmer can force arbitrary bits of an instruction
+to have predefined values.
+
+=======================================================================
+Additional notes:
+
+Encoding of ranges:
+To handle more than one bit position range within an instruction,
+use 0s to mask out the ranges which don't apply.
+May decide to modify the syntax to allow commas separate multiple
+ranges within an instruction (range','range).
+
+Changes in grammar:
+ The number of parms argument to the function entry
+was deleted from the original format such that we now count the fields.
+
+----
+FIXME! should really change lexical analyzer
+to recognize 'dreg' etc. in context sensitive way.
+Currently function names or mnemonics may be incorrectly parsed as keywords
+
+FIXME! hex is ambiguous with any digit
+
+*/
+
+#include "as.h"
+#include "itbl-lex.h"
+#include "itbl-ops.h"
+
+/* #define DEBUG */
+
+#ifdef DEBUG
+#ifndef DBG_LVL
+#define DBG_LVL 1
+#endif
+#else
+#define DBG_LVL 0
+#endif
+
+#if DBG_LVL >= 1
+#define DBG(x) printf x
+#else
+#define DBG(x)
+#endif
+
+#if DBG_LVL >= 2
+#define DBGL2(x) printf x
+#else
+#define DBGL2(x)
+#endif
+
+static int sbit, ebit;
+static struct itbl_entry *insn=0;
+static int yyerror (const char *);
+
+
+#line 326 "itbl-parse.c" /* yacc.c:339 */
+
+# ifndef YY_NULL
+# if defined __cplusplus && 201103L <= __cplusplus
+# define YY_NULL nullptr
+# else
+# define YY_NULL 0
+# endif
+# endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* In a future release of Bison, this section will be replaced
+ by #include "y.tab.h". */
+#ifndef YY_YY_ITBL_PARSE_H_INCLUDED
+# define YY_YY_ITBL_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ DREG = 258,
+ CREG = 259,
+ GREG = 260,
+ IMMED = 261,
+ ADDR = 262,
+ INSN = 263,
+ NUM = 264,
+ ID = 265,
+ NL = 266,
+ PNUM = 267
+ };
+#endif
+/* Tokens. */
+#define DREG 258
+#define CREG 259
+#define GREG 260
+#define IMMED 261
+#define ADDR 262
+#define INSN 263
+#define NUM 264
+#define ID 265
+#define NL 266
+#define PNUM 267
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 282 "./itbl-parse.y" /* yacc.c:355 */
+
+ char *str;
+ int num;
+ int processor;
+ unsigned long val;
+
+
+#line 398 "itbl-parse.c" /* yacc.c:355 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_ITBL_PARSE_H_INCLUDED */
+
+/* Copy the second part of user declarations. */
+
+#line 413 "itbl-parse.c" /* yacc.c:358 */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef __attribute__
+/* This feature is available in gcc versions 2.5 and later. */
+# if (! defined __GNUC__ || __GNUC__ < 2 \
+ || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+# define __attribute__(Spec) /* empty */
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+ _Pragma ("GCC diagnostic push") \
+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+ _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's 'empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+ Stack = &yyptr->Stack_alloc; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(Dst, Src, Count) \
+ __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+# else
+# define YYCOPY(Dst, Src, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 9
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 46
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 20
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 15
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 29
+/* YYNSTATES -- Number of states. */
+#define YYNSTATES 51
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+ by yylex, with out-of-bounds checking. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 267
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, without out-of-bounds checking. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 17, 2, 13, 19, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 18, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 15, 2, 16, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 14, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12
+};
+
+#if YYDEBUG
+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 299, 299, 303, 304, 308, 315, 314, 323, 324,
+ 328, 329, 330, 334, 339, 344, 352, 361, 365, 369,
+ 376, 382, 388, 395, 402, 410, 415, 420, 428, 444
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "DREG", "CREG", "GREG", "IMMED", "ADDR",
+ "INSN", "NUM", "ID", "NL", "PNUM", "','", "'|'", "'['", "']'", "'*'",
+ "':'", "'-'", "$accept", "insntbl", "entrys", "entry", "$@1",
+ "fieldspecs", "ftype", "fieldspec", "flagexpr", "flags", "range", "pnum",
+ "regtype", "name", "value", YY_NULL
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+ (internal) symbol number NUM (which must be that of a token). */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 44, 124, 91, 93, 42, 58, 45
+};
+# endif
+
+#define YYPACT_NINF -16
+
+#define yypact_value_is_default(Yystate) \
+ (!!((Yystate) == (-16)))
+
+#define YYTABLE_NINF -5
+
+#define yytable_value_is_error(Yytable_value) \
+ 0
+
+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+static const yytype_int8 yypact[] =
+{
+ 0, -9, -16, -16, 10, -16, 0, 12, -16, -16,
+ -16, -16, -16, -16, 3, 3, -16, 9, 9, -16,
+ 11, 8, 19, 15, -16, 14, -6, -16, 25, 21,
+ -6, -16, 1, -16, -6, 20, -16, -16, 18, 26,
+ 11, 1, -16, -16, -16, 1, -16, 15, -16, -16,
+ -16
+};
+
+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+ Performed when YYTABLE does not specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint8 yydefact[] =
+{
+ 0, 0, 8, 24, 0, 2, 0, 0, 9, 1,
+ 3, 25, 26, 27, 0, 0, 28, 0, 0, 29,
+ 23, 0, 0, 21, 5, 0, 0, 6, 0, 19,
+ 0, 20, 12, 22, 0, 0, 15, 14, 0, 0,
+ 23, 12, 13, 17, 18, 12, 7, 21, 11, 10,
+ 16
+};
+
+ /* YYPGOTO[NTERM-NUM]. */
+static const yytype_int8 yypgoto[] =
+{
+ -16, -16, 32, -16, -16, -15, -16, 2, -3, -8,
+ 4, -16, 34, 27, 28
+};
+
+ /* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int8 yydefgoto[] =
+{
+ -1, 4, 5, 6, 32, 39, 40, 41, 31, 27,
+ 23, 7, 42, 17, 20
+};
+
+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule whose
+ number is the opposite. If YYTABLE_NINF, syntax error. */
+static const yytype_int8 yytable[] =
+{
+ -4, 1, 8, 29, 11, 12, 13, 36, 37, 30,
+ 9, 2, 3, 16, 38, 11, 12, 13, 19, 24,
+ 14, 11, 12, 13, 36, 37, 48, 35, 25, 22,
+ 49, 43, 26, 28, 33, 34, 44, 46, 10, 50,
+ 45, 15, 18, 0, 47, 0, 21
+};
+
+static const yytype_int8 yycheck[] =
+{
+ 0, 1, 11, 9, 3, 4, 5, 6, 7, 15,
+ 0, 11, 12, 10, 13, 3, 4, 5, 9, 11,
+ 8, 3, 4, 5, 6, 7, 41, 30, 9, 18,
+ 45, 34, 17, 19, 9, 14, 16, 11, 6, 47,
+ 38, 7, 15, -1, 40, -1, 18
+};
+
+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 1, 11, 12, 21, 22, 23, 31, 11, 0,
+ 22, 3, 4, 5, 8, 32, 10, 33, 33, 9,
+ 34, 34, 18, 30, 11, 9, 17, 29, 19, 9,
+ 15, 28, 24, 9, 14, 28, 6, 7, 13, 25,
+ 26, 27, 32, 28, 16, 27, 11, 30, 25, 25,
+ 29
+};
+
+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 20, 21, 22, 22, 23, 24, 23, 23, 23,
+ 25, 25, 25, 26, 26, 26, 27, 28, 28, 28,
+ 29, 29, 30, 30, 31, 32, 32, 32, 33, 34
+};
+
+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 1, 2, 0, 5, 0, 9, 1, 2,
+ 3, 2, 0, 1, 1, 1, 3, 3, 3, 1,
+ 2, 0, 4, 0, 1, 1, 1, 1, 1, 1
+};
+
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+/* Error token number */
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT. |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ YYFPRINTF (yyoutput, "%s %s (",
+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+ {
+ int yybot = *yybottom;
+ YYFPRINTF (stderr, " %d", yybot);
+ }
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr,
+ yystos[yyssp[yyi + 1 - yynrhs]],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ YYFPRINTF (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+ about the unexpected token YYTOKEN for the state stack whose top is
+ YYSSP.
+
+ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
+ not large enough to hold the message. In that case, also set
+ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
+ required number of bytes is too large to store. */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+{
+ YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+ const char *yyformat = YY_NULL;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+ "expected"). */
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+ tokens because there are none.
+ - The only way there can be no lookahead present (in yychar) is if
+ this state is a consistent state with a default action. Thus,
+ detecting the absence of a lookahead is sufficient to determine
+ that there is no unexpected or expected token to report. In that
+ case, just report a simple "syntax error".
+ - Don't assume there isn't a lookahead just because this state is a
+ consistent state with a default action. There might have been a
+ previous inconsistent state, consistent state with a non-default
+ action, or user semantic action that manipulated yychar.
+ - Of course, the expected token list depends on states to have
+ correct lookahead information, and it depends on the parser not
+ to perform extra reductions after fetching a lookahead from the
+ scanner and before detecting a syntax error. Thus, state merging
+ (from LALR or IELR) and default reductions corrupt the expected
+ token list. However, the list is correct for canonical LR with
+ one exception: it will still contain any token that will not be
+ accepted due to an error action in a later state.
+ */
+ if (yytoken != YYEMPTY)
+ {
+ int yyn = yypact[*yyssp];
+ yyarg[yycount++] = yytname[yytoken];
+ if (!yypact_value_is_default (yyn))
+ {
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. In other words, skip the first -YYN actions for
+ this state because they are default actions. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yyx;
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+ && !yytable_value_is_error (yytable[yyx + yyn]))
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+ }
+ }
+ }
+
+ switch (yycount)
+ {
+# define YYCASE_(N, S) \
+ case N: \
+ yyformat = S; \
+ break
+ YYCASE_(0, YY_("syntax error"));
+ YYCASE_(1, YY_("syntax error, unexpected %s"));
+ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+ }
+
+ {
+ YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+
+ if (*yymsg_alloc < yysize)
+ {
+ *yymsg_alloc = 2 * yysize;
+ if (! (yysize <= *yymsg_alloc
+ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+ return 1;
+ }
+
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ {
+ char *yyp = *yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyformat) != '\0')
+ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyformat += 2;
+ }
+ else
+ {
+ yyp++;
+ yyformat++;
+ }
+ }
+ return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+ YYUSE (yyvaluep);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol. */
+int yychar;
+
+/* The semantic value of the lookahead symbol. */
+YYSTYPE yylval;
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+int
+yyparse (void)
+{
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+ 'yyss': related to states.
+ 'yyvs': related to semantic values.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
+ YYSIZE_T yystacksize;
+
+ int yyn;
+ int yyresult;
+ /* Lookahead token as an internal (translated) token number. */
+ int yytoken = 0;
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss_alloc, yyss);
+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ if (yystate == YYFINAL)
+ YYACCEPT;
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ lookahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to lookahead token. */
+ yyn = yypact[yystate];
+ if (yypact_value_is_default (yyn))
+ goto yydefault;
+
+ /* Not known => get a lookahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yytable_value_is_error (yyn))
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the lookahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token. */
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 5:
+#line 309 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
+ insntbl_line, (yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val)));
+ itbl_add_reg ((yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val));
+ }
+#line 1499 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 6:
+#line 315 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
+ insntbl_line, (yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val)));
+ DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, (yyvsp[0].val)));
+ insn=itbl_add_insn ((yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val), sbit, ebit, (yyvsp[0].val));
+ }
+#line 1510 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 7:
+#line 322 "./itbl-parse.y" /* yacc.c:1661 */
+ {}
+#line 1516 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 13:
+#line 335 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("ftype\n"));
+ (yyval.num) = (yyvsp[0].num);
+ }
+#line 1525 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 14:
+#line 340 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("addr\n"));
+ (yyval.num) = ADDR;
+ }
+#line 1534 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 15:
+#line 345 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("immed\n"));
+ (yyval.num) = IMMED;
+ }
+#line 1543 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 16:
+#line 353 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
+ insntbl_line, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val)));
+ itbl_add_operand (insn, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val));
+ }
+#line 1553 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 17:
+#line 362 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.val) = (yyvsp[-2].num) | (yyvsp[0].val);
+ }
+#line 1561 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 18:
+#line 366 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.val) = (yyvsp[-1].val);
+ }
+#line 1569 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 19:
+#line 370 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.val) = (yyvsp[0].num);
+ }
+#line 1577 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 20:
+#line 377 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("flags=%d\n", (yyvsp[0].val)));
+ (yyval.val) = (yyvsp[0].val);
+ }
+#line 1586 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 21:
+#line 382 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.val) = 0;
+ }
+#line 1594 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 22:
+#line 389 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("range %d %d\n", (yyvsp[-2].num), (yyvsp[0].num)));
+ sbit = (yyvsp[-2].num);
+ ebit = (yyvsp[0].num);
+ }
+#line 1604 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 23:
+#line 395 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ sbit = 31;
+ ebit = 0;
+ }
+#line 1613 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 24:
+#line 403 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("pnum=%d\n",(yyvsp[0].num)));
+ (yyval.num) = (yyvsp[0].num);
+ }
+#line 1622 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 25:
+#line 411 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("dreg\n"));
+ (yyval.num) = DREG;
+ }
+#line 1631 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 26:
+#line 416 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("creg\n"));
+ (yyval.num) = CREG;
+ }
+#line 1640 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 27:
+#line 421 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("greg\n"));
+ (yyval.num) = GREG;
+ }
+#line 1649 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 28:
+#line 429 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("name=%s\n",(yyvsp[0].str)));
+ (yyval.str) = (yyvsp[0].str);
+ }
+#line 1658 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 29:
+#line 445 "./itbl-parse.y" /* yacc.c:1661 */
+ {
+ DBGL2 (("val=x%x\n",(yyvsp[0].num)));
+ (yyval.val) = (yyvsp[0].num);
+ }
+#line 1667 "itbl-parse.c" /* yacc.c:1661 */
+ break;
+
+
+#line 1671 "itbl-parse.c" /* yacc.c:1661 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+ that yytoken be updated with the new translation. We take the
+ approach of translating immediately before every use of yytoken.
+ One alternative is translating here after every semantic action,
+ but that translation would be missed if the semantic action invokes
+ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
+ incorrect destructor might then be invoked immediately. In the
+ case of YYERROR or YYBACKUP, subsequent parser actions might lead
+ to an incorrect destructor call or verbose syntax error message
+ before the lookahead is translated. */
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error. |
+`--------------------------------------*/
+yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+ yyssp, yytoken)
+ {
+ char const *yymsgp = YY_("syntax error");
+ int yysyntax_error_status;
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ if (yysyntax_error_status == 0)
+ yymsgp = yymsg;
+ else if (yysyntax_error_status == 1)
+ {
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+ if (!yymsg)
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ yysyntax_error_status = 2;
+ }
+ else
+ {
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ yymsgp = yymsg;
+ }
+ }
+ yyerror (yymsgp);
+ if (yysyntax_error_status == 2)
+ goto yyexhaustedlab;
+ }
+# undef YYSYNTAX_ERROR
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEMPTY)
+ {
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ }
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ return yyresult;
+}
+#line 450 "./itbl-parse.y" /* yacc.c:1906 */
+
+
+static int
+yyerror (const char *msg)
+{
+ printf ("line %d: %s\n", insntbl_line, msg);
+ return 0;
+}
diff --git a/gas/itbl-parse.h b/gas/itbl-parse.h
new file mode 100644
index 0000000..2de51e8
--- /dev/null
+++ b/gas/itbl-parse.h
@@ -0,0 +1,96 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison interface for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+#ifndef YY_YY_ITBL_PARSE_H_INCLUDED
+# define YY_YY_ITBL_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ DREG = 258,
+ CREG = 259,
+ GREG = 260,
+ IMMED = 261,
+ ADDR = 262,
+ INSN = 263,
+ NUM = 264,
+ ID = 265,
+ NL = 266,
+ PNUM = 267
+ };
+#endif
+/* Tokens. */
+#define DREG 258
+#define CREG 259
+#define GREG 260
+#define IMMED 261
+#define ADDR 262
+#define INSN 263
+#define NUM 264
+#define ID 265
+#define NL 266
+#define PNUM 267
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 282 "./itbl-parse.y" /* yacc.c:1915 */
+
+ char *str;
+ int num;
+ int processor;
+ unsigned long val;
+
+
+#line 86 "itbl-parse.h" /* yacc.c:1915 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+#endif /* !YY_YY_ITBL_PARSE_H_INCLUDED */
diff --git a/gas/m68k-parse.c b/gas/m68k-parse.c
new file mode 100644
index 0000000..425a50c
--- /dev/null
+++ b/gas/m68k-parse.c
@@ -0,0 +1,2772 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison implementation for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "3.0"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Push parsers. */
+#define YYPUSH 0
+
+/* Pull parsers. */
+#define YYPULL 1
+
+
+
+
+/* Copy the first part of user declarations. */
+#line 27 "m68k-parse.y" /* yacc.c:339 */
+
+
+#include "as.h"
+#include "tc-m68k.h"
+#include "m68k-parse.h"
+#include "safe-ctype.h"
+
+/* Remap normal yacc parser interface names (yyparse, yylex, yyerror,
+ etc), as well as gratuitously global symbol names If other parser
+ generators (bison, byacc, etc) produce additional global names that
+ conflict at link time, then those parser generators need to be
+ fixed instead of adding those names to this list. */
+
+#define yymaxdepth m68k_maxdepth
+#define yyparse m68k_parse
+#define yylex m68k_lex
+#define yyerror m68k_error
+#define yylval m68k_lval
+#define yychar m68k_char
+#define yydebug m68k_debug
+#define yypact m68k_pact
+#define yyr1 m68k_r1
+#define yyr2 m68k_r2
+#define yydef m68k_def
+#define yychk m68k_chk
+#define yypgo m68k_pgo
+#define yyact m68k_act
+#define yyexca m68k_exca
+#define yyerrflag m68k_errflag
+#define yynerrs m68k_nerrs
+#define yyps m68k_ps
+#define yypv m68k_pv
+#define yys m68k_s
+#define yy_yys m68k_yys
+#define yystate m68k_state
+#define yytmp m68k_tmp
+#define yyv m68k_v
+#define yy_yyv m68k_yyv
+#define yyval m68k_val
+#define yylloc m68k_lloc
+#define yyreds m68k_reds /* With YYDEBUG defined */
+#define yytoks m68k_toks /* With YYDEBUG defined */
+#define yylhs m68k_yylhs
+#define yylen m68k_yylen
+#define yydefred m68k_yydefred
+#define yydgoto m68k_yydgoto
+#define yysindex m68k_yysindex
+#define yyrindex m68k_yyrindex
+#define yygindex m68k_yygindex
+#define yytable m68k_yytable
+#define yycheck m68k_yycheck
+
+#ifndef YYDEBUG
+#define YYDEBUG 1
+#endif
+
+/* Internal functions. */
+
+static enum m68k_register m68k_reg_parse (char **);
+static int yylex (void);
+static void yyerror (const char *);
+
+/* The parser sets fields pointed to by this global variable. */
+static struct m68k_op *op;
+
+
+#line 133 "m68k-parse.c" /* yacc.c:339 */
+
+# ifndef YY_NULL
+# if defined __cplusplus && 201103L <= __cplusplus
+# define YY_NULL nullptr
+# else
+# define YY_NULL 0
+# endif
+# endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int yydebug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ DR = 258,
+ AR = 259,
+ FPR = 260,
+ FPCR = 261,
+ LPC = 262,
+ ZAR = 263,
+ ZDR = 264,
+ LZPC = 265,
+ CREG = 266,
+ INDEXREG = 267,
+ EXPR = 268
+ };
+#endif
+/* Tokens. */
+#define DR 258
+#define AR 259
+#define FPR 260
+#define FPCR 261
+#define LPC 262
+#define ZAR 263
+#define ZDR 264
+#define LZPC 265
+#define CREG 266
+#define INDEXREG 267
+#define EXPR 268
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 95 "m68k-parse.y" /* yacc.c:355 */
+
+ struct m68k_indexreg indexreg;
+ enum m68k_register reg;
+ struct m68k_exp exp;
+ unsigned long mask;
+ int onereg;
+ int trailing_ampersand;
+
+#line 205 "m68k-parse.c" /* yacc.c:355 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE yylval;
+
+int yyparse (void);
+
+
+
+/* Copy the second part of user declarations. */
+
+#line 220 "m68k-parse.c" /* yacc.c:358 */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef __attribute__
+/* This feature is available in gcc versions 2.5 and later. */
+# if (! defined __GNUC__ || __GNUC__ < 2 \
+ || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+# define __attribute__(Spec) /* empty */
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+ _Pragma ("GCC diagnostic push") \
+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+ _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's 'empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+ Stack = &yyptr->Stack_alloc; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(Dst, Src, Count) \
+ __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+# else
+# define YYCOPY(Dst, Src, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 44
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 215
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 27
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 21
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 89
+/* YYNSTATES -- Number of states. */
+#define YYNSTATES 180
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+ by yylex, with out-of-bounds checking. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 268
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, without out-of-bounds checking. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 17, 2, 2, 14, 2,
+ 18, 19, 2, 20, 22, 21, 2, 26, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 15, 2, 16, 2, 25, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 23, 2, 24, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12, 13
+};
+
+#if YYDEBUG
+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 120, 120, 121, 125, 134, 135, 142, 147, 152,
+ 157, 162, 167, 172, 177, 182, 187, 192, 205, 210,
+ 215, 220, 230, 240, 250, 255, 260, 265, 272, 283,
+ 290, 296, 303, 309, 320, 330, 337, 343, 351, 358,
+ 365, 371, 379, 386, 398, 409, 422, 430, 438, 446,
+ 456, 463, 471, 478, 492, 493, 506, 507, 519, 520,
+ 521, 527, 528, 534, 535, 542, 543, 544, 551, 554,
+ 560, 561, 568, 571, 581, 585, 595, 599, 608, 609,
+ 613, 625, 629, 630, 634, 641, 651, 655, 659, 663
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "DR", "AR", "FPR", "FPCR", "LPC", "ZAR",
+ "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'&'", "'<'", "'>'", "'#'",
+ "'('", "')'", "'+'", "'-'", "','", "'['", "']'", "'@'", "'/'", "$accept",
+ "operand", "optional_ampersand", "generic_operand", "motorola_operand",
+ "mit_operand", "zireg", "zdireg", "zadr", "zdr", "apc", "zapc",
+ "optzapc", "zpc", "optczapc", "optcexpr", "optexprc", "reglist",
+ "ireglist", "reglistpair", "reglistreg", YY_NULL
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+ (internal) symbol number NUM (which must be that of a token). */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 38, 60, 62, 35, 40, 41,
+ 43, 45, 44, 91, 93, 64, 47
+};
+# endif
+
+#define YYPACT_NINF -98
+
+#define yypact_value_is_default(Yystate) \
+ (!!((Yystate) == (-98)))
+
+#define YYTABLE_NINF -64
+
+#define yytable_value_is_error(Yytable_value) \
+ 0
+
+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+static const yytype_int16 yypact[] =
+{
+ 89, 14, 9, 31, 35, -98, -98, -98, -98, 0,
+ 36, 42, 28, 56, 63, 67, 90, -98, 75, 75,
+ -98, -98, 86, -98, 96, -15, 123, -98, -98, -98,
+ -98, -98, 97, 115, 119, -98, 120, -98, 122, 16,
+ 126, -98, 127, 157, -98, -98, -98, -98, 19, 154,
+ 154, 154, -98, 140, 29, 144, -98, -98, -98, 123,
+ 141, 99, 18, 70, 147, 105, 148, 152, -98, -98,
+ -98, -98, -98, -98, -98, 142, -13, -98, -98, 146,
+ 150, -98, 133, -98, 140, 60, 146, 149, 133, 153,
+ 140, 151, -98, -98, -98, -98, -98, -98, -98, 155,
+ 158, -98, -98, 159, -98, 62, 143, 154, 154, -98,
+ 160, 161, 162, -98, 133, 163, 164, 165, 166, 116,
+ 168, 167, -98, -98, -98, -98, 169, -98, 173, -98,
+ -98, -98, -98, -98, 174, 176, 133, 116, 177, 175,
+ 175, -98, 175, -98, 175, 170, 178, -98, -98, 180,
+ 181, 175, -98, 171, 179, 182, 183, 187, 186, 189,
+ 175, 175, 190, -98, -98, -98, -98, 79, 143, 195,
+ 191, 192, -98, -98, 193, 194, -98, -98, -98, -98
+};
+
+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+ Performed when YYTABLE does not specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint8 yydefact[] =
+{
+ 68, 86, 87, 88, 89, 64, 67, 66, 13, 14,
+ 0, 0, 0, 0, 0, 0, 0, 2, 5, 5,
+ 65, 69, 0, 17, 78, 0, 0, 16, 7, 8,
+ 15, 61, 63, 64, 67, 62, 66, 56, 0, 76,
+ 72, 57, 0, 0, 1, 6, 3, 4, 46, 0,
+ 0, 0, 63, 72, 0, 18, 24, 25, 26, 0,
+ 72, 0, 0, 0, 0, 0, 0, 76, 47, 48,
+ 86, 87, 88, 89, 79, 82, 81, 85, 80, 0,
+ 0, 23, 0, 19, 72, 0, 77, 0, 0, 74,
+ 72, 0, 73, 36, 59, 70, 60, 71, 54, 0,
+ 0, 55, 58, 0, 20, 0, 0, 0, 0, 35,
+ 0, 0, 0, 21, 0, 73, 74, 0, 0, 0,
+ 0, 0, 30, 22, 32, 34, 49, 77, 0, 83,
+ 84, 31, 33, 29, 0, 0, 0, 0, 0, 74,
+ 74, 75, 74, 40, 74, 0, 50, 27, 28, 0,
+ 0, 74, 38, 0, 0, 0, 0, 0, 76, 0,
+ 74, 74, 0, 42, 44, 39, 45, 0, 0, 0,
+ 0, 0, 37, 52, 0, 0, 41, 43, 51, 53
+};
+
+ /* YYPGOTO[NTERM-NUM]. */
+static const yytype_int16 yypgoto[] =
+{
+ -98, -98, 196, -98, -98, -98, -81, 6, -98, -9,
+ -98, 2, -98, -78, -38, -97, -67, -98, -48, 172,
+ 12
+};
+
+ /* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int8 yydefgoto[] =
+{
+ -1, 16, 46, 17, 18, 19, 100, 40, 101, 102,
+ 20, 92, 22, 103, 64, 120, 62, 23, 74, 75,
+ 76
+};
+
+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule whose
+ number is the opposite. If YYTABLE_NINF, syntax error. */
+static const yytype_int16 yytable[] =
+{
+ 106, 110, 21, 78, 111, 41, 50, 117, 50, -10,
+ 118, 51, 25, 108, -9, 80, 42, 41, 26, 138,
+ 52, 31, 87, 5, 6, 128, 7, 35, 54, 60,
+ 37, -11, 53, 134, -63, -12, 135, 67, 142, 68,
+ 69, 61, 154, 155, 29, 156, 112, 157, 81, 27,
+ 41, 82, 121, 41, 162, 149, 151, 28, 150, 129,
+ 130, 85, 77, 170, 171, 84, 31, 32, 90, 30,
+ 33, 34, 35, 36, 52, 37, 38, 5, 6, 113,
+ 7, 126, 114, 91, 127, 43, 39, 174, 115, 45,
+ 44, 168, 1, 2, 3, 4, 5, 6, 173, 7,
+ 8, 127, 9, 10, 11, 12, 13, 14, 31, 94,
+ 15, 48, 95, 96, 35, 97, 55, 98, 99, 31,
+ 94, 88, 49, 89, 96, 35, 31, 52, 98, 141,
+ 5, 6, 35, 7, 56, 37, 31, 94, 57, 58,
+ 95, 96, 35, 97, 59, 98, 31, 94, 63, 65,
+ 52, 96, 35, 5, 6, 98, 7, 70, 71, 72,
+ 73, 66, 79, 86, 83, 105, 93, 104, 107, 109,
+ 122, 0, 24, 116, 123, 119, 0, 124, 125, 131,
+ 132, 133, 0, 0, 141, 136, 137, 143, 158, 139,
+ 140, 144, 146, 147, 145, 148, 152, 153, 163, 167,
+ 0, 164, 165, 159, 160, 161, 166, 169, 175, 172,
+ 176, 177, 178, 179, 0, 47
+};
+
+static const yytype_int16 yycheck[] =
+{
+ 67, 82, 0, 51, 82, 14, 21, 88, 21, 0,
+ 88, 26, 0, 26, 0, 53, 14, 26, 18, 116,
+ 4, 3, 60, 7, 8, 106, 10, 9, 26, 13,
+ 12, 0, 26, 114, 25, 0, 114, 18, 119, 20,
+ 21, 39, 139, 140, 16, 142, 84, 144, 19, 13,
+ 59, 22, 90, 62, 151, 136, 137, 15, 136, 107,
+ 108, 59, 50, 160, 161, 59, 3, 4, 62, 13,
+ 7, 8, 9, 10, 4, 12, 13, 7, 8, 19,
+ 10, 19, 22, 13, 22, 18, 23, 168, 86, 14,
+ 0, 158, 3, 4, 5, 6, 7, 8, 19, 10,
+ 11, 22, 13, 14, 15, 16, 17, 18, 3, 4,
+ 21, 25, 7, 8, 9, 10, 19, 12, 13, 3,
+ 4, 22, 26, 24, 8, 9, 3, 4, 12, 13,
+ 7, 8, 9, 10, 19, 12, 3, 4, 19, 19,
+ 7, 8, 9, 10, 22, 12, 3, 4, 22, 22,
+ 4, 8, 9, 7, 8, 12, 10, 3, 4, 5,
+ 6, 4, 22, 22, 20, 13, 19, 19, 26, 19,
+ 19, -1, 0, 24, 19, 22, -1, 19, 19, 19,
+ 19, 19, -1, -1, 13, 22, 22, 19, 18, 24,
+ 24, 24, 19, 19, 25, 19, 19, 22, 19, 13,
+ -1, 19, 19, 25, 24, 24, 19, 18, 13, 19,
+ 19, 19, 19, 19, -1, 19
+};
+
+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 3, 4, 5, 6, 7, 8, 10, 11, 13,
+ 14, 15, 16, 17, 18, 21, 28, 30, 31, 32,
+ 37, 38, 39, 44, 46, 47, 18, 13, 15, 16,
+ 13, 3, 4, 7, 8, 9, 10, 12, 13, 23,
+ 34, 36, 38, 18, 0, 14, 29, 29, 25, 26,
+ 21, 26, 4, 34, 38, 19, 19, 19, 19, 22,
+ 13, 38, 43, 22, 41, 22, 4, 18, 20, 21,
+ 3, 4, 5, 6, 45, 46, 47, 47, 45, 22,
+ 41, 19, 22, 20, 34, 38, 22, 41, 22, 24,
+ 34, 13, 38, 19, 4, 7, 8, 10, 12, 13,
+ 33, 35, 36, 40, 19, 13, 43, 26, 26, 19,
+ 33, 40, 41, 19, 22, 38, 24, 33, 40, 22,
+ 42, 41, 19, 19, 19, 19, 19, 22, 33, 45,
+ 45, 19, 19, 19, 33, 40, 22, 22, 42, 24,
+ 24, 13, 33, 19, 24, 25, 19, 19, 19, 33,
+ 40, 33, 19, 22, 42, 42, 42, 42, 18, 25,
+ 24, 24, 42, 19, 19, 19, 19, 13, 43, 18,
+ 42, 42, 19, 19, 33, 13, 19, 19, 19, 19
+};
+
+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 27, 28, 28, 28, 29, 29, 30, 30, 30,
+ 30, 30, 30, 30, 30, 30, 30, 30, 31, 31,
+ 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
+ 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
+ 31, 31, 31, 31, 31, 31, 32, 32, 32, 32,
+ 32, 32, 32, 32, 33, 33, 34, 34, 35, 35,
+ 35, 36, 36, 37, 37, 38, 38, 38, 39, 39,
+ 40, 40, 41, 41, 42, 42, 43, 43, 44, 44,
+ 44, 45, 45, 45, 45, 46, 47, 47, 47, 47
+};
+
+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 1, 2, 2, 0, 1, 2, 2, 1,
+ 1, 1, 1, 1, 1, 2, 2, 1, 3, 4,
+ 4, 5, 5, 4, 3, 3, 3, 7, 7, 6,
+ 5, 6, 5, 6, 5, 5, 4, 9, 7, 8,
+ 6, 10, 8, 10, 8, 8, 2, 3, 3, 5,
+ 6, 10, 9, 10, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 0, 1,
+ 1, 1, 0, 2, 0, 2, 0, 2, 1, 3,
+ 3, 1, 1, 3, 3, 3, 1, 1, 1, 1
+};
+
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+/* Error token number */
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT. |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ YYFPRINTF (yyoutput, "%s %s (",
+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+ {
+ int yybot = *yybottom;
+ YYFPRINTF (stderr, " %d", yybot);
+ }
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr,
+ yystos[yyssp[yyi + 1 - yynrhs]],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ YYFPRINTF (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+ about the unexpected token YYTOKEN for the state stack whose top is
+ YYSSP.
+
+ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
+ not large enough to hold the message. In that case, also set
+ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
+ required number of bytes is too large to store. */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+{
+ YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+ const char *yyformat = YY_NULL;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+ "expected"). */
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+ tokens because there are none.
+ - The only way there can be no lookahead present (in yychar) is if
+ this state is a consistent state with a default action. Thus,
+ detecting the absence of a lookahead is sufficient to determine
+ that there is no unexpected or expected token to report. In that
+ case, just report a simple "syntax error".
+ - Don't assume there isn't a lookahead just because this state is a
+ consistent state with a default action. There might have been a
+ previous inconsistent state, consistent state with a non-default
+ action, or user semantic action that manipulated yychar.
+ - Of course, the expected token list depends on states to have
+ correct lookahead information, and it depends on the parser not
+ to perform extra reductions after fetching a lookahead from the
+ scanner and before detecting a syntax error. Thus, state merging
+ (from LALR or IELR) and default reductions corrupt the expected
+ token list. However, the list is correct for canonical LR with
+ one exception: it will still contain any token that will not be
+ accepted due to an error action in a later state.
+ */
+ if (yytoken != YYEMPTY)
+ {
+ int yyn = yypact[*yyssp];
+ yyarg[yycount++] = yytname[yytoken];
+ if (!yypact_value_is_default (yyn))
+ {
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. In other words, skip the first -YYN actions for
+ this state because they are default actions. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yyx;
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+ && !yytable_value_is_error (yytable[yyx + yyn]))
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+ }
+ }
+ }
+
+ switch (yycount)
+ {
+# define YYCASE_(N, S) \
+ case N: \
+ yyformat = S; \
+ break
+ YYCASE_(0, YY_("syntax error"));
+ YYCASE_(1, YY_("syntax error, unexpected %s"));
+ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+ }
+
+ {
+ YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+
+ if (*yymsg_alloc < yysize)
+ {
+ *yymsg_alloc = 2 * yysize;
+ if (! (yysize <= *yymsg_alloc
+ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+ return 1;
+ }
+
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ {
+ char *yyp = *yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyformat) != '\0')
+ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyformat += 2;
+ }
+ else
+ {
+ yyp++;
+ yyformat++;
+ }
+ }
+ return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+ YYUSE (yyvaluep);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol. */
+int yychar;
+
+/* The semantic value of the lookahead symbol. */
+YYSTYPE yylval;
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+int
+yyparse (void)
+{
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+ 'yyss': related to states.
+ 'yyvs': related to semantic values.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
+ YYSIZE_T yystacksize;
+
+ int yyn;
+ int yyresult;
+ /* Lookahead token as an internal (translated) token number. */
+ int yytoken = 0;
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss_alloc, yyss);
+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ if (yystate == YYFINAL)
+ YYACCEPT;
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ lookahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to lookahead token. */
+ yyn = yypact[yystate];
+ if (yypact_value_is_default (yyn))
+ goto yydefault;
+
+ /* Not known => get a lookahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yytable_value_is_error (yyn))
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the lookahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token. */
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 3:
+#line 122 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
+ }
+#line 1397 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 4:
+#line 126 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
+ }
+#line 1405 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 5:
+#line 134 "m68k-parse.y" /* yacc.c:1661 */
+ { (yyval.trailing_ampersand) = 0; }
+#line 1411 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 6:
+#line 136 "m68k-parse.y" /* yacc.c:1661 */
+ { (yyval.trailing_ampersand) = 1; }
+#line 1417 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 7:
+#line 143 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = LSH;
+ }
+#line 1425 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 8:
+#line 148 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = RSH;
+ }
+#line 1433 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 9:
+#line 153 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = DREG;
+ op->reg = (yyvsp[0].reg);
+ }
+#line 1442 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 10:
+#line 158 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = AREG;
+ op->reg = (yyvsp[0].reg);
+ }
+#line 1451 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 11:
+#line 163 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = FPREG;
+ op->reg = (yyvsp[0].reg);
+ }
+#line 1460 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 12:
+#line 168 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = CONTROL;
+ op->reg = (yyvsp[0].reg);
+ }
+#line 1469 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 13:
+#line 173 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = CONTROL;
+ op->reg = (yyvsp[0].reg);
+ }
+#line 1478 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 14:
+#line 178 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = ABSL;
+ op->disp = (yyvsp[0].exp);
+ }
+#line 1487 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 15:
+#line 183 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = IMMED;
+ op->disp = (yyvsp[0].exp);
+ }
+#line 1496 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 16:
+#line 188 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = IMMED;
+ op->disp = (yyvsp[0].exp);
+ }
+#line 1505 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 17:
+#line 193 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = REGLST;
+ op->mask = (yyvsp[0].mask);
+ }
+#line 1514 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 18:
+#line 206 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = AINDR;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1523 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 19:
+#line 211 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = AINC;
+ op->reg = (yyvsp[-2].reg);
+ }
+#line 1532 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 20:
+#line 216 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = ADEC;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1541 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 21:
+#line 221 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-3].exp);
+ if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
+ || (yyvsp[-1].reg) == ZPC)
+ op->mode = BASE;
+ else
+ op->mode = DISP;
+ }
+#line 1555 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 22:
+#line 231 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-1].exp);
+ if (((yyvsp[-3].reg) >= ZADDR0 && (yyvsp[-3].reg) <= ZADDR7)
+ || (yyvsp[-3].reg) == ZPC)
+ op->mode = BASE;
+ else
+ op->mode = DISP;
+ }
+#line 1569 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 23:
+#line 241 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-3].exp);
+ if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
+ || (yyvsp[-1].reg) == ZPC)
+ op->mode = BASE;
+ else
+ op->mode = DISP;
+ }
+#line 1583 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 24:
+#line 251 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = DISP;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1592 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 25:
+#line 256 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1601 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 26:
+#line 261 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1610 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 27:
+#line 266 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->index = (yyvsp[-1].indexreg);
+ }
+#line 1621 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 28:
+#line 273 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
+ yyerror (_("syntax error"));
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->index.reg = (yyvsp[-3].reg);
+ op->index.size = SIZE_UNSPEC;
+ op->index.scale = 1;
+ }
+#line 1636 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 29:
+#line 284 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-4].exp);
+ op->index = (yyvsp[-2].indexreg);
+ }
+#line 1647 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 30:
+#line 291 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->disp = (yyvsp[-1].exp);
+ op->index = (yyvsp[-3].indexreg);
+ }
+#line 1657 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 31:
+#line 297 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->index = (yyvsp[-1].indexreg);
+ }
+#line 1668 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 32:
+#line 304 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-3].reg);
+ op->index = (yyvsp[-1].indexreg);
+ }
+#line 1678 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 33:
+#line 310 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
+ yyerror (_("syntax error"));
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->index.reg = (yyvsp[-3].reg);
+ op->index.size = SIZE_UNSPEC;
+ op->index.scale = 1;
+ }
+#line 1693 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 34:
+#line 321 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
+ yyerror (_("syntax error"));
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->index.reg = (yyvsp[-3].reg);
+ op->index.size = SIZE_UNSPEC;
+ op->index.scale = 1;
+ }
+#line 1707 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 35:
+#line 331 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->disp = (yyvsp[-4].exp);
+ op->index = (yyvsp[-2].indexreg);
+ }
+#line 1718 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 36:
+#line 338 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-1].reg);
+ op->index = (yyvsp[-2].indexreg);
+ }
+#line 1728 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 37:
+#line 344 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-5].reg);
+ op->disp = (yyvsp[-6].exp);
+ op->index = (yyvsp[-2].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1740 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 38:
+#line 352 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-4].exp);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1751 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 39:
+#line 359 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-5].reg);
+ op->index = (yyvsp[-2].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1762 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 40:
+#line 366 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-3].reg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1772 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 41:
+#line 372 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = PRE;
+ op->reg = (yyvsp[-5].reg);
+ op->disp = (yyvsp[-7].exp);
+ op->index = (yyvsp[-3].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1784 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 42:
+#line 380 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = PRE;
+ op->reg = (yyvsp[-5].reg);
+ op->index = (yyvsp[-3].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1795 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 43:
+#line 387 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
+ yyerror (_("syntax error"));
+ op->mode = PRE;
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-7].exp);
+ op->index.reg = (yyvsp[-5].reg);
+ op->index.size = SIZE_UNSPEC;
+ op->index.scale = 1;
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1811 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 44:
+#line 399 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
+ yyerror (_("syntax error"));
+ op->mode = PRE;
+ op->reg = (yyvsp[-3].reg);
+ op->index.reg = (yyvsp[-5].reg);
+ op->index.size = SIZE_UNSPEC;
+ op->index.scale = 1;
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1826 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 45:
+#line 410 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = PRE;
+ op->reg = (yyvsp[-3].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->index = (yyvsp[-4].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1838 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 46:
+#line 423 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ /* We use optzapc to avoid a shift/reduce conflict. */
+ if ((yyvsp[-1].reg) < ADDR0 || (yyvsp[-1].reg) > ADDR7)
+ yyerror (_("syntax error"));
+ op->mode = AINDR;
+ op->reg = (yyvsp[-1].reg);
+ }
+#line 1850 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 47:
+#line 431 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ /* We use optzapc to avoid a shift/reduce conflict. */
+ if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
+ yyerror (_("syntax error"));
+ op->mode = AINC;
+ op->reg = (yyvsp[-2].reg);
+ }
+#line 1862 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 48:
+#line 439 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ /* We use optzapc to avoid a shift/reduce conflict. */
+ if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
+ yyerror (_("syntax error"));
+ op->mode = ADEC;
+ op->reg = (yyvsp[-2].reg);
+ }
+#line 1874 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 49:
+#line 447 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->reg = (yyvsp[-4].reg);
+ op->disp = (yyvsp[-1].exp);
+ if (((yyvsp[-4].reg) >= ZADDR0 && (yyvsp[-4].reg) <= ZADDR7)
+ || (yyvsp[-4].reg) == ZPC)
+ op->mode = BASE;
+ else
+ op->mode = DISP;
+ }
+#line 1888 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 50:
+#line 457 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = BASE;
+ op->reg = (yyvsp[-5].reg);
+ op->disp = (yyvsp[-2].exp);
+ op->index = (yyvsp[-1].indexreg);
+ }
+#line 1899 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 51:
+#line 464 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-9].reg);
+ op->disp = (yyvsp[-6].exp);
+ op->index = (yyvsp[-1].indexreg);
+ op->odisp = (yyvsp[-2].exp);
+ }
+#line 1911 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 52:
+#line 472 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = POST;
+ op->reg = (yyvsp[-8].reg);
+ op->disp = (yyvsp[-5].exp);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1922 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 53:
+#line 479 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ op->mode = PRE;
+ op->reg = (yyvsp[-9].reg);
+ op->disp = (yyvsp[-6].exp);
+ op->index = (yyvsp[-5].indexreg);
+ op->odisp = (yyvsp[-1].exp);
+ }
+#line 1934 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 55:
+#line 494 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.indexreg).reg = (yyvsp[0].reg);
+ (yyval.indexreg).size = SIZE_UNSPEC;
+ (yyval.indexreg).scale = 1;
+ }
+#line 1944 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 57:
+#line 508 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.indexreg).reg = (yyvsp[0].reg);
+ (yyval.indexreg).size = SIZE_UNSPEC;
+ (yyval.indexreg).scale = 1;
+ }
+#line 1954 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 68:
+#line 551 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = ZADDR0;
+ }
+#line 1962 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 72:
+#line 568 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = ZADDR0;
+ }
+#line 1970 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 73:
+#line 572 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.reg) = (yyvsp[0].reg);
+ }
+#line 1978 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 74:
+#line 581 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.exp).exp.X_op = O_absent;
+ (yyval.exp).size = SIZE_UNSPEC;
+ }
+#line 1987 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 75:
+#line 586 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.exp) = (yyvsp[0].exp);
+ }
+#line 1995 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 76:
+#line 595 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.exp).exp.X_op = O_absent;
+ (yyval.exp).size = SIZE_UNSPEC;
+ }
+#line 2004 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 77:
+#line 600 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.exp) = (yyvsp[-1].exp);
+ }
+#line 2012 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 79:
+#line 610 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
+ }
+#line 2020 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 80:
+#line 614 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
+ }
+#line 2028 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 81:
+#line 626 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mask) = 1 << (yyvsp[0].onereg);
+ }
+#line 2036 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 83:
+#line 631 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
+ }
+#line 2044 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 84:
+#line 635 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
+ }
+#line 2052 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 85:
+#line 642 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].onereg) <= (yyvsp[0].onereg))
+ (yyval.mask) = (1 << ((yyvsp[0].onereg) + 1)) - 1 - ((1 << (yyvsp[-2].onereg)) - 1);
+ else
+ (yyval.mask) = (1 << ((yyvsp[-2].onereg) + 1)) - 1 - ((1 << (yyvsp[0].onereg)) - 1);
+ }
+#line 2063 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 86:
+#line 652 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.onereg) = (yyvsp[0].reg) - DATA0;
+ }
+#line 2071 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 87:
+#line 656 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.onereg) = (yyvsp[0].reg) - ADDR0 + 8;
+ }
+#line 2079 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 88:
+#line 660 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ (yyval.onereg) = (yyvsp[0].reg) - FP0 + 16;
+ }
+#line 2087 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 89:
+#line 664 "m68k-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[0].reg) == FPI)
+ (yyval.onereg) = 24;
+ else if ((yyvsp[0].reg) == FPS)
+ (yyval.onereg) = 25;
+ else
+ (yyval.onereg) = 26;
+ }
+#line 2100 "m68k-parse.c" /* yacc.c:1661 */
+ break;
+
+
+#line 2104 "m68k-parse.c" /* yacc.c:1661 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+ that yytoken be updated with the new translation. We take the
+ approach of translating immediately before every use of yytoken.
+ One alternative is translating here after every semantic action,
+ but that translation would be missed if the semantic action invokes
+ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
+ incorrect destructor might then be invoked immediately. In the
+ case of YYERROR or YYBACKUP, subsequent parser actions might lead
+ to an incorrect destructor call or verbose syntax error message
+ before the lookahead is translated. */
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error. |
+`--------------------------------------*/
+yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+ yyssp, yytoken)
+ {
+ char const *yymsgp = YY_("syntax error");
+ int yysyntax_error_status;
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ if (yysyntax_error_status == 0)
+ yymsgp = yymsg;
+ else if (yysyntax_error_status == 1)
+ {
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+ if (!yymsg)
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ yysyntax_error_status = 2;
+ }
+ else
+ {
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ yymsgp = yymsg;
+ }
+ }
+ yyerror (yymsgp);
+ if (yysyntax_error_status == 2)
+ goto yyexhaustedlab;
+ }
+# undef YYSYNTAX_ERROR
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEMPTY)
+ {
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ }
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ return yyresult;
+}
+#line 674 "m68k-parse.y" /* yacc.c:1906 */
+
+
+/* The string to parse is stored here, and modified by yylex. */
+
+static char *str;
+
+/* The original string pointer. */
+
+static char *strorig;
+
+/* If *CCP could be a register, return the register number and advance
+ *CCP. Otherwise don't change *CCP, and return 0. */
+
+static enum m68k_register
+m68k_reg_parse (char **ccp)
+{
+ char *start = *ccp;
+ char c;
+ char *p;
+ symbolS *symbolp;
+
+ if (flag_reg_prefix_optional)
+ {
+ if (*start == REGISTER_PREFIX)
+ start++;
+ p = start;
+ }
+ else
+ {
+ if (*start != REGISTER_PREFIX)
+ return 0;
+ p = start + 1;
+ }
+
+ if (! is_name_beginner (*p))
+ return 0;
+
+ p++;
+ while (is_part_of_name (*p) && *p != '.' && *p != ':' && *p != '*')
+ p++;
+
+ c = *p;
+ *p = 0;
+ symbolp = symbol_find (start);
+ *p = c;
+
+ if (symbolp != NULL && S_GET_SEGMENT (symbolp) == reg_section)
+ {
+ *ccp = p;
+ return S_GET_VALUE (symbolp);
+ }
+
+ /* In MRI mode, something like foo.bar can be equated to a register
+ name. */
+ while (flag_mri && c == '.')
+ {
+ ++p;
+ while (is_part_of_name (*p) && *p != '.' && *p != ':' && *p != '*')
+ p++;
+ c = *p;
+ *p = '\0';
+ symbolp = symbol_find (start);
+ *p = c;
+ if (symbolp != NULL && S_GET_SEGMENT (symbolp) == reg_section)
+ {
+ *ccp = p;
+ return S_GET_VALUE (symbolp);
+ }
+ }
+
+ return 0;
+}
+
+/* The lexer. */
+
+static int
+yylex (void)
+{
+ enum m68k_register reg;
+ char *s;
+ int parens;
+ int c = 0;
+ int tail = 0;
+ char *hold;
+
+ if (*str == ' ')
+ ++str;
+
+ if (*str == '\0')
+ return 0;
+
+ /* Various special characters are just returned directly. */
+ switch (*str)
+ {
+ case '@':
+ /* In MRI mode, this can be the start of an octal number. */
+ if (flag_mri)
+ {
+ if (ISDIGIT (str[1])
+ || ((str[1] == '+' || str[1] == '-')
+ && ISDIGIT (str[2])))
+ break;
+ }
+ /* Fall through. */
+ case '#':
+ case '&':
+ case ',':
+ case ')':
+ case '/':
+ case '[':
+ case ']':
+ case '<':
+ case '>':
+ return *str++;
+ case '+':
+ /* It so happens that a '+' can only appear at the end of an
+ operand, or if it is trailed by an '&'(see mac load insn).
+ If it appears anywhere else, it must be a unary. */
+ if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
+ return *str++;
+ break;
+ case '-':
+ /* A '-' can only appear in -(ar), rn-rn, or ar@-. If it
+ appears anywhere else, it must be a unary minus on an
+ expression, unless it it trailed by a '&'(see mac load insn). */
+ if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
+ return *str++;
+ s = str + 1;
+ if (*s == '(')
+ ++s;
+ if (m68k_reg_parse (&s) != 0)
+ return *str++;
+ break;
+ case '(':
+ /* A '(' can only appear in `(reg)', `(expr,...', `([', `@(', or
+ `)('. If it appears anywhere else, it must be starting an
+ expression. */
+ if (str[1] == '['
+ || (str > strorig
+ && (str[-1] == '@'
+ || str[-1] == ')')))
+ return *str++;
+ s = str + 1;
+ if (m68k_reg_parse (&s) != 0)
+ return *str++;
+ /* Check for the case of '(expr,...' by scanning ahead. If we
+ find a comma outside of balanced parentheses, we return '('.
+ If we find an unbalanced right parenthesis, then presumably
+ the '(' really starts an expression. */
+ parens = 0;
+ for (s = str + 1; *s != '\0'; s++)
+ {
+ if (*s == '(')
+ ++parens;
+ else if (*s == ')')
+ {
+ if (parens == 0)
+ break;
+ --parens;
+ }
+ else if (*s == ',' && parens == 0)
+ {
+ /* A comma can not normally appear in an expression, so
+ this is a case of '(expr,...'. */
+ return *str++;
+ }
+ }
+ }
+
+ /* See if it's a register. */
+
+ reg = m68k_reg_parse (&str);
+ if (reg != 0)
+ {
+ int ret;
+
+ yylval.reg = reg;
+
+ if (reg >= DATA0 && reg <= DATA7)
+ ret = DR;
+ else if (reg >= ADDR0 && reg <= ADDR7)
+ ret = AR;
+ else if (reg >= FP0 && reg <= FP7)
+ return FPR;
+ else if (reg == FPI
+ || reg == FPS
+ || reg == FPC)
+ return FPCR;
+ else if (reg == PC)
+ return LPC;
+ else if (reg >= ZDATA0 && reg <= ZDATA7)
+ ret = ZDR;
+ else if (reg >= ZADDR0 && reg <= ZADDR7)
+ ret = ZAR;
+ else if (reg == ZPC)
+ return LZPC;
+ else
+ return CREG;
+
+ /* If we get here, we have a data or address register. We
+ must check for a size or scale; if we find one, we must
+ return INDEXREG. */
+
+ s = str;
+
+ if (*s != '.' && *s != ':' && *s != '*')
+ return ret;
+
+ yylval.indexreg.reg = reg;
+
+ if (*s != '.' && *s != ':')
+ yylval.indexreg.size = SIZE_UNSPEC;
+ else
+ {
+ ++s;
+ switch (*s)
+ {
+ case 'w':
+ case 'W':
+ yylval.indexreg.size = SIZE_WORD;
+ ++s;
+ break;
+ case 'l':
+ case 'L':
+ yylval.indexreg.size = SIZE_LONG;
+ ++s;
+ break;
+ default:
+ yyerror (_("illegal size specification"));
+ yylval.indexreg.size = SIZE_UNSPEC;
+ break;
+ }
+ }
+
+ yylval.indexreg.scale = 1;
+
+ if (*s == '*' || *s == ':')
+ {
+ expressionS scale;
+
+ ++s;
+
+ hold = input_line_pointer;
+ input_line_pointer = s;
+ expression (&scale);
+ s = input_line_pointer;
+ input_line_pointer = hold;
+
+ if (scale.X_op != O_constant)
+ yyerror (_("scale specification must resolve to a number"));
+ else
+ {
+ switch (scale.X_add_number)
+ {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ yylval.indexreg.scale = scale.X_add_number;
+ break;
+ default:
+ yyerror (_("invalid scale value"));
+ break;
+ }
+ }
+ }
+
+ str = s;
+
+ return INDEXREG;
+ }
+
+ /* It must be an expression. Before we call expression, we need to
+ look ahead to see if there is a size specification. We must do
+ that first, because otherwise foo.l will be treated as the symbol
+ foo.l, rather than as the symbol foo with a long size
+ specification. The grammar requires that all expressions end at
+ the end of the operand, or with ',', '(', ']', ')'. */
+
+ parens = 0;
+ for (s = str; *s != '\0'; s++)
+ {
+ if (*s == '(')
+ {
+ if (parens == 0
+ && s > str
+ && (s[-1] == ')' || ISALNUM (s[-1])))
+ break;
+ ++parens;
+ }
+ else if (*s == ')')
+ {
+ if (parens == 0)
+ break;
+ --parens;
+ }
+ else if (parens == 0
+ && (*s == ',' || *s == ']'))
+ break;
+ }
+
+ yylval.exp.size = SIZE_UNSPEC;
+ if (s <= str + 2
+ || (s[-2] != '.' && s[-2] != ':'))
+ tail = 0;
+ else
+ {
+ switch (s[-1])
+ {
+ case 's':
+ case 'S':
+ case 'b':
+ case 'B':
+ yylval.exp.size = SIZE_BYTE;
+ break;
+ case 'w':
+ case 'W':
+ yylval.exp.size = SIZE_WORD;
+ break;
+ case 'l':
+ case 'L':
+ yylval.exp.size = SIZE_LONG;
+ break;
+ default:
+ break;
+ }
+ if (yylval.exp.size != SIZE_UNSPEC)
+ tail = 2;
+ }
+
+#ifdef OBJ_ELF
+ {
+ /* Look for @PLTPC, etc. */
+ char *cp;
+
+ yylval.exp.pic_reloc = pic_none;
+ cp = s - tail;
+ if (cp - 7 > str && cp[-7] == '@')
+ {
+ if (strncmp (cp - 7, "@TLSLDM", 7) == 0)
+ {
+ yylval.exp.pic_reloc = pic_tls_ldm;
+ tail += 7;
+ }
+ else if (strncmp (cp - 7, "@TLSLDO", 7) == 0)
+ {
+ yylval.exp.pic_reloc = pic_tls_ldo;
+ tail += 7;
+ }
+ }
+ else if (cp - 6 > str && cp[-6] == '@')
+ {
+ if (strncmp (cp - 6, "@PLTPC", 6) == 0)
+ {
+ yylval.exp.pic_reloc = pic_plt_pcrel;
+ tail += 6;
+ }
+ else if (strncmp (cp - 6, "@GOTPC", 6) == 0)
+ {
+ yylval.exp.pic_reloc = pic_got_pcrel;
+ tail += 6;
+ }
+ else if (strncmp (cp - 6, "@TLSGD", 6) == 0)
+ {
+ yylval.exp.pic_reloc = pic_tls_gd;
+ tail += 6;
+ }
+ else if (strncmp (cp - 6, "@TLSIE", 6) == 0)
+ {
+ yylval.exp.pic_reloc = pic_tls_ie;
+ tail += 6;
+ }
+ else if (strncmp (cp - 6, "@TLSLE", 6) == 0)
+ {
+ yylval.exp.pic_reloc = pic_tls_le;
+ tail += 6;
+ }
+ }
+ else if (cp - 4 > str && cp[-4] == '@')
+ {
+ if (strncmp (cp - 4, "@PLT", 4) == 0)
+ {
+ yylval.exp.pic_reloc = pic_plt_off;
+ tail += 4;
+ }
+ else if (strncmp (cp - 4, "@GOT", 4) == 0)
+ {
+ yylval.exp.pic_reloc = pic_got_off;
+ tail += 4;
+ }
+ }
+ }
+#endif
+
+ if (tail != 0)
+ {
+ c = s[-tail];
+ s[-tail] = 0;
+ }
+
+ hold = input_line_pointer;
+ input_line_pointer = str;
+ expression (&yylval.exp.exp);
+ str = input_line_pointer;
+ input_line_pointer = hold;
+
+ if (tail != 0)
+ {
+ s[-tail] = c;
+ str = s;
+ }
+
+ return EXPR;
+}
+
+/* Parse an m68k operand. This is the only function which is called
+ from outside this file. */
+
+int
+m68k_ip_op (char *s, struct m68k_op *oparg)
+{
+ memset (oparg, 0, sizeof *oparg);
+ oparg->error = NULL;
+ oparg->index.reg = ZDATA0;
+ oparg->index.scale = 1;
+ oparg->disp.exp.X_op = O_absent;
+ oparg->odisp.exp.X_op = O_absent;
+
+ str = strorig = s;
+ op = oparg;
+
+ return yyparse ();
+}
+
+/* The error handler. */
+
+static void
+yyerror (const char *s)
+{
+ op->error = s;
+}
diff --git a/gas/po/es.gmo b/gas/po/es.gmo
new file mode 100644
index 0000000..0b17373
--- /dev/null
+++ b/gas/po/es.gmo
Binary files differ
diff --git a/gas/po/fi.gmo b/gas/po/fi.gmo
new file mode 100644
index 0000000..72df64d
--- /dev/null
+++ b/gas/po/fi.gmo
Binary files differ
diff --git a/gas/po/fr.gmo b/gas/po/fr.gmo
new file mode 100644
index 0000000..4859b43
--- /dev/null
+++ b/gas/po/fr.gmo
Binary files differ
diff --git a/gas/po/id.gmo b/gas/po/id.gmo
new file mode 100644
index 0000000..2ecf194
--- /dev/null
+++ b/gas/po/id.gmo
Binary files differ
diff --git a/gas/po/ja.gmo b/gas/po/ja.gmo
new file mode 100644
index 0000000..07f7f92
--- /dev/null
+++ b/gas/po/ja.gmo
Binary files differ
diff --git a/gas/po/ru.gmo b/gas/po/ru.gmo
new file mode 100644
index 0000000..87734f2
--- /dev/null
+++ b/gas/po/ru.gmo
Binary files differ
diff --git a/gas/po/rw.gmo b/gas/po/rw.gmo
new file mode 100644
index 0000000..8879b0e
--- /dev/null
+++ b/gas/po/rw.gmo
Binary files differ
diff --git a/gas/po/tr.gmo b/gas/po/tr.gmo
new file mode 100644
index 0000000..bf7736d
--- /dev/null
+++ b/gas/po/tr.gmo
Binary files differ
diff --git a/gas/po/uk.gmo b/gas/po/uk.gmo
new file mode 100644
index 0000000..fed385d
--- /dev/null
+++ b/gas/po/uk.gmo
Binary files differ
diff --git a/gas/po/zh_CN.gmo b/gas/po/zh_CN.gmo
new file mode 100644
index 0000000..3366997
--- /dev/null
+++ b/gas/po/zh_CN.gmo
Binary files differ
diff --git a/gas/rl78-parse.c b/gas/rl78-parse.c
new file mode 100644
index 0000000..725f50c
--- /dev/null
+++ b/gas/rl78-parse.c
@@ -0,0 +1,4786 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison implementation for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "3.0"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Push parsers. */
+#define YYPUSH 0
+
+/* Pull parsers. */
+#define YYPULL 1
+
+
+/* Substitute the variable and function names. */
+#define yyparse rl78_parse
+#define yylex rl78_lex
+#define yyerror rl78_error
+#define yydebug rl78_debug
+#define yynerrs rl78_nerrs
+
+#define yylval rl78_lval
+#define yychar rl78_char
+
+/* Copy the first part of user declarations. */
+#line 20 "./config/rl78-parse.y" /* yacc.c:339 */
+
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "rl78-defs.h"
+
+static int rl78_lex (void);
+
+/* Ok, here are the rules for using these macros...
+
+ B*() is used to specify the base opcode bytes. Fields to be filled
+ in later, leave zero. Call this first.
+
+ F() and FE() are used to fill in fields within the base opcode bytes. You MUST
+ call B*() before any F() or FE().
+
+ [UN]*O*(), PC*() appends operands to the end of the opcode. You
+ must call P() and B*() before any of these, so that the fixups
+ have the right byte location.
+ O = signed, UO = unsigned, NO = negated, PC = pcrel
+
+ IMM() adds an immediate and fills in the field for it.
+ NIMM() same, but negates the immediate.
+ NBIMM() same, but negates the immediate, for sbb.
+ DSP() adds a displacement, and fills in the field for it.
+
+ Note that order is significant for the O, IMM, and DSP macros, as
+ they append their data to the operand buffer in the order that you
+ call them.
+
+ Use "disp" for displacements whenever possible; this handles the
+ "0" case properly. */
+
+#define B1(b1) rl78_base1 (b1)
+#define B2(b1, b2) rl78_base2 (b1, b2)
+#define B3(b1, b2, b3) rl78_base3 (b1, b2, b3)
+#define B4(b1, b2, b3, b4) rl78_base4 (b1, b2, b3, b4)
+
+/* POS is bits from the MSB of the first byte to the LSB of the last byte. */
+#define F(val,pos,sz) rl78_field (val, pos, sz)
+#define FE(exp,pos,sz) rl78_field (exp_val (exp), pos, sz);
+
+#define O1(v) rl78_op (v, 1, RL78REL_DATA)
+#define O2(v) rl78_op (v, 2, RL78REL_DATA)
+#define O3(v) rl78_op (v, 3, RL78REL_DATA)
+#define O4(v) rl78_op (v, 4, RL78REL_DATA)
+
+#define PC1(v) rl78_op (v, 1, RL78REL_PCREL)
+#define PC2(v) rl78_op (v, 2, RL78REL_PCREL)
+#define PC3(v) rl78_op (v, 3, RL78REL_PCREL)
+
+#define IMM(v,pos) F (immediate (v, RL78REL_SIGNED, pos), pos, 2); \
+ if (v.X_op != O_constant && v.X_op != O_big) rl78_linkrelax_imm (pos)
+#define NIMM(v,pos) F (immediate (v, RL78REL_NEGATIVE, pos), pos, 2)
+#define NBIMM(v,pos) F (immediate (v, RL78REL_NEGATIVE_BORROW, pos), pos, 2)
+#define DSP(v,pos,msz) if (!v.X_md) rl78_relax (RL78_RELAX_DISP, pos); \
+ else rl78_linkrelax_dsp (pos); \
+ F (displacement (v, msz), pos, 2)
+
+#define id24(a,b2,b3) B3 (0xfb+a, b2, b3)
+
+static int expr_is_sfr (expressionS);
+static int expr_is_saddr (expressionS);
+static int expr_is_word_aligned (expressionS);
+static int exp_val (expressionS exp);
+
+static int need_flag = 0;
+static int rl78_in_brackets = 0;
+static int rl78_last_token = 0;
+static char * rl78_init_start;
+static char * rl78_last_exp_start = 0;
+static int rl78_bit_insn = 0;
+
+#define YYDEBUG 1
+#define YYERROR_VERBOSE 1
+
+#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
+#define SA(e) if (!expr_is_saddr (e)) NOT_SADDR;
+
+#define SET_SA(e) e.X_md = BFD_RELOC_RL78_SADDR
+
+#define NOT_SFR rl78_error ("Expression not 0xFFF00 to 0xFFFFF")
+#define SFR(e) if (!expr_is_sfr (e)) NOT_SFR;
+
+#define NOT_SFR_OR_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFFFF")
+
+#define NOT_ES if (rl78_has_prefix()) rl78_error ("ES: prefix not allowed here");
+
+#define WA(x) if (!expr_is_word_aligned (x)) rl78_error ("Expression not word-aligned");
+
+#define ISA_G10(s) if (!rl78_isa_g10()) rl78_error (s " is only supported on the G10")
+#define ISA_G13(s) if (!rl78_isa_g13()) rl78_error (s " is only supported on the G13")
+#define ISA_G14(s) if (!rl78_isa_g14()) rl78_error (s " is only supported on the G14")
+
+static void check_expr_is_bit_index (expressionS);
+#define Bit(e) check_expr_is_bit_index (e);
+
+/* Returns TRUE (non-zero) if the expression is a constant in the
+ given range. */
+static int check_expr_is_const (expressionS, int vmin, int vmax);
+
+/* Convert a "regb" value to a "reg_xbc" value. Error if other
+ registers are passed. Needed to avoid reduce-reduce conflicts. */
+static int
+reg_xbc (int reg)
+{
+ switch (reg)
+ {
+ case 0: /* X */
+ return 0x10;
+ case 3: /* B */
+ return 0x20;
+ case 2: /* C */
+ return 0x30;
+ default:
+ rl78_error ("Only X, B, or C allowed here");
+ return 0;
+ }
+}
+
+
+#line 196 "rl78-parse.c" /* yacc.c:339 */
+
+# ifndef YY_NULL
+# if defined __cplusplus && 201103L <= __cplusplus
+# define YY_NULL nullptr
+# else
+# define YY_NULL 0
+# endif
+# endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* In a future release of Bison, this section will be replaced
+ by #include "y.tab.h". */
+#ifndef YY_RL78_RL_PARSE_H_INCLUDED
+# define YY_RL78_RL_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int rl78_debug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ A = 258,
+ X = 259,
+ B = 260,
+ C = 261,
+ D = 262,
+ E = 263,
+ H = 264,
+ L = 265,
+ AX = 266,
+ BC = 267,
+ DE = 268,
+ HL = 269,
+ SPL = 270,
+ SPH = 271,
+ PSW = 272,
+ CS = 273,
+ ES = 274,
+ PMC = 275,
+ MEM = 276,
+ FLAG = 277,
+ SP = 278,
+ CY = 279,
+ RB0 = 280,
+ RB1 = 281,
+ RB2 = 282,
+ RB3 = 283,
+ EXPR = 284,
+ UNKNOWN_OPCODE = 285,
+ IS_OPCODE = 286,
+ DOT_S = 287,
+ DOT_B = 288,
+ DOT_W = 289,
+ DOT_L = 290,
+ DOT_A = 291,
+ DOT_UB = 292,
+ DOT_UW = 293,
+ ADD = 294,
+ ADDC = 295,
+ ADDW = 296,
+ AND_ = 297,
+ AND1 = 298,
+ BF = 299,
+ BH = 300,
+ BNC = 301,
+ BNH = 302,
+ BNZ = 303,
+ BR = 304,
+ BRK = 305,
+ BRK1 = 306,
+ BT = 307,
+ BTCLR = 308,
+ BZ = 309,
+ CALL = 310,
+ CALLT = 311,
+ CLR1 = 312,
+ CLRB = 313,
+ CLRW = 314,
+ CMP = 315,
+ CMP0 = 316,
+ CMPS = 317,
+ CMPW = 318,
+ DEC = 319,
+ DECW = 320,
+ DI = 321,
+ DIVHU = 322,
+ DIVWU = 323,
+ EI = 324,
+ HALT = 325,
+ INC = 326,
+ INCW = 327,
+ MACH = 328,
+ MACHU = 329,
+ MOV = 330,
+ MOV1 = 331,
+ MOVS = 332,
+ MOVW = 333,
+ MULH = 334,
+ MULHU = 335,
+ MULU = 336,
+ NOP = 337,
+ NOT1 = 338,
+ ONEB = 339,
+ ONEW = 340,
+ OR = 341,
+ OR1 = 342,
+ POP = 343,
+ PUSH = 344,
+ RET = 345,
+ RETI = 346,
+ RETB = 347,
+ ROL = 348,
+ ROLC = 349,
+ ROLWC = 350,
+ ROR = 351,
+ RORC = 352,
+ SAR = 353,
+ SARW = 354,
+ SEL = 355,
+ SET1 = 356,
+ SHL = 357,
+ SHLW = 358,
+ SHR = 359,
+ SHRW = 360,
+ SKC = 361,
+ SKH = 362,
+ SKNC = 363,
+ SKNH = 364,
+ SKNZ = 365,
+ SKZ = 366,
+ STOP = 367,
+ SUB = 368,
+ SUBC = 369,
+ SUBW = 370,
+ XCH = 371,
+ XCHW = 372,
+ XOR = 373,
+ XOR1 = 374
+ };
+#endif
+/* Tokens. */
+#define A 258
+#define X 259
+#define B 260
+#define C 261
+#define D 262
+#define E 263
+#define H 264
+#define L 265
+#define AX 266
+#define BC 267
+#define DE 268
+#define HL 269
+#define SPL 270
+#define SPH 271
+#define PSW 272
+#define CS 273
+#define ES 274
+#define PMC 275
+#define MEM 276
+#define FLAG 277
+#define SP 278
+#define CY 279
+#define RB0 280
+#define RB1 281
+#define RB2 282
+#define RB3 283
+#define EXPR 284
+#define UNKNOWN_OPCODE 285
+#define IS_OPCODE 286
+#define DOT_S 287
+#define DOT_B 288
+#define DOT_W 289
+#define DOT_L 290
+#define DOT_A 291
+#define DOT_UB 292
+#define DOT_UW 293
+#define ADD 294
+#define ADDC 295
+#define ADDW 296
+#define AND_ 297
+#define AND1 298
+#define BF 299
+#define BH 300
+#define BNC 301
+#define BNH 302
+#define BNZ 303
+#define BR 304
+#define BRK 305
+#define BRK1 306
+#define BT 307
+#define BTCLR 308
+#define BZ 309
+#define CALL 310
+#define CALLT 311
+#define CLR1 312
+#define CLRB 313
+#define CLRW 314
+#define CMP 315
+#define CMP0 316
+#define CMPS 317
+#define CMPW 318
+#define DEC 319
+#define DECW 320
+#define DI 321
+#define DIVHU 322
+#define DIVWU 323
+#define EI 324
+#define HALT 325
+#define INC 326
+#define INCW 327
+#define MACH 328
+#define MACHU 329
+#define MOV 330
+#define MOV1 331
+#define MOVS 332
+#define MOVW 333
+#define MULH 334
+#define MULHU 335
+#define MULU 336
+#define NOP 337
+#define NOT1 338
+#define ONEB 339
+#define ONEW 340
+#define OR 341
+#define OR1 342
+#define POP 343
+#define PUSH 344
+#define RET 345
+#define RETI 346
+#define RETB 347
+#define ROL 348
+#define ROLC 349
+#define ROLWC 350
+#define ROR 351
+#define RORC 352
+#define SAR 353
+#define SARW 354
+#define SEL 355
+#define SET1 356
+#define SHL 357
+#define SHLW 358
+#define SHR 359
+#define SHRW 360
+#define SKC 361
+#define SKH 362
+#define SKNC 363
+#define SKNH 364
+#define SKNZ 365
+#define SKZ 366
+#define STOP 367
+#define SUB 368
+#define SUBC 369
+#define SUBW 370
+#define XCH 371
+#define XCHW 372
+#define XOR 373
+#define XOR1 374
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 144 "./config/rl78-parse.y" /* yacc.c:355 */
+
+ int regno;
+ expressionS exp;
+
+#line 479 "rl78-parse.c" /* yacc.c:355 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE rl78_lval;
+
+int rl78_parse (void);
+
+#endif /* !YY_RL78_RL_PARSE_H_INCLUDED */
+
+/* Copy the second part of user declarations. */
+
+#line 494 "rl78-parse.c" /* yacc.c:358 */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef __attribute__
+/* This feature is available in gcc versions 2.5 and later. */
+# if (! defined __GNUC__ || __GNUC__ < 2 \
+ || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+# define __attribute__(Spec) /* empty */
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+ _Pragma ("GCC diagnostic push") \
+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+ _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's 'empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+ Stack = &yyptr->Stack_alloc; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(Dst, Src, Count) \
+ __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+# else
+# define YYCOPY(Dst, Src, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 180
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 844
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 129
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 56
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 324
+/* YYNSTATES -- Number of states. */
+#define YYNSTATES 744
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+ by yylex, with out-of-bounds checking. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 374
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, without out-of-bounds checking. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 122, 2, 121, 127, 2, 2, 2,
+ 2, 2, 2, 125, 120, 2, 126, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 128, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 123, 2, 124, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
+ 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+ 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
+ 115, 116, 117, 118, 119
+};
+
+#if YYDEBUG
+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 187, 187, 208, 211, 211, 214, 217, 220, 223,
+ 223, 226, 229, 232, 235, 238, 241, 250, 253, 256,
+ 256, 259, 262, 265, 268, 276, 276, 279, 279, 288,
+ 288, 291, 291, 296, 299, 302, 305, 308, 311, 316,
+ 319, 328, 331, 336, 339, 342, 345, 348, 353, 356,
+ 361, 364, 367, 370, 373, 394, 397, 400, 409, 412,
+ 415, 420, 422, 424, 426, 429, 429, 432, 437, 439,
+ 444, 447, 450, 453, 456, 456, 459, 464, 469, 472,
+ 472, 474, 476, 478, 480, 485, 488, 488, 491, 494,
+ 499, 502, 507, 507, 510, 510, 513, 516, 516, 524,
+ 524, 527, 527, 530, 530, 535, 543, 545, 548, 555,
+ 555, 564, 567, 570, 573, 576, 576, 585, 588, 591,
+ 594, 597, 597, 606, 606, 606, 609, 612, 619, 619,
+ 619, 626, 629, 632, 635, 638, 641, 644, 647, 650,
+ 653, 656, 659, 662, 665, 668, 671, 674, 677, 680,
+ 683, 686, 689, 692, 695, 698, 701, 704, 704, 707,
+ 707, 710, 710, 713, 713, 716, 716, 719, 719, 724,
+ 733, 736, 739, 742, 751, 754, 757, 762, 767, 770,
+ 773, 773, 782, 782, 791, 791, 800, 803, 806, 809,
+ 812, 815, 818, 821, 824, 827, 830, 833, 836, 839,
+ 842, 845, 848, 851, 854, 857, 860, 860, 863, 863,
+ 866, 866, 869, 869, 872, 872, 875, 878, 881, 884,
+ 887, 892, 897, 902, 905, 908, 911, 916, 919, 922,
+ 927, 932, 937, 942, 947, 952, 959, 964, 971, 974,
+ 977, 980, 985, 990, 995, 1000, 1005, 1012, 1017, 1024,
+ 1027, 1030, 1033, 1036, 1039, 1044, 1049, 1056, 1059, 1062,
+ 1065, 1068, 1071, 1074, 1077, 1088, 1097, 1098, 1102, 1103,
+ 1104, 1105, 1106, 1107, 1108, 1109, 1112, 1113, 1114, 1115,
+ 1116, 1117, 1118, 1121, 1122, 1123, 1124, 1127, 1128, 1129,
+ 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1144, 1145, 1146,
+ 1147, 1148, 1149, 1150, 1151, 1154, 1155, 1156, 1159, 1160,
+ 1161, 1164, 1165, 1166, 1169, 1170, 1173, 1174, 1177, 1178,
+ 1181, 1182, 1185, 1186, 1189
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "A", "X", "B", "C", "D", "E", "H", "L",
+ "AX", "BC", "DE", "HL", "SPL", "SPH", "PSW", "CS", "ES", "PMC", "MEM",
+ "FLAG", "SP", "CY", "RB0", "RB1", "RB2", "RB3", "EXPR", "UNKNOWN_OPCODE",
+ "IS_OPCODE", "DOT_S", "DOT_B", "DOT_W", "DOT_L", "DOT_A", "DOT_UB",
+ "DOT_UW", "ADD", "ADDC", "ADDW", "AND_", "AND1", "BF", "BH", "BNC",
+ "BNH", "BNZ", "BR", "BRK", "BRK1", "BT", "BTCLR", "BZ", "CALL", "CALLT",
+ "CLR1", "CLRB", "CLRW", "CMP", "CMP0", "CMPS", "CMPW", "DEC", "DECW",
+ "DI", "DIVHU", "DIVWU", "EI", "HALT", "INC", "INCW", "MACH", "MACHU",
+ "MOV", "MOV1", "MOVS", "MOVW", "MULH", "MULHU", "MULU", "NOP", "NOT1",
+ "ONEB", "ONEW", "OR", "OR1", "POP", "PUSH", "RET", "RETI", "RETB", "ROL",
+ "ROLC", "ROLWC", "ROR", "RORC", "SAR", "SARW", "SEL", "SET1", "SHL",
+ "SHLW", "SHR", "SHRW", "SKC", "SKH", "SKNC", "SKNH", "SKNZ", "SKZ",
+ "STOP", "SUB", "SUBC", "SUBW", "XCH", "XCHW", "XOR", "XOR1", "','",
+ "'#'", "'!'", "'['", "']'", "'+'", "'.'", "'$'", "':'", "$accept",
+ "statement", "$@1", "$@2", "$@3", "$@4", "$@5", "$@6", "$@7", "$@8",
+ "$@9", "$@10", "$@11", "$@12", "$@13", "$@14", "$@15", "$@16", "$@17",
+ "$@18", "$@19", "$@20", "$@21", "$@22", "$@23", "$@24", "$@25", "$@26",
+ "$@27", "$@28", "$@29", "$@30", "$@31", "$@32", "$@33", "$@34", "$@35",
+ "$@36", "$@37", "$@38", "opt_es", "regb", "regb_na", "regw", "regw_na",
+ "sfr", "addsub", "addsubw", "andor1", "bt_bf", "setclr1", "oneclrb",
+ "oneclrw", "incdec", "incdecw", "mov1", YY_NULL
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+ (internal) symbol number NUM (which must be that of a token). */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
+ 275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
+ 285, 286, 287, 288, 289, 290, 291, 292, 293, 294,
+ 295, 296, 297, 298, 299, 300, 301, 302, 303, 304,
+ 305, 306, 307, 308, 309, 310, 311, 312, 313, 314,
+ 315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
+ 325, 326, 327, 328, 329, 330, 331, 332, 333, 334,
+ 335, 336, 337, 338, 339, 340, 341, 342, 343, 344,
+ 345, 346, 347, 348, 349, 350, 351, 352, 353, 354,
+ 355, 356, 357, 358, 359, 360, 361, 362, 363, 364,
+ 365, 366, 367, 368, 369, 370, 371, 372, 373, 374,
+ 44, 35, 33, 91, 93, 43, 46, 36, 58
+};
+# endif
+
+#define YYPACT_NINF -212
+
+#define yypact_value_is_default(Yystate) \
+ (!!((Yystate) == (-212)))
+
+#define YYTABLE_NINF -1
+
+#define yytable_value_is_error(Yytable_value) \
+ 0
+
+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+static const yytype_int16 yypact[] =
+{
+ 226, -44, -212, -212, -212, -212, -212, -212, -212, -34,
+ -15, 14, 20, 42, -212, -212, -212, -212, 45, 91,
+ -80, -212, -212, -212, -212, 347, 134, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, 53,
+ -212, 136, 430, -212, -212, 153, -212, 150, -212, -212,
+ -212, -212, 413, 451, -212, -212, -212, 181, 186, 198,
+ 192, 212, 214, 225, 232, -212, 368, 210, 236, 231,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ 242, 244, -212, -212, 261, 221, 107, 325, 162, 343,
+ 403, 222, 10, 235, 362, 328, 341, 385, 394, 402,
+ -212, 38, 81, 411, -212, -212, -212, -212, 82, 263,
+ -212, 428, -212, -212, -212, -212, 300, -212, 273, 351,
+ -212, -212, -212, -212, 367, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, 376, -212, -212, 457,
+ 11, 372, 383, 384, 386, -212, -212, -212, 388, 36,
+ 389, -212, -212, -212, -212, -212, -212, -212, -212, 390,
+ 391, 392, 393, 395, 396, 397, 398, -212, -212, -212,
+ -212, 401, 404, 405, 406, 407, 408, 409, 410, 412,
+ -212, 414, -212, 415, 416, 418, 419, 420, 379, 300,
+ 417, 421, 422, 423, -212, 424, 0, 425, -212, -212,
+ -212, -212, -212, 431, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, 426, -212, 485, 505, -212, -212,
+ 233, -212, 432, 427, 434, 436, 435, -212, -212, -212,
+ -212, -212, -212, 491, -212, 493, -212, -212, 494, 502,
+ 439, -212, -212, 504, 136, 80, 440, 437, -79, 184,
+ 29, 72, 521, 123, 41, 79, 512, 239, 102, 513,
+ 516, 517, 523, 526, 527, 535, 536, 537, 538, 539,
+ 540, 541, 542, 543, 429, 399, 18, 453, 545, 572,
+ 95, 455, 381, 548, 549, 565, 551, 552, 553, 554,
+ 570, 556, -212, 557, 267, -212, -212, 462, -212, 559,
+ 575, 561, 400, 562, 578, 564, -212, -212, -212, -212,
+ -212, -212, 471, 566, 63, -212, -212, 567, 5, 6,
+ 161, 473, 268, 280, 330, -212, 569, 86, 571, 573,
+ -212, 474, -212, 574, 65, -212, -212, 576, 55, 342,
+ 481, 480, 335, 345, 348, -212, -212, -212, 577, 486,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, 344, -212, -212, -212,
+ -212, 580, 352, -212, 489, 487, -212, -212, 582, 354,
+ -212, 583, 488, 490, 492, 495, 497, 498, 496, 499,
+ -212, -212, 500, 501, -212, -212, 584, 608, 594, -212,
+ 503, 507, 506, 508, 510, 509, 511, 514, 519, 610,
+ -212, 518, 600, 433, 520, -212, 601, -212, 607, 522,
+ 524, 525, 530, 531, 613, 532, 111, 533, 614, -212,
+ -212, 615, -212, -212, 616, -212, 534, 618, 438, -212,
+ -212, 625, 544, 546, 547, 626, 555, 558, 627, 560,
+ 629, 563, 630, -212, -212, 631, 632, 465, -212, -212,
+ 633, 641, 634, 568, -212, -212, 635, 651, -212, 637,
+ 638, 655, 643, 550, 579, 581, 585, 644, 587, -212,
+ 586, 590, 645, 652, 650, 653, 667, 656, 660, 589,
+ 662, 591, 363, -212, -212, 593, 356, 358, 360, 7,
+ -212, -212, -212, 588, 598, 599, 8, 684, 596, 685,
+ 597, 602, 603, 27, 604, -212, -212, -212, 605, 382,
+ -212, -212, 606, 364, 366, 369, -212, -212, 611, 612,
+ 617, -212, 679, 680, 609, 681, 619, 682, 620, -212,
+ -212, 371, 373, -212, 375, -212, 665, -212, 377, -212,
+ -212, 621, -212, 666, 668, 669, 670, -212, 671, 672,
+ -212, 622, -212, -212, -212, 623, -212, -212, 673, -212,
+ 674, 624, 628, 636, -212, -212, 675, -212, 114, -212,
+ 676, -212, 693, -212, 28, 30, 31, -212, 694, -212,
+ 639, -212, 642, 646, 647, -212, 695, 648, -212, -212,
+ 649, 640, 654, 657, -212, -212, 696, -212, 705, -212,
+ 706, -212, 698, 699, 725, -212, -212, 659, -212, 663,
+ -212, 664, -212, 709, -212, 139, -212, 165, -212, -212,
+ 710, -212, -212, 661, -212, -212, -212, 677, -212, -212,
+ 658, -212, 678, 683, 686, -212, -212, -212, 687, 688,
+ 689, 690, -212, 691, -212, -212, 711, -212, 712, -212,
+ 713, -212, 32, 746, 747, 33, -212, -212, 35, 692,
+ -212, -212, -212, 697, 700, -212, 701, -212, -212, -212,
+ 740, 742, -212, 743, 702, 703, 704, 707, 708, 714,
+ 715, 716, 726, 717, -212, 727, 733, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, 729, -212, -212,
+ -212, 732, -212, -212, 734, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, 736, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212
+};
+
+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+ Performed when YYTABLE does not specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint16 yydefact[] =
+{
+ 0, 0, 2, 297, 298, 305, 302, 308, 312, 0,
+ 0, 0, 0, 0, 48, 49, 311, 313, 0, 0,
+ 0, 315, 317, 319, 301, 266, 0, 307, 321, 323,
+ 90, 97, 99, 91, 105, 320, 322, 103, 101, 266,
+ 324, 266, 266, 94, 92, 0, 221, 0, 316, 318,
+ 303, 309, 0, 0, 227, 228, 229, 0, 0, 0,
+ 0, 0, 0, 0, 0, 314, 0, 0, 0, 0,
+ 249, 250, 251, 252, 253, 254, 255, 299, 300, 306,
+ 0, 0, 304, 310, 0, 266, 0, 0, 266, 266,
+ 266, 0, 0, 266, 266, 0, 0, 0, 0, 0,
+ 43, 0, 0, 0, 283, 284, 285, 286, 0, 0,
+ 50, 0, 70, 71, 72, 73, 0, 74, 0, 0,
+ 98, 100, 104, 102, 0, 276, 278, 277, 280, 279,
+ 282, 281, 290, 291, 292, 293, 294, 295, 296, 0,
+ 0, 0, 0, 0, 0, 287, 288, 289, 0, 0,
+ 0, 95, 93, 96, 222, 224, 223, 226, 225, 0,
+ 0, 0, 0, 0, 0, 0, 0, 238, 239, 240,
+ 241, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 0, 4, 0, 0, 0, 0, 0, 0, 294,
+ 0, 0, 0, 0, 55, 0, 0, 0, 61, 62,
+ 63, 64, 65, 0, 68, 69, 269, 268, 271, 270,
+ 273, 272, 275, 274, 0, 79, 0, 0, 78, 86,
+ 0, 85, 0, 0, 0, 0, 0, 33, 37, 34,
+ 38, 36, 46, 0, 44, 0, 35, 52, 0, 0,
+ 0, 267, 75, 0, 266, 266, 267, 0, 0, 0,
+ 266, 266, 0, 266, 0, 0, 0, 0, 266, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 266, 0, 266, 0, 0, 0,
+ 266, 0, 266, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 66, 0, 0, 80, 81, 0, 87, 0,
+ 0, 0, 266, 0, 0, 0, 47, 45, 53, 51,
+ 54, 76, 0, 0, 0, 114, 126, 0, 0, 0,
+ 0, 0, 0, 0, 0, 113, 0, 0, 0, 0,
+ 127, 0, 219, 0, 0, 186, 218, 0, 0, 0,
+ 0, 0, 0, 0, 0, 187, 220, 214, 0, 0,
+ 230, 231, 232, 233, 234, 235, 236, 237, 242, 243,
+ 244, 245, 246, 247, 248, 264, 0, 256, 265, 6,
+ 9, 0, 0, 7, 0, 0, 8, 19, 0, 0,
+ 18, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 58, 57, 0, 0, 56, 67, 0, 0, 0, 88,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 106, 121, 0, 0, 0, 118, 0, 115, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 107,
+ 123, 0, 108, 128, 0, 178, 182, 0, 0, 217,
+ 184, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 215, 179, 0, 0, 0, 10, 3,
+ 0, 0, 0, 0, 20, 17, 0, 0, 24, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 82,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 122, 117, 0, 0, 0, 0, 0,
+ 111, 116, 109, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 124, 120, 129, 0, 0,
+ 183, 188, 0, 0, 0, 0, 185, 180, 0, 0,
+ 0, 189, 0, 0, 0, 0, 0, 0, 0, 216,
+ 257, 0, 0, 11, 0, 5, 0, 21, 0, 29,
+ 27, 0, 25, 0, 0, 0, 0, 59, 0, 0,
+ 83, 0, 174, 170, 169, 0, 171, 173, 0, 175,
+ 0, 0, 0, 0, 154, 131, 0, 136, 0, 163,
+ 0, 119, 0, 110, 0, 0, 0, 156, 0, 132,
+ 0, 137, 0, 0, 0, 167, 0, 0, 125, 130,
+ 0, 0, 0, 0, 203, 190, 0, 194, 0, 208,
+ 0, 181, 0, 0, 0, 205, 191, 0, 195, 0,
+ 212, 0, 258, 0, 260, 0, 12, 0, 16, 23,
+ 0, 30, 28, 0, 26, 41, 40, 0, 39, 60,
+ 0, 89, 0, 0, 0, 146, 149, 153, 0, 0,
+ 0, 0, 164, 0, 112, 147, 0, 150, 0, 155,
+ 0, 152, 0, 0, 0, 0, 168, 159, 0, 0,
+ 198, 200, 202, 0, 0, 209, 0, 199, 201, 204,
+ 0, 0, 213, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 84, 0, 0, 77, 134, 141,
+ 143, 139, 161, 145, 148, 151, 135, 0, 142, 144,
+ 140, 0, 160, 165, 0, 177, 192, 196, 206, 193,
+ 197, 210, 259, 262, 263, 261, 14, 15, 13, 22,
+ 31, 0, 172, 176, 162, 133, 138, 166, 157, 207,
+ 211, 32, 42, 158
+};
+
+ /* YYPGOTO[NTERM-NUM]. */
+static const yytype_int16 yypgoto[] =
+{
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212, -212, -212, -212, -212,
+ -39, 529, -84, -48, -211, -82, -212, -212, -212, -212,
+ -212, -212, -212, -212, -212, -212
+};
+
+ /* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int16 yydefgoto[] =
+{
+ -1, 84, 277, 458, 464, 634, 632, 631, 741, 292,
+ 242, 295, 298, 152, 151, 120, 121, 123, 122, 583,
+ 501, 493, 515, 598, 517, 599, 743, 712, 734, 652,
+ 737, 666, 611, 520, 526, 739, 675, 740, 682, 453,
+ 118, 218, 141, 110, 150, 142, 85, 86, 87, 88,
+ 89, 90, 91, 92, 93, 94
+};
+
+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule whose
+ number is the opposite. If YYTABLE_NINF, syntax error. */
+static const yytype_uint16 yytable[] =
+{
+ 140, 184, 143, 149, 156, 158, 192, 197, 415, 417,
+ 581, 587, 226, 206, 207, 208, 209, 210, 211, 212,
+ 213, 369, 125, 126, 127, 128, 129, 130, 131, 214,
+ 595, 655, 325, 657, 659, 706, 710, 116, 713, 215,
+ 248, 319, 335, 111, 320, 221, 183, 370, 116, 191,
+ 196, 203, 336, 100, 220, 225, 124, 125, 126, 127,
+ 128, 129, 130, 131, 368, 255, 440, 232, 132, 133,
+ 134, 135, 136, 137, 138, 206, 207, 208, 209, 210,
+ 211, 212, 213, 95, 125, 126, 127, 128, 129, 130,
+ 131, 116, 411, 96, 436, 132, 133, 134, 135, 189,
+ 137, 138, 104, 105, 106, 107, 104, 105, 106, 107,
+ 234, 237, 97, 345, 116, 430, 510, 511, 185, 649,
+ 650, 116, 289, 290, 377, 346, 416, 418, 582, 588,
+ 186, 347, 216, 217, 249, 145, 146, 147, 119, 371,
+ 512, 98, 116, 651, 685, 686, 332, 99, 596, 656,
+ 326, 658, 660, 707, 711, 116, 714, 153, 256, 257,
+ 233, 315, 337, 316, 101, 188, 419, 420, 687, 102,
+ 688, 689, 103, 421, 154, 139, 441, 132, 133, 134,
+ 135, 189, 137, 138, 159, 412, 413, 437, 438, 160,
+ 367, 190, 373, 328, 690, 163, 321, 322, 323, 338,
+ 385, 313, 339, 235, 238, 312, 314, 324, 431, 161,
+ 162, 327, 329, 108, 334, 164, 378, 165, 109, 349,
+ 405, 174, 175, 348, 181, 125, 126, 127, 128, 129,
+ 130, 131, 380, 204, 205, 366, 166, 372, 1, 176,
+ 116, 379, 177, 384, 333, 178, 104, 105, 106, 107,
+ 182, 341, 342, 343, 116, 179, 2, 167, 168, 169,
+ 170, 180, 344, 404, 219, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
+ 78, 79, 80, 81, 82, 83, 193, 442, 443, 187,
+ 112, 113, 114, 115, 444, 299, 300, 227, 132, 133,
+ 134, 135, 189, 137, 138, 222, 116, 194, 571, 572,
+ 228, 171, 195, 172, 173, 573, 117, 132, 133, 134,
+ 135, 189, 137, 138, 382, 239, 223, 601, 602, 396,
+ 397, 224, 423, 424, 603, 243, 132, 133, 134, 135,
+ 189, 137, 138, 402, 425, 426, 198, 199, 200, 201,
+ 383, 145, 146, 147, 229, 132, 133, 134, 135, 189,
+ 137, 138, 116, 230, 104, 105, 106, 107, 241, 403,
+ 155, 231, 202, 125, 126, 127, 128, 129, 130, 131,
+ 236, 144, 145, 146, 147, 495, 496, 497, 116, 116,
+ 522, 523, 524, 148, 427, 428, 498, 240, 365, 447,
+ 448, 525, 104, 105, 106, 107, 456, 457, 157, 449,
+ 450, 244, 451, 452, 460, 461, 466, 467, 541, 542,
+ 575, 576, 577, 578, 579, 580, 247, 245, 605, 606,
+ 607, 608, 250, 609, 610, 622, 623, 624, 625, 626,
+ 627, 629, 630, 251, 246, 283, 253, 252, 254, 258,
+ 259, 260, 261, 262, 296, 263, 264, 265, 266, 297,
+ 306, 267, 307, 308, 268, 269, 270, 271, 272, 273,
+ 274, 309, 275, 311, 276, 331, 279, 278, 280, 281,
+ 282, 340, 350, 284, 285, 351, 352, 302, 286, 287,
+ 288, 291, 353, 293, 294, 354, 355, 318, 301, 304,
+ 303, 305, 317, 310, 356, 357, 358, 359, 360, 361,
+ 362, 363, 364, 374, 375, 376, 381, 386, 387, 388,
+ 389, 390, 391, 392, 393, 394, 395, 398, 399, 400,
+ 401, 406, 407, 408, 409, 410, 414, 422, 429, 434,
+ 432, 445, 433, 435, 446, 439, 454, 463, 455, 459,
+ 462, 465, 468, 479, 469, 471, 470, 473, 474, 476,
+ 475, 472, 480, 481, 491, 478, 477, 483, 482, 494,
+ 500, 488, 484, 486, 485, 487, 502, 531, 489, 490,
+ 499, 492, 508, 514, 516, 518, 503, 521, 504, 505,
+ 506, 507, 509, 513, 527, 544, 534, 519, 536, 538,
+ 539, 540, 543, 545, 547, 548, 549, 550, 528, 551,
+ 529, 530, 552, 557, 561, 532, 562, 553, 533, 563,
+ 535, 565, 564, 537, 567, 566, 569, 589, 591, 546,
+ 615, 616, 618, 620, 628, 635, 715, 636, 637, 638,
+ 639, 640, 643, 644, 648, 653, 554, 555, 584, 677,
+ 678, 559, 556, 558, 560, 568, 570, 574, 585, 586,
+ 590, 592, 654, 661, 667, 673, 593, 594, 597, 600,
+ 604, 612, 613, 617, 674, 676, 679, 614, 684, 691,
+ 703, 704, 705, 619, 621, 633, 641, 642, 645, 708,
+ 709, 719, 646, 720, 721, 730, 732, 733, 735, 662,
+ 647, 736, 663, 738, 670, 742, 664, 665, 668, 669,
+ 0, 0, 0, 0, 0, 0, 0, 0, 671, 680,
+ 330, 672, 694, 681, 683, 0, 0, 692, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 693, 0, 0,
+ 0, 0, 0, 696, 695, 0, 0, 0, 0, 0,
+ 697, 698, 699, 700, 701, 702, 0, 0, 0, 0,
+ 0, 716, 0, 0, 717, 718, 722, 723, 724, 0,
+ 0, 725, 726, 0, 0, 0, 0, 0, 727, 728,
+ 729, 0, 0, 0, 731
+};
+
+static const yytype_int16 yycheck[] =
+{
+ 39, 85, 41, 42, 52, 53, 88, 89, 3, 3,
+ 3, 3, 94, 3, 4, 5, 6, 7, 8, 9,
+ 10, 3, 4, 5, 6, 7, 8, 9, 10, 19,
+ 3, 3, 3, 3, 3, 3, 3, 19, 3, 29,
+ 29, 120, 253, 123, 123, 93, 85, 29, 19, 88,
+ 89, 90, 11, 11, 93, 94, 3, 4, 5, 6,
+ 7, 8, 9, 10, 275, 29, 11, 29, 15, 16,
+ 17, 18, 19, 20, 21, 3, 4, 5, 6, 7,
+ 8, 9, 10, 127, 4, 5, 6, 7, 8, 9,
+ 10, 19, 29, 127, 29, 15, 16, 17, 18, 19,
+ 20, 21, 11, 12, 13, 14, 11, 12, 13, 14,
+ 29, 29, 127, 11, 19, 29, 5, 6, 11, 5,
+ 6, 19, 122, 123, 29, 23, 121, 121, 121, 121,
+ 23, 29, 122, 123, 123, 12, 13, 14, 4, 121,
+ 29, 127, 19, 29, 5, 6, 23, 127, 121, 121,
+ 121, 121, 121, 121, 121, 19, 121, 4, 122, 123,
+ 122, 245, 121, 245, 122, 3, 5, 6, 29, 127,
+ 5, 6, 127, 12, 24, 122, 121, 15, 16, 17,
+ 18, 19, 20, 21, 3, 122, 123, 122, 123, 3,
+ 274, 29, 276, 121, 29, 3, 12, 13, 14, 120,
+ 282, 121, 123, 122, 122, 244, 245, 23, 122, 11,
+ 12, 250, 251, 122, 253, 3, 121, 3, 127, 258,
+ 302, 11, 12, 121, 3, 4, 5, 6, 7, 8,
+ 9, 10, 280, 11, 12, 274, 11, 276, 12, 3,
+ 19, 280, 11, 282, 121, 3, 11, 12, 13, 14,
+ 29, 12, 13, 14, 19, 11, 30, 25, 26, 27,
+ 28, 0, 23, 302, 29, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
+ 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
+ 94, 95, 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
+ 114, 115, 116, 117, 118, 119, 3, 5, 6, 24,
+ 3, 4, 5, 6, 12, 122, 123, 29, 15, 16,
+ 17, 18, 19, 20, 21, 3, 19, 24, 5, 6,
+ 29, 3, 29, 5, 6, 12, 29, 15, 16, 17,
+ 18, 19, 20, 21, 3, 122, 24, 5, 6, 122,
+ 123, 29, 124, 125, 12, 122, 15, 16, 17, 18,
+ 19, 20, 21, 3, 124, 125, 3, 4, 5, 6,
+ 29, 12, 13, 14, 29, 15, 16, 17, 18, 19,
+ 20, 21, 19, 29, 11, 12, 13, 14, 128, 29,
+ 17, 29, 29, 4, 5, 6, 7, 8, 9, 10,
+ 29, 11, 12, 13, 14, 12, 13, 14, 19, 19,
+ 12, 13, 14, 23, 124, 125, 23, 29, 29, 124,
+ 125, 23, 11, 12, 13, 14, 122, 123, 17, 124,
+ 125, 120, 124, 125, 122, 123, 122, 123, 13, 14,
+ 124, 125, 124, 125, 124, 125, 29, 120, 124, 125,
+ 124, 125, 120, 124, 125, 124, 125, 124, 125, 124,
+ 125, 124, 125, 120, 128, 126, 120, 123, 120, 120,
+ 120, 120, 120, 120, 29, 120, 120, 120, 120, 14,
+ 29, 120, 29, 29, 120, 120, 120, 120, 120, 120,
+ 120, 29, 120, 29, 120, 14, 120, 122, 120, 120,
+ 120, 29, 29, 126, 123, 29, 29, 120, 126, 126,
+ 126, 126, 29, 122, 128, 29, 29, 120, 126, 123,
+ 126, 126, 122, 124, 29, 29, 29, 29, 29, 29,
+ 29, 29, 29, 120, 29, 3, 121, 29, 29, 14,
+ 29, 29, 29, 29, 14, 29, 29, 125, 29, 14,
+ 29, 29, 14, 29, 123, 29, 29, 124, 29, 125,
+ 29, 120, 29, 29, 124, 29, 29, 120, 122, 29,
+ 121, 29, 29, 29, 126, 123, 126, 120, 120, 120,
+ 124, 126, 14, 29, 14, 124, 126, 120, 125, 29,
+ 29, 120, 126, 123, 126, 126, 29, 11, 124, 120,
+ 120, 123, 29, 29, 29, 29, 124, 29, 124, 124,
+ 120, 120, 120, 120, 29, 14, 29, 123, 29, 29,
+ 29, 29, 29, 29, 29, 14, 29, 29, 124, 14,
+ 124, 124, 29, 29, 29, 120, 24, 127, 120, 29,
+ 120, 14, 29, 120, 24, 29, 24, 3, 3, 121,
+ 11, 11, 11, 11, 29, 29, 4, 29, 29, 29,
+ 29, 29, 29, 29, 29, 29, 127, 126, 120, 11,
+ 11, 125, 127, 126, 124, 126, 125, 124, 120, 120,
+ 124, 124, 29, 29, 29, 29, 124, 124, 124, 124,
+ 124, 120, 120, 124, 29, 29, 11, 120, 29, 29,
+ 29, 29, 29, 124, 124, 124, 124, 124, 124, 3,
+ 3, 11, 124, 11, 11, 29, 29, 24, 29, 120,
+ 124, 29, 120, 29, 124, 29, 120, 120, 120, 120,
+ -1, -1, -1, -1, -1, -1, -1, -1, 124, 120,
+ 251, 124, 124, 120, 120, -1, -1, 126, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, 120, -1, -1,
+ -1, -1, -1, 120, 126, -1, -1, -1, -1, -1,
+ 124, 124, 124, 124, 124, 124, -1, -1, -1, -1,
+ -1, 124, -1, -1, 124, 124, 124, 124, 124, -1,
+ -1, 124, 124, -1, -1, -1, -1, -1, 124, 124,
+ 124, -1, -1, -1, 127
+};
+
+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 12, 30, 39, 40, 41, 42, 43, 44, 45,
+ 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,
+ 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 79, 80, 81, 82, 83, 84, 85,
+ 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
+ 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
+ 116, 117, 118, 119, 130, 175, 176, 177, 178, 179,
+ 180, 181, 182, 183, 184, 127, 127, 127, 127, 127,
+ 11, 122, 127, 127, 11, 12, 13, 14, 122, 127,
+ 172, 123, 3, 4, 5, 6, 19, 29, 169, 4,
+ 144, 145, 147, 146, 3, 4, 5, 6, 7, 8,
+ 9, 10, 15, 16, 17, 18, 19, 20, 21, 122,
+ 169, 171, 174, 169, 11, 12, 13, 14, 23, 169,
+ 173, 143, 142, 4, 24, 17, 172, 17, 172, 3,
+ 3, 11, 12, 3, 3, 3, 11, 25, 26, 27,
+ 28, 3, 5, 6, 11, 12, 3, 11, 3, 11,
+ 0, 3, 29, 169, 171, 11, 23, 24, 3, 19,
+ 29, 169, 174, 3, 24, 29, 169, 174, 3, 4,
+ 5, 6, 29, 169, 11, 12, 3, 4, 5, 6,
+ 7, 8, 9, 10, 19, 29, 122, 123, 170, 29,
+ 169, 172, 3, 24, 29, 169, 174, 29, 29, 29,
+ 29, 29, 29, 122, 29, 122, 29, 29, 122, 122,
+ 29, 128, 139, 122, 120, 120, 128, 29, 29, 123,
+ 120, 120, 123, 120, 120, 29, 122, 123, 120, 120,
+ 120, 120, 120, 120, 120, 120, 120, 120, 120, 120,
+ 120, 120, 120, 120, 120, 120, 120, 131, 122, 120,
+ 120, 120, 120, 126, 126, 123, 126, 126, 126, 122,
+ 123, 126, 138, 122, 128, 140, 29, 14, 141, 122,
+ 123, 126, 120, 126, 123, 126, 29, 29, 29, 29,
+ 124, 29, 169, 121, 169, 171, 174, 122, 120, 120,
+ 123, 12, 13, 14, 23, 3, 121, 169, 121, 169,
+ 170, 14, 23, 121, 169, 173, 11, 121, 120, 123,
+ 29, 12, 13, 14, 23, 11, 23, 29, 121, 169,
+ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
+ 29, 29, 29, 29, 29, 29, 169, 171, 173, 3,
+ 29, 121, 169, 171, 120, 29, 3, 29, 121, 169,
+ 172, 121, 3, 29, 169, 174, 29, 29, 14, 29,
+ 29, 29, 29, 14, 29, 29, 122, 123, 125, 29,
+ 14, 29, 3, 29, 169, 174, 29, 14, 29, 123,
+ 29, 29, 122, 123, 29, 3, 121, 3, 121, 5,
+ 6, 12, 124, 124, 125, 124, 125, 124, 125, 29,
+ 29, 122, 29, 29, 125, 29, 29, 122, 123, 29,
+ 11, 121, 5, 6, 12, 120, 124, 124, 125, 124,
+ 125, 124, 125, 168, 29, 122, 122, 123, 132, 29,
+ 122, 123, 121, 120, 133, 29, 122, 123, 29, 126,
+ 126, 123, 126, 120, 120, 124, 120, 126, 124, 29,
+ 14, 29, 125, 120, 126, 126, 123, 126, 120, 124,
+ 120, 14, 123, 150, 29, 12, 13, 14, 23, 120,
+ 29, 149, 29, 124, 124, 124, 120, 120, 29, 120,
+ 5, 6, 29, 120, 29, 151, 29, 153, 29, 123,
+ 162, 29, 12, 13, 14, 23, 163, 29, 124, 124,
+ 124, 11, 120, 120, 29, 120, 29, 120, 29, 29,
+ 29, 13, 14, 29, 14, 29, 121, 29, 14, 29,
+ 29, 14, 29, 127, 127, 126, 127, 29, 126, 125,
+ 124, 29, 24, 29, 29, 14, 29, 24, 126, 24,
+ 125, 5, 6, 12, 124, 124, 125, 124, 125, 124,
+ 125, 3, 121, 148, 120, 120, 120, 3, 121, 3,
+ 124, 3, 124, 124, 124, 3, 121, 124, 152, 154,
+ 124, 5, 6, 12, 124, 124, 125, 124, 125, 124,
+ 125, 161, 120, 120, 120, 11, 11, 124, 11, 124,
+ 11, 124, 124, 125, 124, 125, 124, 125, 29, 124,
+ 125, 136, 135, 124, 134, 29, 29, 29, 29, 29,
+ 29, 124, 124, 29, 29, 124, 124, 124, 29, 5,
+ 6, 29, 158, 29, 29, 3, 121, 3, 121, 3,
+ 121, 29, 120, 120, 120, 120, 160, 29, 120, 120,
+ 124, 124, 124, 29, 29, 165, 29, 11, 11, 11,
+ 120, 120, 167, 120, 29, 5, 6, 29, 5, 6,
+ 29, 29, 126, 120, 124, 126, 120, 124, 124, 124,
+ 124, 124, 124, 29, 29, 29, 3, 121, 3, 3,
+ 3, 121, 156, 3, 121, 4, 124, 124, 124, 11,
+ 11, 11, 124, 124, 124, 124, 124, 124, 124, 124,
+ 29, 127, 29, 24, 157, 29, 29, 159, 29, 164,
+ 166, 137, 29, 155
+};
+
+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 129, 130, 130, 131, 130, 130, 130, 130, 132,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 133,
+ 130, 130, 130, 130, 130, 134, 130, 135, 130, 136,
+ 130, 137, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 138, 130, 130, 130, 130,
+ 130, 130, 130, 130, 139, 130, 130, 130, 130, 140,
+ 130, 130, 130, 130, 130, 130, 141, 130, 130, 130,
+ 130, 130, 142, 130, 143, 130, 130, 144, 130, 145,
+ 130, 146, 130, 147, 130, 130, 130, 130, 130, 148,
+ 130, 130, 130, 130, 130, 149, 130, 130, 130, 130,
+ 130, 150, 130, 151, 152, 130, 130, 130, 153, 154,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 155, 130, 156,
+ 130, 157, 130, 158, 130, 159, 130, 160, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 161, 130, 162, 130, 163, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 164, 130, 165, 130,
+ 166, 130, 167, 130, 168, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 130, 130, 130, 130,
+ 130, 130, 130, 130, 130, 130, 169, 169, 170, 170,
+ 170, 170, 170, 170, 170, 170, 171, 171, 171, 171,
+ 171, 171, 171, 172, 172, 172, 172, 173, 173, 173,
+ 174, 174, 174, 174, 174, 174, 174, 175, 175, 175,
+ 175, 175, 175, 175, 175, 176, 176, 176, 177, 177,
+ 177, 178, 178, 178, 179, 179, 180, 180, 181, 181,
+ 182, 182, 183, 183, 184
+};
+
+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 1, 5, 0, 6, 4, 4, 4, 0,
+ 5, 6, 7, 9, 9, 9, 7, 5, 4, 0,
+ 5, 6, 9, 7, 5, 0, 7, 0, 7, 0,
+ 7, 0, 10, 3, 3, 3, 3, 3, 3, 7,
+ 7, 7, 10, 2, 3, 4, 3, 4, 1, 1,
+ 2, 4, 3, 4, 4, 2, 4, 4, 4, 6,
+ 7, 2, 2, 2, 2, 0, 3, 4, 2, 2,
+ 2, 2, 2, 2, 0, 3, 4, 9, 2, 0,
+ 3, 3, 5, 6, 8, 2, 0, 3, 4, 7,
+ 1, 1, 0, 2, 0, 2, 2, 0, 2, 0,
+ 2, 0, 2, 0, 2, 1, 5, 5, 5, 0,
+ 7, 6, 8, 4, 4, 0, 6, 6, 5, 7,
+ 6, 0, 6, 0, 0, 7, 4, 4, 0, 0,
+ 7, 7, 7, 10, 9, 9, 7, 7, 10, 9,
+ 9, 9, 9, 9, 9, 9, 8, 8, 9, 8,
+ 8, 9, 8, 8, 7, 8, 7, 0, 11, 0,
+ 9, 0, 10, 0, 8, 0, 10, 0, 8, 6,
+ 6, 6, 9, 6, 6, 6, 9, 9, 5, 5,
+ 0, 7, 0, 6, 0, 6, 4, 4, 6, 6,
+ 7, 7, 9, 9, 7, 7, 9, 9, 8, 8,
+ 8, 8, 8, 7, 8, 7, 0, 10, 0, 8,
+ 0, 10, 0, 8, 0, 5, 6, 5, 4, 4,
+ 4, 1, 2, 2, 2, 2, 2, 1, 1, 1,
+ 4, 4, 4, 4, 4, 4, 4, 4, 2, 2,
+ 2, 2, 4, 4, 4, 4, 4, 4, 4, 1,
+ 1, 1, 1, 1, 1, 1, 4, 6, 7, 9,
+ 7, 9, 9, 9, 4, 4, 0, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1
+};
+
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+/* Error token number */
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT. |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ YYFPRINTF (yyoutput, "%s %s (",
+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+ {
+ int yybot = *yybottom;
+ YYFPRINTF (stderr, " %d", yybot);
+ }
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr,
+ yystos[yyssp[yyi + 1 - yynrhs]],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ YYFPRINTF (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+ about the unexpected token YYTOKEN for the state stack whose top is
+ YYSSP.
+
+ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
+ not large enough to hold the message. In that case, also set
+ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
+ required number of bytes is too large to store. */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+{
+ YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+ const char *yyformat = YY_NULL;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+ "expected"). */
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+ tokens because there are none.
+ - The only way there can be no lookahead present (in yychar) is if
+ this state is a consistent state with a default action. Thus,
+ detecting the absence of a lookahead is sufficient to determine
+ that there is no unexpected or expected token to report. In that
+ case, just report a simple "syntax error".
+ - Don't assume there isn't a lookahead just because this state is a
+ consistent state with a default action. There might have been a
+ previous inconsistent state, consistent state with a non-default
+ action, or user semantic action that manipulated yychar.
+ - Of course, the expected token list depends on states to have
+ correct lookahead information, and it depends on the parser not
+ to perform extra reductions after fetching a lookahead from the
+ scanner and before detecting a syntax error. Thus, state merging
+ (from LALR or IELR) and default reductions corrupt the expected
+ token list. However, the list is correct for canonical LR with
+ one exception: it will still contain any token that will not be
+ accepted due to an error action in a later state.
+ */
+ if (yytoken != YYEMPTY)
+ {
+ int yyn = yypact[*yyssp];
+ yyarg[yycount++] = yytname[yytoken];
+ if (!yypact_value_is_default (yyn))
+ {
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. In other words, skip the first -YYN actions for
+ this state because they are default actions. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yyx;
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+ && !yytable_value_is_error (yytable[yyx + yyn]))
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+ }
+ }
+ }
+
+ switch (yycount)
+ {
+# define YYCASE_(N, S) \
+ case N: \
+ yyformat = S; \
+ break
+ YYCASE_(0, YY_("syntax error"));
+ YYCASE_(1, YY_("syntax error, unexpected %s"));
+ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+ }
+
+ {
+ YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+
+ if (*yymsg_alloc < yysize)
+ {
+ *yymsg_alloc = 2 * yysize;
+ if (! (yysize <= *yymsg_alloc
+ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+ return 1;
+ }
+
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ {
+ char *yyp = *yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyformat) != '\0')
+ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyformat += 2;
+ }
+ else
+ {
+ yyp++;
+ yyformat++;
+ }
+ }
+ return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+ YYUSE (yyvaluep);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol. */
+int yychar;
+
+/* The semantic value of the lookahead symbol. */
+YYSTYPE yylval;
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+int
+yyparse (void)
+{
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+ 'yyss': related to states.
+ 'yyvs': related to semantic values.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
+ YYSIZE_T yystacksize;
+
+ int yyn;
+ int yyresult;
+ /* Lookahead token as an internal (translated) token number. */
+ int yytoken = 0;
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss_alloc, yyss);
+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ if (yystate == YYFINAL)
+ YYACCEPT;
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ lookahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to lookahead token. */
+ yyn = yypact[yystate];
+ if (yypact_value_is_default (yyn))
+ goto yydefault;
+
+ /* Not known => get a lookahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yytable_value_is_error (yyn))
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the lookahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token. */
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 2:
+#line 188 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { as_bad (_("Unknown opcode: %s"), rl78_init_start); }
+#line 2079 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 3:
+#line 209 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0c|(yyvsp[-4].regno)); O1 ((yyvsp[0].exp)); }
+#line 2085 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 4:
+#line 211 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2091 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 5:
+#line 212 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0a|(yyvsp[-5].regno)); SET_SA ((yyvsp[-4].exp)); O1 ((yyvsp[-4].exp)); O1 ((yyvsp[0].exp)); }
+#line 2097 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 6:
+#line 215 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x01|(yyvsp[-3].regno)); }
+#line 2103 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 7:
+#line 218 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x08|(yyvsp[-3].regno)); F ((yyvsp[0].regno), 13, 3); }
+#line 2109 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 8:
+#line 221 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x00|(yyvsp[-3].regno)); F ((yyvsp[-2].regno), 13, 3); }
+#line 2115 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 9:
+#line 223 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2121 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 10:
+#line 224 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0b|(yyvsp[-4].regno)); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2127 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 11:
+#line 227 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0f|(yyvsp[-5].regno)); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2133 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 12:
+#line 230 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0d|(yyvsp[-6].regno)); }
+#line 2139 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 13:
+#line 233 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x0e|(yyvsp[-8].regno)); O1 ((yyvsp[-1].exp)); }
+#line 2145 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 14:
+#line 236 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x80|(yyvsp[-8].regno)); }
+#line 2151 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 15:
+#line 239 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x82|(yyvsp[-8].regno)); }
+#line 2157 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 16:
+#line 242 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-6].regno) != 0x40)
+ { rl78_error ("Only CMP takes these operands"); }
+ else
+ { B1 (0x00|(yyvsp[-6].regno)); O2 ((yyvsp[-3].exp)); O1 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+ }
+#line 2167 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 17:
+#line 251 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x04|(yyvsp[-4].regno)); O2 ((yyvsp[0].exp)); }
+#line 2173 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 18:
+#line 254 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x01|(yyvsp[-3].regno)); F ((yyvsp[0].regno), 5, 2); }
+#line 2179 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 19:
+#line 256 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2185 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 20:
+#line 257 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x06|(yyvsp[-4].regno)); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2191 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 21:
+#line 260 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x02|(yyvsp[-5].regno)); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2197 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 22:
+#line 263 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x09|(yyvsp[-8].regno)); O1 ((yyvsp[-1].exp)); }
+#line 2203 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 23:
+#line 266 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x61, 0x09|(yyvsp[-6].regno), 0); }
+#line 2209 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 24:
+#line 269 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 ((yyvsp[-4].regno) ? 0x20 : 0x10); O1 ((yyvsp[0].exp));
+ if ((yyvsp[-4].regno) == 0x40)
+ rl78_error ("CMPW SP,#imm not allowed");
+ }
+#line 2218 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 25:
+#line 276 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {Bit((yyvsp[0].exp))}
+#line 2224 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 26:
+#line 277 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x08|(yyvsp[-6].regno), (yyvsp[-3].regno)); FE ((yyvsp[-1].exp), 9, 3); }
+#line 2230 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 27:
+#line 279 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {Bit((yyvsp[0].exp))}
+#line 2236 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 28:
+#line 280 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[-3].exp)))
+ { B2 (0x71, 0x08|(yyvsp[-6].regno)); FE ((yyvsp[-1].exp), 9, 3); O1 ((yyvsp[-3].exp)); }
+ else if (expr_is_saddr ((yyvsp[-3].exp)))
+ { B2 (0x71, 0x00|(yyvsp[-6].regno)); FE ((yyvsp[-1].exp), 9, 3); SET_SA ((yyvsp[-3].exp)); O1 ((yyvsp[-3].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2248 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 29:
+#line 288 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {Bit((yyvsp[0].exp))}
+#line 2254 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 30:
+#line 289 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x88|(yyvsp[-6].regno)); FE ((yyvsp[-1].exp), 9, 3); }
+#line 2260 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 31:
+#line 291 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {Bit((yyvsp[0].exp))}
+#line 2266 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 32:
+#line 292 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x80|(yyvsp[-9].regno)); FE ((yyvsp[-1].exp), 9, 3); }
+#line 2272 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 33:
+#line 297 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xdc); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2278 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 34:
+#line 300 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xde); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2284 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 35:
+#line 303 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xdd); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2290 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 36:
+#line 306 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xdf); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2296 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 37:
+#line 309 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xc3); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2302 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 38:
+#line 312 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xd3); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2308 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 39:
+#line 317 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x31, 0x80|(yyvsp[-6].regno), (yyvsp[-5].regno)); FE ((yyvsp[-3].exp), 9, 3); PC1 ((yyvsp[0].exp)); }
+#line 2314 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 40:
+#line 320 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[-5].exp)))
+ { B2 (0x31, 0x80|(yyvsp[-6].regno)); FE ((yyvsp[-3].exp), 9, 3); O1 ((yyvsp[-5].exp)); PC1 ((yyvsp[0].exp)); }
+ else if (expr_is_saddr ((yyvsp[-5].exp)))
+ { B2 (0x31, 0x00|(yyvsp[-6].regno)); FE ((yyvsp[-3].exp), 9, 3); SET_SA ((yyvsp[-5].exp)); O1 ((yyvsp[-5].exp)); PC1 ((yyvsp[0].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2326 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 41:
+#line 329 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x31, 0x01|(yyvsp[-6].regno)); FE ((yyvsp[-3].exp), 9, 3); PC1 ((yyvsp[0].exp)); }
+#line 2332 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 42:
+#line 332 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x31, 0x81|(yyvsp[-9].regno)); FE ((yyvsp[-3].exp), 9, 3); PC1 ((yyvsp[0].exp)); }
+#line 2338 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 43:
+#line 337 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xcb); }
+#line 2344 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 44:
+#line 340 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xef); PC1 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2350 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 45:
+#line 343 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xee); PC2 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2356 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 46:
+#line 346 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xed); O2 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2362 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 47:
+#line 349 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xec); O3 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2368 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 48:
+#line 354 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xcc); }
+#line 2374 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 49:
+#line 357 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xff); }
+#line 2380 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 50:
+#line 362 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xca); F ((yyvsp[0].regno), 10, 2); }
+#line 2386 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 51:
+#line 365 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xfe); PC2 ((yyvsp[0].exp)); }
+#line 2392 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 52:
+#line 368 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xfd); O2 ((yyvsp[0].exp)); }
+#line 2398 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 53:
+#line 371 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xfc); O3 ((yyvsp[0].exp)); rl78_linkrelax_branch (); }
+#line 2404 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 54:
+#line 374 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-1].exp).X_op != O_constant)
+ rl78_error ("CALLT requires a numeric address");
+ else
+ {
+ int i = (yyvsp[-1].exp).X_add_number;
+ if (i < 0x80 || i > 0xbe)
+ rl78_error ("CALLT address not 0x80..0xbe");
+ else if (i & 1)
+ rl78_error ("CALLT address not even");
+ else
+ {
+ B2 (0x61, 0x84);
+ F ((i >> 1) & 7, 9, 3);
+ F ((i >> 4) & 7, 14, 2);
+ }
+ }
+ }
+#line 2426 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 55:
+#line 395 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, (yyvsp[-1].regno) ? 0x88 : 0x80); }
+#line 2432 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 56:
+#line 398 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x0a|(yyvsp[-3].regno), (yyvsp[-2].regno)); FE ((yyvsp[0].exp), 9, 3); }
+#line 2438 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 57:
+#line 401 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[-2].exp)))
+ { B2 (0x71, 0x0a|(yyvsp[-3].regno)); FE ((yyvsp[0].exp), 9, 3); O1 ((yyvsp[-2].exp)); }
+ else if (expr_is_saddr ((yyvsp[-2].exp)))
+ { B2 (0x71, 0x02|(yyvsp[-3].regno)); FE ((yyvsp[0].exp), 9, 3); SET_SA ((yyvsp[-2].exp)); O1 ((yyvsp[-2].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2450 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 58:
+#line 410 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x8a|(yyvsp[-3].regno)); FE ((yyvsp[0].exp), 9, 3); }
+#line 2456 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 59:
+#line 413 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x00+(yyvsp[-5].regno)*0x08); FE ((yyvsp[0].exp), 9, 3); O2 ((yyvsp[-2].exp)); rl78_linkrelax_addr16 (); }
+#line 2462 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 60:
+#line 416 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x82|(yyvsp[-6].regno)); FE ((yyvsp[0].exp), 9, 3); }
+#line 2468 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 61:
+#line 421 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe1|(yyvsp[-1].regno)); }
+#line 2474 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 62:
+#line 423 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe0|(yyvsp[-1].regno)); }
+#line 2480 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 63:
+#line 425 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe3|(yyvsp[-1].regno)); }
+#line 2486 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 64:
+#line 427 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe2|(yyvsp[-1].regno)); }
+#line 2492 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 65:
+#line 429 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2498 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 66:
+#line 430 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe4|(yyvsp[-2].regno)); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2504 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 67:
+#line 433 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe5|(yyvsp[-3].regno)); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2510 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 68:
+#line 438 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe6|(yyvsp[-1].regno)); }
+#line 2516 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 69:
+#line 440 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xe7|(yyvsp[-1].regno)); }
+#line 2522 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 70:
+#line 445 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd1); }
+#line 2528 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 71:
+#line 448 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd0); }
+#line 2534 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 72:
+#line 451 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd3); }
+#line 2540 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 73:
+#line 454 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd2); }
+#line 2546 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 74:
+#line 456 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2552 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 75:
+#line 457 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd4); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2558 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 76:
+#line 460 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd5); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2564 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 77:
+#line 465 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xde); O1 ((yyvsp[-1].exp)); }
+#line 2570 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 78:
+#line 470 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x80|(yyvsp[-1].regno)); F ((yyvsp[0].regno), 5, 3); }
+#line 2576 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 79:
+#line 472 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2582 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 80:
+#line 473 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa4|(yyvsp[-2].regno)); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2588 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 81:
+#line 475 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa0|(yyvsp[-2].regno)); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2594 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 82:
+#line 477 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x11, 0xa0|(yyvsp[-4].regno)); O2 ((yyvsp[0].exp)); }
+#line 2600 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 83:
+#line 479 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x59+(yyvsp[-5].regno)); O1 ((yyvsp[-1].exp)); }
+#line 2606 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 84:
+#line 481 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x11, 0x61, 0x59+(yyvsp[-7].regno)); O1 ((yyvsp[-1].exp)); }
+#line 2612 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 85:
+#line 486 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa1|(yyvsp[-1].regno)); F ((yyvsp[0].regno), 5, 2); }
+#line 2618 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 86:
+#line 488 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2624 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 87:
+#line 489 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa6|(yyvsp[-2].regno)); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+#line 2630 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 88:
+#line 492 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa2|(yyvsp[-3].regno)); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2636 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 89:
+#line 495 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0x79+(yyvsp[-6].regno)); O1 ((yyvsp[-1].exp)); }
+#line 2642 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 90:
+#line 500 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x7b, 0xfa); }
+#line 2648 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 91:
+#line 503 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x7a, 0xfa); }
+#line 2654 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 92:
+#line 507 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("MULHU"); }
+#line 2660 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 93:
+#line 508 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x01); }
+#line 2666 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 94:
+#line 510 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("MULH"); }
+#line 2672 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 95:
+#line 511 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x02); }
+#line 2678 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 96:
+#line 514 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd6); }
+#line 2684 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 97:
+#line 516 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("DIVHU"); }
+#line 2690 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 98:
+#line 517 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x03); }
+#line 2696 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 99:
+#line 524 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("DIVWU"); }
+#line 2702 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 100:
+#line 525 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x0b); }
+#line 2708 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 101:
+#line 527 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("MACHU"); }
+#line 2714 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 102:
+#line 528 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x05); }
+#line 2720 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 103:
+#line 530 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { ISA_G14 ("MACH"); }
+#line 2726 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 104:
+#line 531 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xce, 0xfb, 0x06); }
+#line 2732 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 105:
+#line 536 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xed); }
+#line 2738 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 106:
+#line 544 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x51); O1 ((yyvsp[0].exp)); }
+#line 2744 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 107:
+#line 546 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x50); F((yyvsp[-3].regno), 5, 3); O1 ((yyvsp[0].exp)); }
+#line 2750 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 108:
+#line 549 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-3].regno) != 0xfd)
+ { B2 (0xce, (yyvsp[-3].regno)); O1 ((yyvsp[0].exp)); }
+ else
+ { B1 (0x41); O1 ((yyvsp[0].exp)); }
+ }
+#line 2760 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 109:
+#line 555 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 2766 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 110:
+#line 556 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[-4].exp)))
+ { B1 (0xce); O1 ((yyvsp[-4].exp)); O1 ((yyvsp[-1].exp)); }
+ else if (expr_is_saddr ((yyvsp[-4].exp)))
+ { B1 (0xcd); SET_SA ((yyvsp[-4].exp)); O1 ((yyvsp[-4].exp)); O1 ((yyvsp[-1].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2778 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 111:
+#line 565 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xcf); O2 ((yyvsp[-3].exp)); O1 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2784 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 112:
+#line 568 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x11, 0xcf); O2 ((yyvsp[-3].exp)); O1 ((yyvsp[0].exp)); }
+#line 2790 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 113:
+#line 571 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x70); F ((yyvsp[-2].regno), 5, 3); }
+#line 2796 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 114:
+#line 574 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x60); F ((yyvsp[0].regno), 5, 3); }
+#line 2802 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 115:
+#line 576 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 2808 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 116:
+#line 577 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[-3].exp)))
+ { B1 (0x9e); O1 ((yyvsp[-3].exp)); }
+ else if (expr_is_saddr ((yyvsp[-3].exp)))
+ { B1 (0x9d); SET_SA ((yyvsp[-3].exp)); O1 ((yyvsp[-3].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2820 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 117:
+#line 586 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x8f); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2826 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 118:
+#line 589 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x9f); O2 ((yyvsp[-2].exp)); rl78_linkrelax_addr16 (); }
+#line 2832 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 119:
+#line 592 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x11, 0x9f); O2 ((yyvsp[-2].exp)); }
+#line 2838 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 120:
+#line 595 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xc9|reg_xbc((yyvsp[-4].regno))); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 2844 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 121:
+#line 597 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 2850 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 122:
+#line 598 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-1].exp)))
+ { B1 (0x8d); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); }
+ else if (expr_is_sfr ((yyvsp[-1].exp)))
+ { B1 (0x8e); O1 ((yyvsp[-1].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 2862 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 123:
+#line 606 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2868 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 124:
+#line 606 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 2874 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 125:
+#line 607 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xc8|reg_xbc((yyvsp[-5].regno))); SET_SA ((yyvsp[-2].exp)); O1 ((yyvsp[-2].exp)); }
+#line 2880 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 126:
+#line 610 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x8e, (yyvsp[0].regno)); }
+#line 2886 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 127:
+#line 613 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) != 1)
+ rl78_error ("Only A allowed here");
+ else
+ { B2 (0x9e, (yyvsp[-2].regno)); }
+ }
+#line 2896 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 128:
+#line 619 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 2902 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 129:
+#line 619 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 2908 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 130:
+#line 620 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-5].regno) != 0xfd)
+ rl78_error ("Only ES allowed here");
+ else
+ { B2 (0x61, 0xb8); SET_SA ((yyvsp[-2].exp)); O1 ((yyvsp[-2].exp)); }
+ }
+#line 2918 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 131:
+#line 627 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x89); }
+#line 2924 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 132:
+#line 630 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x99); }
+#line 2930 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 133:
+#line 633 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xca); O1 ((yyvsp[-4].exp)); O1 ((yyvsp[0].exp)); }
+#line 2936 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 134:
+#line 636 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x8a); O1 ((yyvsp[-1].exp)); }
+#line 2942 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 135:
+#line 639 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x9a); O1 ((yyvsp[-3].exp)); }
+#line 2948 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 136:
+#line 642 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x8b); }
+#line 2954 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 137:
+#line 645 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x9b); }
+#line 2960 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 138:
+#line 648 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xcc); O1 ((yyvsp[-4].exp)); O1 ((yyvsp[0].exp)); }
+#line 2966 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 139:
+#line 651 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x8c); O1 ((yyvsp[-1].exp)); }
+#line 2972 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 140:
+#line 654 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x9c); O1 ((yyvsp[-3].exp)); }
+#line 2978 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 141:
+#line 657 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xc9); }
+#line 2984 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 142:
+#line 660 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xd9); }
+#line 2990 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 143:
+#line 663 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xe9); }
+#line 2996 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 144:
+#line 666 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xf9); }
+#line 3002 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 145:
+#line 669 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x19); O2 ((yyvsp[-6].exp)); O1 ((yyvsp[0].exp)); }
+#line 3008 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 146:
+#line 672 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x09); O2 ((yyvsp[-3].exp)); }
+#line 3014 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 147:
+#line 675 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x18); O2 ((yyvsp[-5].exp)); }
+#line 3020 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 148:
+#line 678 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x38); O2 ((yyvsp[-6].exp)); O1 ((yyvsp[0].exp)); }
+#line 3026 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 149:
+#line 681 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x29); O2 ((yyvsp[-3].exp)); }
+#line 3032 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 150:
+#line 684 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x28); O2 ((yyvsp[-5].exp)); }
+#line 3038 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 151:
+#line 687 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x39); O2 ((yyvsp[-6].exp)); O1 ((yyvsp[0].exp)); }
+#line 3044 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 152:
+#line 690 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x39, 0, 0); O1 ((yyvsp[0].exp)); }
+#line 3050 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 153:
+#line 693 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x49); O2 ((yyvsp[-3].exp)); }
+#line 3056 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 154:
+#line 696 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x49, 0, 0); }
+#line 3062 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 155:
+#line 699 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x48); O2 ((yyvsp[-5].exp)); }
+#line 3068 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 156:
+#line 702 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x48, 0, 0); }
+#line 3074 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 157:
+#line 704 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3080 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 158:
+#line 705 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xc8); O1 ((yyvsp[-5].exp)); O1 ((yyvsp[-1].exp)); }
+#line 3086 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 159:
+#line 707 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3092 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 160:
+#line 708 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xc8, 0); O1 ((yyvsp[-1].exp)); }
+#line 3098 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 161:
+#line 710 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3104 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 162:
+#line 711 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x88); O1 ((yyvsp[-2].exp)); }
+#line 3110 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 163:
+#line 713 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3116 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 164:
+#line 714 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x88, 0); }
+#line 3122 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 165:
+#line 716 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3128 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 166:
+#line 717 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x98); O1 ((yyvsp[-4].exp)); }
+#line 3134 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 167:
+#line 719 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3140 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 168:
+#line 720 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x98, 0); }
+#line 3146 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 169:
+#line 725 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-2].exp)))
+ { B2 (0x71, 0x04); FE ((yyvsp[0].exp), 9, 3); SET_SA ((yyvsp[-2].exp)); O1 ((yyvsp[-2].exp)); }
+ else if (expr_is_sfr ((yyvsp[-2].exp)))
+ { B2 (0x71, 0x0c); FE ((yyvsp[0].exp), 9, 3); O1 ((yyvsp[-2].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3158 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 170:
+#line 734 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x8c); FE ((yyvsp[0].exp), 9, 3); }
+#line 3164 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 171:
+#line 737 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x0c, (yyvsp[-2].regno)); FE ((yyvsp[0].exp), 9, 3); }
+#line 3170 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 172:
+#line 740 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x84); FE ((yyvsp[0].exp), 9, 3); }
+#line 3176 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 173:
+#line 743 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-4].exp)))
+ { B2 (0x71, 0x01); FE ((yyvsp[-2].exp), 9, 3); SET_SA ((yyvsp[-4].exp)); O1 ((yyvsp[-4].exp)); }
+ else if (expr_is_sfr ((yyvsp[-4].exp)))
+ { B2 (0x71, 0x09); FE ((yyvsp[-2].exp), 9, 3); O1 ((yyvsp[-4].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3188 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 174:
+#line 752 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x89); FE ((yyvsp[-2].exp), 9, 3); }
+#line 3194 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 175:
+#line 755 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x71, 0x09, (yyvsp[-4].regno)); FE ((yyvsp[-2].exp), 9, 3); }
+#line 3200 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 176:
+#line 758 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0x81); FE ((yyvsp[-2].exp), 9, 3); }
+#line 3206 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 177:
+#line 763 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xce); O1 ((yyvsp[-3].exp)); }
+#line 3212 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 178:
+#line 768 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x30); O2 ((yyvsp[0].exp)); }
+#line 3218 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 179:
+#line 771 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x30); F ((yyvsp[-3].regno), 5, 2); O2 ((yyvsp[0].exp)); }
+#line 3224 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 180:
+#line 773 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3230 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 181:
+#line 774 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-4].exp)))
+ { B1 (0xc9); SET_SA ((yyvsp[-4].exp)); O1 ((yyvsp[-4].exp)); O2 ((yyvsp[-1].exp)); }
+ else if (expr_is_sfr ((yyvsp[-4].exp)))
+ { B1 (0xcb); O1 ((yyvsp[-4].exp)); O2 ((yyvsp[-1].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3242 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 182:
+#line 782 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3248 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 183:
+#line 783 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-1].exp)))
+ { B1 (0xad); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); WA((yyvsp[-1].exp)); }
+ else if (expr_is_sfr ((yyvsp[-1].exp)))
+ { B1 (0xae); O1 ((yyvsp[-1].exp)); WA((yyvsp[-1].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3260 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 184:
+#line 791 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3266 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 185:
+#line 792 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_saddr ((yyvsp[-3].exp)))
+ { B1 (0xbd); SET_SA ((yyvsp[-3].exp)); O1 ((yyvsp[-3].exp)); WA((yyvsp[-3].exp)); }
+ else if (expr_is_sfr ((yyvsp[-3].exp)))
+ { B1 (0xbe); O1 ((yyvsp[-3].exp)); WA((yyvsp[-3].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3278 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 186:
+#line 801 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x11); F ((yyvsp[0].regno), 5, 2); }
+#line 3284 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 187:
+#line 804 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x10); F ((yyvsp[-2].regno), 5, 2); }
+#line 3290 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 188:
+#line 807 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xaf); O2 ((yyvsp[0].exp)); WA((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 3296 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 189:
+#line 810 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xbf); O2 ((yyvsp[-2].exp)); WA((yyvsp[-2].exp)); rl78_linkrelax_addr16 (); }
+#line 3302 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 190:
+#line 813 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa9); }
+#line 3308 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 191:
+#line 816 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xb9); }
+#line 3314 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 192:
+#line 819 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xaa); O1 ((yyvsp[-1].exp)); }
+#line 3320 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 193:
+#line 822 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xba); O1 ((yyvsp[-3].exp)); }
+#line 3326 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 194:
+#line 825 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xab); }
+#line 3332 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 195:
+#line 828 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xbb); }
+#line 3338 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 196:
+#line 831 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xac); O1 ((yyvsp[-1].exp)); }
+#line 3344 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 197:
+#line 834 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xbc); O1 ((yyvsp[-3].exp)); }
+#line 3350 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 198:
+#line 837 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x59); O2 ((yyvsp[-3].exp)); }
+#line 3356 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 199:
+#line 840 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x58); O2 ((yyvsp[-5].exp)); }
+#line 3362 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 200:
+#line 843 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x69); O2 ((yyvsp[-3].exp)); }
+#line 3368 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 201:
+#line 846 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x68); O2 ((yyvsp[-5].exp)); }
+#line 3374 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 202:
+#line 849 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x79); O2 ((yyvsp[-3].exp)); }
+#line 3380 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 203:
+#line 852 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x79, 0, 0); }
+#line 3386 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 204:
+#line 855 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x78); O2 ((yyvsp[-5].exp)); }
+#line 3392 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 205:
+#line 858 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0x78, 0, 0); }
+#line 3398 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 206:
+#line 860 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3404 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 207:
+#line 861 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xa8); O1 ((yyvsp[-2].exp)); WA((yyvsp[-2].exp));}
+#line 3410 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 208:
+#line 863 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3416 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 209:
+#line 864 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xa8, 0); }
+#line 3422 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 210:
+#line 866 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3428 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 211:
+#line 867 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xb8); O1 ((yyvsp[-4].exp)); WA((yyvsp[-4].exp)); }
+#line 3434 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 212:
+#line 869 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {NOT_ES}
+#line 3440 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 213:
+#line 870 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xb8, 0); }
+#line 3446 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 214:
+#line 872 "./config/rl78-parse.y" /* yacc.c:1661 */
+ {SA((yyvsp[0].exp))}
+#line 3452 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 215:
+#line 873 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xca); F ((yyvsp[-3].regno), 2, 2); SET_SA ((yyvsp[-1].exp)); O1 ((yyvsp[-1].exp)); WA((yyvsp[-1].exp)); }
+#line 3458 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 216:
+#line 876 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xcb); F ((yyvsp[-4].regno), 2, 2); O2 ((yyvsp[0].exp)); WA((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 3464 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 217:
+#line 879 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xcb, 0xf8); O2 ((yyvsp[0].exp)); }
+#line 3470 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 218:
+#line 882 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xbe, 0xf8); }
+#line 3476 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 219:
+#line 885 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0xae, 0xf8); }
+#line 3482 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 220:
+#line 888 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B3 (0xcb, 0xf8, 0xff); F ((yyvsp[-2].regno), 2, 2); }
+#line 3488 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 221:
+#line 893 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x00); }
+#line 3494 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 222:
+#line 898 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x71, 0xc0); }
+#line 3500 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 223:
+#line 903 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xc0); F ((yyvsp[0].regno), 5, 2); }
+#line 3506 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 224:
+#line 906 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xcd); }
+#line 3512 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 225:
+#line 909 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xc1); F ((yyvsp[0].regno), 5, 2); }
+#line 3518 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 226:
+#line 912 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xdd); }
+#line 3524 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 227:
+#line 917 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0xd7); }
+#line 3530 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 228:
+#line 920 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xfc); }
+#line 3536 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 229:
+#line 923 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xec); }
+#line 3542 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 230:
+#line 928 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xeb); }
+ }
+#line 3550 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 231:
+#line 933 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xdc); }
+ }
+#line 3558 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 232:
+#line 938 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xee); }
+ }
+#line 3566 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 233:
+#line 943 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xfe); }
+ }
+#line 3574 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 234:
+#line 948 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xdb); }
+ }
+#line 3582 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 235:
+#line 953 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 1))
+ { B2 (0x61, 0xfb);}
+ }
+#line 3590 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 236:
+#line 960 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 7))
+ { B2 (0x31, 0x0b); FE ((yyvsp[0].exp), 9, 3); }
+ }
+#line 3598 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 237:
+#line 965 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 15))
+ { B2 (0x31, 0x0f); FE ((yyvsp[0].exp), 8, 4); }
+ }
+#line 3606 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 238:
+#line 972 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xcf); }
+#line 3612 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 239:
+#line 975 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xdf); }
+#line 3618 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 240:
+#line 978 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xef); }
+#line 3624 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 241:
+#line 981 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xff); }
+#line 3630 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 242:
+#line 986 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 7))
+ { B2 (0x31, 0x09); FE ((yyvsp[0].exp), 9, 3); }
+ }
+#line 3638 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 243:
+#line 991 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 7))
+ { B2 (0x31, 0x08); FE ((yyvsp[0].exp), 9, 3); }
+ }
+#line 3646 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 244:
+#line 996 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 7))
+ { B2 (0x31, 0x07); FE ((yyvsp[0].exp), 9, 3); }
+ }
+#line 3654 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 245:
+#line 1001 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 15))
+ { B2 (0x31, 0x0d); FE ((yyvsp[0].exp), 8, 4); }
+ }
+#line 3662 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 246:
+#line 1006 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 15))
+ { B2 (0x31, 0x0c); FE ((yyvsp[0].exp), 8, 4); }
+ }
+#line 3670 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 247:
+#line 1013 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 7))
+ { B2 (0x31, 0x0a); FE ((yyvsp[0].exp), 9, 3); }
+ }
+#line 3678 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 248:
+#line 1018 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (check_expr_is_const ((yyvsp[0].exp), 1, 15))
+ { B2 (0x31, 0x0e); FE ((yyvsp[0].exp), 8, 4); }
+ }
+#line 3686 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 249:
+#line 1025 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xc8); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3692 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 250:
+#line 1028 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xe3); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3698 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 251:
+#line 1031 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xd8); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3704 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 252:
+#line 1034 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xf3); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3710 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 253:
+#line 1037 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xf8); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3716 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 254:
+#line 1040 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xe8); rl78_relax (RL78_RELAX_BRANCH, 0); }
+#line 3722 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 255:
+#line 1045 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xfd); }
+#line 3728 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 256:
+#line 1050 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) == 0) /* X */
+ { B1 (0x08); }
+ else
+ { B2 (0x61, 0x88); F ((yyvsp[0].regno), 13, 3); }
+ }
+#line 3738 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 257:
+#line 1057 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xaa); O2 ((yyvsp[0].exp)); rl78_linkrelax_addr16 (); }
+#line 3744 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 258:
+#line 1060 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xae); }
+#line 3750 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 259:
+#line 1063 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xaf); O1 ((yyvsp[-1].exp)); }
+#line 3756 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 260:
+#line 1066 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xac); }
+#line 3762 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 261:
+#line 1069 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xad); O1 ((yyvsp[-1].exp)); }
+#line 3768 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 262:
+#line 1072 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xb9); }
+#line 3774 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 263:
+#line 1075 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B2 (0x61, 0xa9); }
+#line 3780 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 264:
+#line 1078 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { if (expr_is_sfr ((yyvsp[0].exp)))
+ { B2 (0x61, 0xab); O1 ((yyvsp[0].exp)); }
+ else if (expr_is_saddr ((yyvsp[0].exp)))
+ { B2 (0x61, 0xa8); SET_SA ((yyvsp[0].exp)); O1 ((yyvsp[0].exp)); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+#line 3792 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 265:
+#line 1089 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { B1 (0x31); F ((yyvsp[0].regno), 5, 2); }
+#line 3798 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 267:
+#line 1099 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { rl78_prefix (0x11); }
+#line 3804 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 268:
+#line 1102 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; }
+#line 3810 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 269:
+#line 1103 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3816 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 270:
+#line 1104 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3822 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 271:
+#line 1105 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 3; }
+#line 3828 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 272:
+#line 1106 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 4; }
+#line 3834 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 273:
+#line 1107 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 5; }
+#line 3840 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 274:
+#line 1108 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 6; }
+#line 3846 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 275:
+#line 1109 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 7; }
+#line 3852 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 276:
+#line 1112 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; }
+#line 3858 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 277:
+#line 1113 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3864 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 278:
+#line 1114 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 3; }
+#line 3870 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 279:
+#line 1115 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 4; }
+#line 3876 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 280:
+#line 1116 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 5; }
+#line 3882 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 281:
+#line 1117 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 6; }
+#line 3888 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 282:
+#line 1118 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 7; }
+#line 3894 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 283:
+#line 1121 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; }
+#line 3900 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 284:
+#line 1122 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3906 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 285:
+#line 1123 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3912 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 286:
+#line 1124 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 3; }
+#line 3918 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 287:
+#line 1127 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3924 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 288:
+#line 1128 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3930 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 289:
+#line 1129 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 3; }
+#line 3936 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 290:
+#line 1132 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xf8; }
+#line 3942 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 291:
+#line 1133 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xf9; }
+#line 3948 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 292:
+#line 1134 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xfa; }
+#line 3954 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 293:
+#line 1135 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xfc; }
+#line 3960 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 294:
+#line 1136 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xfd; }
+#line 3966 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 295:
+#line 1137 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xfe; }
+#line 3972 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 296:
+#line 1138 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0xff; }
+#line 3978 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 297:
+#line 1144 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 3984 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 298:
+#line 1145 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x10; }
+#line 3990 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 299:
+#line 1146 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x20; }
+#line 3996 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 300:
+#line 1147 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x30; }
+#line 4002 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 301:
+#line 1148 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x40; }
+#line 4008 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 302:
+#line 1149 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x50; }
+#line 4014 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 303:
+#line 1150 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x60; }
+#line 4020 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 304:
+#line 1151 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x70; }
+#line 4026 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 305:
+#line 1154 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 4032 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 306:
+#line 1155 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x20; }
+#line 4038 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 307:
+#line 1156 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x40; }
+#line 4044 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 308:
+#line 1159 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x05; rl78_bit_insn = 1; }
+#line 4050 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 309:
+#line 1160 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x06; rl78_bit_insn = 1; }
+#line 4056 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 310:
+#line 1161 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x07; rl78_bit_insn = 1; }
+#line 4062 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 311:
+#line 1164 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x02; rl78_bit_insn = 1; rl78_linkrelax_branch (); }
+#line 4068 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 312:
+#line 1165 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x04; rl78_bit_insn = 1; rl78_linkrelax_branch (); }
+#line 4074 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 313:
+#line 1166 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; rl78_bit_insn = 1; }
+#line 4080 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 314:
+#line 1169 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; rl78_bit_insn = 1; }
+#line 4086 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 315:
+#line 1170 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; rl78_bit_insn = 1; }
+#line 4092 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 316:
+#line 1173 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 4098 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 317:
+#line 1174 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x10; }
+#line 4104 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 318:
+#line 1177 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 4110 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 319:
+#line 1178 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x10; }
+#line 4116 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 320:
+#line 1181 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 4122 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 321:
+#line 1182 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x10; }
+#line 4128 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 322:
+#line 1185 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x00; }
+#line 4134 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 323:
+#line 1186 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0x10; }
+#line 4140 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 324:
+#line 1189 "./config/rl78-parse.y" /* yacc.c:1661 */
+ { rl78_bit_insn = 1; }
+#line 4146 "rl78-parse.c" /* yacc.c:1661 */
+ break;
+
+
+#line 4150 "rl78-parse.c" /* yacc.c:1661 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+ that yytoken be updated with the new translation. We take the
+ approach of translating immediately before every use of yytoken.
+ One alternative is translating here after every semantic action,
+ but that translation would be missed if the semantic action invokes
+ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
+ incorrect destructor might then be invoked immediately. In the
+ case of YYERROR or YYBACKUP, subsequent parser actions might lead
+ to an incorrect destructor call or verbose syntax error message
+ before the lookahead is translated. */
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error. |
+`--------------------------------------*/
+yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+ yyssp, yytoken)
+ {
+ char const *yymsgp = YY_("syntax error");
+ int yysyntax_error_status;
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ if (yysyntax_error_status == 0)
+ yymsgp = yymsg;
+ else if (yysyntax_error_status == 1)
+ {
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+ if (!yymsg)
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ yysyntax_error_status = 2;
+ }
+ else
+ {
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ yymsgp = yymsg;
+ }
+ }
+ yyerror (yymsgp);
+ if (yysyntax_error_status == 2)
+ goto yyexhaustedlab;
+ }
+# undef YYSYNTAX_ERROR
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEMPTY)
+ {
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ }
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ return yyresult;
+}
+#line 1192 "./config/rl78-parse.y" /* yacc.c:1906 */
+
+/* ====================================================================== */
+
+static struct
+{
+ const char * string;
+ int token;
+ int val;
+}
+token_table[] =
+{
+ { "r0", X, 0 },
+ { "r1", A, 1 },
+ { "r2", C, 2 },
+ { "r3", B, 3 },
+ { "r4", E, 4 },
+ { "r5", D, 5 },
+ { "r6", L, 6 },
+ { "r7", H, 7 },
+ { "x", X, 0 },
+ { "a", A, 1 },
+ { "c", C, 2 },
+ { "b", B, 3 },
+ { "e", E, 4 },
+ { "d", D, 5 },
+ { "l", L, 6 },
+ { "h", H, 7 },
+
+ { "rp0", AX, 0 },
+ { "rp1", BC, 1 },
+ { "rp2", DE, 2 },
+ { "rp3", HL, 3 },
+ { "ax", AX, 0 },
+ { "bc", BC, 1 },
+ { "de", DE, 2 },
+ { "hl", HL, 3 },
+
+ { "RB0", RB0, 0 },
+ { "RB1", RB1, 1 },
+ { "RB2", RB2, 2 },
+ { "RB3", RB3, 3 },
+
+ { "sp", SP, 0 },
+ { "cy", CY, 0 },
+
+ { "spl", SPL, 0xf8 },
+ { "sph", SPH, 0xf9 },
+ { "psw", PSW, 0xfa },
+ { "cs", CS, 0xfc },
+ { "es", ES, 0xfd },
+ { "pmc", PMC, 0xfe },
+ { "mem", MEM, 0xff },
+
+ { ".s", DOT_S, 0 },
+ { ".b", DOT_B, 0 },
+ { ".w", DOT_W, 0 },
+ { ".l", DOT_L, 0 },
+ { ".a", DOT_A , 0},
+ { ".ub", DOT_UB, 0 },
+ { ".uw", DOT_UW , 0},
+
+ { "c", FLAG, 0 },
+ { "z", FLAG, 1 },
+ { "s", FLAG, 2 },
+ { "o", FLAG, 3 },
+ { "i", FLAG, 8 },
+ { "u", FLAG, 9 },
+
+#define OPC(x) { #x, x, IS_OPCODE }
+
+ OPC(ADD),
+ OPC(ADDC),
+ OPC(ADDW),
+ { "and", AND_, IS_OPCODE },
+ OPC(AND1),
+ OPC(BC),
+ OPC(BF),
+ OPC(BH),
+ OPC(BNC),
+ OPC(BNH),
+ OPC(BNZ),
+ OPC(BR),
+ OPC(BRK),
+ OPC(BRK1),
+ OPC(BT),
+ OPC(BTCLR),
+ OPC(BZ),
+ OPC(CALL),
+ OPC(CALLT),
+ OPC(CLR1),
+ OPC(CLRB),
+ OPC(CLRW),
+ OPC(CMP),
+ OPC(CMP0),
+ OPC(CMPS),
+ OPC(CMPW),
+ OPC(DEC),
+ OPC(DECW),
+ OPC(DI),
+ OPC(DIVHU),
+ OPC(DIVWU),
+ OPC(EI),
+ OPC(HALT),
+ OPC(INC),
+ OPC(INCW),
+ OPC(MACH),
+ OPC(MACHU),
+ OPC(MOV),
+ OPC(MOV1),
+ OPC(MOVS),
+ OPC(MOVW),
+ OPC(MULH),
+ OPC(MULHU),
+ OPC(MULU),
+ OPC(NOP),
+ OPC(NOT1),
+ OPC(ONEB),
+ OPC(ONEW),
+ OPC(OR),
+ OPC(OR1),
+ OPC(POP),
+ OPC(PUSH),
+ OPC(RET),
+ OPC(RETI),
+ OPC(RETB),
+ OPC(ROL),
+ OPC(ROLC),
+ OPC(ROLWC),
+ OPC(ROR),
+ OPC(RORC),
+ OPC(SAR),
+ OPC(SARW),
+ OPC(SEL),
+ OPC(SET1),
+ OPC(SHL),
+ OPC(SHLW),
+ OPC(SHR),
+ OPC(SHRW),
+ OPC(SKC),
+ OPC(SKH),
+ OPC(SKNC),
+ OPC(SKNH),
+ OPC(SKNZ),
+ OPC(SKZ),
+ OPC(STOP),
+ OPC(SUB),
+ OPC(SUBC),
+ OPC(SUBW),
+ OPC(XCH),
+ OPC(XCHW),
+ OPC(XOR),
+ OPC(XOR1),
+};
+
+#define NUM_TOKENS (sizeof (token_table) / sizeof (token_table[0]))
+
+void
+rl78_lex_init (char * beginning, char * ending)
+{
+ rl78_init_start = beginning;
+ rl78_lex_start = beginning;
+ rl78_lex_end = ending;
+ rl78_in_brackets = 0;
+ rl78_last_token = 0;
+
+ rl78_bit_insn = 0;
+
+ setbuf (stdout, 0);
+}
+
+/* Return a pointer to the '.' in a bit index expression (like
+ foo.5), or NULL if none is found. */
+static char *
+find_bit_index (char *tok)
+{
+ char *last_dot = NULL;
+ char *last_digit = NULL;
+ while (*tok && *tok != ',')
+ {
+ if (*tok == '.')
+ {
+ last_dot = tok;
+ last_digit = NULL;
+ }
+ else if (*tok >= '0' && *tok <= '7'
+ && last_dot != NULL
+ && last_digit == NULL)
+ {
+ last_digit = tok;
+ }
+ else if (ISSPACE (*tok))
+ {
+ /* skip */
+ }
+ else
+ {
+ last_dot = NULL;
+ last_digit = NULL;
+ }
+ tok ++;
+ }
+ if (last_dot != NULL
+ && last_digit != NULL)
+ return last_dot;
+ return NULL;
+}
+
+static int
+rl78_lex (void)
+{
+ /*unsigned int ci;*/
+ char * save_input_pointer;
+ char * bit = NULL;
+
+ while (ISSPACE (*rl78_lex_start)
+ && rl78_lex_start != rl78_lex_end)
+ rl78_lex_start ++;
+
+ rl78_last_exp_start = rl78_lex_start;
+
+ if (rl78_lex_start == rl78_lex_end)
+ return 0;
+
+ if (ISALPHA (*rl78_lex_start)
+ || (*rl78_lex_start == '.' && ISALPHA (rl78_lex_start[1])))
+ {
+ unsigned int i;
+ char * e;
+ char save;
+
+ for (e = rl78_lex_start + 1;
+ e < rl78_lex_end && ISALNUM (*e);
+ e ++)
+ ;
+ save = *e;
+ *e = 0;
+
+ for (i = 0; i < NUM_TOKENS; i++)
+ if (strcasecmp (rl78_lex_start, token_table[i].string) == 0
+ && !(token_table[i].val == IS_OPCODE && rl78_last_token != 0)
+ && !(token_table[i].token == FLAG && !need_flag))
+ {
+ rl78_lval.regno = token_table[i].val;
+ *e = save;
+ rl78_lex_start = e;
+ rl78_last_token = token_table[i].token;
+ return token_table[i].token;
+ }
+ *e = save;
+ }
+
+ if (rl78_last_token == 0)
+ {
+ rl78_last_token = UNKNOWN_OPCODE;
+ return UNKNOWN_OPCODE;
+ }
+
+ if (rl78_last_token == UNKNOWN_OPCODE)
+ return 0;
+
+ if (*rl78_lex_start == '[')
+ rl78_in_brackets = 1;
+ if (*rl78_lex_start == ']')
+ rl78_in_brackets = 0;
+
+ /* '.' is funny - the syntax includes it for bitfields, but only for
+ bitfields. We check for it specially so we can allow labels
+ with '.' in them. */
+
+ if (rl78_bit_insn
+ && *rl78_lex_start == '.'
+ && find_bit_index (rl78_lex_start) == rl78_lex_start)
+ {
+ rl78_last_token = *rl78_lex_start;
+ return *rl78_lex_start ++;
+ }
+
+ if ((rl78_in_brackets && *rl78_lex_start == '+')
+ || strchr ("[],#!$:", *rl78_lex_start))
+ {
+ rl78_last_token = *rl78_lex_start;
+ return *rl78_lex_start ++;
+ }
+
+ /* Again, '.' is funny. Look for '.<digit>' at the end of the line
+ or before a comma, which is a bitfield, not an expression. */
+
+ if (rl78_bit_insn)
+ {
+ bit = find_bit_index (rl78_lex_start);
+ if (bit)
+ *bit = 0;
+ else
+ bit = NULL;
+ }
+
+ save_input_pointer = input_line_pointer;
+ input_line_pointer = rl78_lex_start;
+ rl78_lval.exp.X_md = 0;
+ expression (&rl78_lval.exp);
+
+ if (bit)
+ *bit = '.';
+
+ rl78_lex_start = input_line_pointer;
+ input_line_pointer = save_input_pointer;
+ rl78_last_token = EXPR;
+ return EXPR;
+}
+
+int
+rl78_error (const char * str)
+{
+ int len;
+
+ len = rl78_last_exp_start - rl78_init_start;
+
+ as_bad ("%s", rl78_init_start);
+ as_bad ("%*s^ %s", len, "", str);
+ return 0;
+}
+
+static int
+expr_is_sfr (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 0;
+
+ v = exp.X_add_number;
+ if (0xFFF00 <= v && v <= 0xFFFFF)
+ return 1;
+ return 0;
+}
+
+static int
+expr_is_saddr (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 1;
+
+ v = exp.X_add_number;
+ if (0xFFE20 <= v && v <= 0xFFF1F)
+ return 1;
+ return 0;
+}
+
+static int
+expr_is_word_aligned (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 1;
+
+ v = exp.X_add_number;
+ if (v & 1)
+ return 0;
+ return 1;
+
+}
+
+static void
+check_expr_is_bit_index (expressionS exp)
+{
+ int val;
+
+ if (exp.X_op != O_constant)
+ {
+ rl78_error (_("bit index must be a constant"));
+ return;
+ }
+ val = exp.X_add_number;
+
+ if (val < 0 || val > 7)
+ rl78_error (_("rtsd size must be 0..7"));
+}
+
+static int
+exp_val (expressionS exp)
+{
+ if (exp.X_op != O_constant)
+ {
+ rl78_error (_("constant expected"));
+ return 0;
+ }
+ return exp.X_add_number;
+}
+
+static int
+check_expr_is_const (expressionS e, int vmin, int vmax)
+{
+ static char buf[100];
+ if (e.X_op != O_constant
+ || e.X_add_number < vmin
+ || e.X_add_number > vmax)
+ {
+ if (vmin == vmax)
+ sprintf (buf, "%d expected here", vmin);
+ else
+ sprintf (buf, "%d..%d expected here", vmin, vmax);
+ rl78_error(buf);
+ return 0;
+ }
+ return 1;
+}
diff --git a/gas/rl78-parse.h b/gas/rl78-parse.h
new file mode 100644
index 0000000..aac72f4
--- /dev/null
+++ b/gas/rl78-parse.h
@@ -0,0 +1,307 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison interface for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+#ifndef YY_RL78_RL_PARSE_H_INCLUDED
+# define YY_RL78_RL_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int rl78_debug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ A = 258,
+ X = 259,
+ B = 260,
+ C = 261,
+ D = 262,
+ E = 263,
+ H = 264,
+ L = 265,
+ AX = 266,
+ BC = 267,
+ DE = 268,
+ HL = 269,
+ SPL = 270,
+ SPH = 271,
+ PSW = 272,
+ CS = 273,
+ ES = 274,
+ PMC = 275,
+ MEM = 276,
+ FLAG = 277,
+ SP = 278,
+ CY = 279,
+ RB0 = 280,
+ RB1 = 281,
+ RB2 = 282,
+ RB3 = 283,
+ EXPR = 284,
+ UNKNOWN_OPCODE = 285,
+ IS_OPCODE = 286,
+ DOT_S = 287,
+ DOT_B = 288,
+ DOT_W = 289,
+ DOT_L = 290,
+ DOT_A = 291,
+ DOT_UB = 292,
+ DOT_UW = 293,
+ ADD = 294,
+ ADDC = 295,
+ ADDW = 296,
+ AND_ = 297,
+ AND1 = 298,
+ BF = 299,
+ BH = 300,
+ BNC = 301,
+ BNH = 302,
+ BNZ = 303,
+ BR = 304,
+ BRK = 305,
+ BRK1 = 306,
+ BT = 307,
+ BTCLR = 308,
+ BZ = 309,
+ CALL = 310,
+ CALLT = 311,
+ CLR1 = 312,
+ CLRB = 313,
+ CLRW = 314,
+ CMP = 315,
+ CMP0 = 316,
+ CMPS = 317,
+ CMPW = 318,
+ DEC = 319,
+ DECW = 320,
+ DI = 321,
+ DIVHU = 322,
+ DIVWU = 323,
+ EI = 324,
+ HALT = 325,
+ INC = 326,
+ INCW = 327,
+ MACH = 328,
+ MACHU = 329,
+ MOV = 330,
+ MOV1 = 331,
+ MOVS = 332,
+ MOVW = 333,
+ MULH = 334,
+ MULHU = 335,
+ MULU = 336,
+ NOP = 337,
+ NOT1 = 338,
+ ONEB = 339,
+ ONEW = 340,
+ OR = 341,
+ OR1 = 342,
+ POP = 343,
+ PUSH = 344,
+ RET = 345,
+ RETI = 346,
+ RETB = 347,
+ ROL = 348,
+ ROLC = 349,
+ ROLWC = 350,
+ ROR = 351,
+ RORC = 352,
+ SAR = 353,
+ SARW = 354,
+ SEL = 355,
+ SET1 = 356,
+ SHL = 357,
+ SHLW = 358,
+ SHR = 359,
+ SHRW = 360,
+ SKC = 361,
+ SKH = 362,
+ SKNC = 363,
+ SKNH = 364,
+ SKNZ = 365,
+ SKZ = 366,
+ STOP = 367,
+ SUB = 368,
+ SUBC = 369,
+ SUBW = 370,
+ XCH = 371,
+ XCHW = 372,
+ XOR = 373,
+ XOR1 = 374
+ };
+#endif
+/* Tokens. */
+#define A 258
+#define X 259
+#define B 260
+#define C 261
+#define D 262
+#define E 263
+#define H 264
+#define L 265
+#define AX 266
+#define BC 267
+#define DE 268
+#define HL 269
+#define SPL 270
+#define SPH 271
+#define PSW 272
+#define CS 273
+#define ES 274
+#define PMC 275
+#define MEM 276
+#define FLAG 277
+#define SP 278
+#define CY 279
+#define RB0 280
+#define RB1 281
+#define RB2 282
+#define RB3 283
+#define EXPR 284
+#define UNKNOWN_OPCODE 285
+#define IS_OPCODE 286
+#define DOT_S 287
+#define DOT_B 288
+#define DOT_W 289
+#define DOT_L 290
+#define DOT_A 291
+#define DOT_UB 292
+#define DOT_UW 293
+#define ADD 294
+#define ADDC 295
+#define ADDW 296
+#define AND_ 297
+#define AND1 298
+#define BF 299
+#define BH 300
+#define BNC 301
+#define BNH 302
+#define BNZ 303
+#define BR 304
+#define BRK 305
+#define BRK1 306
+#define BT 307
+#define BTCLR 308
+#define BZ 309
+#define CALL 310
+#define CALLT 311
+#define CLR1 312
+#define CLRB 313
+#define CLRW 314
+#define CMP 315
+#define CMP0 316
+#define CMPS 317
+#define CMPW 318
+#define DEC 319
+#define DECW 320
+#define DI 321
+#define DIVHU 322
+#define DIVWU 323
+#define EI 324
+#define HALT 325
+#define INC 326
+#define INCW 327
+#define MACH 328
+#define MACHU 329
+#define MOV 330
+#define MOV1 331
+#define MOVS 332
+#define MOVW 333
+#define MULH 334
+#define MULHU 335
+#define MULU 336
+#define NOP 337
+#define NOT1 338
+#define ONEB 339
+#define ONEW 340
+#define OR 341
+#define OR1 342
+#define POP 343
+#define PUSH 344
+#define RET 345
+#define RETI 346
+#define RETB 347
+#define ROL 348
+#define ROLC 349
+#define ROLWC 350
+#define ROR 351
+#define RORC 352
+#define SAR 353
+#define SARW 354
+#define SEL 355
+#define SET1 356
+#define SHL 357
+#define SHLW 358
+#define SHR 359
+#define SHRW 360
+#define SKC 361
+#define SKH 362
+#define SKNC 363
+#define SKNH 364
+#define SKNZ 365
+#define SKZ 366
+#define STOP 367
+#define SUB 368
+#define SUBC 369
+#define SUBW 370
+#define XCH 371
+#define XCHW 372
+#define XOR 373
+#define XOR1 374
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 144 "./config/rl78-parse.y" /* yacc.c:1915 */
+
+ int regno;
+ expressionS exp;
+
+#line 297 "rl78-parse.h" /* yacc.c:1915 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE rl78_lval;
+
+int rl78_parse (void);
+
+#endif /* !YY_RL78_RL_PARSE_H_INCLUDED */
diff --git a/gas/rx-parse.c b/gas/rx-parse.c
new file mode 100644
index 0000000..74e1c59
--- /dev/null
+++ b/gas/rx-parse.c
@@ -0,0 +1,4678 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison implementation for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "3.0"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Push parsers. */
+#define YYPUSH 0
+
+/* Pull parsers. */
+#define YYPULL 1
+
+
+/* Substitute the variable and function names. */
+#define yyparse rx_parse
+#define yylex rx_lex
+#define yyerror rx_error
+#define yydebug rx_debug
+#define yynerrs rx_nerrs
+
+#define yylval rx_lval
+#define yychar rx_char
+
+/* Copy the first part of user declarations. */
+#line 20 "./config/rx-parse.y" /* yacc.c:339 */
+
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "rx-defs.h"
+
+static int rx_lex (void);
+
+#define COND_EQ 0
+#define COND_NE 1
+
+#define MEMEX 0x06
+
+#define BSIZE 0
+#define WSIZE 1
+#define LSIZE 2
+
+/* .sb .sw .l .uw */
+static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE };
+
+/* Ok, here are the rules for using these macros...
+
+ B*() is used to specify the base opcode bytes. Fields to be filled
+ in later, leave zero. Call this first.
+
+ F() and FE() are used to fill in fields within the base opcode bytes. You MUST
+ call B*() before any F() or FE().
+
+ [UN]*O*(), PC*() appends operands to the end of the opcode. You
+ must call P() and B*() before any of these, so that the fixups
+ have the right byte location.
+ O = signed, UO = unsigned, NO = negated, PC = pcrel
+
+ IMM() adds an immediate and fills in the field for it.
+ NIMM() same, but negates the immediate.
+ NBIMM() same, but negates the immediate, for sbb.
+ DSP() adds a displacement, and fills in the field for it.
+
+ Note that order is significant for the O, IMM, and DSP macros, as
+ they append their data to the operand buffer in the order that you
+ call them.
+
+ Use "disp" for displacements whenever possible; this handles the
+ "0" case properly. */
+
+#define B1(b1) rx_base1 (b1)
+#define B2(b1, b2) rx_base2 (b1, b2)
+#define B3(b1, b2, b3) rx_base3 (b1, b2, b3)
+#define B4(b1, b2, b3, b4) rx_base4 (b1, b2, b3, b4)
+
+/* POS is bits from the MSB of the first byte to the LSB of the last byte. */
+#define F(val,pos,sz) rx_field (val, pos, sz)
+#define FE(exp,pos,sz) rx_field (exp_val (exp), pos, sz);
+
+#define O1(v) rx_op (v, 1, RXREL_SIGNED); rx_range (v, -128, 255)
+#define O2(v) rx_op (v, 2, RXREL_SIGNED); rx_range (v, -32768, 65536)
+#define O3(v) rx_op (v, 3, RXREL_SIGNED); rx_range (v, -8388608, 16777216)
+#define O4(v) rx_op (v, 4, RXREL_SIGNED)
+
+#define UO1(v) rx_op (v, 1, RXREL_UNSIGNED); rx_range (v, 0, 255)
+#define UO2(v) rx_op (v, 2, RXREL_UNSIGNED); rx_range (v, 0, 65536)
+#define UO3(v) rx_op (v, 3, RXREL_UNSIGNED); rx_range (v, 0, 16777216)
+#define UO4(v) rx_op (v, 4, RXREL_UNSIGNED)
+
+#define NO1(v) rx_op (v, 1, RXREL_NEGATIVE)
+#define NO2(v) rx_op (v, 2, RXREL_NEGATIVE)
+#define NO3(v) rx_op (v, 3, RXREL_NEGATIVE)
+#define NO4(v) rx_op (v, 4, RXREL_NEGATIVE)
+
+#define PC1(v) rx_op (v, 1, RXREL_PCREL)
+#define PC2(v) rx_op (v, 2, RXREL_PCREL)
+#define PC3(v) rx_op (v, 3, RXREL_PCREL)
+
+#define IMM_(v,pos,size) F (immediate (v, RXREL_SIGNED, pos, size), pos, 2); \
+ if (v.X_op != O_constant && v.X_op != O_big) rx_linkrelax_imm (pos)
+#define IMM(v,pos) IMM_ (v, pos, 32)
+#define IMMW(v,pos) IMM_ (v, pos, 16); rx_range (v, -32768, 65536)
+#define IMMB(v,pos) IMM_ (v, pos, 8); rx_range (v, -128, 255)
+#define NIMM(v,pos) F (immediate (v, RXREL_NEGATIVE, pos, 32), pos, 2)
+#define NBIMM(v,pos) F (immediate (v, RXREL_NEGATIVE_BORROW, pos, 32), pos, 2)
+#define DSP(v,pos,msz) if (!v.X_md) rx_relax (RX_RELAX_DISP, pos); \
+ else rx_linkrelax_dsp (pos); \
+ F (displacement (v, msz), pos, 2)
+
+#define id24(a,b2,b3) B3 (0xfb + a, b2, b3)
+
+static void rx_check_float_support (void);
+static int rx_intop (expressionS, int, int);
+static int rx_uintop (expressionS, int);
+static int rx_disp3op (expressionS);
+static int rx_disp5op (expressionS *, int);
+static int rx_disp5op0 (expressionS *, int);
+static int exp_val (expressionS exp);
+static expressionS zero_expr (void);
+static int immediate (expressionS, int, int, int);
+static int displacement (expressionS, int);
+static void rtsd_immediate (expressionS);
+static void rx_range (expressionS, int, int);
+static void rx_check_v2 (void);
+
+static int need_flag = 0;
+static int rx_in_brackets = 0;
+static int rx_last_token = 0;
+static char * rx_init_start;
+static char * rx_last_exp_start = 0;
+static int sub_op;
+static int sub_op2;
+
+#define YYDEBUG 1
+#define YYERROR_VERBOSE 1
+
+
+#line 187 "rx-parse.c" /* yacc.c:339 */
+
+# ifndef YY_NULL
+# if defined __cplusplus && 201103L <= __cplusplus
+# define YY_NULL nullptr
+# else
+# define YY_NULL 0
+# endif
+# endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* In a future release of Bison, this section will be replaced
+ by #include "y.tab.h". */
+#ifndef YY_RX_RX_PARSE_H_INCLUDED
+# define YY_RX_RX_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int rx_debug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ REG = 258,
+ FLAG = 259,
+ CREG = 260,
+ ACC = 261,
+ EXPR = 262,
+ UNKNOWN_OPCODE = 263,
+ IS_OPCODE = 264,
+ DOT_S = 265,
+ DOT_B = 266,
+ DOT_W = 267,
+ DOT_L = 268,
+ DOT_A = 269,
+ DOT_UB = 270,
+ DOT_UW = 271,
+ ABS = 272,
+ ADC = 273,
+ ADD = 274,
+ AND_ = 275,
+ BCLR = 276,
+ BCND = 277,
+ BMCND = 278,
+ BNOT = 279,
+ BRA = 280,
+ BRK = 281,
+ BSET = 282,
+ BSR = 283,
+ BTST = 284,
+ CLRPSW = 285,
+ CMP = 286,
+ DBT = 287,
+ DIV = 288,
+ DIVU = 289,
+ EDIV = 290,
+ EDIVU = 291,
+ EMACA = 292,
+ EMSBA = 293,
+ EMUL = 294,
+ EMULA = 295,
+ EMULU = 296,
+ FADD = 297,
+ FCMP = 298,
+ FDIV = 299,
+ FMUL = 300,
+ FREIT = 301,
+ FSUB = 302,
+ FSQRT = 303,
+ FTOI = 304,
+ FTOU = 305,
+ INT = 306,
+ ITOF = 307,
+ JMP = 308,
+ JSR = 309,
+ MACHI = 310,
+ MACLH = 311,
+ MACLO = 312,
+ MAX = 313,
+ MIN = 314,
+ MOV = 315,
+ MOVCO = 316,
+ MOVLI = 317,
+ MOVU = 318,
+ MSBHI = 319,
+ MSBLH = 320,
+ MSBLO = 321,
+ MUL = 322,
+ MULHI = 323,
+ MULLH = 324,
+ MULLO = 325,
+ MULU = 326,
+ MVFACHI = 327,
+ MVFACGU = 328,
+ MVFACMI = 329,
+ MVFACLO = 330,
+ MVFC = 331,
+ MVTACGU = 332,
+ MVTACHI = 333,
+ MVTACLO = 334,
+ MVTC = 335,
+ MVTIPL = 336,
+ NEG = 337,
+ NOP = 338,
+ NOT = 339,
+ OR = 340,
+ POP = 341,
+ POPC = 342,
+ POPM = 343,
+ PUSH = 344,
+ PUSHA = 345,
+ PUSHC = 346,
+ PUSHM = 347,
+ RACL = 348,
+ RACW = 349,
+ RDACL = 350,
+ RDACW = 351,
+ REIT = 352,
+ REVL = 353,
+ REVW = 354,
+ RMPA = 355,
+ ROLC = 356,
+ RORC = 357,
+ ROTL = 358,
+ ROTR = 359,
+ ROUND = 360,
+ RTE = 361,
+ RTFI = 362,
+ RTS = 363,
+ RTSD = 364,
+ SAT = 365,
+ SATR = 366,
+ SBB = 367,
+ SCCND = 368,
+ SCMPU = 369,
+ SETPSW = 370,
+ SHAR = 371,
+ SHLL = 372,
+ SHLR = 373,
+ SMOVB = 374,
+ SMOVF = 375,
+ SMOVU = 376,
+ SSTR = 377,
+ STNZ = 378,
+ STOP = 379,
+ STZ = 380,
+ SUB = 381,
+ SUNTIL = 382,
+ SWHILE = 383,
+ TST = 384,
+ UTOF = 385,
+ WAIT = 386,
+ XCHG = 387,
+ XOR = 388
+ };
+#endif
+/* Tokens. */
+#define REG 258
+#define FLAG 259
+#define CREG 260
+#define ACC 261
+#define EXPR 262
+#define UNKNOWN_OPCODE 263
+#define IS_OPCODE 264
+#define DOT_S 265
+#define DOT_B 266
+#define DOT_W 267
+#define DOT_L 268
+#define DOT_A 269
+#define DOT_UB 270
+#define DOT_UW 271
+#define ABS 272
+#define ADC 273
+#define ADD 274
+#define AND_ 275
+#define BCLR 276
+#define BCND 277
+#define BMCND 278
+#define BNOT 279
+#define BRA 280
+#define BRK 281
+#define BSET 282
+#define BSR 283
+#define BTST 284
+#define CLRPSW 285
+#define CMP 286
+#define DBT 287
+#define DIV 288
+#define DIVU 289
+#define EDIV 290
+#define EDIVU 291
+#define EMACA 292
+#define EMSBA 293
+#define EMUL 294
+#define EMULA 295
+#define EMULU 296
+#define FADD 297
+#define FCMP 298
+#define FDIV 299
+#define FMUL 300
+#define FREIT 301
+#define FSUB 302
+#define FSQRT 303
+#define FTOI 304
+#define FTOU 305
+#define INT 306
+#define ITOF 307
+#define JMP 308
+#define JSR 309
+#define MACHI 310
+#define MACLH 311
+#define MACLO 312
+#define MAX 313
+#define MIN 314
+#define MOV 315
+#define MOVCO 316
+#define MOVLI 317
+#define MOVU 318
+#define MSBHI 319
+#define MSBLH 320
+#define MSBLO 321
+#define MUL 322
+#define MULHI 323
+#define MULLH 324
+#define MULLO 325
+#define MULU 326
+#define MVFACHI 327
+#define MVFACGU 328
+#define MVFACMI 329
+#define MVFACLO 330
+#define MVFC 331
+#define MVTACGU 332
+#define MVTACHI 333
+#define MVTACLO 334
+#define MVTC 335
+#define MVTIPL 336
+#define NEG 337
+#define NOP 338
+#define NOT 339
+#define OR 340
+#define POP 341
+#define POPC 342
+#define POPM 343
+#define PUSH 344
+#define PUSHA 345
+#define PUSHC 346
+#define PUSHM 347
+#define RACL 348
+#define RACW 349
+#define RDACL 350
+#define RDACW 351
+#define REIT 352
+#define REVL 353
+#define REVW 354
+#define RMPA 355
+#define ROLC 356
+#define RORC 357
+#define ROTL 358
+#define ROTR 359
+#define ROUND 360
+#define RTE 361
+#define RTFI 362
+#define RTS 363
+#define RTSD 364
+#define SAT 365
+#define SATR 366
+#define SBB 367
+#define SCCND 368
+#define SCMPU 369
+#define SETPSW 370
+#define SHAR 371
+#define SHLL 372
+#define SHLR 373
+#define SMOVB 374
+#define SMOVF 375
+#define SMOVU 376
+#define SSTR 377
+#define STNZ 378
+#define STOP 379
+#define STZ 380
+#define SUB 381
+#define SUNTIL 382
+#define SWHILE 383
+#define TST 384
+#define UTOF 385
+#define WAIT 386
+#define XCHG 387
+#define XOR 388
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 135 "./config/rx-parse.y" /* yacc.c:355 */
+
+ int regno;
+ expressionS exp;
+
+#line 498 "rx-parse.c" /* yacc.c:355 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE rx_lval;
+
+int rx_parse (void);
+
+#endif /* !YY_RX_RX_PARSE_H_INCLUDED */
+
+/* Copy the second part of user declarations. */
+
+#line 513 "rx-parse.c" /* yacc.c:358 */
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#else
+typedef signed char yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if defined YYENABLE_NLS && YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(Msgid) dgettext ("bison-runtime", Msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(Msgid) Msgid
+# endif
+#endif
+
+#ifndef __attribute__
+/* This feature is available in gcc versions 2.5 and later. */
+# if (! defined __GNUC__ || __GNUC__ < 2 \
+ || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
+# define __attribute__(Spec) /* empty */
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(E) ((void) (E))
+#else
+# define YYUSE(E) /* empty */
+#endif
+
+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
+ _Pragma ("GCC diagnostic push") \
+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
+ _Pragma ("GCC diagnostic pop")
+#else
+# define YY_INITIAL_VALUE(Value) Value
+#endif
+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
+#endif
+#ifndef YY_INITIAL_VALUE
+# define YY_INITIAL_VALUE(Value) /* Nothing. */
+#endif
+
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+ /* Use EXIT_SUCCESS as a witness for stdlib.h. */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's 'empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined EXIT_SUCCESS \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef EXIT_SUCCESS
+# define EXIT_SUCCESS 0
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined EXIT_SUCCESS
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined EXIT_SUCCESS
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss_alloc;
+ YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+# define YYCOPY_NEEDED 1
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
+ Stack = &yyptr->Stack_alloc; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from SRC to DST. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(Dst, Src, Count) \
+ __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src)))
+# else
+# define YYCOPY(Dst, Src, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (Dst)[yyi] = (Src)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 255
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 780
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 140
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 76
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 294
+/* YYNSTATES -- Number of states. */
+#define YYNSTATES 760
+
+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
+ by yylex, with out-of-bounds checking. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 388
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, without out-of-bounds checking. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 134, 2, 2, 2, 2,
+ 2, 2, 2, 139, 135, 138, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 136, 2, 137, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
+ 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+ 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
+ 115, 116, 117, 118, 119, 120, 121, 122, 123, 124,
+ 125, 126, 127, 128, 129, 130, 131, 132, 133
+};
+
+#if YYDEBUG
+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 178, 178, 183, 186, 189, 192, 197, 212, 215,
+ 220, 229, 234, 242, 245, 250, 252, 254, 259, 277,
+ 280, 283, 286, 294, 300, 308, 317, 322, 325, 330,
+ 335, 338, 346, 353, 361, 367, 373, 379, 385, 393,
+ 403, 408, 408, 409, 409, 410, 410, 414, 427, 440,
+ 445, 450, 452, 457, 462, 464, 466, 471, 476, 481,
+ 491, 501, 503, 508, 510, 512, 514, 519, 521, 523,
+ 525, 530, 532, 534, 539, 544, 546, 548, 550, 555,
+ 561, 569, 583, 588, 593, 598, 603, 608, 610, 612,
+ 617, 622, 622, 623, 623, 624, 624, 625, 625, 626,
+ 626, 627, 627, 628, 628, 629, 629, 630, 630, 631,
+ 631, 632, 632, 633, 633, 634, 634, 635, 635, 636,
+ 636, 640, 640, 641, 641, 642, 642, 643, 643, 644,
+ 644, 648, 650, 652, 654, 657, 659, 661, 663, 668,
+ 668, 669, 669, 670, 670, 671, 671, 672, 672, 673,
+ 673, 674, 674, 675, 675, 676, 676, 683, 685, 690,
+ 696, 702, 704, 706, 708, 710, 712, 714, 716, 722,
+ 724, 726, 728, 730, 732, 732, 733, 735, 735, 736,
+ 738, 738, 739, 747, 758, 760, 765, 767, 772, 774,
+ 779, 779, 780, 780, 781, 781, 782, 782, 786, 794,
+ 801, 803, 808, 815, 821, 826, 829, 832, 837, 837,
+ 838, 838, 839, 839, 840, 840, 841, 841, 846, 851,
+ 856, 861, 863, 865, 867, 869, 871, 873, 875, 877,
+ 877, 878, 880, 888, 896, 912, 914, 916, 918, 925,
+ 927, 935, 937, 939, 945, 950, 951, 955, 956, 960,
+ 962, 967, 972, 972, 974, 979, 981, 983, 990, 994,
+ 996, 998, 1002, 1004, 1006, 1008, 1013, 1013, 1016, 1020,
+ 1020, 1023, 1023, 1029, 1029, 1053, 1054, 1057, 1057, 1062,
+ 1063, 1064, 1065, 1066, 1069, 1070, 1071, 1072, 1075, 1076,
+ 1077, 1080, 1081, 1084, 1085
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || 0
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "REG", "FLAG", "CREG", "ACC", "EXPR",
+ "UNKNOWN_OPCODE", "IS_OPCODE", "DOT_S", "DOT_B", "DOT_W", "DOT_L",
+ "DOT_A", "DOT_UB", "DOT_UW", "ABS", "ADC", "ADD", "AND_", "BCLR", "BCND",
+ "BMCND", "BNOT", "BRA", "BRK", "BSET", "BSR", "BTST", "CLRPSW", "CMP",
+ "DBT", "DIV", "DIVU", "EDIV", "EDIVU", "EMACA", "EMSBA", "EMUL", "EMULA",
+ "EMULU", "FADD", "FCMP", "FDIV", "FMUL", "FREIT", "FSUB", "FSQRT",
+ "FTOI", "FTOU", "INT", "ITOF", "JMP", "JSR", "MACHI", "MACLH", "MACLO",
+ "MAX", "MIN", "MOV", "MOVCO", "MOVLI", "MOVU", "MSBHI", "MSBLH", "MSBLO",
+ "MUL", "MULHI", "MULLH", "MULLO", "MULU", "MVFACHI", "MVFACGU",
+ "MVFACMI", "MVFACLO", "MVFC", "MVTACGU", "MVTACHI", "MVTACLO", "MVTC",
+ "MVTIPL", "NEG", "NOP", "NOT", "OR", "POP", "POPC", "POPM", "PUSH",
+ "PUSHA", "PUSHC", "PUSHM", "RACL", "RACW", "RDACL", "RDACW", "REIT",
+ "REVL", "REVW", "RMPA", "ROLC", "RORC", "ROTL", "ROTR", "ROUND", "RTE",
+ "RTFI", "RTS", "RTSD", "SAT", "SATR", "SBB", "SCCND", "SCMPU", "SETPSW",
+ "SHAR", "SHLL", "SHLR", "SMOVB", "SMOVF", "SMOVU", "SSTR", "STNZ",
+ "STOP", "STZ", "SUB", "SUNTIL", "SWHILE", "TST", "UTOF", "WAIT", "XCHG",
+ "XOR", "'#'", "','", "'['", "']'", "'-'", "'+'", "$accept", "statement",
+ "$@1", "$@2", "$@3", "$@4", "$@5", "$@6", "$@7", "$@8", "$@9", "$@10",
+ "$@11", "$@12", "$@13", "$@14", "$@15", "$@16", "$@17", "$@18", "$@19",
+ "$@20", "$@21", "$@22", "$@23", "$@24", "$@25", "$@26", "$@27", "$@28",
+ "$@29", "$@30", "$@31", "$@32", "$@33", "$@34", "$@35", "$@36", "$@37",
+ "$@38", "$@39", "$@40", "$@41", "$@42", "$@43", "$@44", "$@45",
+ "op_subadd", "op_dp20_rm_l", "op_dp20_rm", "op_dp20_i", "op_dp20_rim",
+ "op_dp20_rim_l", "op_dp20_rr", "op_dp20_r", "op_dp20_ri", "$@46",
+ "op_xchg", "op_shift_rot", "op_shift", "float3_op", "float2_op", "$@47",
+ "float2_op_ni", "$@48", "$@49", "mvfa_op", "$@50", "disp", "flag",
+ "$@51", "memex", "bwl", "bw", "opt_l", "opt_b", YY_NULL
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
+ (internal) symbol number NUM (which must be that of a token). */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
+ 275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
+ 285, 286, 287, 288, 289, 290, 291, 292, 293, 294,
+ 295, 296, 297, 298, 299, 300, 301, 302, 303, 304,
+ 305, 306, 307, 308, 309, 310, 311, 312, 313, 314,
+ 315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
+ 325, 326, 327, 328, 329, 330, 331, 332, 333, 334,
+ 335, 336, 337, 338, 339, 340, 341, 342, 343, 344,
+ 345, 346, 347, 348, 349, 350, 351, 352, 353, 354,
+ 355, 356, 357, 358, 359, 360, 361, 362, 363, 364,
+ 365, 366, 367, 368, 369, 370, 371, 372, 373, 374,
+ 375, 376, 377, 378, 379, 380, 381, 382, 383, 384,
+ 385, 386, 387, 388, 35, 44, 91, 93, 45, 43
+};
+# endif
+
+#define YYPACT_NINF -600
+
+#define yypact_value_is_default(Yystate) \
+ (!!((Yystate) == (-600)))
+
+#define YYTABLE_NINF -270
+
+#define yytable_value_is_error(Yytable_value) \
+ 0
+
+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+static const yytype_int16 yypact[] =
+{
+ 645, -600, -600, -600, -128, -112, 14, 114, -98, 24,
+ 71, -600, 28, 60, 29, -600, 16, -600, -600, -600,
+ 46, 48, -75, 68, -45, -600, -600, -600, -600, -600,
+ -600, -600, -600, -39, -600, 98, 112, 132, 151, 167,
+ -600, -600, 34, 169, 54, 57, 194, 203, 205, 81,
+ 213, 214, 215, 216, -600, 217, 219, 220, 221, 223,
+ 224, 30, 95, -600, -600, -600, 96, 225, 226, 230,
+ 148, 229, 232, 104, 105, 106, 108, -600, -600, 148,
+ 238, 240, 110, 111, -600, -600, -600, -600, 113, 243,
+ -600, 115, 199, -600, -600, -600, -600, -600, -600, -600,
+ -600, 148, -600, -600, 116, 148, 148, -600, -600, -600,
+ -600, -600, 248, 249, 21, 244, 5, 246, 5, 120,
+ 250, -600, 251, 252, 254, 255, 121, 256, -600, 257,
+ 258, 259, -600, 261, 266, 135, 264, -600, 267, 268,
+ 270, 141, 271, -600, 273, 144, -600, 274, 146, 22,
+ 22, 145, 149, 152, 6, 150, 152, 6, 23, 31,
+ 31, 23, 23, 280, 280, 280, 281, 6, -600, -600,
+ 154, 155, 156, 22, 22, 153, 158, 159, 287, 0,
+ 160, 293, -600, -600, 7, 162, 163, 164, 295, 5,
+ 165, 168, 170, -600, -600, -600, -600, -600, -600, -600,
+ 171, 172, 173, 174, 175, 297, 304, 249, 249, 305,
+ 5, -600, -600, 176, -600, -600, -600, 58, -600, 177,
+ 306, 309, 310, 311, 316, 316, -600, -600, -600, 313,
+ 316, 314, 316, 280, 315, -600, 317, 89, 320, 318,
+ -600, 32, 32, 32, -600, 152, 152, 319, 5, -600,
+ -600, 22, 6, 6, 22, -600, 193, -600, 196, 322,
+ -600, -600, -600, 191, 198, 201, -600, 204, 206, -600,
+ 124, 207, -600, -600, -600, 208, 179, 209, -600, -600,
+ -600, -600, -600, 181, 210, -600, -600, -600, 184, 211,
+ -600, 327, 212, 329, 218, -600, -600, -600, 222, -600,
+ 331, 332, -600, 227, -600, 228, 334, -600, -600, 231,
+ 341, -600, 233, -600, 234, -600, 335, 318, -600, -600,
+ -600, -600, -600, -600, -600, -600, 336, 346, 347, -600,
+ -600, 344, 345, 348, 235, 236, 237, -1, 239, 241,
+ 242, 245, 1, 351, 353, 354, 247, -600, 356, 357,
+ 358, -600, 253, -600, -600, -600, 360, 359, 361, 366,
+ 369, 260, -600, -600, -600, 265, -600, 373, -600, 263,
+ 376, 275, 276, 277, 278, 279, -600, -600, 282, -600,
+ 283, -600, -600, 284, 285, -600, -600, 269, 377, -600,
+ -600, -600, -600, -600, -600, 380, -600, 286, -600, -600,
+ -600, -600, -600, 382, 383, 288, 385, 386, 387, 388,
+ 389, -600, 272, 186, 189, -600, 289, 192, -600, 290,
+ 195, -600, 291, 197, -600, 390, 292, 391, 393, 296,
+ 298, 399, 400, 299, 403, 300, 406, 408, 301, 294,
+ 302, 303, 307, 308, 312, 321, 413, 8, 419, -7,
+ 421, 425, 323, 429, 436, 40, 437, 324, 325, 326,
+ 438, 328, 330, 333, 439, -600, -600, -600, -600, -600,
+ 375, 441, -600, 442, -600, 443, 444, 445, 446, 450,
+ 451, 452, 454, 459, 461, 337, 338, -600, 463, -600,
+ -600, 464, 339, 340, 342, 343, -600, 466, -600, 349,
+ -600, 350, 467, -600, 352, 468, -600, 355, 471, -600,
+ 362, -600, 75, -600, 363, 472, 473, -600, 364, 475,
+ 367, 479, 368, 371, 480, 481, 483, 484, 486, 11,
+ 33, 13, -600, -600, 372, 2, 370, 490, 374, 379,
+ 381, 384, 491, -600, 392, 492, 395, 394, 396, 493,
+ 497, 498, -600, 504, 505, 506, 397, -600, -600, 398,
+ -600, -600, -600, -600, -600, -600, -600, 401, -600, 404,
+ 494, 514, -600, -600, 435, 516, 517, 94, 405, 519,
+ 520, 407, 521, 409, 522, 410, 523, -600, -600, -600,
+ 402, -600, 414, 101, -600, -600, 107, -600, 524, -600,
+ 435, 525, -600, 411, -600, -600, -600, 531, 415, 533,
+ 416, -600, 535, 417, 537, 41, 540, 420, 422, 200,
+ 423, 426, -600, -600, 428, 427, 542, 430, 431, -600,
+ -600, -600, -600, -600, -600, 544, -600, 551, -600, 432,
+ -600, 433, -600, -600, 434, 440, 476, 447, 448, 476,
+ 449, 476, 453, 476, 455, 553, 554, 456, 458, 460,
+ 462, -600, 465, -600, 435, 457, 557, 469, 567, 470,
+ 568, 474, 569, -600, 477, 478, 202, 482, -600, 485,
+ 570, 571, 573, 487, -600, 574, 575, 488, -600, 576,
+ 577, 578, 579, -600, -600, 572, 476, -600, 476, -600,
+ 585, -600, 587, -600, -600, 584, 586, 596, 598, 599,
+ 489, -600, 495, -600, 496, -600, 499, -600, 500, -600,
+ -600, -600, 502, 601, 602, -600, -600, -600, 605, -600,
+ -600, 606, -600, -600, -600, -600, -600, -600, -600, -600,
+ -600, -600, -600, -600, -600, -600, 607, -600, -600, -600,
+ -600, 609, -600, 503, -600, -600, -600, 507, -600, -600
+};
+
+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
+ Performed when YYTABLE does not specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint16 yydefact[] =
+{
+ 0, 2, 97, 95, 210, 214, 0, 0, 0, 0,
+ 291, 3, 0, 291, 0, 277, 275, 4, 107, 109,
+ 0, 0, 121, 0, 123, 143, 141, 147, 145, 139,
+ 149, 151, 153, 0, 127, 0, 0, 0, 0, 0,
+ 99, 101, 284, 0, 0, 288, 0, 0, 0, 212,
+ 0, 0, 0, 174, 229, 177, 180, 0, 0, 0,
+ 0, 0, 0, 93, 6, 115, 216, 0, 0, 0,
+ 284, 0, 0, 0, 0, 0, 0, 196, 194, 284,
+ 0, 0, 190, 192, 155, 76, 75, 5, 0, 0,
+ 78, 91, 284, 67, 277, 43, 45, 41, 69, 70,
+ 68, 284, 119, 117, 208, 284, 284, 111, 129, 77,
+ 125, 113, 0, 0, 275, 0, 275, 0, 275, 0,
+ 0, 18, 0, 0, 0, 0, 0, 0, 7, 0,
+ 0, 0, 292, 0, 0, 0, 0, 10, 0, 0,
+ 0, 0, 0, 62, 0, 0, 276, 0, 0, 275,
+ 275, 0, 0, 0, 275, 0, 0, 275, 275, 271,
+ 271, 275, 275, 271, 271, 271, 0, 275, 63, 64,
+ 0, 0, 0, 275, 275, 285, 286, 287, 0, 0,
+ 0, 0, 289, 290, 0, 0, 0, 0, 0, 275,
+ 0, 0, 0, 173, 273, 273, 176, 273, 179, 273,
+ 0, 0, 169, 171, 0, 0, 0, 0, 0, 0,
+ 275, 58, 60, 0, 285, 286, 287, 275, 59, 0,
+ 0, 0, 0, 0, 0, 0, 74, 56, 55, 0,
+ 0, 0, 0, 271, 0, 54, 0, 275, 287, 275,
+ 61, 0, 0, 0, 73, 252, 252, 0, 275, 71,
+ 72, 275, 275, 275, 275, 1, 250, 98, 0, 0,
+ 247, 248, 96, 0, 0, 0, 211, 0, 0, 215,
+ 275, 0, 12, 13, 17, 0, 275, 0, 9, 14,
+ 15, 8, 65, 275, 0, 16, 11, 66, 275, 0,
+ 278, 0, 0, 0, 0, 245, 246, 108, 0, 110,
+ 0, 0, 104, 0, 122, 0, 0, 106, 124, 0,
+ 0, 144, 0, 142, 0, 268, 0, 275, 148, 146,
+ 140, 150, 152, 154, 50, 128, 0, 0, 0, 100,
+ 102, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 213, 0, 0,
+ 0, 175, 0, 230, 178, 181, 0, 0, 0, 0,
+ 0, 0, 79, 94, 116, 0, 217, 0, 57, 0,
+ 0, 0, 182, 0, 0, 0, 197, 195, 0, 191,
+ 0, 193, 156, 40, 0, 92, 157, 0, 0, 261,
+ 44, 46, 42, 254, 120, 0, 118, 0, 209, 112,
+ 130, 126, 114, 0, 0, 0, 0, 0, 0, 0,
+ 0, 132, 0, 275, 275, 134, 0, 275, 131, 0,
+ 275, 133, 0, 275, 26, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 165, 0, 167, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 161, 0, 163, 0, 199, 231, 170, 172, 198,
+ 0, 0, 48, 0, 47, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 253, 0, 249,
+ 239, 0, 0, 34, 235, 0, 36, 0, 52, 0,
+ 203, 0, 0, 204, 0, 0, 51, 0, 0, 53,
+ 0, 33, 281, 241, 0, 0, 0, 255, 0, 0,
+ 263, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 39, 85, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 29, 0, 0, 0, 0, 0, 0,
+ 0, 0, 35, 0, 0, 0, 0, 202, 37, 0,
+ 232, 183, 233, 234, 258, 200, 201, 0, 218, 0,
+ 0, 0, 32, 244, 291, 0, 0, 281, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 279, 280, 282,
+ 0, 283, 0, 281, 221, 222, 281, 223, 0, 262,
+ 291, 0, 270, 0, 166, 224, 168, 0, 0, 0,
+ 0, 38, 0, 0, 0, 0, 0, 0, 0, 275,
+ 0, 0, 219, 220, 0, 0, 0, 0, 0, 225,
+ 226, 227, 162, 228, 164, 0, 90, 0, 158, 259,
+ 251, 0, 49, 238, 0, 0, 293, 0, 0, 293,
+ 0, 293, 0, 293, 0, 0, 0, 0, 0, 0,
+ 0, 265, 0, 267, 291, 0, 0, 0, 0, 0,
+ 0, 0, 0, 82, 0, 0, 275, 0, 86, 0,
+ 0, 0, 0, 0, 30, 0, 0, 0, 25, 0,
+ 0, 0, 0, 294, 136, 0, 293, 138, 293, 135,
+ 0, 137, 0, 27, 28, 0, 0, 0, 0, 0,
+ 0, 19, 0, 20, 0, 21, 0, 80, 0, 184,
+ 185, 81, 0, 0, 0, 186, 187, 31, 0, 188,
+ 189, 0, 260, 240, 236, 237, 88, 159, 160, 87,
+ 89, 242, 243, 256, 257, 264, 0, 22, 23, 24,
+ 205, 0, 206, 0, 207, 274, 272, 0, 83, 84
+};
+
+ /* YYPGOTO[NTERM-NUM]. */
+static const yytype_int16 yypgoto[] =
+{
+ -600, -600, -600, -600, -600, -600, -600, -600, -600, -600,
+ -600, -600, -600, -600, -600, -600, -600, -600, -600, -600,
+ -600, -600, -600, -600, -600, -600, -600, -600, -600, -600,
+ -600, -600, -600, -600, -600, -600, -600, -600, -600, -600,
+ -600, -600, -600, -600, -600, -600, -600, -81, 412, -600,
+ -93, -80, -600, -131, -600, 534, -600, -119, -168, -139,
+ 52, 501, -600, -122, -600, -600, -14, -600, -16, 526,
+ -600, -538, -26, -600, -12, -599
+};
+
+ /* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int16 yydefgoto[] =
+{
+ -1, 112, 243, 241, 242, 237, 207, 114, 113, 173,
+ 174, 153, 156, 149, 150, 251, 254, 208, 246, 245,
+ 154, 157, 253, 167, 252, 162, 159, 158, 161, 160,
+ 163, 164, 165, 233, 194, 197, 199, 230, 232, 225,
+ 224, 248, 116, 189, 118, 210, 195, 266, 260, 295,
+ 296, 297, 262, 257, 487, 394, 395, 304, 389, 390,
+ 311, 313, 314, 315, 316, 317, 351, 352, 298, 143,
+ 144, 592, 179, 184, 134, 694
+};
+
+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule whose
+ number is the opposite. If YYTABLE_NINF, syntax error. */
+static const yytype_int16 yytable[] =
+{
+ 148, 140, 449, 335, 455, 615, 115, 336, 265, 303,
+ 340, 533, 146, 146, 341, 534, 611, 119, 146, 145,
+ 146, 261, 117, 146, 258, 294, 309, 126, 146, 146,
+ 146, 135, 141, 204, -269, 375, 125, 269, 308, 645,
+ 146, 321, 322, 323, 217, 175, 176, 177, 325, 151,
+ 697, 152, 699, 226, 701, 658, 376, 377, 660, -103,
+ 302, 368, 379, 307, 381, 146, 239, 137, 182, 183,
+ 299, 155, 138, 132, 139, 244, 363, 364, 128, 249,
+ 250, 129, 130, 131, 132, 133, 587, 588, 589, -105,
+ 590, 591, 258, 329, 330, 166, 146, 737, 263, 738,
+ 267, 168, 267, 391, 392, 587, 588, 589, 347, 644,
+ 591, 382, 587, 588, 589, 169, 657, 591, 587, 588,
+ 589, 121, 659, 591, 122, 123, 124, 411, 537, 366,
+ 538, 146, 539, 400, 401, 170, 337, 450, 305, 456,
+ 616, 305, 312, 342, 535, 312, 312, 607, 120, 612,
+ 147, 305, 393, 393, 171, 259, 259, 310, 127, 214,
+ 215, 216, 136, 142, 205, -266, 388, 398, 178, 609,
+ 172, 399, 180, 267, 402, 545, 672, 546, 673, 547,
+ 674, 353, 415, 354, 418, 355, 146, 421, 146, 498,
+ 181, 146, 500, 146, 267, 503, 146, 185, 506, 146,
+ 509, 369, 146, 678, 146, 721, 186, 146, 187, 146,
+ 214, 215, 238, 319, 320, 188, 190, 191, 192, 193,
+ 196, 263, 198, 387, 201, 200, 202, 203, 211, 206,
+ 209, 212, 267, 213, 218, 219, 305, 305, 220, 221,
+ 222, 227, 223, 228, 229, 231, 235, 234, 255, 236,
+ 247, 264, 256, 268, 412, 270, 276, 271, 272, 273,
+ 416, 274, 275, 277, 278, 279, 280, 419, 281, 282,
+ 283, 284, 422, 287, 285, 286, 288, 290, 289, 291,
+ 300, 292, 293, -269, 301, 306, 259, 331, 324, 326,
+ 327, 328, 332, 333, 334, 338, 339, 343, 344, 345,
+ 348, 439, 346, 349, 361, 350, 356, 357, 358, 359,
+ 360, 362, 365, 371, 367, 370, 372, 373, 374, 375,
+ 378, 380, 383, 386, 384, 146, 397, 406, 403, 405,
+ 424, 404, 426, 407, 429, 430, 408, 433, 438, 440,
+ 409, 410, 413, 414, 417, 420, 423, 425, 435, 441,
+ 442, 443, 444, 427, 457, 445, 458, 459, 428, 461,
+ 462, 463, 431, 465, 432, 466, 434, 467, 437, 436,
+ 446, 447, 468, 448, 469, 451, 472, 453, 452, 474,
+ 557, 454, 460, 486, 485, 489, 490, 464, 492, 493,
+ 494, 495, 496, 511, 513, 470, 514, 499, 501, 473,
+ 471, 504, 517, 518, 507, 484, 520, 510, 497, 522,
+ 475, 476, 477, 478, 479, 523, 532, 480, 481, 482,
+ 483, 488, 536, 491, 540, 502, 505, 508, 541, 512,
+ 525, 515, 543, 516, 519, 521, 524, 526, 527, 544,
+ 548, 552, 528, 529, 558, 559, 556, 530, 132, 560,
+ 561, 562, 563, 564, 565, 566, 531, 567, 542, 549,
+ 550, 551, 568, 553, 569, 554, 572, 573, 555, 578,
+ 581, 583, 570, 571, 585, 575, 574, 576, 594, 595,
+ 577, 597, 599, 602, 603, 579, 580, 693, 582, 604,
+ 605, 584, 606, 618, 623, 625, 0, 639, 586, 629,
+ 593, 596, 598, 630, 631, 600, 601, 617, 614, 619,
+ 632, 633, 634, 608, 610, 613, 620, 640, 621, 642,
+ 643, 622, 647, 648, 650, 652, 654, 661, 663, 624,
+ 626, 627, 635, 628, 665, 636, 667, 655, 669, 637,
+ 671, 638, 646, 675, 649, 684, 651, 653, 664, 656,
+ 687, 666, 668, 670, 688, 676, 703, 704, 680, 677,
+ 712, 681, 641, 682, 683, 685, 686, 689, 690, 691,
+ 714, 716, 718, 725, 726, 692, 727, 729, 730, 732,
+ 733, 734, 735, 736, 695, 696, 698, 741, 662, 742,
+ 700, 705, 702, 706, 711, 707, 739, 708, 740, 743,
+ 709, 744, 745, 679, 752, 753, 713, 715, 754, 755,
+ 756, 717, 757, 0, 719, 720, 0, 723, 0, 0,
+ 240, 724, 728, 731, 746, 0, 0, 0, 0, 0,
+ 0, 0, 747, 748, 0, 0, 749, 750, 751, 0,
+ 758, 0, 0, 0, 759, 0, 0, 0, 0, 385,
+ 0, 0, 710, 1, 0, 0, 0, 0, 0, 0,
+ 722, 318, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 0, 0, 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 0, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,
+ 47, 48, 49, 50, 51, 52, 0, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,
+ 66, 67, 68, 69, 70, 0, 71, 72, 73, 74,
+ 75, 76, 0, 77, 78, 79, 80, 81, 82, 83,
+ 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
+ 94, 95, 96, 97, 98, 99, 100, 101, 102, 0,
+ 103, 104, 105, 106, 107, 108, 109, 110, 111, 0,
+ 396
+};
+
+static const yytype_int16 yycheck[] =
+{
+ 16, 13, 3, 3, 3, 3, 134, 7, 3, 3,
+ 3, 3, 7, 7, 7, 7, 3, 3, 7, 3,
+ 7, 114, 134, 7, 3, 3, 3, 3, 7, 7,
+ 7, 3, 3, 3, 3, 3, 134, 118, 157, 577,
+ 7, 163, 164, 165, 70, 11, 12, 13, 167, 3,
+ 649, 3, 651, 79, 653, 593, 224, 225, 596, 134,
+ 153, 3, 230, 156, 232, 7, 92, 7, 11, 12,
+ 150, 3, 12, 13, 14, 101, 207, 208, 7, 105,
+ 106, 10, 11, 12, 13, 14, 11, 12, 13, 134,
+ 15, 16, 3, 173, 174, 134, 7, 696, 114, 698,
+ 116, 3, 118, 242, 243, 11, 12, 13, 189, 15,
+ 16, 233, 11, 12, 13, 3, 15, 16, 11, 12,
+ 13, 7, 15, 16, 10, 11, 12, 3, 135, 210,
+ 137, 7, 139, 252, 253, 3, 136, 138, 154, 138,
+ 138, 157, 158, 136, 136, 161, 162, 136, 134, 136,
+ 134, 167, 245, 246, 3, 134, 134, 134, 134, 11,
+ 12, 13, 134, 134, 134, 134, 134, 248, 134, 136,
+ 3, 251, 3, 189, 254, 135, 135, 137, 137, 139,
+ 139, 195, 3, 197, 3, 199, 7, 3, 7, 3,
+ 136, 7, 3, 7, 210, 3, 7, 3, 3, 7,
+ 3, 217, 7, 3, 7, 3, 3, 7, 3, 7,
+ 11, 12, 13, 161, 162, 134, 3, 3, 3, 3,
+ 3, 237, 3, 239, 3, 5, 3, 3, 3, 134,
+ 134, 5, 248, 3, 5, 3, 252, 253, 134, 134,
+ 134, 3, 134, 3, 134, 134, 3, 134, 0, 134,
+ 134, 7, 3, 7, 270, 135, 135, 7, 7, 7,
+ 276, 7, 7, 7, 7, 7, 7, 283, 7, 3,
+ 135, 7, 288, 3, 7, 7, 135, 4, 7, 135,
+ 135, 7, 136, 3, 135, 135, 134, 134, 7, 135,
+ 135, 135, 134, 134, 7, 135, 3, 135, 135, 135,
+ 135, 317, 7, 135, 7, 135, 135, 135, 135, 135,
+ 135, 7, 7, 7, 138, 138, 7, 7, 7, 3,
+ 7, 7, 7, 3, 7, 7, 7, 136, 135, 7,
+ 3, 135, 3, 135, 3, 3, 135, 3, 3, 3,
+ 136, 135, 135, 135, 135, 135, 135, 135, 7, 3,
+ 3, 7, 7, 135, 3, 7, 3, 3, 136, 3,
+ 3, 3, 135, 3, 136, 6, 135, 6, 134, 136,
+ 135, 135, 6, 136, 5, 136, 3, 135, 137, 3,
+ 5, 136, 135, 3, 7, 3, 3, 134, 3, 3,
+ 3, 3, 3, 3, 3, 135, 3, 413, 414, 136,
+ 135, 417, 3, 3, 420, 136, 3, 423, 136, 3,
+ 135, 135, 135, 135, 135, 7, 3, 135, 135, 135,
+ 135, 135, 3, 135, 3, 136, 136, 136, 3, 137,
+ 136, 135, 3, 135, 135, 135, 135, 135, 135, 3,
+ 3, 3, 135, 135, 3, 3, 7, 135, 13, 6,
+ 6, 6, 6, 3, 3, 3, 135, 3, 135, 135,
+ 135, 135, 3, 135, 3, 135, 3, 3, 135, 3,
+ 3, 3, 135, 135, 3, 135, 137, 135, 6, 6,
+ 137, 6, 3, 3, 3, 136, 136, 11, 136, 6,
+ 6, 136, 6, 3, 3, 3, -1, 3, 136, 6,
+ 137, 137, 135, 6, 6, 137, 135, 137, 136, 135,
+ 6, 6, 6, 529, 530, 531, 137, 3, 137, 3,
+ 3, 137, 3, 3, 3, 3, 3, 3, 3, 137,
+ 135, 137, 135, 137, 3, 137, 3, 135, 3, 138,
+ 3, 137, 137, 3, 137, 3, 137, 137, 137, 135,
+ 6, 136, 136, 136, 3, 135, 3, 3, 135, 137,
+ 3, 135, 574, 135, 137, 135, 135, 135, 135, 135,
+ 3, 3, 3, 3, 3, 135, 3, 3, 3, 3,
+ 3, 3, 3, 11, 137, 137, 137, 3, 600, 3,
+ 137, 135, 137, 135, 137, 135, 11, 135, 11, 3,
+ 135, 3, 3, 619, 3, 3, 137, 137, 3, 3,
+ 3, 137, 3, -1, 137, 137, -1, 135, -1, -1,
+ 94, 136, 135, 135, 135, -1, -1, -1, -1, -1,
+ -1, -1, 137, 137, -1, -1, 137, 137, 136, -1,
+ 137, -1, -1, -1, 137, -1, -1, -1, -1, 237,
+ -1, -1, 664, 8, -1, -1, -1, -1, -1, -1,
+ 676, 160, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ -1, -1, 37, 38, 39, 40, 41, 42, 43, 44,
+ 45, -1, 47, 48, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, -1, 72, 73, 74,
+ 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 87, 88, 89, -1, 91, 92, 93, 94,
+ 95, 96, -1, 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110, 111, 112, 113, 114,
+ 115, 116, 117, 118, 119, 120, 121, 122, 123, -1,
+ 125, 126, 127, 128, 129, 130, 131, 132, 133, -1,
+ 246
+};
+
+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 8, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 72, 73, 74, 75, 76, 77, 78,
+ 79, 80, 81, 82, 83, 84, 85, 86, 87, 88,
+ 89, 91, 92, 93, 94, 95, 96, 98, 99, 100,
+ 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
+ 111, 112, 113, 114, 115, 116, 117, 118, 119, 120,
+ 121, 122, 123, 125, 126, 127, 128, 129, 130, 131,
+ 132, 133, 141, 148, 147, 134, 182, 134, 184, 3,
+ 134, 7, 10, 11, 12, 134, 3, 134, 7, 10,
+ 11, 12, 13, 14, 214, 3, 134, 7, 12, 14,
+ 214, 3, 134, 209, 210, 3, 7, 134, 208, 153,
+ 154, 3, 3, 151, 160, 3, 152, 161, 167, 166,
+ 169, 168, 165, 170, 171, 172, 134, 163, 3, 3,
+ 3, 3, 3, 149, 150, 11, 12, 13, 134, 212,
+ 3, 136, 11, 12, 213, 3, 3, 3, 134, 183,
+ 3, 3, 3, 3, 174, 186, 3, 175, 3, 176,
+ 5, 3, 3, 3, 3, 134, 134, 146, 157, 134,
+ 185, 3, 5, 3, 11, 12, 13, 212, 5, 3,
+ 134, 134, 134, 134, 180, 179, 212, 3, 3, 134,
+ 177, 134, 178, 173, 134, 3, 134, 145, 13, 212,
+ 209, 143, 144, 142, 212, 159, 158, 134, 181, 212,
+ 212, 155, 164, 162, 156, 0, 3, 193, 3, 134,
+ 188, 190, 192, 208, 7, 3, 187, 208, 7, 187,
+ 135, 7, 7, 7, 7, 7, 135, 7, 7, 7,
+ 7, 7, 3, 135, 7, 7, 7, 3, 135, 7,
+ 4, 135, 7, 136, 3, 189, 190, 191, 208, 191,
+ 135, 135, 190, 3, 197, 208, 135, 190, 197, 3,
+ 134, 200, 208, 201, 202, 203, 204, 205, 201, 200,
+ 200, 203, 203, 203, 7, 197, 135, 135, 135, 191,
+ 191, 134, 134, 134, 7, 3, 7, 136, 135, 3,
+ 3, 7, 136, 135, 135, 135, 7, 187, 135, 135,
+ 135, 206, 207, 206, 206, 206, 135, 135, 135, 135,
+ 135, 7, 7, 193, 193, 7, 187, 138, 3, 208,
+ 138, 7, 7, 7, 7, 3, 198, 198, 7, 198,
+ 7, 198, 203, 7, 7, 188, 3, 208, 134, 198,
+ 199, 199, 199, 190, 195, 196, 195, 7, 187, 191,
+ 197, 197, 191, 135, 135, 7, 136, 135, 135, 136,
+ 135, 3, 208, 135, 135, 3, 208, 135, 3, 208,
+ 135, 3, 208, 135, 3, 135, 3, 135, 136, 3,
+ 3, 135, 136, 3, 135, 7, 136, 134, 3, 208,
+ 3, 3, 3, 7, 7, 7, 135, 135, 136, 3,
+ 138, 136, 137, 135, 136, 3, 138, 3, 3, 3,
+ 135, 3, 3, 3, 134, 3, 6, 6, 6, 5,
+ 135, 135, 3, 136, 3, 135, 135, 135, 135, 135,
+ 135, 135, 135, 135, 136, 7, 3, 194, 135, 3,
+ 3, 135, 3, 3, 3, 3, 3, 136, 3, 208,
+ 3, 208, 136, 3, 208, 136, 3, 208, 136, 3,
+ 208, 3, 137, 3, 3, 135, 135, 3, 3, 135,
+ 3, 135, 3, 7, 135, 136, 135, 135, 135, 135,
+ 135, 135, 3, 3, 7, 136, 3, 135, 137, 139,
+ 3, 3, 135, 3, 3, 135, 137, 139, 3, 135,
+ 135, 135, 3, 135, 135, 135, 7, 5, 3, 3,
+ 6, 6, 6, 6, 3, 3, 3, 3, 3, 3,
+ 135, 135, 3, 3, 137, 135, 135, 137, 3, 136,
+ 136, 3, 136, 3, 136, 3, 136, 11, 12, 13,
+ 15, 16, 211, 137, 6, 6, 137, 6, 135, 3,
+ 137, 135, 3, 3, 6, 6, 6, 136, 208, 136,
+ 208, 3, 136, 208, 136, 3, 138, 137, 3, 135,
+ 137, 137, 137, 3, 137, 3, 135, 137, 137, 6,
+ 6, 6, 6, 6, 6, 135, 137, 138, 137, 3,
+ 3, 214, 3, 3, 15, 211, 137, 3, 3, 137,
+ 3, 137, 3, 137, 3, 135, 135, 15, 211, 15,
+ 211, 3, 214, 3, 137, 3, 136, 3, 136, 3,
+ 136, 3, 135, 137, 139, 3, 135, 137, 3, 208,
+ 135, 135, 135, 137, 3, 135, 135, 6, 3, 135,
+ 135, 135, 135, 11, 215, 137, 137, 215, 137, 215,
+ 137, 215, 137, 3, 3, 135, 135, 135, 135, 135,
+ 214, 137, 3, 137, 3, 137, 3, 137, 3, 137,
+ 137, 3, 208, 135, 136, 3, 3, 3, 135, 3,
+ 3, 135, 3, 3, 3, 3, 11, 215, 215, 11,
+ 11, 3, 3, 3, 3, 3, 135, 137, 137, 137,
+ 137, 136, 3, 3, 3, 3, 3, 3, 137, 137
+};
+
+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 140, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 142, 141, 143, 141, 144, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 145, 141, 146, 141, 147, 141, 148, 141, 149,
+ 141, 150, 141, 151, 141, 152, 141, 153, 141, 154,
+ 141, 155, 141, 156, 141, 157, 141, 158, 141, 159,
+ 141, 160, 141, 161, 141, 162, 141, 163, 141, 164,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 165,
+ 141, 166, 141, 167, 141, 168, 141, 169, 141, 170,
+ 141, 171, 141, 172, 141, 173, 141, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 141, 141, 141, 141, 174, 141, 141, 175, 141, 141,
+ 176, 141, 141, 141, 141, 141, 141, 141, 141, 141,
+ 177, 141, 178, 141, 179, 141, 180, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 181, 141,
+ 182, 141, 183, 141, 184, 141, 185, 141, 141, 141,
+ 141, 141, 141, 141, 141, 141, 141, 141, 141, 186,
+ 141, 141, 141, 141, 141, 187, 187, 187, 187, 188,
+ 188, 189, 189, 189, 190, 191, 191, 192, 192, 193,
+ 193, 194, 196, 195, 195, 197, 197, 197, 198, 199,
+ 199, 199, 200, 200, 200, 200, 202, 201, 201, 204,
+ 203, 205, 203, 207, 206, 208, 208, 210, 209, 211,
+ 211, 211, 211, 211, 212, 212, 212, 212, 213, 213,
+ 213, 214, 214, 215, 215
+};
+
+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 1, 1, 1, 1, 1, 2, 3, 3,
+ 2, 3, 3, 3, 3, 3, 3, 3, 2, 8,
+ 8, 8, 9, 9, 9, 7, 4, 8, 8, 5,
+ 7, 8, 5, 5, 5, 5, 5, 5, 6, 5,
+ 3, 0, 3, 0, 3, 0, 3, 4, 4, 7,
+ 3, 5, 5, 5, 2, 2, 2, 3, 2, 2,
+ 2, 2, 2, 2, 2, 3, 3, 1, 1, 1,
+ 1, 2, 2, 2, 2, 1, 1, 1, 1, 3,
+ 8, 8, 7, 10, 11, 5, 7, 9, 9, 9,
+ 6, 0, 3, 0, 3, 0, 3, 0, 3, 0,
+ 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
+ 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
+ 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
+ 3, 4, 4, 4, 4, 8, 8, 8, 8, 0,
+ 3, 0, 3, 0, 3, 0, 3, 0, 3, 0,
+ 3, 0, 3, 0, 3, 0, 3, 3, 6, 9,
+ 9, 4, 6, 4, 6, 4, 6, 4, 6, 2,
+ 4, 2, 4, 2, 0, 3, 2, 0, 3, 2,
+ 0, 3, 3, 5, 8, 8, 8, 8, 8, 8,
+ 0, 3, 0, 3, 0, 3, 0, 3, 4, 4,
+ 5, 5, 5, 5, 5, 9, 9, 9, 0, 3,
+ 0, 3, 0, 3, 0, 3, 0, 3, 5, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 0,
+ 3, 4, 5, 5, 5, 3, 7, 7, 5, 3,
+ 7, 3, 7, 7, 4, 1, 1, 1, 1, 3,
+ 1, 3, 0, 2, 1, 3, 7, 7, 3, 4,
+ 6, 1, 4, 3, 7, 5, 0, 5, 1, 0,
+ 4, 0, 8, 0, 7, 0, 1, 0, 2, 1,
+ 1, 0, 1, 1, 0, 1, 1, 1, 0, 1,
+ 1, 0, 1, 0, 1
+};
+
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+/* Error token number */
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+/* This macro is provided for backward compatibility. */
+#ifndef YY_LOCATION_PRINT
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+#endif
+
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+
+/*----------------------------------------.
+| Print this symbol's value on YYOUTPUT. |
+`----------------------------------------*/
+
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ FILE *yyo = yyoutput;
+ YYUSE (yyo);
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ YYUSE (yytype);
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+{
+ YYFPRINTF (yyoutput, "%s %s (",
+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; yybottom <= yytop; yybottom++)
+ {
+ int yybot = *yybottom;
+ YYFPRINTF (stderr, " %d", yybot);
+ }
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+static void
+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
+{
+ unsigned long int yylno = yyrline[yyrule];
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ YYFPRINTF (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr,
+ yystos[yyssp[yyi + 1 - yynrhs]],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ YYFPRINTF (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyssp, yyvsp, Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+yystrlen (const char *yystr)
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+ about the unexpected token YYTOKEN for the state stack whose top is
+ YYSSP.
+
+ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
+ not large enough to hold the message. In that case, also set
+ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
+ required number of bytes is too large to store. */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+ yytype_int16 *yyssp, int yytoken)
+{
+ YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
+ YYSIZE_T yysize = yysize0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ /* Internationalized format string. */
+ const char *yyformat = YY_NULL;
+ /* Arguments of yyformat. */
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ /* Number of reported tokens (one for the "unexpected", one per
+ "expected"). */
+ int yycount = 0;
+
+ /* There are many possibilities here to consider:
+ - If this state is a consistent state with a default action, then
+ the only way this function was invoked is if the default action
+ is an error action. In that case, don't check for expected
+ tokens because there are none.
+ - The only way there can be no lookahead present (in yychar) is if
+ this state is a consistent state with a default action. Thus,
+ detecting the absence of a lookahead is sufficient to determine
+ that there is no unexpected or expected token to report. In that
+ case, just report a simple "syntax error".
+ - Don't assume there isn't a lookahead just because this state is a
+ consistent state with a default action. There might have been a
+ previous inconsistent state, consistent state with a non-default
+ action, or user semantic action that manipulated yychar.
+ - Of course, the expected token list depends on states to have
+ correct lookahead information, and it depends on the parser not
+ to perform extra reductions after fetching a lookahead from the
+ scanner and before detecting a syntax error. Thus, state merging
+ (from LALR or IELR) and default reductions corrupt the expected
+ token list. However, the list is correct for canonical LR with
+ one exception: it will still contain any token that will not be
+ accepted due to an error action in a later state.
+ */
+ if (yytoken != YYEMPTY)
+ {
+ int yyn = yypact[*yyssp];
+ yyarg[yycount++] = yytname[yytoken];
+ if (!yypact_value_is_default (yyn))
+ {
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. In other words, skip the first -YYN actions for
+ this state because they are default actions. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yyx;
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+ && !yytable_value_is_error (yytable[yyx + yyn]))
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ {
+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
+ if (! (yysize <= yysize1
+ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+ }
+ }
+ }
+
+ switch (yycount)
+ {
+# define YYCASE_(N, S) \
+ case N: \
+ yyformat = S; \
+ break
+ YYCASE_(0, YY_("syntax error"));
+ YYCASE_(1, YY_("syntax error, unexpected %s"));
+ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+ }
+
+ {
+ YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
+ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ return 2;
+ yysize = yysize1;
+ }
+
+ if (*yymsg_alloc < yysize)
+ {
+ *yymsg_alloc = 2 * yysize;
+ if (! (yysize <= *yymsg_alloc
+ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+ return 1;
+ }
+
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ {
+ char *yyp = *yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyformat) != '\0')
+ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyformat += 2;
+ }
+ else
+ {
+ yyp++;
+ yyformat++;
+ }
+ }
+ return 0;
+}
+#endif /* YYERROR_VERBOSE */
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+{
+ YYUSE (yyvaluep);
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ YYUSE (yytype);
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+}
+
+
+
+
+/* The lookahead symbol. */
+int yychar;
+
+/* The semantic value of the lookahead symbol. */
+YYSTYPE yylval;
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+int
+yyparse (void)
+{
+ int yystate;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+
+ /* The stacks and their tools:
+ 'yyss': related to states.
+ 'yyvs': related to semantic values.
+
+ Refer to the stacks through separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs;
+ YYSTYPE *yyvsp;
+
+ YYSIZE_T yystacksize;
+
+ int yyn;
+ int yyresult;
+ /* Lookahead token as an internal (translated) token number. */
+ int yytoken = 0;
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ yyssp = yyss = yyssa;
+ yyvsp = yyvs = yyvsa;
+ yystacksize = YYINITDEPTH;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss_alloc, yyss);
+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ if (yystate == YYFINAL)
+ YYACCEPT;
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ lookahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to lookahead token. */
+ yyn = yypact[yystate];
+ if (yypact_value_is_default (yyn))
+ goto yydefault;
+
+ /* Not known => get a lookahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = yylex ();
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yytable_value_is_error (yyn))
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the lookahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token. */
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ '$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 2:
+#line 179 "./config/rx-parse.y" /* yacc.c:1661 */
+ { as_bad (_("Unknown opcode: %s"), rx_init_start); }
+#line 2092 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 3:
+#line 184 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x00); }
+#line 2098 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 4:
+#line 187 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x01); }
+#line 2104 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 5:
+#line 190 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x02); }
+#line 2110 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 6:
+#line 193 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x03); }
+#line 2116 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 7:
+#line 198 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_disp3op ((yyvsp[0].exp)))
+ { B1 (0x08); rx_disp3 ((yyvsp[0].exp), 5); }
+ else if (rx_intop ((yyvsp[0].exp), 8, 8))
+ { B1 (0x2e); PC1 ((yyvsp[0].exp)); }
+ else if (rx_intop ((yyvsp[0].exp), 16, 16))
+ { B1 (0x38); PC2 ((yyvsp[0].exp)); }
+ else if (rx_intop ((yyvsp[0].exp), 24, 24))
+ { B1 (0x04); PC3 ((yyvsp[0].exp)); }
+ else
+ { rx_relax (RX_RELAX_BRANCH, 0);
+ rx_linkrelax_branch ();
+ /* We'll convert this to a longer one later if needed. */
+ B1 (0x08); rx_disp3 ((yyvsp[0].exp), 5); } }
+#line 2134 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 8:
+#line 213 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x04); PC3 ((yyvsp[0].exp)); }
+#line 2140 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 9:
+#line 216 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x08); rx_disp3 ((yyvsp[0].exp), 5); }
+#line 2146 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 10:
+#line 221 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_intop ((yyvsp[0].exp), 16, 16))
+ { B1 (0x39); PC2 ((yyvsp[0].exp)); }
+ else if (rx_intop ((yyvsp[0].exp), 24, 24))
+ { B1 (0x05); PC3 ((yyvsp[0].exp)); }
+ else
+ { rx_relax (RX_RELAX_BRANCH, 0);
+ rx_linkrelax_branch ();
+ B1 (0x39); PC2 ((yyvsp[0].exp)); } }
+#line 2159 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 11:
+#line 230 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x05), PC3 ((yyvsp[0].exp)); }
+#line 2165 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 12:
+#line 235 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-2].regno) == COND_EQ || (yyvsp[-2].regno) == COND_NE)
+ { B1 ((yyvsp[-2].regno) == COND_EQ ? 0x10 : 0x18); rx_disp3 ((yyvsp[0].exp), 5); }
+ else
+ as_bad (_("Only BEQ and BNE may have .S")); }
+#line 2174 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 13:
+#line 243 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x20); F ((yyvsp[-2].regno), 4, 4); PC1 ((yyvsp[0].exp)); }
+#line 2180 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 14:
+#line 246 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x2e), PC1 ((yyvsp[0].exp)); }
+#line 2186 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 15:
+#line 251 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x38), PC2 ((yyvsp[0].exp)); }
+#line 2192 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 16:
+#line 253 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x39), PC2 ((yyvsp[0].exp)); }
+#line 2198 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 17:
+#line 255 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-2].regno) == COND_EQ || (yyvsp[-2].regno) == COND_NE)
+ { B1 ((yyvsp[-2].regno) == COND_EQ ? 0x3a : 0x3b); PC2 ((yyvsp[0].exp)); }
+ else
+ as_bad (_("Only BEQ and BNE may have .W")); }
+#line 2207 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 18:
+#line 260 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-1].regno) == COND_EQ || (yyvsp[-1].regno) == COND_NE)
+ {
+ rx_relax (RX_RELAX_BRANCH, 0);
+ rx_linkrelax_branch ();
+ B1 ((yyvsp[-1].regno) == COND_EQ ? 0x10 : 0x18); rx_disp3 ((yyvsp[0].exp), 5);
+ }
+ else
+ {
+ rx_relax (RX_RELAX_BRANCH, 0);
+ /* This is because we might turn it into a
+ jump-over-jump long branch. */
+ rx_linkrelax_branch ();
+ B1 (0x20); F ((yyvsp[-1].regno), 4, 4); PC1 ((yyvsp[0].exp));
+ } }
+#line 2226 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 19:
+#line 278 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf8, 0x04); F ((yyvsp[-1].regno), 8, 4); IMMB ((yyvsp[-4].exp), 12);}
+#line 2232 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 20:
+#line 281 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf8, 0x01); F ((yyvsp[-1].regno), 8, 4); IMMW ((yyvsp[-4].exp), 12);}
+#line 2238 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 21:
+#line 284 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf8, 0x02); F ((yyvsp[-1].regno), 8, 4); IMM ((yyvsp[-4].exp), 12);}
+#line 2244 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 22:
+#line 288 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-1].regno) <= 7 && rx_uintop ((yyvsp[-5].exp), 8) && rx_disp5op0 (&(yyvsp[-3].exp), BSIZE))
+ { B2 (0x3c, 0); rx_field5s2 ((yyvsp[-3].exp)); F ((yyvsp[-1].regno), 9, 3); O1 ((yyvsp[-5].exp)); }
+ else
+ { B2 (0xf8, 0x04); F ((yyvsp[-1].regno), 8, 4); DSP ((yyvsp[-3].exp), 6, BSIZE); O1 ((yyvsp[-5].exp));
+ if ((yyvsp[-5].exp).X_op != O_constant && (yyvsp[-5].exp).X_op != O_big) rx_linkrelax_imm (12); } }
+#line 2254 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 23:
+#line 295 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-1].regno) <= 7 && rx_uintop ((yyvsp[-5].exp), 8) && rx_disp5op0 (&(yyvsp[-3].exp), WSIZE))
+ { B2 (0x3d, 0); rx_field5s2 ((yyvsp[-3].exp)); F ((yyvsp[-1].regno), 9, 3); O1 ((yyvsp[-5].exp)); }
+ else
+ { B2 (0xf8, 0x01); F ((yyvsp[-1].regno), 8, 4); DSP ((yyvsp[-3].exp), 6, WSIZE); IMMW ((yyvsp[-5].exp), 12); } }
+#line 2263 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 24:
+#line 301 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-1].regno) <= 7 && rx_uintop ((yyvsp[-5].exp), 8) && rx_disp5op0 (&(yyvsp[-3].exp), LSIZE))
+ { B2 (0x3e, 0); rx_field5s2 ((yyvsp[-3].exp)); F ((yyvsp[-1].regno), 9, 3); O1 ((yyvsp[-5].exp)); }
+ else
+ { B2 (0xf8, 0x02); F ((yyvsp[-1].regno), 8, 4); DSP ((yyvsp[-3].exp), 6, LSIZE); IMM ((yyvsp[-5].exp), 12); } }
+#line 2272 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 25:
+#line 309 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x3f, 0); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); rtsd_immediate ((yyvsp[-4].exp));
+ if ((yyvsp[-2].regno) == 0)
+ rx_error (_("RTSD cannot pop R0"));
+ if ((yyvsp[-2].regno) > (yyvsp[0].regno))
+ rx_error (_("RTSD first reg must be <= second reg")); }
+#line 2282 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 26:
+#line 318 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x47, 0); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 2288 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 27:
+#line 323 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x44, 0); F ((yyvsp[-4].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); DSP ((yyvsp[-6].exp), 6, BSIZE); }
+#line 2294 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 28:
+#line 326 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B3 (MEMEX, 0x04, 0); F ((yyvsp[-2].regno), 8, 2); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, sizemap[(yyvsp[-2].regno)]); }
+#line 2300 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 29:
+#line 331 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x5b, 0x00); F ((yyvsp[-3].regno), 5, 1); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 2306 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 30:
+#line 336 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x58, 0x00); F ((yyvsp[-5].regno), 5, 1); F ((yyvsp[-3].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 2312 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 31:
+#line 339 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-3].regno) <= 7 && (yyvsp[0].regno) <= 7 && rx_disp5op (&(yyvsp[-5].exp), (yyvsp[-6].regno)))
+ { B2 (0xb0, 0); F ((yyvsp[-6].regno), 4, 1); F ((yyvsp[-3].regno), 9, 3); F ((yyvsp[0].regno), 13, 3); rx_field5s ((yyvsp[-5].exp)); }
+ else
+ { B2 (0x58, 0x00); F ((yyvsp[-6].regno), 5, 1); F ((yyvsp[-3].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); DSP ((yyvsp[-5].exp), 6, (yyvsp[-6].regno)); } }
+#line 2321 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 32:
+#line 347 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x60, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else
+ /* This is really an add, but we negate the immediate. */
+ { B2 (0x70, 0); F ((yyvsp[0].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); NIMM ((yyvsp[-2].exp), 6); } }
+#line 2331 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 33:
+#line 354 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x61, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else if (rx_uintop ((yyvsp[-2].exp), 8))
+ { B2 (0x75, 0x50); F ((yyvsp[0].regno), 12, 4); UO1 ((yyvsp[-2].exp)); }
+ else
+ { B2 (0x74, 0x00); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-2].exp), 6); } }
+#line 2342 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 34:
+#line 362 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x62, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else
+ { B2 (0x70, 0); F ((yyvsp[0].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-2].exp), 6); } }
+#line 2351 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 35:
+#line 368 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x63, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else
+ { B2 (0x74, 0x10); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-2].exp), 6); } }
+#line 2360 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 36:
+#line 374 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x64, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else
+ { B2 (0x74, 0x20); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-2].exp), 6); } }
+#line 2369 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 37:
+#line 380 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x65, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else
+ { B2 (0x74, 0x30); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-2].exp), 6); } }
+#line 2378 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 38:
+#line 386 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x66, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else if (rx_uintop ((yyvsp[-2].exp), 8))
+ { B2 (0x75, 0x40); F ((yyvsp[0].regno), 12, 4); UO1 ((yyvsp[-2].exp)); }
+ else
+ { B2 (0xfb, 0x02); F ((yyvsp[0].regno), 8, 4); IMM ((yyvsp[-2].exp), 12); } }
+#line 2389 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 39:
+#line 394 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if (rx_uintop ((yyvsp[-2].exp), 4))
+ { B2 (0x66, 0); FE ((yyvsp[-2].exp), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ else if (rx_uintop ((yyvsp[-2].exp), 8))
+ { B2 (0x75, 0x40); F ((yyvsp[0].regno), 12, 4); UO1 ((yyvsp[-2].exp)); }
+ else
+ { B2 (0xfb, 0x02); F ((yyvsp[0].regno), 8, 4); IMM ((yyvsp[-2].exp), 12); } }
+#line 2400 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 40:
+#line 404 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B1 (0x67); rtsd_immediate ((yyvsp[0].exp)); }
+#line 2406 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 41:
+#line 408 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 0; }
+#line 2412 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 43:
+#line 409 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 1; }
+#line 2418 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 45:
+#line 410 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 2; }
+#line 2424 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 47:
+#line 415 "./config/rx-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].regno) == (yyvsp[0].regno))
+ { B2 (0x7e, 0x80); F (LSIZE, 10, 2); F ((yyvsp[-2].regno), 12, 4); }
+ else
+ { B2 (0x6e, 0); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ if ((yyvsp[-2].regno) == 0)
+ rx_error (_("PUSHM cannot push R0"));
+ if ((yyvsp[-2].regno) > (yyvsp[0].regno))
+ rx_error (_("PUSHM first reg must be <= second reg")); }
+#line 2438 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 48:
+#line 428 "./config/rx-parse.y" /* yacc.c:1661 */
+ {
+ if ((yyvsp[-2].regno) == (yyvsp[0].regno))
+ { B2 (0x7e, 0xb0); F ((yyvsp[-2].regno), 12, 4); }
+ else
+ { B2 (0x6f, 0); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+ if ((yyvsp[-2].regno) == 0)
+ rx_error (_("POPM cannot pop R0"));
+ if ((yyvsp[-2].regno) > (yyvsp[0].regno))
+ rx_error (_("POPM first reg must be <= second reg")); }
+#line 2452 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 49:
+#line 441 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x70, 0x00); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); IMM ((yyvsp[-4].exp), 6); }
+#line 2458 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 50:
+#line 446 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2(0x75, 0x60), UO1 ((yyvsp[0].exp)); }
+#line 2464 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 51:
+#line 451 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x78, 0); FE ((yyvsp[-2].exp), 7, 5); F ((yyvsp[0].regno), 12, 4); }
+#line 2470 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 52:
+#line 453 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7a, 0); FE ((yyvsp[-2].exp), 7, 5); F ((yyvsp[0].regno), 12, 4); }
+#line 2476 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 53:
+#line 458 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7c, 0x00); FE ((yyvsp[-2].exp), 7, 5); F ((yyvsp[0].regno), 12, 4); }
+#line 2482 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 54:
+#line 463 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, 0x30); F ((yyvsp[0].regno), 12, 4); }
+#line 2488 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 55:
+#line 465 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, 0x40); F ((yyvsp[0].regno), 12, 4); }
+#line 2494 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 56:
+#line 467 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, 0x50); F ((yyvsp[0].regno), 12, 4); }
+#line 2500 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 57:
+#line 472 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, 0x80); F ((yyvsp[-1].regno), 10, 2); F ((yyvsp[0].regno), 12, 4); }
+#line 2506 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 58:
+#line 477 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, 0xb0); F ((yyvsp[0].regno), 12, 4); }
+#line 2512 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 59:
+#line 482 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) == 13)
+ { rx_check_v2 (); }
+ if ((yyvsp[0].regno) < 16)
+ { B2 (0x7e, 0xc0); F ((yyvsp[0].regno), 12, 4); }
+ else
+ as_bad (_("PUSHC can only push the first 16 control registers")); }
+#line 2523 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 60:
+#line 492 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) == 13)
+ { rx_check_v2 (); }
+ if ((yyvsp[0].regno) < 16)
+ { B2 (0x7e, 0xe0); F ((yyvsp[0].regno), 12, 4); }
+ else
+ as_bad (_("POPC can only pop the first 16 control registers")); }
+#line 2534 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 61:
+#line 502 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0xa0); F ((yyvsp[0].regno), 12, 4); }
+#line 2540 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 62:
+#line 504 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0xb0); F ((yyvsp[0].regno), 12, 4); }
+#line 2546 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 63:
+#line 509 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x00); F ((yyvsp[0].regno), 12, 4); }
+#line 2552 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 64:
+#line 511 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x10); F ((yyvsp[0].regno), 12, 4); }
+#line 2558 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 65:
+#line 513 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x40); F ((yyvsp[0].regno), 12, 4); }
+#line 2564 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 66:
+#line 515 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x50); F ((yyvsp[0].regno), 12, 4); }
+#line 2570 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 67:
+#line 520 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x83); rx_note_string_insn_use (); }
+#line 2576 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 68:
+#line 522 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x87); rx_note_string_insn_use (); }
+#line 2582 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 69:
+#line 524 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x8b); rx_note_string_insn_use (); }
+#line 2588 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 70:
+#line 526 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x8f); rx_note_string_insn_use (); }
+#line 2594 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 71:
+#line 531 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x80); F ((yyvsp[0].regno), 14, 2); rx_note_string_insn_use (); }
+#line 2600 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 72:
+#line 533 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x84); F ((yyvsp[0].regno), 14, 2); rx_note_string_insn_use (); }
+#line 2606 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 73:
+#line 535 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x88); F ((yyvsp[0].regno), 14, 2); }
+#line 2612 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 74:
+#line 540 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x8c); F ((yyvsp[0].regno), 14, 2); rx_note_string_insn_use (); }
+#line 2618 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 75:
+#line 545 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x94); }
+#line 2624 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 76:
+#line 547 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x95); }
+#line 2630 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 77:
+#line 549 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x96); }
+#line 2636 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 78:
+#line 551 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7f, 0x93); }
+#line 2642 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 79:
+#line 556 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B3 (0x75, 0x70, 0x00); FE ((yyvsp[0].exp), 20, 4); }
+#line 2648 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 80:
+#line 562 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-5].regno) <= 7 && (yyvsp[-1].regno) <= 7 && rx_disp5op (&(yyvsp[-3].exp), (yyvsp[-6].regno)))
+ { B2 (0x80, 0); F ((yyvsp[-6].regno), 2, 2); F ((yyvsp[-1].regno), 9, 3); F ((yyvsp[-5].regno), 13, 3); rx_field5s ((yyvsp[-3].exp)); }
+ else
+ { B2 (0xc3, 0x00); F ((yyvsp[-6].regno), 2, 2); F ((yyvsp[-1].regno), 8, 4); F ((yyvsp[-5].regno), 12, 4); DSP ((yyvsp[-3].exp), 4, (yyvsp[-6].regno)); }}
+#line 2657 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 81:
+#line 570 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-3].regno) <= 7 && (yyvsp[0].regno) <= 7 && rx_disp5op (&(yyvsp[-5].exp), (yyvsp[-6].regno)))
+ { B2 (0x88, 0); F ((yyvsp[-6].regno), 2, 2); F ((yyvsp[-3].regno), 9, 3); F ((yyvsp[0].regno), 13, 3); rx_field5s ((yyvsp[-5].exp)); }
+ else
+ { B2 (0xcc, 0x00); F ((yyvsp[-6].regno), 2, 2); F ((yyvsp[-3].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); DSP ((yyvsp[-5].exp), 6, (yyvsp[-6].regno)); } }
+#line 2666 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 82:
+#line 584 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xc3, 0x00); F ((yyvsp[-5].regno), 2, 2); F ((yyvsp[-1].regno), 8, 4); F ((yyvsp[-4].regno), 12, 4); }
+#line 2672 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 83:
+#line 589 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xc0, 0); F ((yyvsp[-8].regno), 2, 2); F ((yyvsp[-6].regno), 8, 4); F ((yyvsp[-1].regno), 12, 4); DSP ((yyvsp[-3].exp), 4, (yyvsp[-8].regno)); }
+#line 2678 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 84:
+#line 594 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xc0, 0x00); F ((yyvsp[-9].regno), 2, 2); F ((yyvsp[-6].regno), 8, 4); F ((yyvsp[-1].regno), 12, 4); DSP ((yyvsp[-8].exp), 6, (yyvsp[-9].regno)); DSP ((yyvsp[-3].exp), 4, (yyvsp[-9].regno)); }
+#line 2684 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 85:
+#line 599 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xcf, 0x00); F ((yyvsp[-3].regno), 2, 2); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 2690 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 86:
+#line 604 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xcc, 0x00); F ((yyvsp[-5].regno), 2, 2); F ((yyvsp[-3].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 2696 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 87:
+#line 609 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf0, 0x00); F ((yyvsp[-2].regno), 8, 4); FE ((yyvsp[-6].exp), 13, 3); DSP ((yyvsp[-4].exp), 6, BSIZE); }
+#line 2702 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 88:
+#line 611 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf0, 0x08); F ((yyvsp[-2].regno), 8, 4); FE ((yyvsp[-6].exp), 13, 3); DSP ((yyvsp[-4].exp), 6, BSIZE); }
+#line 2708 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 89:
+#line 613 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf4, 0x00); F ((yyvsp[-2].regno), 8, 4); FE ((yyvsp[-6].exp), 13, 3); DSP ((yyvsp[-4].exp), 6, BSIZE); }
+#line 2714 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 90:
+#line 618 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0xf4, 0x08); F ((yyvsp[-4].regno), 14, 2); F ((yyvsp[-1].regno), 8, 4); DSP ((yyvsp[-3].exp), 6, (yyvsp[-4].regno)); }
+#line 2720 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 91:
+#line 622 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 0; }
+#line 2726 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 93:
+#line 623 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 1; sub_op2 = 1; }
+#line 2732 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 95:
+#line 624 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 2; }
+#line 2738 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 97:
+#line 625 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 3; sub_op2 = 2; }
+#line 2744 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 99:
+#line 626 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 4; }
+#line 2750 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 101:
+#line 627 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 5; }
+#line 2756 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 103:
+#line 628 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 6; }
+#line 2762 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 105:
+#line 629 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 7; }
+#line 2768 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 107:
+#line 630 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 8; }
+#line 2774 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 109:
+#line 631 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 9; }
+#line 2780 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 111:
+#line 632 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 12; }
+#line 2786 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 113:
+#line 633 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 13; }
+#line 2792 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 115:
+#line 634 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 14; sub_op2 = 0; }
+#line 2798 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 117:
+#line 635 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 14; sub_op2 = 0; }
+#line 2804 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 119:
+#line 636 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 15; sub_op2 = 1; }
+#line 2810 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 121:
+#line 640 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 6; }
+#line 2816 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 123:
+#line 641 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 7; }
+#line 2822 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 125:
+#line 642 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 16; }
+#line 2828 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 127:
+#line 643 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 17; }
+#line 2834 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 129:
+#line 644 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 21; }
+#line 2840 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 131:
+#line 649 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x63, 0x00); F ((yyvsp[0].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); }
+#line 2846 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 132:
+#line 651 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x67, 0x00); F ((yyvsp[0].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); }
+#line 2852 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 133:
+#line 653 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x6b, 0x00); F ((yyvsp[0].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); }
+#line 2858 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 134:
+#line 655 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x6f, 0x00); F ((yyvsp[0].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); }
+#line 2864 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 135:
+#line 658 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x60, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[-6].regno), 20, 4); DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2870 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 136:
+#line 660 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x64, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[-6].regno), 20, 4); DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2876 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 137:
+#line 662 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x68, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[-6].regno), 20, 4); DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2882 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 138:
+#line 664 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x6c, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[-6].regno), 20, 4); DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2888 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 139:
+#line 668 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 0; }
+#line 2894 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 141:
+#line 669 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 1; }
+#line 2900 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 143:
+#line 670 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 2; }
+#line 2906 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 145:
+#line 671 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 3; }
+#line 2912 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 147:
+#line 672 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 4; }
+#line 2918 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 149:
+#line 673 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 8; }
+#line 2924 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 151:
+#line 674 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 5; }
+#line 2930 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 153:
+#line 675 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 9; }
+#line 2936 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 155:
+#line 676 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 6; }
+#line 2942 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 157:
+#line 684 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0xdb, 0x00); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 16, 4); }
+#line 2948 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 158:
+#line 686 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0xd0, 0x00); F ((yyvsp[-5].regno), 20, 4); F ((yyvsp[-4].regno), 12, 2); F ((yyvsp[-1].regno), 16, 4); DSP ((yyvsp[-3].exp), 14, (yyvsp[-4].regno)); }
+#line 2954 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 159:
+#line 691 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0xe0, 0x00); F ((yyvsp[-8].regno), 20, 4); FE ((yyvsp[-6].exp), 11, 3);
+ F ((yyvsp[-2].regno), 16, 4); DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2961 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 160:
+#line 697 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0xe0, 0x0f); FE ((yyvsp[-6].exp), 11, 3); F ((yyvsp[-2].regno), 16, 4);
+ DSP ((yyvsp[-4].exp), 14, BSIZE); }
+#line 2968 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 161:
+#line 703 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x00, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 2974 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 162:
+#line 705 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x00, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 2980 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 163:
+#line 707 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x01, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 2986 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 164:
+#line 709 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x01, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 2992 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 165:
+#line 711 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x04, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 2998 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 166:
+#line 713 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x04, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3004 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 167:
+#line 715 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x05, 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3010 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 168:
+#line 717 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x05, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3016 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 169:
+#line 723 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x17, 0x00); F ((yyvsp[0].regno), 20, 4); }
+#line 3022 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 170:
+#line 725 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x17, 0x00); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 16, 1); }
+#line 3028 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 171:
+#line 727 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x17, 0x10); F ((yyvsp[0].regno), 20, 4); }
+#line 3034 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 172:
+#line 729 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x17, 0x10); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 16, 1); }
+#line 3040 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 173:
+#line 731 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x1f, 0x00); F ((yyvsp[0].regno), 20, 4); }
+#line 3046 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 174:
+#line 732 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 0; }
+#line 3052 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 176:
+#line 734 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x1f, 0x20); F ((yyvsp[0].regno), 20, 4); }
+#line 3058 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 177:
+#line 735 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 2; }
+#line 3064 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 179:
+#line 737 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x1f, 0x10); F ((yyvsp[0].regno), 20, 4); }
+#line 3070 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 180:
+#line 738 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 1; }
+#line 3076 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 182:
+#line 740 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x18, 0x00);
+ if (rx_uintop ((yyvsp[0].exp), 4) && (yyvsp[0].exp).X_add_number == 1)
+ ;
+ else if (rx_uintop ((yyvsp[0].exp), 4) && (yyvsp[0].exp).X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RACW expects #1 or #2"));}
+#line 3088 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 183:
+#line 748 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x18, 0x00); F ((yyvsp[0].regno), 16, 1);
+ if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 1)
+ ;
+ else if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RACW expects #1 or #2"));}
+#line 3100 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 184:
+#line 759 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x20, 0); F ((yyvsp[-6].regno), 14, 2); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[-5].regno), 20, 4); }
+#line 3106 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 185:
+#line 761 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x24, 0); F ((yyvsp[-6].regno), 14, 2); F ((yyvsp[-1].regno), 16, 4); F ((yyvsp[-5].regno), 20, 4); }
+#line 3112 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 186:
+#line 766 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x28, 0); F ((yyvsp[-6].regno), 14, 2); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3118 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 187:
+#line 768 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x2c, 0); F ((yyvsp[-6].regno), 14, 2); F ((yyvsp[-3].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3124 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 188:
+#line 773 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x38, 0); F ((yyvsp[-6].regno), 15, 1); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3130 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 189:
+#line 775 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x3c, 0); F ((yyvsp[-6].regno), 15, 1); F ((yyvsp[-3].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3136 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 190:
+#line 779 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 6; }
+#line 3142 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 192:
+#line 780 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 4; }
+#line 3148 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 194:
+#line 781 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 5; }
+#line 3154 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 196:
+#line 782 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 7; }
+#line 3160 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 198:
+#line 787 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) == 13)
+ rx_check_v2 ();
+ id24 (2, 0x68, 0x00); F ((yyvsp[0].regno) % 16, 20, 4); F ((yyvsp[0].regno) / 16, 15, 1);
+ F ((yyvsp[-2].regno), 16, 4); }
+#line 3169 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 199:
+#line 795 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[-2].regno) == 13)
+ rx_check_v2 ();
+ id24 (2, 0x6a, 0); F ((yyvsp[-2].regno), 15, 5); F ((yyvsp[0].regno), 20, 4); }
+#line 3177 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 200:
+#line 802 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x6e, 0); FE ((yyvsp[-2].exp), 15, 5); F ((yyvsp[0].regno), 20, 4); }
+#line 3183 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 201:
+#line 804 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x6c, 0); FE ((yyvsp[-2].exp), 15, 5); F ((yyvsp[0].regno), 20, 4); }
+#line 3189 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 202:
+#line 809 "./config/rx-parse.y" /* yacc.c:1661 */
+ { if ((yyvsp[0].regno) == 13)
+ rx_check_v2 ();
+ id24 (2, 0x73, 0x00); F ((yyvsp[0].regno), 19, 5); IMM ((yyvsp[-2].exp), 12); }
+#line 3197 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 203:
+#line 816 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0xe0, 0x00); F ((yyvsp[-4].regno), 16, 4); FE ((yyvsp[-2].exp), 11, 5);
+ F ((yyvsp[0].regno), 20, 4); }
+#line 3204 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 204:
+#line 822 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0xe0, 0xf0); FE ((yyvsp[-2].exp), 11, 5); F ((yyvsp[0].regno), 20, 4); }
+#line 3210 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 205:
+#line 827 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (3, 0x00, 0); F ((yyvsp[-7].regno), 10, 2); F ((yyvsp[-3].regno), 12, 4); F ((yyvsp[-1].regno), 16, 4); F ((yyvsp[-6].regno), 20, 4); }
+#line 3216 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 206:
+#line 830 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (3, 0x40, 0); F ((yyvsp[-7].regno), 10, 2); F ((yyvsp[-5].regno), 12, 4); F ((yyvsp[-3].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3222 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 207:
+#line 833 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (3, 0xc0, 0); F ((yyvsp[-7].regno), 10, 2); F ((yyvsp[-5].regno), 12, 4); F ((yyvsp[-3].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3228 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 208:
+#line 837 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 0; }
+#line 3234 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 210:
+#line 838 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 2; }
+#line 3240 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 212:
+#line 839 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 3; }
+#line 3246 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 214:
+#line 840 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 4; }
+#line 3252 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 216:
+#line 841 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 5; }
+#line 3258 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 218:
+#line 847 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x70, 0x20); F ((yyvsp[0].regno), 20, 4); NBIMM ((yyvsp[-2].exp), 12); }
+#line 3264 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 219:
+#line 852 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); B3 (0xfd, 0x27, 0x00); F ((yyvsp[-1].regno), 16, 4); F ((yyvsp[-4].regno), 20, 4); }
+#line 3270 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 220:
+#line 857 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); B3 (0xfd, 0x2f, 0x00); F ((yyvsp[-3].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3276 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 221:
+#line 862 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x07, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3282 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 222:
+#line 864 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x47, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3288 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 223:
+#line 866 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x03, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3294 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 224:
+#line 868 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x06, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3300 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 225:
+#line 870 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x44, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3306 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 226:
+#line 872 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x46, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3312 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 227:
+#line 874 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x45, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3318 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 228:
+#line 876 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x02, 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 1); }
+#line 3324 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 229:
+#line 877 "./config/rx-parse.y" /* yacc.c:1661 */
+ { sub_op = 3; }
+#line 3330 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 231:
+#line 879 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x17, 0x30); F ((yyvsp[0].regno), 16, 1); F ((yyvsp[-2].regno), 20, 4); }
+#line 3336 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 232:
+#line 881 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x19, 0x00); F ((yyvsp[0].regno), 16, 1);
+ if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 1)
+ ;
+ else if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RACL expects #1 or #2"));}
+#line 3348 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 233:
+#line 889 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x19, 0x40); F ((yyvsp[0].regno), 16, 1);
+ if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 1)
+ ;
+ else if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RDACL expects #1 or #2"));}
+#line 3360 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 234:
+#line 897 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (2, 0x18, 0x40); F ((yyvsp[0].regno), 16, 1);
+ if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 1)
+ ;
+ else if (rx_uintop ((yyvsp[-2].exp), 4) && (yyvsp[-2].exp).X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RDACW expects #1 or #2"));}
+#line 3372 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 235:
+#line 913 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x43 + (sub_op<<2), 0); F ((yyvsp[-2].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 3378 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 236:
+#line 915 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x40 + (sub_op<<2), 0); F ((yyvsp[-4].regno), 8, 4); F ((yyvsp[0].regno), 12, 4); DSP ((yyvsp[-6].exp), 6, BSIZE); }
+#line 3384 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 237:
+#line 917 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B3 (MEMEX, sub_op<<2, 0); F ((yyvsp[-2].regno), 8, 2); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, sizemap[(yyvsp[-2].regno)]); }
+#line 3390 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 238:
+#line 919 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (4, sub_op<<4, 0), F ((yyvsp[0].regno), 12, 4), F ((yyvsp[-4].regno), 16, 4), F ((yyvsp[-2].regno), 20, 4); }
+#line 3396 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 239:
+#line 926 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x03 + (sub_op<<2), 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3402 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 240:
+#line 928 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B4 (MEMEX, 0xa0, 0x00 + sub_op, 0x00);
+ F ((yyvsp[-4].regno), 24, 4); F ((yyvsp[0].regno), 28, 4); DSP ((yyvsp[-6].exp), 14, LSIZE); }
+#line 3409 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 241:
+#line 936 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x03 + (sub_op<<2), 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3415 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 242:
+#line 938 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x00 + (sub_op<<2), 0x00); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, BSIZE); }
+#line 3421 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 243:
+#line 940 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B4 (MEMEX, 0x20 + ((yyvsp[-2].regno) << 6), 0x00 + sub_op, 0x00);
+ F ((yyvsp[-4].regno), 24, 4); F ((yyvsp[0].regno), 28, 4); DSP ((yyvsp[-6].exp), 14, sizemap[(yyvsp[-2].regno)]); }
+#line 3428 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 244:
+#line 946 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x70, sub_op<<4); F ((yyvsp[0].regno), 20, 4); IMM ((yyvsp[-2].exp), 12); }
+#line 3434 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 249:
+#line 961 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x03 + (sub_op<<2), 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3440 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 250:
+#line 963 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x7e, sub_op2 << 4); F ((yyvsp[0].regno), 12, 4); }
+#line 3446 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 251:
+#line 968 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x4b + (sub_op2<<2), 0x00); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3452 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 252:
+#line 972 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); }
+#line 3458 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 255:
+#line 980 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x03 + (sub_op<<2), 0); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3464 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 256:
+#line 982 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x00 + (sub_op<<2), 0); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, BSIZE); }
+#line 3470 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 257:
+#line 984 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B4 (MEMEX, 0x20, 0x00 + sub_op, 0); F ((yyvsp[-2].regno), 8, 2); F ((yyvsp[-4].regno), 24, 4); F ((yyvsp[0].regno), 28, 4);
+ DSP ((yyvsp[-6].exp), 14, sizemap[(yyvsp[-2].regno)]); }
+#line 3477 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 258:
+#line 991 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x60 + sub_op, 0); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3483 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 259:
+#line 995 "./config/rx-parse.y" /* yacc.c:1661 */
+ { B2 (0x68 + (sub_op<<1), 0); FE ((yyvsp[-2].exp), 7, 5); F ((yyvsp[0].regno), 12, 4); }
+#line 3489 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 260:
+#line 997 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x80 + (sub_op << 5), 0); FE ((yyvsp[-4].exp), 11, 5); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3495 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 262:
+#line 1003 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ((yyvsp[0].regno), 20, 4); O4 ((yyvsp[-2].exp)); }
+#line 3501 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 263:
+#line 1005 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3507 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 264:
+#line 1007 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, LSIZE); }
+#line 3513 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 265:
+#line 1009 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); id24 (4, 0x80 + (sub_op << 4), 0 ); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[-2].regno), 20, 4); F ((yyvsp[0].regno), 12, 4); }
+#line 3519 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 266:
+#line 1013 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); }
+#line 3525 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 267:
+#line 1015 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x72, sub_op << 4); F ((yyvsp[0].regno), 20, 4); O4 ((yyvsp[-2].exp)); }
+#line 3531 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 269:
+#line 1020 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); }
+#line 3537 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 270:
+#line 1022 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x83 + (sub_op << 2), 0); F ((yyvsp[-2].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); }
+#line 3543 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 271:
+#line 1023 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_float_support (); }
+#line 3549 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 272:
+#line 1025 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (1, 0x80 + (sub_op << 2), 0); F ((yyvsp[-4].regno), 16, 4); F ((yyvsp[0].regno), 20, 4); DSP ((yyvsp[-6].exp), 14, LSIZE); }
+#line 3555 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 273:
+#line 1029 "./config/rx-parse.y" /* yacc.c:1661 */
+ { rx_check_v2 (); }
+#line 3561 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 274:
+#line 1031 "./config/rx-parse.y" /* yacc.c:1661 */
+ { id24 (2, 0x1e, sub_op << 4); F ((yyvsp[0].regno), 20, 4); F ((yyvsp[-2].regno), 16, 1);
+ if (rx_uintop ((yyvsp[-4].exp), 4))
+ {
+ switch (exp_val ((yyvsp[-4].exp)))
+ {
+ case 0:
+ F (1, 15, 1);
+ break;
+ case 1:
+ F (1, 15, 1);
+ F (1, 17, 1);
+ break;
+ case 2:
+ break;
+ default:
+ as_bad (_("IMM expects #0 to #2"));}
+ } else
+ as_bad (_("IMM expects #0 to #2"));}
+#line 3584 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 275:
+#line 1053 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.exp) = zero_expr (); }
+#line 3590 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 276:
+#line 1054 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.exp) = (yyvsp[0].exp); }
+#line 3596 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 277:
+#line 1057 "./config/rx-parse.y" /* yacc.c:1661 */
+ { need_flag = 1; }
+#line 3602 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 278:
+#line 1057 "./config/rx-parse.y" /* yacc.c:1661 */
+ { need_flag = 0; (yyval.regno) = (yyvsp[0].regno); }
+#line 3608 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 279:
+#line 1062 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; }
+#line 3614 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 280:
+#line 1063 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3620 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 281:
+#line 1064 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3626 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 282:
+#line 1065 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 2; }
+#line 3632 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 283:
+#line 1066 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 3; }
+#line 3638 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 284:
+#line 1069 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = LSIZE; }
+#line 3644 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 285:
+#line 1070 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = BSIZE; }
+#line 3650 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 286:
+#line 1071 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = WSIZE; }
+#line 3656 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 287:
+#line 1072 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = LSIZE; }
+#line 3662 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 288:
+#line 1075 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3668 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 289:
+#line 1076 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 0; }
+#line 3674 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 290:
+#line 1077 "./config/rx-parse.y" /* yacc.c:1661 */
+ { (yyval.regno) = 1; }
+#line 3680 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 291:
+#line 1080 "./config/rx-parse.y" /* yacc.c:1661 */
+ {}
+#line 3686 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 292:
+#line 1081 "./config/rx-parse.y" /* yacc.c:1661 */
+ {}
+#line 3692 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 293:
+#line 1084 "./config/rx-parse.y" /* yacc.c:1661 */
+ {}
+#line 3698 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+ case 294:
+#line 1085 "./config/rx-parse.y" /* yacc.c:1661 */
+ {}
+#line 3704 "rx-parse.c" /* yacc.c:1661 */
+ break;
+
+
+#line 3708 "rx-parse.c" /* yacc.c:1661 */
+ default: break;
+ }
+ /* User semantic actions sometimes alter yychar, and that requires
+ that yytoken be updated with the new translation. We take the
+ approach of translating immediately before every use of yytoken.
+ One alternative is translating here after every semantic action,
+ but that translation would be missed if the semantic action invokes
+ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
+ incorrect destructor might then be invoked immediately. In the
+ case of YYERROR or YYBACKUP, subsequent parser actions might lead
+ to an incorrect destructor call or verbose syntax error message
+ before the lookahead is translated. */
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+ /* Now 'shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*--------------------------------------.
+| yyerrlab -- here on detecting error. |
+`--------------------------------------*/
+yyerrlab:
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+ yyssp, yytoken)
+ {
+ char const *yymsgp = YY_("syntax error");
+ int yysyntax_error_status;
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ if (yysyntax_error_status == 0)
+ yymsgp = yymsg;
+ else if (yysyntax_error_status == 1)
+ {
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+ if (!yymsg)
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ yysyntax_error_status = 2;
+ }
+ else
+ {
+ yysyntax_error_status = YYSYNTAX_ERROR;
+ yymsgp = yymsg;
+ }
+ }
+ yyerror (yymsgp);
+ if (yysyntax_error_status == 2)
+ goto yyexhaustedlab;
+ }
+# undef YYSYNTAX_ERROR
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse lookahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse lookahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (!yypact_value_is_default (yyn))
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
+ *++yyvsp = yylval;
+ YY_IGNORE_MAYBE_UNINITIALIZED_END
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#if !defined yyoverflow || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEMPTY)
+ {
+ /* Make sure we have latest lookahead translation. See comments at
+ user semantic actions for why this is necessary. */
+ yytoken = YYTRANSLATE (yychar);
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ }
+ /* Do not reclaim the symbols of the rule whose action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ return yyresult;
+}
+#line 1088 "./config/rx-parse.y" /* yacc.c:1906 */
+
+/* ====================================================================== */
+
+static struct
+{
+ const char * string;
+ int token;
+ int val;
+}
+token_table[] =
+{
+ { "r0", REG, 0 },
+ { "r1", REG, 1 },
+ { "r2", REG, 2 },
+ { "r3", REG, 3 },
+ { "r4", REG, 4 },
+ { "r5", REG, 5 },
+ { "r6", REG, 6 },
+ { "r7", REG, 7 },
+ { "r8", REG, 8 },
+ { "r9", REG, 9 },
+ { "r10", REG, 10 },
+ { "r11", REG, 11 },
+ { "r12", REG, 12 },
+ { "r13", REG, 13 },
+ { "r14", REG, 14 },
+ { "r15", REG, 15 },
+
+ { "psw", CREG, 0 },
+ { "pc", CREG, 1 },
+ { "usp", CREG, 2 },
+ { "fpsw", CREG, 3 },
+ /* reserved */
+ /* reserved */
+ /* reserved */
+ { "wr", CREG, 7 },
+
+ { "bpsw", CREG, 8 },
+ { "bpc", CREG, 9 },
+ { "isp", CREG, 10 },
+ { "fintv", CREG, 11 },
+ { "intb", CREG, 12 },
+ { "extb", CREG, 13 },
+
+ { "pbp", CREG, 16 },
+ { "pben", CREG, 17 },
+
+ { "bbpsw", CREG, 24 },
+ { "bbpc", CREG, 25 },
+
+ { ".s", DOT_S, 0 },
+ { ".b", DOT_B, 0 },
+ { ".w", DOT_W, 0 },
+ { ".l", DOT_L, 0 },
+ { ".a", DOT_A , 0},
+ { ".ub", DOT_UB, 0 },
+ { ".uw", DOT_UW , 0},
+
+ { "c", FLAG, 0 },
+ { "z", FLAG, 1 },
+ { "s", FLAG, 2 },
+ { "o", FLAG, 3 },
+ { "i", FLAG, 8 },
+ { "u", FLAG, 9 },
+
+ { "a0", ACC, 0 },
+ { "a1", ACC, 1 },
+
+#define OPC(x) { #x, x, IS_OPCODE }
+ OPC(ABS),
+ OPC(ADC),
+ OPC(ADD),
+ { "and", AND_, IS_OPCODE },
+ OPC(BCLR),
+ OPC(BCND),
+ OPC(BMCND),
+ OPC(BNOT),
+ OPC(BRA),
+ OPC(BRK),
+ OPC(BSET),
+ OPC(BSR),
+ OPC(BTST),
+ OPC(CLRPSW),
+ OPC(CMP),
+ OPC(DBT),
+ OPC(DIV),
+ OPC(DIVU),
+ OPC(EDIV),
+ OPC(EDIVU),
+ OPC(EMACA),
+ OPC(EMSBA),
+ OPC(EMUL),
+ OPC(EMULA),
+ OPC(EMULU),
+ OPC(FADD),
+ OPC(FCMP),
+ OPC(FDIV),
+ OPC(FMUL),
+ OPC(FREIT),
+ OPC(FSQRT),
+ OPC(FTOU),
+ OPC(FSUB),
+ OPC(FTOI),
+ OPC(INT),
+ OPC(ITOF),
+ OPC(JMP),
+ OPC(JSR),
+ OPC(MVFACGU),
+ OPC(MVFACHI),
+ OPC(MVFACMI),
+ OPC(MVFACLO),
+ OPC(MVFC),
+ OPC(MVTACGU),
+ OPC(MVTACHI),
+ OPC(MVTACLO),
+ OPC(MVTC),
+ OPC(MVTIPL),
+ OPC(MACHI),
+ OPC(MACLO),
+ OPC(MACLH),
+ OPC(MAX),
+ OPC(MIN),
+ OPC(MOV),
+ OPC(MOVCO),
+ OPC(MOVLI),
+ OPC(MOVU),
+ OPC(MSBHI),
+ OPC(MSBLH),
+ OPC(MSBLO),
+ OPC(MUL),
+ OPC(MULHI),
+ OPC(MULLH),
+ OPC(MULLO),
+ OPC(MULU),
+ OPC(NEG),
+ OPC(NOP),
+ OPC(NOT),
+ OPC(OR),
+ OPC(POP),
+ OPC(POPC),
+ OPC(POPM),
+ OPC(PUSH),
+ OPC(PUSHA),
+ OPC(PUSHC),
+ OPC(PUSHM),
+ OPC(RACL),
+ OPC(RACW),
+ OPC(RDACL),
+ OPC(RDACW),
+ OPC(REIT),
+ OPC(REVL),
+ OPC(REVW),
+ OPC(RMPA),
+ OPC(ROLC),
+ OPC(RORC),
+ OPC(ROTL),
+ OPC(ROTR),
+ OPC(ROUND),
+ OPC(RTE),
+ OPC(RTFI),
+ OPC(RTS),
+ OPC(RTSD),
+ OPC(SAT),
+ OPC(SATR),
+ OPC(SBB),
+ OPC(SCCND),
+ OPC(SCMPU),
+ OPC(SETPSW),
+ OPC(SHAR),
+ OPC(SHLL),
+ OPC(SHLR),
+ OPC(SMOVB),
+ OPC(SMOVF),
+ OPC(SMOVU),
+ OPC(SSTR),
+ OPC(STNZ),
+ OPC(STOP),
+ OPC(STZ),
+ OPC(SUB),
+ OPC(SUNTIL),
+ OPC(SWHILE),
+ OPC(TST),
+ OPC(UTOF),
+ OPC(WAIT),
+ OPC(XCHG),
+ OPC(XOR),
+};
+
+#define NUM_TOKENS (sizeof (token_table) / sizeof (token_table[0]))
+
+static struct
+{
+ const char * string;
+ int token;
+}
+condition_opcode_table[] =
+{
+ { "b", BCND },
+ { "bm", BMCND },
+ { "sc", SCCND },
+};
+
+#define NUM_CONDITION_OPCODES (sizeof (condition_opcode_table) / sizeof (condition_opcode_table[0]))
+
+static struct
+{
+ const char * string;
+ int val;
+}
+condition_table[] =
+{
+ { "z", 0 },
+ { "eq", 0 },
+ { "geu", 2 },
+ { "c", 2 },
+ { "gtu", 4 },
+ { "pz", 6 },
+ { "ge", 8 },
+ { "gt", 10 },
+ { "o", 12},
+ /* always = 14 */
+ { "nz", 1 },
+ { "ne", 1 },
+ { "ltu", 3 },
+ { "nc", 3 },
+ { "leu", 5 },
+ { "n", 7 },
+ { "lt", 9 },
+ { "le", 11 },
+ { "no", 13 }
+ /* never = 15 */
+};
+
+#define NUM_CONDITIONS (sizeof (condition_table) / sizeof (condition_table[0]))
+
+void
+rx_lex_init (char * beginning, char * ending)
+{
+ rx_init_start = beginning;
+ rx_lex_start = beginning;
+ rx_lex_end = ending;
+ rx_in_brackets = 0;
+ rx_last_token = 0;
+
+ setbuf (stdout, 0);
+}
+
+static int
+check_condition (const char * base)
+{
+ char * cp;
+ unsigned int i;
+
+ if ((unsigned) (rx_lex_end - rx_lex_start) < strlen (base) + 1)
+ return 0;
+ if (memcmp (rx_lex_start, base, strlen (base)))
+ return 0;
+ cp = rx_lex_start + strlen (base);
+ for (i = 0; i < NUM_CONDITIONS; i ++)
+ {
+ if (strcasecmp (cp, condition_table[i].string) == 0)
+ {
+ rx_lval.regno = condition_table[i].val;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int
+rx_lex (void)
+{
+ unsigned int ci;
+ char * save_input_pointer;
+
+ while (ISSPACE (*rx_lex_start)
+ && rx_lex_start != rx_lex_end)
+ rx_lex_start ++;
+
+ rx_last_exp_start = rx_lex_start;
+
+ if (rx_lex_start == rx_lex_end)
+ return 0;
+
+ if (ISALPHA (*rx_lex_start)
+ || (rx_pid_register != -1 && memcmp (rx_lex_start, "%pidreg", 7) == 0)
+ || (rx_gp_register != -1 && memcmp (rx_lex_start, "%gpreg", 6) == 0)
+ || (*rx_lex_start == '.' && ISALPHA (rx_lex_start[1])))
+ {
+ unsigned int i;
+ char * e;
+ char save;
+
+ for (e = rx_lex_start + 1;
+ e < rx_lex_end && ISALNUM (*e);
+ e ++)
+ ;
+ save = *e;
+ *e = 0;
+
+ if (strcmp (rx_lex_start, "%pidreg") == 0)
+ {
+ {
+ rx_lval.regno = rx_pid_register;
+ *e = save;
+ rx_lex_start = e;
+ rx_last_token = REG;
+ return REG;
+ }
+ }
+
+ if (strcmp (rx_lex_start, "%gpreg") == 0)
+ {
+ {
+ rx_lval.regno = rx_gp_register;
+ *e = save;
+ rx_lex_start = e;
+ rx_last_token = REG;
+ return REG;
+ }
+ }
+
+ if (rx_last_token == 0)
+ for (ci = 0; ci < NUM_CONDITION_OPCODES; ci ++)
+ if (check_condition (condition_opcode_table[ci].string))
+ {
+ *e = save;
+ rx_lex_start = e;
+ rx_last_token = condition_opcode_table[ci].token;
+ return condition_opcode_table[ci].token;
+ }
+
+ for (i = 0; i < NUM_TOKENS; i++)
+ if (strcasecmp (rx_lex_start, token_table[i].string) == 0
+ && !(token_table[i].val == IS_OPCODE && rx_last_token != 0)
+ && !(token_table[i].token == FLAG && !need_flag))
+ {
+ rx_lval.regno = token_table[i].val;
+ *e = save;
+ rx_lex_start = e;
+ rx_last_token = token_table[i].token;
+ return token_table[i].token;
+ }
+ *e = save;
+ }
+
+ if (rx_last_token == 0)
+ {
+ rx_last_token = UNKNOWN_OPCODE;
+ return UNKNOWN_OPCODE;
+ }
+
+ if (rx_last_token == UNKNOWN_OPCODE)
+ return 0;
+
+ if (*rx_lex_start == '[')
+ rx_in_brackets = 1;
+ if (*rx_lex_start == ']')
+ rx_in_brackets = 0;
+
+ if (rx_in_brackets
+ || rx_last_token == REG
+ || strchr ("[],#", *rx_lex_start))
+ {
+ rx_last_token = *rx_lex_start;
+ return *rx_lex_start ++;
+ }
+
+ save_input_pointer = input_line_pointer;
+ input_line_pointer = rx_lex_start;
+ rx_lval.exp.X_md = 0;
+ expression (&rx_lval.exp);
+
+ /* We parse but ignore any :<size> modifier on expressions. */
+ if (*input_line_pointer == ':')
+ {
+ char *cp;
+
+ for (cp = input_line_pointer + 1; *cp && cp < rx_lex_end; cp++)
+ if (!ISDIGIT (*cp))
+ break;
+ if (cp > input_line_pointer+1)
+ input_line_pointer = cp;
+ }
+
+ rx_lex_start = input_line_pointer;
+ input_line_pointer = save_input_pointer;
+ rx_last_token = EXPR;
+ return EXPR;
+}
+
+int
+rx_error (const char * str)
+{
+ int len;
+
+ len = rx_last_exp_start - rx_init_start;
+
+ as_bad ("%s", rx_init_start);
+ as_bad ("%*s^ %s", len, "", str);
+ return 0;
+}
+
+static int
+rx_intop (expressionS exp, int nbits, int opbits)
+{
+ long v;
+ long mask, msb;
+
+ if (exp.X_op == O_big)
+ {
+ if (nbits == 32)
+ return 1;
+ if (exp.X_add_number == -1)
+ return 0;
+ }
+ else if (exp.X_op != O_constant)
+ return 0;
+ v = exp.X_add_number;
+
+ msb = 1UL << (opbits - 1);
+ mask = (1UL << opbits) - 1;
+
+ if ((v & msb) && ! (v & ~mask))
+ v -= 1UL << opbits;
+
+ switch (nbits)
+ {
+ case 4:
+ return -0x8 <= v && v <= 0x7;
+ case 5:
+ return -0x10 <= v && v <= 0x17;
+ case 8:
+ return -0x80 <= v && v <= 0x7f;
+ case 16:
+ return -0x8000 <= v && v <= 0x7fff;
+ case 24:
+ return -0x800000 <= v && v <= 0x7fffff;
+ case 32:
+ return 1;
+ default:
+ printf ("rx_intop passed %d\n", nbits);
+ abort ();
+ }
+ return 1;
+}
+
+static int
+rx_uintop (expressionS exp, int nbits)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 0;
+ v = exp.X_add_number;
+
+ switch (nbits)
+ {
+ case 4:
+ return v <= 0xf;
+ case 8:
+ return v <= 0xff;
+ case 16:
+ return v <= 0xffff;
+ case 24:
+ return v <= 0xffffff;
+ default:
+ printf ("rx_uintop passed %d\n", nbits);
+ abort ();
+ }
+ return 1;
+}
+
+static int
+rx_disp3op (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 0;
+ v = exp.X_add_number;
+ if (v < 3 || v > 10)
+ return 0;
+ return 1;
+}
+
+static int
+rx_disp5op (expressionS * exp, int msize)
+{
+ long v;
+
+ if (exp->X_op != O_constant)
+ return 0;
+ v = exp->X_add_number;
+
+ switch (msize)
+ {
+ case BSIZE:
+ if (0 <= v && v <= 31)
+ return 1;
+ break;
+ case WSIZE:
+ if (v & 1)
+ return 0;
+ if (0 <= v && v <= 63)
+ {
+ exp->X_add_number >>= 1;
+ return 1;
+ }
+ break;
+ case LSIZE:
+ if (v & 3)
+ return 0;
+ if (0 <= v && v <= 127)
+ {
+ exp->X_add_number >>= 2;
+ return 1;
+ }
+ break;
+ }
+ return 0;
+}
+
+/* Just like the above, but allows a zero displacement. */
+
+static int
+rx_disp5op0 (expressionS * exp, int msize)
+{
+ if (exp->X_op != O_constant)
+ return 0;
+ if (exp->X_add_number == 0)
+ return 1;
+ return rx_disp5op (exp, msize);
+}
+
+static int
+exp_val (expressionS exp)
+{
+ if (exp.X_op != O_constant)
+ {
+ rx_error (_("constant expected"));
+ return 0;
+ }
+ return exp.X_add_number;
+}
+
+static expressionS
+zero_expr (void)
+{
+ /* Static, so program load sets it to all zeros, which is what we want. */
+ static expressionS zero;
+ zero.X_op = O_constant;
+ return zero;
+}
+
+static int
+immediate (expressionS exp, int type, int pos, int bits)
+{
+ /* We will emit constants ourself here, so negate them. */
+ if (type == RXREL_NEGATIVE && exp.X_op == O_constant)
+ exp.X_add_number = - exp.X_add_number;
+ if (type == RXREL_NEGATIVE_BORROW)
+ {
+ if (exp.X_op == O_constant)
+ exp.X_add_number = - exp.X_add_number - 1;
+ else
+ rx_error (_("sbb cannot use symbolic immediates"));
+ }
+
+ if (rx_intop (exp, 8, bits))
+ {
+ rx_op (exp, 1, type);
+ return 1;
+ }
+ else if (rx_intop (exp, 16, bits))
+ {
+ rx_op (exp, 2, type);
+ return 2;
+ }
+ else if (rx_uintop (exp, 16) && bits == 16)
+ {
+ rx_op (exp, 2, type);
+ return 2;
+ }
+ else if (rx_intop (exp, 24, bits))
+ {
+ rx_op (exp, 3, type);
+ return 3;
+ }
+ else if (rx_intop (exp, 32, bits))
+ {
+ rx_op (exp, 4, type);
+ return 0;
+ }
+ else if (type == RXREL_SIGNED)
+ {
+ /* This is a symbolic immediate, we will relax it later. */
+ rx_relax (RX_RELAX_IMM, pos);
+ rx_op (exp, linkrelax ? 4 : 1, type);
+ return 1;
+ }
+ else
+ {
+ /* Let the linker deal with it. */
+ rx_op (exp, 4, type);
+ return 0;
+ }
+}
+
+static int
+displacement (expressionS exp, int msize)
+{
+ int val;
+ int vshift = 0;
+
+ if (exp.X_op == O_symbol
+ && exp.X_md)
+ {
+ switch (exp.X_md)
+ {
+ case BFD_RELOC_GPREL16:
+ switch (msize)
+ {
+ case BSIZE:
+ exp.X_md = BFD_RELOC_RX_GPRELB;
+ break;
+ case WSIZE:
+ exp.X_md = BFD_RELOC_RX_GPRELW;
+ break;
+ case LSIZE:
+ exp.X_md = BFD_RELOC_RX_GPRELL;
+ break;
+ }
+ O2 (exp);
+ return 2;
+ }
+ }
+
+ if (exp.X_op == O_subtract)
+ {
+ exp.X_md = BFD_RELOC_RX_DIFF;
+ O2 (exp);
+ return 2;
+ }
+
+ if (exp.X_op != O_constant)
+ {
+ rx_error (_("displacements must be constants"));
+ return -1;
+ }
+ val = exp.X_add_number;
+
+ if (val == 0)
+ return 0;
+
+ switch (msize)
+ {
+ case BSIZE:
+ break;
+ case WSIZE:
+ if (val & 1)
+ rx_error (_("word displacement not word-aligned"));
+ vshift = 1;
+ break;
+ case LSIZE:
+ if (val & 3)
+ rx_error (_("long displacement not long-aligned"));
+ vshift = 2;
+ break;
+ default:
+ as_bad (_("displacement with unknown size (internal bug?)\n"));
+ break;
+ }
+
+ val >>= vshift;
+ exp.X_add_number = val;
+
+ if (0 <= val && val <= 255 )
+ {
+ O1 (exp);
+ return 1;
+ }
+
+ if (0 <= val && val <= 65535)
+ {
+ O2 (exp);
+ return 2;
+ }
+ if (val < 0)
+ rx_error (_("negative displacements not allowed"));
+ else
+ rx_error (_("displacement too large"));
+ return -1;
+}
+
+static void
+rtsd_immediate (expressionS exp)
+{
+ int val;
+
+ if (exp.X_op != O_constant)
+ {
+ rx_error (_("rtsd size must be constant"));
+ return;
+ }
+ val = exp.X_add_number;
+ if (val & 3)
+ rx_error (_("rtsd size must be multiple of 4"));
+
+ if (val < 0 || val > 1020)
+ rx_error (_("rtsd size must be 0..1020"));
+
+ val >>= 2;
+ exp.X_add_number = val;
+ O1 (exp);
+}
+
+static void
+rx_range (expressionS exp, int minv, int maxv)
+{
+ int val;
+
+ if (exp.X_op != O_constant)
+ return;
+
+ val = exp.X_add_number;
+ if (val < minv || val > maxv)
+ as_warn (_("Value %d out of range %d..%d"), val, minv, maxv);
+}
+
+static void
+rx_check_float_support (void)
+{
+ if (rx_cpu == RX100 || rx_cpu == RX200)
+ rx_error (_("target CPU type does not support floating point instructions"));
+}
+
+static void
+rx_check_v2 (void)
+{
+ if (rx_cpu < RXV2)
+ rx_error (_("target CPU type does not support v2 instructions"));
+}
diff --git a/gas/rx-parse.h b/gas/rx-parse.h
new file mode 100644
index 0000000..3880b2e
--- /dev/null
+++ b/gas/rx-parse.h
@@ -0,0 +1,335 @@
+/* A Bison parser, made by GNU Bison 3.0. */
+
+/* Bison interface for Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+#ifndef YY_RX_RX_PARSE_H_INCLUDED
+# define YY_RX_RX_PARSE_H_INCLUDED
+/* Debug traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+#if YYDEBUG
+extern int rx_debug;
+#endif
+
+/* Token type. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ enum yytokentype
+ {
+ REG = 258,
+ FLAG = 259,
+ CREG = 260,
+ ACC = 261,
+ EXPR = 262,
+ UNKNOWN_OPCODE = 263,
+ IS_OPCODE = 264,
+ DOT_S = 265,
+ DOT_B = 266,
+ DOT_W = 267,
+ DOT_L = 268,
+ DOT_A = 269,
+ DOT_UB = 270,
+ DOT_UW = 271,
+ ABS = 272,
+ ADC = 273,
+ ADD = 274,
+ AND_ = 275,
+ BCLR = 276,
+ BCND = 277,
+ BMCND = 278,
+ BNOT = 279,
+ BRA = 280,
+ BRK = 281,
+ BSET = 282,
+ BSR = 283,
+ BTST = 284,
+ CLRPSW = 285,
+ CMP = 286,
+ DBT = 287,
+ DIV = 288,
+ DIVU = 289,
+ EDIV = 290,
+ EDIVU = 291,
+ EMACA = 292,
+ EMSBA = 293,
+ EMUL = 294,
+ EMULA = 295,
+ EMULU = 296,
+ FADD = 297,
+ FCMP = 298,
+ FDIV = 299,
+ FMUL = 300,
+ FREIT = 301,
+ FSUB = 302,
+ FSQRT = 303,
+ FTOI = 304,
+ FTOU = 305,
+ INT = 306,
+ ITOF = 307,
+ JMP = 308,
+ JSR = 309,
+ MACHI = 310,
+ MACLH = 311,
+ MACLO = 312,
+ MAX = 313,
+ MIN = 314,
+ MOV = 315,
+ MOVCO = 316,
+ MOVLI = 317,
+ MOVU = 318,
+ MSBHI = 319,
+ MSBLH = 320,
+ MSBLO = 321,
+ MUL = 322,
+ MULHI = 323,
+ MULLH = 324,
+ MULLO = 325,
+ MULU = 326,
+ MVFACHI = 327,
+ MVFACGU = 328,
+ MVFACMI = 329,
+ MVFACLO = 330,
+ MVFC = 331,
+ MVTACGU = 332,
+ MVTACHI = 333,
+ MVTACLO = 334,
+ MVTC = 335,
+ MVTIPL = 336,
+ NEG = 337,
+ NOP = 338,
+ NOT = 339,
+ OR = 340,
+ POP = 341,
+ POPC = 342,
+ POPM = 343,
+ PUSH = 344,
+ PUSHA = 345,
+ PUSHC = 346,
+ PUSHM = 347,
+ RACL = 348,
+ RACW = 349,
+ RDACL = 350,
+ RDACW = 351,
+ REIT = 352,
+ REVL = 353,
+ REVW = 354,
+ RMPA = 355,
+ ROLC = 356,
+ RORC = 357,
+ ROTL = 358,
+ ROTR = 359,
+ ROUND = 360,
+ RTE = 361,
+ RTFI = 362,
+ RTS = 363,
+ RTSD = 364,
+ SAT = 365,
+ SATR = 366,
+ SBB = 367,
+ SCCND = 368,
+ SCMPU = 369,
+ SETPSW = 370,
+ SHAR = 371,
+ SHLL = 372,
+ SHLR = 373,
+ SMOVB = 374,
+ SMOVF = 375,
+ SMOVU = 376,
+ SSTR = 377,
+ STNZ = 378,
+ STOP = 379,
+ STZ = 380,
+ SUB = 381,
+ SUNTIL = 382,
+ SWHILE = 383,
+ TST = 384,
+ UTOF = 385,
+ WAIT = 386,
+ XCHG = 387,
+ XOR = 388
+ };
+#endif
+/* Tokens. */
+#define REG 258
+#define FLAG 259
+#define CREG 260
+#define ACC 261
+#define EXPR 262
+#define UNKNOWN_OPCODE 263
+#define IS_OPCODE 264
+#define DOT_S 265
+#define DOT_B 266
+#define DOT_W 267
+#define DOT_L 268
+#define DOT_A 269
+#define DOT_UB 270
+#define DOT_UW 271
+#define ABS 272
+#define ADC 273
+#define ADD 274
+#define AND_ 275
+#define BCLR 276
+#define BCND 277
+#define BMCND 278
+#define BNOT 279
+#define BRA 280
+#define BRK 281
+#define BSET 282
+#define BSR 283
+#define BTST 284
+#define CLRPSW 285
+#define CMP 286
+#define DBT 287
+#define DIV 288
+#define DIVU 289
+#define EDIV 290
+#define EDIVU 291
+#define EMACA 292
+#define EMSBA 293
+#define EMUL 294
+#define EMULA 295
+#define EMULU 296
+#define FADD 297
+#define FCMP 298
+#define FDIV 299
+#define FMUL 300
+#define FREIT 301
+#define FSUB 302
+#define FSQRT 303
+#define FTOI 304
+#define FTOU 305
+#define INT 306
+#define ITOF 307
+#define JMP 308
+#define JSR 309
+#define MACHI 310
+#define MACLH 311
+#define MACLO 312
+#define MAX 313
+#define MIN 314
+#define MOV 315
+#define MOVCO 316
+#define MOVLI 317
+#define MOVU 318
+#define MSBHI 319
+#define MSBLH 320
+#define MSBLO 321
+#define MUL 322
+#define MULHI 323
+#define MULLH 324
+#define MULLO 325
+#define MULU 326
+#define MVFACHI 327
+#define MVFACGU 328
+#define MVFACMI 329
+#define MVFACLO 330
+#define MVFC 331
+#define MVTACGU 332
+#define MVTACHI 333
+#define MVTACLO 334
+#define MVTC 335
+#define MVTIPL 336
+#define NEG 337
+#define NOP 338
+#define NOT 339
+#define OR 340
+#define POP 341
+#define POPC 342
+#define POPM 343
+#define PUSH 344
+#define PUSHA 345
+#define PUSHC 346
+#define PUSHM 347
+#define RACL 348
+#define RACW 349
+#define RDACL 350
+#define RDACW 351
+#define REIT 352
+#define REVL 353
+#define REVW 354
+#define RMPA 355
+#define ROLC 356
+#define RORC 357
+#define ROTL 358
+#define ROTR 359
+#define ROUND 360
+#define RTE 361
+#define RTFI 362
+#define RTS 363
+#define RTSD 364
+#define SAT 365
+#define SATR 366
+#define SBB 367
+#define SCCND 368
+#define SCMPU 369
+#define SETPSW 370
+#define SHAR 371
+#define SHLL 372
+#define SHLR 373
+#define SMOVB 374
+#define SMOVF 375
+#define SMOVU 376
+#define SSTR 377
+#define STNZ 378
+#define STOP 379
+#define STZ 380
+#define SUB 381
+#define SUNTIL 382
+#define SWHILE 383
+#define TST 384
+#define UTOF 385
+#define WAIT 386
+#define XCHG 387
+#define XOR 388
+
+/* Value type. */
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE YYSTYPE;
+union YYSTYPE
+{
+#line 135 "./config/rx-parse.y" /* yacc.c:1915 */
+
+ int regno;
+ expressionS exp;
+
+#line 325 "rx-parse.h" /* yacc.c:1915 */
+};
+# define YYSTYPE_IS_TRIVIAL 1
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+extern YYSTYPE rx_lval;
+
+int rx_parse (void);
+
+#endif /* !YY_RX_RX_PARSE_H_INCLUDED */
generated by cgit v1.1 at 2024-11-22 07:55:55 +0000