[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>

where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
	and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
	for AARCH64_OPND_QLF_imm_tag.
	(operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
	(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
	for both offset and pre/post indexed versions.
	(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Exempt STGP.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
	stzg, stz2g and stgp.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.

6 files changed, 140 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 784a638..57a3c38 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,17 @@
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
+	* config/tc-aarch64.c (parse_operands): Add switch case for
+	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
+	(fix_insn): Likewise.
+	(warn_unpredictable_ldst): Exempt STGP.
+	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
+	stzg, stz2g and stgp.
+	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
+	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
 	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
 	subps and cmpp.
 	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5f79e92..a5eee96 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6214,6 +6214,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
 	case AARCH64_OPND_ADDR_SIMM9:
 	case AARCH64_OPND_ADDR_SIMM9_2:
+	case AARCH64_OPND_ADDR_SIMM11:
+	case AARCH64_OPND_ADDR_SIMM13:
 	  po_misc_or_fail (parse_address (&str, info));
 	  if (info->addr.pcrel || info->addr.offset.is_reg
 	      || (!info->addr.preind && !info->addr.postind)
@@ -6773,6 +6775,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
 	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
 	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
 	  && opnds[2].addr.base_regno != REG_SP
+	  /* Exempt STGP.  */
+	  && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
 	  && opnds[2].addr.writeback)
 	    as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       /* Load operations must load different registers.  */
@@ -7674,6 +7678,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
     case AARCH64_OPND_ADDR_SIMM9_2:
     case AARCH64_OPND_ADDR_SIMM10:
     case AARCH64_OPND_ADDR_UIMM12:
+    case AARCH64_OPND_ADDR_SIMM11:
+    case AARCH64_OPND_ADDR_SIMM13:
       /* Immediate offset in an address.  */
       insn = get_aarch64_insn (buf);
 
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index a7cb6c4..4140646 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -55,3 +55,61 @@ Disassembly of section \.text:
 .*:	badb037f 	cmpp	x27, x27
 .*:	bac003ff 	cmpp	sp, x0
 .*:	badf001f 	cmpp	x0, sp
+.*:	d920081f 	stg	\[x0\]
+.*:	d9200b7f 	stg	\[x27\]
+.*:	d93fb81f 	stg	\[x0, #-80\]
+.*:	d9200c1f 	stg	\[x0, #0\]!
+.*:	d920ac1f 	stg	\[x0, #160\]!
+.*:	d920041f 	stg	\[x0\], #0
+.*:	d93a641f 	stg	\[x0\], #-1440
+.*:	d92ffbff 	stg	\[sp, #4080\]
+.*:	d9300bff 	stg	\[sp, #-4096\]
+.*:	d92fffff 	stg	\[sp, #4080\]!
+.*:	d93007ff 	stg	\[sp\], #-4096
+.*:	d960081f 	stzg	\[x0\]
+.*:	d9600b7f 	stzg	\[x27\]
+.*:	d97fb81f 	stzg	\[x0, #-80\]
+.*:	d9600c1f 	stzg	\[x0, #0\]!
+.*:	d960ac1f 	stzg	\[x0, #160\]!
+.*:	d960041f 	stzg	\[x0\], #0
+.*:	d97a641f 	stzg	\[x0\], #-1440
+.*:	d96ffbff 	stzg	\[sp, #4080\]
+.*:	d9700bff 	stzg	\[sp, #-4096\]
+.*:	d96fffff 	stzg	\[sp, #4080\]!
+.*:	d97007ff 	stzg	\[sp\], #-4096
+.*:	d9a0081f 	st2g	\[x0\]
+.*:	d9a00b7f 	st2g	\[x27\]
+.*:	d9bfb81f 	st2g	\[x0, #-80\]
+.*:	d9a00c1f 	st2g	\[x0, #0\]!
+.*:	d9a0ac1f 	st2g	\[x0, #160\]!
+.*:	d9a0041f 	st2g	\[x0\], #0
+.*:	d9ba641f 	st2g	\[x0\], #-1440
+.*:	d9affbff 	st2g	\[sp, #4080\]
+.*:	d9b00bff 	st2g	\[sp, #-4096\]
+.*:	d9afffff 	st2g	\[sp, #4080\]!
+.*:	d9b007ff 	st2g	\[sp\], #-4096
+.*:	d9e0081f 	stz2g	\[x0\]
+.*:	d9e00b7f 	stz2g	\[x27\]
+.*:	d9ffb81f 	stz2g	\[x0, #-80\]
+.*:	d9e00c1f 	stz2g	\[x0, #0\]!
+.*:	d9e0ac1f 	stz2g	\[x0, #160\]!
+.*:	d9e0041f 	stz2g	\[x0\], #0
+.*:	d9fa641f 	stz2g	\[x0\], #-1440
+.*:	d9effbff 	stz2g	\[sp, #4080\]
+.*:	d9f00bff 	stz2g	\[sp, #-4096\]
+.*:	d9efffff 	stz2g	\[sp, #4080\]!
+.*:	d9f007ff 	stz2g	\[sp\], #-4096
+.*:	69000000 	stgp	x0, x0, \[x0\]
+.*:	69006c00 	stgp	x0, x27, \[x0\]
+.*:	6900001b 	stgp	x27, x0, \[x0\]
+.*:	69006c1b 	stgp	x27, x27, \[x0\]
+.*:	69000360 	stgp	x0, x0, \[x27\]
+.*:	693d8000 	stgp	x0, x0, \[x0, #-80\]
+.*:	69800000 	stgp	x0, x0, \[x0, #0\]!
+.*:	69850000 	stgp	x0, x0, \[x0, #160\]!
+.*:	68800000 	stgp	x0, x0, \[x0\], #0
+.*:	68bb8000 	stgp	x0, x0, \[x0\], #-144
+.*:	691f801f 	stgp	xzr, x0, \[x0, #1008\]
+.*:	69207c00 	stgp	x0, xzr, \[x0, #-1024\]
+.*:	699f83e0 	stgp	x0, x0, \[sp, #1008\]!
+.*:	68a003e0 	stgp	x0, x0, \[sp\], #-1024
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index f17f87e..729dae6 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -16,6 +16,20 @@ func:
 	\op x27, x27, #0, #0
 	.endm
 
+	.macro expand_stg op
+	\op [x0, #0]
+	\op [x27, #0]
+	\op [x0, #-80]
+	\op [x0, #0]!
+	\op [x0, #160]!
+	\op [x0], #0
+	\op [x0], #-1440
+	\op [sp, #4080]
+	\op [sp, #-4096]
+	\op [sp, #4080]!
+	\op [sp], #-4096
+	.endm
+
 	# IRG
 	expand_3_reg irg
 	irg sp, x0
@@ -55,3 +69,23 @@ func:
 	cmpp x27, x27
 	cmpp sp, x0
 	cmpp x0, sp
+
+	expand_stg stg
+	expand_stg stzg
+	expand_stg st2g
+	expand_stg stz2g
+
+	stgp x0, x0, [x0, #0]
+	stgp x0, x27, [x0, #0]
+	stgp x27, x0, [x0, #0]
+	stgp x27, x27, [x0, #0]
+	stgp x0, x0, [x27, #0]
+	stgp x0, x0, [x0, #-80]
+	stgp x0, x0, [x0, #0]!
+	stgp x0, x0, [x0, #160]!
+	stgp x0, x0, [x0], #0
+	stgp x0, x0, [x0], #-144
+	stgp xzr, x0, [x0, #1008]
+	stgp x0, xzr, [x0, #-1024]
+	stgp x0, x0, [sp, #1008]!
+	stgp x0, x0, [sp], #-1024
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 4da0c35..dd568cc 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -4,6 +4,12 @@
 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
 [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
 [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
+[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
+[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
+[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
+[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
 [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
 [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
 [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -20,3 +26,10 @@
 [^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
 [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
 [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
+[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 7eab07f..2a66366 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -8,6 +8,16 @@ func:
 	addg x1, x2, #0x3f0, #0x10
 	subg x1, x2, #0x3f0, -4
 
+	# STG/STZG/ST2G : Fail imm
+	stg [x1, #15]
+	stzg [x1, #-4097]!
+	st2g [x1], #4096
+
+	# STGP : Fail imm
+	stgp x1, x2, [x3, #1009]
+	stgp x1, x2, [x3, #33]
+	stgp x1, x2, [x3, #-1025]
+
 	# Illegal SP/XZR registers
 	irg xzr, x2, x3
 	irg x1, xzr, x3
@@ -25,3 +35,10 @@ func:
 	subps x1, x2, xzr
 	cmpp xzr, x2
 	cmpp x2, xzr
+	stg [xzr, #0]
+	st2g [xzr, #0]!
+	stzg [xzr], #0
+	stz2g [xzr, #0]
+	stgp sp, x2, [x3]
+	stgp x1, sp, [x3]
+	stgp x0, x0, [xzr]