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authorJan Beulich <jbeulich@novell.com>2018-04-26 08:30:06 +0200
committerJan Beulich <jbeulich@suse.com>2018-04-26 08:30:06 +0200
commit2f1bada2dc2e7215cd633b6c39a6c31dbd875bc0 (patch)
tree9cdf4c97da8b6e792181ea59c0ceb4376f3f53c4 /gas
parentdcd7e323760ab296262a2e18e9869d37ff59f340 (diff)
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x86: drop VexImmExt
It's only used in assertions, and hence not really needed for correct code generation.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-i386.c10
2 files changed, 8 insertions, 7 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7cd0a10..2691eb8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2018-04-26 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (build_modrm_byte): Drop .veximmext uses.
+ Move part of the remaining assertion.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
* config/tc-i386.c (build_modrm_byte): Extend assertion in
vex_3_sources handling to cover more cases.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7126ca4..2ddbe19 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6573,9 +6573,6 @@ build_modrm_byte (void)
unsigned int nds, reg_slot;
expressionS *exp;
- gas_assert (!i.tm.opcode_modifier.veximmext
- || !i.tm.opcode_modifier.immext);
-
dest = i.operands - 1;
nds = dest - 1;
@@ -6585,13 +6582,10 @@ build_modrm_byte (void)
VexW0 or VexW1. The destination must be either XMM, YMM or
ZMM register.
2. 4 operands: 4 register operands or 3 register operands
- plus 1 memory operand, VexXDS, and VexImmExt */
+ plus 1 memory operand, with VexXDS. */
gas_assert ((i.reg_operands == 4
|| (i.reg_operands == 3 && i.mem_operands == 1))
&& i.tm.opcode_modifier.vexvvvv == VEXXDS
- && (i.tm.opcode_modifier.veximmext
- || (i.imm_operands == 1
- && i.types[0].bitfield.vec_imm4))
&& i.tm.opcode_modifier.vexw
&& i.tm.operand_types[dest].bitfield.regsimd);
@@ -6625,6 +6619,8 @@ build_modrm_byte (void)
{
unsigned int imm_slot;
+ gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
+
if (i.tm.opcode_modifier.vexw == VEXW0)
{
/* If VexW0 is set, the third operand is the source and