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| author | Nick Clifton <nickc@redhat.com> | 1998-01-29 00:41:46 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 1998-01-29 00:41:46 +0000 |
| commit | 79420f9af93ad2a3d4562e625857988c5ea1ce02 (patch) | |
| tree | 961f9c79d658054db884c125422941a76f75fe6b /gas | |
| parent | ed29580469374a53b995b74181b5c4f5fc9db516 (diff) | |
| download | gdb-79420f9af93ad2a3d4562e625857988c5ea1ce02.zip gdb-79420f9af93ad2a3d4562e625857988c5ea1ce02.tar.gz gdb-79420f9af93ad2a3d4562e625857988c5ea1ce02.tar.bz2 | |
Sanitization fixes.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/config/tc-m32r.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c index 7232d4b..b634944 100644 --- a/gas/config/tc-m32r.c +++ b/gas/config/tc-m32r.c @@ -475,6 +475,7 @@ can_make_parallel (a, b) m32r_insn * a; m32r_insn * b; { +/* start-sanitize-m32rx */ PIPE_ATTR a_pipe; PIPE_ATTR b_pipe; @@ -495,6 +496,7 @@ can_make_parallel (a, b) || b_pipe == PIPE_O) return "Instructions share the same execution pipeline"; +/* end-sanitize-m32rx */ if ( writes_to_dest_reg (a->insn) && writes_to_dest_reg (b->insn) && (get_dest_reg (a->fields) == get_dest_reg (b->fields))) @@ -561,7 +563,8 @@ assemble_parallel_insn (str, str2) as_bad (errmsg); return; } - + +/* start-sanitize-m32rx */ /* Check to see if this is an allowable parallel insn. */ if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) { @@ -575,6 +578,7 @@ assemble_parallel_insn (str, str2) as_bad ("instruction '%s' is for the M32RX only", str); return; } +/* end-sanitize-m32rx */ *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ str3 = str; /* Save the original string pointer. */ @@ -592,6 +596,7 @@ assemble_parallel_insn (str, str2) return; } +/* start-sanitize-m32rx */ /* Check it. */ if (! enable_m32rx && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) @@ -609,6 +614,7 @@ assemble_parallel_insn (str, str2) return; } } +/* end-sanitize-m32rx */ /* We assume that if the first instruction writes to a register that is read by the second instruction it is because the programmer intended |