New port: National Semiconductor's CR16

89 files changed, 7274 insertions, 8 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c7f3fea..bacf2bc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+2007-06-29  M R Swami Reddy  <MR.Swami.Redd@nsc.com>
+
+	* Makefile.am: Add CR16 related entry.
+	* Makefile.in: Regenerate.
+	* config/tc-cr16.h: New file
+	* config/tc-cr16.c: New file
+	* doc/c-cr16.texi: New file for cr16 
+	* doc/all.texi: Entry for cr16 
+	* doc/Makefile.am: Added c-cr16.texi
+	* doc/Makefile.in: Regenerate 
+	* doc/as.texinfo: Entry for CR16 target
+	* NEWS: Announce the support for the new target.
+
 2007-06-26  Paul Brook  <paul@codesourcery.com>
 
 	* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 7b82979..1567d4e 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -48,6 +48,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -240,6 +241,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -294,6 +296,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -1053,6 +1056,11 @@ DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
   $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
   $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
@@ -1482,6 +1490,11 @@ DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
   $(INCDIR)/obstack.h
@@ -1838,6 +1851,11 @@ DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
   $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
diff --git a/gas/Makefile.in b/gas/Makefile.in
index 2ed2297..5618cc9 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -293,6 +293,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -483,6 +484,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -537,6 +539,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -824,6 +827,12 @@ DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
   $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
 
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
+
 DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
@@ -1332,6 +1341,12 @@ DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
+DEPOBJ_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+
 DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
   $(INCDIR)/obstack.h
@@ -1767,6 +1782,12 @@ DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h
 
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
@@ -2124,15 +2145,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
 	    *$$dep*) \
-	      echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
-	      cd $(srcdir) && $(AUTOMAKE) --cygnus  \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
+	      cd $(srcdir) && $(AUTOMAKE) --foreign  \
 		&& exit 0; \
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --cygnus  Makefile
+	  $(AUTOMAKE) --foreign  Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
diff --git a/gas/NEWS b/gas/NEWS
index 0dcb8f3..bf278ef 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,4 +1,6 @@
 -*- text -*-
+* Support for the National Semiconductor CR16 target has been added.
+
 * Added gas .reloc pseudo.  This is a low-level interface for creating
   relocations.
 
diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c
new file mode 100644
index 0000000..2c4c6a4
--- /dev/null
+++ b/gas/config/tc-cr16.c
@@ -0,0 +1,2444 @@
+/* tc-cr16.c -- Assembler code for the CR16 CPU core.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "dwarf2dbg.h"
+#include "opcode/cr16.h"
+#include "elf/cr16.h"
+
+
+/* Word is considered here as a 16-bit unsigned short int.  */
+#define WORD_SHIFT  16
+
+/* Register is 2-byte size.  */
+#define REG_SIZE   2
+
+/* Maximum size of a single instruction (in words).  */
+#define INSN_MAX_SIZE   3
+
+/* Maximum bits which may be set in a `mask16' operand.  */
+#define MAX_REGS_IN_MASK16  8
+
+/* Assign a number NUM, shifted by SHIFT bytes, into a location
+   pointed by index BYTE of array 'output_opcode'.  */
+#define CR16_PRINT(BYTE, NUM, SHIFT)   output_opcode[BYTE] |= (NUM << SHIFT)
+
+/* Operand errors.  */
+typedef enum
+  {
+    OP_LEGAL = 0,       /* Legal operand.  */
+    OP_OUT_OF_RANGE,    /* Operand not within permitted range.  */
+    OP_NOT_EVEN         /* Operand is Odd number, should be even.  */
+  }
+op_err;
+
+/* Opcode mnemonics hash table.  */
+static struct hash_control *cr16_inst_hash;
+/* CR16 registers hash table.  */
+static struct hash_control *reg_hash;
+/* CR16 register pair hash table.  */
+static struct hash_control *regp_hash;
+/* CR16 processor registers hash table.  */
+static struct hash_control *preg_hash;
+/* CR16 processor registers 32 bit hash table.  */
+static struct hash_control *pregp_hash;
+/* Current instruction we're assembling.  */
+const inst *instruction;
+
+
+static int code_label = 0;
+
+/* Global variables.  */
+
+/* Array to hold an instruction encoding.  */
+long output_opcode[2];
+
+/* Nonzero means a relocatable symbol.  */
+int relocatable;
+
+/* A copy of the original instruction (used in error messages).  */
+char ins_parse[MAX_INST_LEN];
+
+/* The current processed argument number.  */
+int cur_arg_num;
+
+/* Generic assembler global variables which must be defined by all targets.  */
+
+/* Characters which always start a comment.  */
+const char comment_chars[] = "#";
+
+/* Characters which start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* This array holds machine specific line separator characters.  */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums.  */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant as in 0f12.456  */
+const char FLT_CHARS[] = "f'";
+
+/* Target-specific multicharacter options, not const-declared at usage.  */
+const char *md_shortopts = "";
+struct option md_longopts[] =
+{
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+static void
+l_cons (int nbytes)
+{
+  int c;
+  expressionS exp;
+
+#ifdef md_flush_pending_output
+    md_flush_pending_output ();
+#endif
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+#ifdef TC_ADDRESS_BYTES
+  if (nbytes == 0)
+    nbytes = TC_ADDRESS_BYTES ();
+#endif
+
+#ifdef md_cons_align
+  md_cons_align (nbytes);
+#endif
+
+  c = 0;
+  do
+    {
+      unsigned int bits_available = BITS_PER_CHAR * nbytes;
+      char *hold = input_line_pointer;
+
+      expression (&exp);
+
+      if (*input_line_pointer == ':')
+	{
+	  /* Bitfields.  */
+	  long value = 0;
+
+	  for (;;)
+	    {
+	      unsigned long width;
+
+	      if (*input_line_pointer != ':')
+		{
+		  input_line_pointer = hold;
+		  break;
+		}
+	      if (exp.X_op == O_absent)
+		{
+		  as_warn (_("using a bit field width of zero"));
+		  exp.X_add_number = 0;
+		  exp.X_op = O_constant;
+		}
+
+	      if (exp.X_op != O_constant)
+		{
+		  *input_line_pointer = '\0';
+		  as_bad (_("field width \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = ':';
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      if ((width = exp.X_add_number) >
+		  (unsigned int)(BITS_PER_CHAR * nbytes))
+		{
+		  as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
+		  width = BITS_PER_CHAR * nbytes;
+		}                   /* Too big.  */
+
+
+	      if (width > bits_available)
+		{
+		  /* FIXME-SOMEDAY: backing up and reparsing is wasteful.  */
+		  input_line_pointer = hold;
+		  exp.X_add_number = value;
+		  break;
+		}
+
+	      /* Skip ':'.  */
+	      hold = ++input_line_pointer;
+
+	      expression (&exp);
+	      if (exp.X_op != O_constant)
+		{
+		  char cache = *input_line_pointer;
+
+		  *input_line_pointer = '\0';
+		  as_bad (_("field value \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = cache;
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      value |= ((~(-1 << width) & exp.X_add_number)
+			<< ((BITS_PER_CHAR * nbytes) - bits_available));
+
+	      if ((bits_available -= width) == 0
+		  || is_it_end_of_statement ()
+		  || *input_line_pointer != ',')
+		break;
+
+	      hold = ++input_line_pointer;
+	      expression (&exp);
+	    }
+
+	  exp.X_add_number = value;
+	  exp.X_op = O_constant;
+	  exp.X_unsigned = 1;
+	}
+
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	code_label = 1;
+      emit_expr (&exp, (unsigned int) nbytes);
+      ++c;
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	{
+	  input_line_pointer +=3;
+	  break;
+	}
+    }
+  while ((*input_line_pointer++ == ','));
+
+  /* Put terminator back into stream.  */
+  input_line_pointer--;
+
+  demand_empty_rest_of_line ();
+}
+
+
+/* This table describes all the machine specific pseudo-ops
+   the assembler has to support.  The fields are:
+   *** Pseudo-op name without dot.
+   *** Function to call to execute this pseudo-op.
+   *** Integer arg to pass to the function.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* In CR16 machine, align is in bytes (not a ptwo boundary).  */
+  {"align", s_align_bytes, 0},
+  {"long", l_cons,  4 },
+  {0, 0, 0}
+};
+
+/* CR16 relaxation table.  */
+const relax_typeS md_relax_table[] =
+{
+  /* bCC  */
+  {0xfa, -0x100, 2, 1},                 /*  8 */
+  {0xfffe, -0x10000, 4, 2},             /* 16 */
+  {0xfffffe, -0x1000000, 6, 0},         /* 24 */
+};
+
+/* Return the bit size for a given operand.  */
+
+static int
+get_opbits (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].bit_size;
+
+  return 0;
+}
+
+/* Return the argument type of a given operand.  */
+
+static argtype
+get_optype (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].arg_type;
+  else
+    return nullargs;
+}
+
+/* Return the flags of a given operand.  */
+
+static int
+get_opflags (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].flags;
+
+  return 0;
+}
+
+/* Get the cc code.  */
+
+static int
+get_cc (char *cc_name)
+{
+   unsigned int i;
+
+   for (i = 0; i < cr16_num_cc; i++)
+     if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0)
+       return i;
+
+   return -1;
+}
+
+/* Get the core processor register 'reg_name'.  */
+
+static reg
+get_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor register-pair 'reg_name'.  */
+
+static reg
+get_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+  char tmp_rp[16]="\0";
+
+  /* Add '(' and ')' to the reg pair, if its not present.  */
+  if (reg_name[0] != '(') 
+    {
+      tmp_rp[0] = '(';
+      strcat (tmp_rp, reg_name);
+      strcat (tmp_rp,")");
+      reg = (const reg_entry *) hash_find (regp_hash, tmp_rp);
+    }
+  else
+    reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+} 
+
+/* Get the index register 'reg_name'.  */
+
+static reg
+get_index_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if ((reg != NULL)
+      && ((reg->value.reg_val == 12) || (reg->value.reg_val == 13)))
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor index register-pair 'reg_name'.  */
+
+static reg
+get_index_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    {
+      if ((reg->value.reg_val != 1) || (reg->value.reg_val != 7)
+	  || (reg->value.reg_val != 9) || (reg->value.reg_val > 10))
+	return reg->value.reg_val;
+
+      as_bad (_("Unknown register pair - index relative mode: `%d'"), reg->value.reg_val);
+    }
+
+  return nullregister;
+}
+
+/* Get the processor register 'preg_name'.  */
+
+static preg
+get_pregister (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (preg_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+/* Get the processor register 'preg_name 32 bit'.  */
+
+static preg
+get_pregisterp (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (pregp_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+
+/* Round up a section size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT val)
+{
+  /* Round .text section to a multiple of 2.  */
+  if (seg == text_section)
+    return (val + 1) & ~1;
+  return val;
+}
+
+/* Parse an operand that is machine-specific (remove '*').  */
+
+void
+md_operand (expressionS * exp)
+{
+  char c = *input_line_pointer;
+
+  switch (c)
+    {
+    case '*':
+      input_line_pointer++;
+      expression (exp);
+      break;
+    default:
+      break;
+    }
+}
+
+/* Reset global variables before parsing a new instruction.  */
+
+static void
+reset_vars (char *op)
+{
+  cur_arg_num = relocatable = 0;
+  memset (& output_opcode, '\0', sizeof (output_opcode));
+
+  /* Save a copy of the original OP (used in error messages).  */
+  strncpy (ins_parse, op, sizeof ins_parse - 1);
+  ins_parse [sizeof ins_parse - 1] = 0;
+}
+
+/* This macro decides whether a particular reloc is an entry in a
+   switch table.  It is used when relaxing, because the linker needs
+   to know about all such entries so that it can adjust them if
+   necessary.  */
+
+#define SWITCH_TABLE(fix)                                  \
+  (   (fix)->fx_addsy != NULL                              \
+   && (fix)->fx_subsy != NULL                              \
+   && S_GET_SEGMENT ((fix)->fx_addsy) ==                   \
+      S_GET_SEGMENT ((fix)->fx_subsy)                      \
+   && S_GET_SEGMENT (fix->fx_addsy) != undefined_section   \
+   && (   (fix)->fx_r_type == BFD_RELOC_CR16_NUM8          \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a))
+
+/* See whether we need to force a relocation into the output file.
+   This is used to force out switch and PC relative relocations when
+   relaxing.  */
+
+int
+cr16_force_relocation (fixS *fix)
+{
+  /* REVISIT: Check if the "SWITCH_TABLE (fix)" should be added
+     if (generic_force_reloc (fix) || SWITCH_TABLE (fix))  */
+  if (generic_force_reloc (fix))
+    return 1;
+
+  return 0;
+}
+
+/* Record a fixup for a cons expression.  */
+
+void
+cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp)
+{
+  int rtype;
+  switch (len)
+    {
+    default: rtype = BFD_RELOC_NONE; break;
+    case 1: rtype = BFD_RELOC_CR16_NUM8 ; break;
+    case 2: rtype = BFD_RELOC_CR16_NUM16; break;
+    case 4:
+      if (code_label)
+	{
+	  rtype = BFD_RELOC_CR16_NUM32a;
+	  code_label = 0;
+	}
+      else
+	rtype = BFD_RELOC_CR16_NUM32;
+      break;
+    }
+
+  fix_new_exp (frag, offset, len, exp, 0, rtype);
+}
+
+/* Generate a relocation entry for a fixup.  */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
+{
+  arelent * reloc;
+
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+  reloc->addend = fixP->fx_offset;
+
+  if (fixP->fx_subsy != NULL)
+    {
+      if (SWITCH_TABLE (fixP))
+        {
+          /* Keep the current difference in the addend.  */
+          reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
+                           - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
+
+          switch (fixP->fx_r_type)
+            {
+	    case BFD_RELOC_CR16_NUM8:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM8;
+	      break;
+	    case BFD_RELOC_CR16_NUM16:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM16;
+	      break;
+	    case BFD_RELOC_CR16_NUM32:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32;
+	      break;
+	    case BFD_RELOC_CR16_NUM32a:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32a;
+	      break;
+	    default:
+	      abort ();
+	      break;
+            }
+        }
+      else
+        {
+          /* We only resolve difference expressions in the same section.  */
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+                        fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+                        segment_name (fixP->fx_addsy
+                                      ? S_GET_SEGMENT (fixP->fx_addsy)
+                                      : absolute_section),
+                        S_GET_NAME (fixP->fx_subsy),
+                        segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
+        }
+    }
+
+  assert ((int) fixP->fx_r_type > 0);
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+                    _("internal error: reloc %d (`%s') not supported by object file format"),
+                    fixP->fx_r_type,
+                    bfd_get_reloc_code_name (fixP->fx_r_type));
+      return NULL;
+    }
+  assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+  return reloc;
+}
+
+/* Prepare machine-dependent frags for relaxation.  */
+
+int
+md_estimate_size_before_relax (fragS *fragp, asection *seg)
+{
+  /* If symbol is undefined or located in a different section,
+     select the largest supported relocation.  */
+  relax_substateT subtype;
+  relax_substateT rlx_state[] = {0, 2};
+
+  for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
+    {
+      if (fragp->fr_subtype == rlx_state[subtype]
+          && (!S_IS_DEFINED (fragp->fr_symbol)
+              || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+        {
+          fragp->fr_subtype = rlx_state[subtype + 1];
+          break;
+        }
+    }
+
+  if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
+    abort ();
+
+  return md_relax_table[fragp->fr_subtype].rlx_length;
+}
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
+{
+  /* 'opcode' points to the start of the instruction, whether
+     we need to change the instruction's fixed encoding.  */
+  bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
+
+  subseg_change (sec, 0);
+
+  fix_new (fragP, fragP->fr_fix,
+           bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
+           fragP->fr_symbol, fragP->fr_offset, 1, reloc);
+  fragP->fr_var = 0;
+  fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+/* Process machine-dependent command line options.  Called once for
+   each option on the command line that the machine-independent part of
+   GAS does not understand.  */
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Machine-dependent usage-output.  */
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+  return;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  int i;
+  LITTLENUM_TYPE words[4];
+  char *t;
+
+  switch (type)
+    {
+      case 'f':
+        prec = 2;
+        break;
+
+      case 'd':
+        prec = 4;
+        break;
+
+      default:
+        *sizeP = 0;
+        return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  if (! target_big_endian)
+    {
+      for (i = prec - 1; i >= 0; i--)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+  else
+    {
+      for (i = 0; i < prec; i++)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+
+  return NULL;
+}
+
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+   enough info to complete immediately) to the data in a frag.
+   Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
+   relaxation of debug sections, this function is called only when
+   fixuping relocations of debug sections.  */
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  valueT val = * valP;
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+  fixP->fx_offset = 0;
+
+  switch (fixP->fx_r_type)
+    {
+      case BFD_RELOC_CR16_NUM8:
+        bfd_put_8 (stdoutput, (unsigned char) val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM16:
+        bfd_put_16 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32a:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      default:
+        /* We shouldn't ever get here because linkrelax is nonzero.  */
+        abort ();
+        break;
+    }
+
+  fixP->fx_done = 0;
+
+  if (fixP->fx_addsy == NULL
+      && fixP->fx_pcrel == 0)
+    fixP->fx_done = 1;
+
+  if (fixP->fx_pcrel == 1
+      && fixP->fx_addsy != NULL
+      && S_GET_SEGMENT (fixP->fx_addsy) == seg)
+    fixP->fx_done = 1;
+}
+
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+static void
+initialise_reg_hash_table (struct hash_control ** hash_table,
+			   const reg_entry * register_table,
+			   const unsigned int num_entries)
+{
+  const reg_entry * reg;
+  const char *hashret;
+
+  if ((* hash_table = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  for (reg = register_table;
+       reg < (register_table + num_entries);
+       reg++)
+    {
+      hashret = hash_insert (* hash_table, reg->name, (char *) reg);
+      if (hashret)
+	as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		  reg->name, hashret);
+    }
+}
+
+/* This function is called once, at assembler startup time.  This should
+   set up all the tables, etc that the MD part of the assembler needs.  */
+
+void
+md_begin (void)
+{
+  int i = 0;
+
+  /* Set up a hash table for the instructions.  */
+  if ((cr16_inst_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  while (cr16_instruction[i].mnemonic != NULL)
+    {
+      const char *hashret;
+      const char *mnemonic = cr16_instruction[i].mnemonic;
+
+      hashret = hash_insert (cr16_inst_hash, mnemonic,
+			     (char *)(cr16_instruction + i));
+
+      if (hashret != NULL && *hashret != '\0')
+        as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic,
+                  *hashret == 0 ? _("(unknown reason)") : hashret);
+
+      /* Insert unique names into hash table.  The CR16 instruction set
+         has many identical opcode names that have different opcodes based
+         on the operands.  This hash table then provides a quick index to
+         the first opcode with a particular name in the opcode table.  */
+      do
+        {
+          ++i;
+        }
+      while (cr16_instruction[i].mnemonic != NULL
+             && streq (cr16_instruction[i].mnemonic, mnemonic));
+    }
+
+  /* Initialize reg_hash hash table.  */
+  initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS);
+  /* Initialize regp_hash hash table.  */
+  initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS);
+  /* Initialize preg_hash hash table.  */
+  initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS);
+  /* Initialize pregp_hash hash table.  */
+  initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS);
+
+  /*  Set linkrelax here to avoid fixups in most sections.  */
+  linkrelax = 1;
+}
+
+/* Process constants (immediate/absolute)
+   and labels (jump targets/Memory locations).  */
+
+static void
+process_label_constant (char *str, ins * cr16_ins)
+{
+  char *saved_input_line_pointer;
+  int symbol_with_at = 0;
+  int symbol_with_s = 0;
+  int symbol_with_m = 0;
+  int symbol_with_l = 0;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num;  /* Current argument.  */
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
+
+  expression (&cr16_ins->exp);
+
+  switch (cr16_ins->exp.X_op)
+    {
+    case O_big:
+    case O_absent:
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      str);
+      cr16_ins->exp.X_op = O_constant;
+      cr16_ins->exp.X_add_number = 0;
+      cr16_ins->exp.X_add_symbol = NULL;
+      cr16_ins->exp.X_op_symbol = NULL;
+      /* Fall through.  */
+
+    case O_constant:
+      cur_arg->X_op = O_constant;
+      cur_arg->constant = cr16_ins->exp.X_add_number;
+      break;
+
+    case O_symbol:
+    case O_subtract:
+    case O_add:
+      cur_arg->X_op = O_symbol;
+      cr16_ins->rtype = BFD_RELOC_NONE;
+      relocatable = 1;
+
+      if (strneq (input_line_pointer, "@c", 2))
+	symbol_with_at = 1;
+
+      if (strneq (input_line_pointer, "@l", 2)
+	  || strneq (input_line_pointer, ":l", 2))
+	symbol_with_l = 1;
+
+      if (strneq (input_line_pointer, "@m", 2)
+	  || strneq (input_line_pointer, ":m", 2))
+	symbol_with_m = 1;
+
+      if (strneq (input_line_pointer, "@s", 2)
+	  || strneq (input_line_pointer, ":s", 2))
+	symbol_with_s = 1;
+
+      switch (cur_arg->type)
+        {
+	case arg_cr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (cur_arg->size == 20)
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+	    }
+	  break;
+
+	case arg_crp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1:
+		switch (cur_arg->size)
+		  {
+		  case 0:
+		    cr16_ins->rtype = BFD_RELOC_CR16_REGREL0;
+		    break;
+		  case 4:
+		    if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4;
+		    else
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a;
+		    break;
+		  default: break;
+		  }
+		break;
+	      case 2:
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL16;
+		break;
+	      case 3:
+		if (cur_arg->size == 20)
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+		else
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+		break;
+	      default:
+		break;
+	      }
+	  break;
+
+	case arg_idxr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	  break;
+
+	case arg_idxrp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break;
+	      case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break;
+	      case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break;
+	      default: break;
+	      }
+	  break;
+
+	case arg_c:
+	  if (IS_INSN_MNEMONIC ("bal"))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	  else if (IS_INSN_TYPE (BRANCH_INS))
+	    {
+	      if (symbol_with_s)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP8;
+	      else if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP16;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	    }
+	  else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS)
+		   || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (symbol_with_s)
+		as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str);
+	      if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS20;
+	      else /* Default to (symbol_with_l) */
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS24;
+	    }
+	  else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP4;
+          break;
+
+        case arg_ic:
+          if (IS_INSN_TYPE (ARITH_INS))
+            {
+              if (symbol_with_s)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM4;
+              else if (symbol_with_m)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM20;
+              else if (symbol_with_at)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32a;
+              else /* Default to (symbol_with_l) */
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32;
+            }
+          else if (IS_INSN_TYPE (ARITH_BYTE_INS))
+	    {
+	      cr16_ins->rtype = BFD_RELOC_CR16_IMM16;
+	    }
+          break;
+        default:
+          break;
+	}
+      break;
+
+    default:
+      cur_arg->X_op = cr16_ins->exp.X_op;
+      break;
+    }
+
+  input_line_pointer = saved_input_line_pointer;
+  return;
+}
+
+/* Retrieve the opcode image of a given register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int is_procreg = 0; /* Nonzero means argument should be processor reg.  */
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regtab + r;
+  else /* Register not found.  */
+    {
+      as_bad (_("Unknown register: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register is illegal.  */
+#define IMAGE_ERR \
+  as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                            \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_R_REGTYPE:
+      if (! is_procreg)
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CR16_P_REGTYPE:
+      return reg->image;
+      break;
+
+    default:
+      IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Parsing different types of operands
+   -> constants             Immediate/Absolute/Relative numbers
+   -> Labels                Relocatable symbols
+   -> (reg pair base)       Register pair base
+   -> (rbase)               Register base
+   -> disp(rbase)           Register relative
+   -> [rinx]disp(reg pair)  Register index with reg pair mode
+   -> disp(rbase,ridx,scl)  Register index mode.  */
+
+static void
+set_operand (char *operand, ins * cr16_ins)
+{
+  char *operandS; /* Pointer to start of sub-opearand.  */
+  char *operandE; /* Pointer to end of sub-opearand.  */
+
+  argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument.  */
+
+  /* Initialize pointers.  */
+  operandS = operandE = operand;
+
+  switch (cur_arg->type)
+    {
+    case arg_ic:    /* Case $0x18.  */
+      operandS++;
+    case arg_c:     /* Case 0x18.  */
+      /* Set constant.  */
+      process_label_constant (operandS, cr16_ins);
+
+      if (cur_arg->type != arg_ic)
+        cur_arg->type = arg_c;
+      break;
+
+    case arg_icr:   /* Case $0x18(r1).  */
+      operandS++;
+    case arg_cr:    /* Case 0x18(r1).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+    case arg_rbase: /* Case (r1) or (r1,r0).  */
+      operandS++;
+      /* Set register base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->r = get_register (operandS)) == nullregister)
+         as_bad (_("Illegal register `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+
+      /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
+      if ((cur_arg->type != arg_rbase)
+	  && ((getreg_image (cur_arg->r) == 12)
+	      || (getreg_image (cur_arg->r) == 13)
+	      || (getreg_image (cur_arg->r) == 14)
+	      || (getreg_image (cur_arg->r) == 15)))
+         {
+           cur_arg->type = arg_crp;
+           cur_arg->rp = cur_arg->r;
+         }
+      break;
+
+    case arg_crp:    /* Case 0x18(r1,r0).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+      operandS++;
+      /* Set register pair base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->rp = get_register_pair (operandS)) == nullregister)
+         as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+      break;
+
+    case arg_idxr:
+      /* Set register pair base.  */
+      if ((strchr (operandS,'(') != NULL))
+        {
+         while ((*operandE != '(') && (! ISSPACE (*operandE)))
+           operandE++;
+         if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister)
+              as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+                            operandS, ins_parse);
+         *operandE++ = '\0';
+         cur_arg->type = arg_idxrp;
+        }
+      else
+	cur_arg->rp = -1;
+
+       operandE = operandS;
+      /* Set displacement constant.  */
+      while (*operandE != ']')
+        operandE++;
+      process_label_constant (++operandE, cr16_ins);
+      *operandE++ = '\0';
+      operandE = operandS;
+
+      /* Set index register .  */
+      operandS = strchr (operandE,'[');
+      if (operandS != NULL)
+        { /* Eliminate '[', detach from rest of operand.  */
+          *operandS++ = '\0';
+
+          operandE = strchr (operandS, ']');
+
+          if (operandE == NULL)
+            as_bad (_("unmatched '['"));
+          else
+            { /* Eliminate ']' and make sure it was the last thing
+                 in the string.  */
+              *operandE = '\0';
+              if (*(operandE + 1) != '\0')
+                as_bad (_("garbage after index spec ignored"));
+            }
+        }
+
+      if ((cur_arg->i_r = get_index_register (operandS)) == nullregister)
+        as_bad (_("Illegal register `%s' in Instruction `%s'"),
+                operandS, ins_parse);
+      *operandE = '\0';
+      *operandS = '\0';
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Parse a single operand.
+   operand - Current operand to parse.
+   cr16_ins - Current assembled instruction.  */
+
+static void
+parse_operand (char *operand, ins * cr16_ins)
+{
+  int ret_val;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument.  */
+
+  /* Initialize the type to NULL before parsing.  */
+  cur_arg->type = nullargs;
+
+  /* Check whether this is a condition code .  */
+  if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1))
+    {
+      cur_arg->type = arg_cc;
+      cur_arg->cc = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a general processor register.  */
+  if ((ret_val = get_register (operand)) != nullregister)
+    {
+      cur_arg->type = arg_r;
+      cur_arg->r = ret_val;
+      cur_arg->X_op = 0;
+      return;
+    }
+
+  /* Check whether this is a general processor register pair.  */
+  if ((operand[0] == '(')
+      && ((ret_val = get_register_pair (operand)) != nullregister))
+    {
+      cur_arg->type = arg_rp;
+      cur_arg->rp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether the operand is a processor register.
+     For "lprd" and "sprd" instruction, only 32 bit
+     processor registers used.  */
+  if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
+      && ((ret_val = get_pregister (operand)) != nullpregister))
+    {
+      cur_arg->type = arg_pr;
+      cur_arg->pr = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a processor register - 32 bit.  */
+  if ((ret_val = get_pregisterp (operand)) != nullpregister)
+    {
+      cur_arg->type = arg_prp;
+      cur_arg->prp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Deal with special characters.  */
+  switch (operand[0])
+    {
+    case '$':
+      if (strchr (operand, '(') != NULL)
+	cur_arg->type = arg_icr;
+      else
+	cur_arg->type = arg_ic;
+      goto set_params;
+      break;
+
+    case '(':
+      cur_arg->type = arg_rbase;
+      goto set_params;
+      break;
+
+    case '[':
+      cur_arg->type = arg_idxr;
+      goto set_params;
+      break;
+
+    default:
+      break;
+    }
+
+  if (strchr (operand, '(') != NULL)
+    {
+      if (strchr (operand, ',') != NULL
+          && (strchr (operand, ',') > strchr (operand, '(')))
+        cur_arg->type = arg_crp;
+      else
+        cur_arg->type = arg_cr;
+    }
+  else
+    cur_arg->type = arg_c;
+
+/* Parse an operand according to its type.  */
+ set_params:
+  cur_arg->constant = 0;
+  set_operand (operand, cr16_ins);
+}
+
+/* Parse the various operands. Each operand is then analyzed to fillup
+   the fields in the cr16_ins data structure.  */
+
+static void
+parse_operands (ins * cr16_ins, char *operands)
+{
+  char *operandS;            /* Operands string.  */
+  char *operandH, *operandT; /* Single operand head/tail pointers.  */
+  int allocated = 0;         /* Indicates a new operands string was allocated.*/
+  char *operand[MAX_OPERANDS];/* Separating the operands.  */
+  int op_num = 0;             /* Current operand number we are parsing.  */
+  int bracket_flag = 0;       /* Indicates a bracket '(' was found.  */
+  int sq_bracket_flag = 0;    /* Indicates a square bracket '[' was found.  */
+
+  /* Preprocess the list of registers, if necessary.  */
+  operandS = operandH = operandT = operands;
+
+  while (*operandT != '\0')
+    {
+      if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
+        {
+          *operandT++ = '\0';
+          operand[op_num++] = strdup (operandH);
+          operandH = operandT;
+          continue;
+        }
+
+      if (*operandT == ' ')
+        as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
+
+      if (*operandT == '(')
+        bracket_flag = 1;
+      else if (*operandT == '[')
+        sq_bracket_flag = 1;
+
+      if (*operandT == ')')
+        {
+          if (bracket_flag)
+            bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+      else if (*operandT == ']')
+        {
+          if (sq_bracket_flag)
+            sq_bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+
+      if (bracket_flag == 1 && *operandT == ')')
+        bracket_flag = 0;
+      else if (sq_bracket_flag == 1 && *operandT == ']')
+        sq_bracket_flag = 0;
+
+      operandT++;
+    }
+
+  /* Adding the last operand.  */
+  operand[op_num++] = strdup (operandH);
+  cr16_ins->nargs = op_num;
+
+  /* Verifying correct syntax of operands (all brackets should be closed).  */
+  if (bracket_flag || sq_bracket_flag)
+    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+
+  /* Now we parse each operand separately.  */
+  for (op_num = 0; op_num < cr16_ins->nargs; op_num++)
+    {
+      cur_arg_num = op_num;
+      parse_operand (operand[op_num], cr16_ins);
+      free (operand[op_num]);
+    }
+
+  if (allocated)
+    free (operandS);
+}
+
+/* Get the trap index in dispatch table, given its name.
+   This routine is used by assembling the 'excp' instruction.  */
+
+static int
+gettrap (char *s)
+{
+  const trap_entry *trap;
+
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (strcasecmp (trap->name, s) == 0)
+      return trap->entry;
+
+  /* To make compatable with CR16 4.1 tools, the below 3-lines of
+   * code added. Refer: Development Tracker item #123 */
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (trap->entry  == (unsigned int) atoi (s))
+      return trap->entry;
+
+  as_bad (_("Unknown exception: `%s'"), s);
+  return 0;
+}
+
+/* Top level module where instruction parsing starts.
+   cr16_ins - data structure holds some information.
+   operands - holds the operands part of the whole instruction.  */
+
+static void
+parse_insn (ins *insn, char *operands)
+{
+  int i;
+
+  /* Handle instructions with no operands.  */
+  for (i = 0; cr16_no_op_insn[i] != NULL; i++)
+  {
+    if (streq (cr16_no_op_insn[i], instruction->mnemonic))
+    {
+      insn->nargs = 0;
+      return;
+    }
+  }
+
+  /* Handle 'excp' instructions.  */
+  if (IS_INSN_MNEMONIC ("excp"))
+    {
+      insn->nargs = 1;
+      insn->arg[0].type = arg_ic;
+      insn->arg[0].constant = gettrap (operands);
+      insn->arg[0].X_op = O_constant;
+      return;
+    }
+
+  if (operands != NULL)
+    parse_operands (insn, operands);
+}
+
+/* bCC instruction requires special handling.  */
+static char *
+get_b_cc (char * op)
+{
+  unsigned int i;
+  char op1[5];
+
+  for (i = 1; i < strlen (op); i++)
+     op1[i-1] = op[i];
+
+  op1[i-1] = '\0';
+
+  for (i = 0; i < cr16_num_cc ; i++)
+    if (streq (op1, cr16_b_cond_tab[i]))
+      return (char *) cr16_b_cond_tab[i];
+
+   return NULL;
+}
+
+/* bCC instruction requires special handling.  */
+static int
+is_bcc_insn (char * op)
+{
+  if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b")
+	|| streq (op, "beq0w") || streq (op, "bnq0w")))
+    if ((op[0] == 'b') && (get_b_cc (op) != NULL))
+      return 1;
+  return 0;
+}
+
+/* Cinv instruction requires special handling.  */
+
+static int
+check_cinv_options (char * operand)
+{
+  char *p = operand;
+  int i_used = 0, u_used = 0, d_used = 0;
+
+  while (*++p != ']')
+    {
+      if (*p == ',' || *p == ' ')
+        continue;
+
+      else if (*p == 'i')
+        i_used = 1;
+      else if (*p == 'u')
+        u_used = 1;
+      else if (*p == 'd')
+        d_used = 1;
+      else
+        as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                 \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_RP_REGTYPE:
+      return reg->image;
+    default:
+      RPAIR_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given index register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getidxregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define IDX_RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                       \
+
+  if (reg->type == CR16_RP_REGTYPE)
+    {
+      switch (reg->image)
+	{
+	case 0:  return 0; break;
+	case 2:  return 1; break;
+	case 4:  return 2; break;
+	case 6:  return 3; break;
+	case 8:  return 4; break;
+	case 10: return 5; break;
+	case 3:  return 6; break;
+	case 5:  return 7; break;
+	default:
+	  break;
+	}
+    }
+
+  IDX_RPAIR_IMAGE_ERR;
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    reg = &cr16_pregtab[r - MAX_REG];
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREG_IMAGE_ERR \
+  as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                      \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREG_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int pregptab_disp = 0;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    {
+      r = r - MAX_REG;
+      switch (r)
+        {
+	case 4: pregptab_disp = 1;  break;
+	case 6: pregptab_disp = 2;  break;
+	case 8:
+	case 9:
+	case 10:
+	  pregptab_disp = 3;  break;
+	case 12:
+	  pregptab_disp = 4;  break;
+	case 14:
+	  pregptab_disp = 5;  break;
+	default: break;
+        }
+      reg = &cr16_pregptab[r - pregptab_disp];
+    }
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register (32 bit) : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREGP_IMAGE_ERR \
+  as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\
+            reg_name, ins_parse);                                              \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREGP_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Routine used to represent integer X using NBITS bits.  */
+
+static long
+getconstant (long x, int nbits)
+{
+  /* The following expression avoids overflow if
+     'nbits' is the number of bits in 'bfd_vma'.  */
+  return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
+}
+
+/* Print a constant value to 'output_opcode':
+   ARG holds the operand's type and value.
+   SHIFT represents the location of the operand to be print into.
+   NBITS determines the size (in bits) of the constant.  */
+
+static void
+print_constant (int nbits, int shift, argument *arg)
+{
+  unsigned long mask = 0;
+
+  long constant = getconstant (arg->constant, nbits);
+
+  switch (nbits)
+    {
+    case 32:
+    case 28:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | x X x X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
+      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+      break;
+
+    case 21:
+      if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20;
+    case 24:
+    case 22:
+    case 20:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2          3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | - X - X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	{
+	  if (arg->type == arg_idxrp)
+	    {
+	      CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	  else
+	    {
+	      CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	}
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 14:
+      if (arg->type == arg_idxrp)
+	{
+	  if (instruction->size == 2)
+	    {
+	      CR16_PRINT (0, ((constant)&0xf), shift);         // 0-3 bits
+	      CR16_PRINT (0, ((constant>>4)&0x3), (shift+20)); // 4-5 bits
+	      CR16_PRINT (0, ((constant>>6)&0x3), (shift+14)); // 6-7 bits
+	      CR16_PRINT (0, ((constant>>8)&0x3f), (shift+8)); // 8-13 bits
+	    }
+	  else
+	    CR16_PRINT (0, constant, shift);
+	}
+      break;
+
+    case 16:
+    case 12:
+      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+	 always filling the upper part of output_opcode[1]. If we mistakenly
+	 write it to output_opcode[0], the constant prefix (that is, 'match')
+	 will be overriden.
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 | 'match' |         | X X X X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	CR16_PRINT (1, constant, WORD_SHIFT);
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 8:
+      CR16_PRINT (0, ((constant/2)&0xf), shift);
+      CR16_PRINT (0, ((constant/2)>>4),  (shift+8));
+      break;
+
+    default:
+      CR16_PRINT (0, constant,  shift);
+      break;
+    }
+}
+
+/* Print an operand to 'output_opcode', which later on will be
+   printed to the object file:
+   ARG holds the operand's type, size and value.
+   SHIFT represents the printing location of operand.
+   NBITS determines the size (in bits) of a constant operand.  */
+
+static void
+print_operand (int nbits, int shift, argument *arg)
+{
+  switch (arg->type)
+    {
+    case arg_cc:
+      CR16_PRINT (0, arg->cc, shift);
+      break;
+
+    case arg_r:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_rp:
+      CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    case arg_pr:
+      CR16_PRINT (0, getprocreg_image (arg->pr), shift);
+      break;
+
+    case arg_prp:
+      CR16_PRINT (0, getprocregp_image (arg->prp), shift);
+      break;
+
+    case arg_idxrp:
+      /*    16      12      8    6      0
+            +-----------------------------+
+            | r_index | disp  | rp_base   |
+            +-----------------------------+          */
+
+      if (instruction->size == 3)
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 0);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 3);
+	  else
+	    CR16_PRINT (0, 1, 3);
+	}
+      else
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 16);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 19);
+	  else
+	    CR16_PRINT (0, 1, 19);
+	}
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_idxr:
+      if (getreg_image (arg->i_r) == 12)
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 0, 23);
+	else CR16_PRINT (0, 0, 24);
+      else
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 1, 23);
+	else CR16_PRINT (0, 1, 24);
+
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_ic:
+    case arg_c:
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_rbase:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_cr:
+      print_constant (nbits, shift , arg);
+      /* Add the register argument to the output_opcode.  */
+      CR16_PRINT (0, getreg_image (arg->r), (shift+16));
+      break;
+
+    case arg_crp:
+      print_constant (nbits, shift , arg);
+      if (instruction->size > 1)
+	CR16_PRINT (0, getregp_image (arg->rp), (shift + 16));
+      else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS)))
+	{
+	  if (instruction->size == 2)
+	    CR16_PRINT (0, getregp_image (arg->rp), (shift - 8));
+	  else if (instruction->size == 1)
+	    CR16_PRINT (0, getregp_image (arg->rp), 16);
+	}
+      else
+	CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Retrieve the number of operands for the current assembled instruction.  */
+
+static int
+get_number_of_operands (void)
+{
+  int i;
+
+  for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+    ;
+  return i;
+}
+
+/* Verify that the number NUM can be represented in BITS bits (that is,
+   within its permitted range), based on the instruction's FLAGS.
+   If UPDATE is nonzero, update the value of NUM if necessary.
+   Return OP_LEGAL upon success, actual error type upon failure.  */
+
+static op_err
+check_range (long *num, int bits, int unsigned flags, int update)
+{
+  long min, max;
+  int retval = OP_LEGAL;
+  long value = *num;
+
+  if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
+
+  /* For hosts witah longs bigger than 32-bits make sure that the top
+     bits of a 32-bit negative value read in by the parser are set,
+     so that the correct comparisons are made.  */
+  if (value & 0x80000000)
+    value |= (-1L << 31);
+
+
+  /* Verify operand value is even.  */
+  if (flags & OP_EVEN)
+    {
+      if (value % 2)
+        return OP_NOT_EVEN;
+    }
+
+  if (flags & OP_DEC)
+    {
+      value -= 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_SHIFT)
+    {
+      value >>= 1;
+      if (update)
+        *num = value;
+    }
+  else if (flags & OP_SHIFT_DEC)
+    {
+      value = (value >> 1) - 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_ABS20)
+    {
+      if (value > 0xEFFFF)
+        return OP_OUT_OF_RANGE;
+    }
+
+  if (flags & OP_ESC)
+    {
+      if (value == 0xB || value == 0x9)
+        return OP_OUT_OF_RANGE;
+      else if (value == -1)
+	{
+	  if (update)
+	    *num = 9;
+	  return retval;
+	}
+    }
+
+  if (flags & OP_ESC1)
+    {
+      if (value > 13)
+        return OP_OUT_OF_RANGE;
+    }
+
+   if (flags & OP_SIGNED)
+     {
+       max = (1 << (bits - 1)) - 1;
+       min = - (1 << (bits - 1));
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_UNSIGNED)
+     {
+       max = ((((1 << (bits - 1)) - 1) << 1) | 1);
+       min = 0;
+       if (((unsigned long) value > (unsigned long) max)
+            || ((unsigned long) value < (unsigned long) min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_NEG)
+     {
+       max = - 1;
+       min = - ((1 << (bits - 1))-1);
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   return retval;
+}
+
+/* Bunch of error checkings.
+   The checks are made after a matching instruction was found.  */
+
+static void
+warn_if_needed (ins *insn)
+{
+  /* If the post-increment address mode is used and the load/store
+     source register is the same as rbase, the result of the
+     instruction is undefined.  */
+  if (IS_INSN_TYPE (LD_STOR_INS_INC))
+    {
+      /* Enough to verify that one of the arguments is a simple reg.  */
+      if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
+        if (insn->arg[0].r == insn->arg[1].r)
+          as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r);
+    }
+
+  if (IS_INSN_MNEMONIC ("pop")
+      || IS_INSN_MNEMONIC ("push")
+      || IS_INSN_MNEMONIC ("popret"))
+    {
+      unsigned int count = insn->arg[0].constant, reg_val;
+
+      /* Check if count operand caused to save/retrive the RA twice
+	 to generate warning message.  */
+     if (insn->nargs > 2)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         if (   ((reg_val == 9) &&  (count > 7))
+	     || ((reg_val == 10) && (count > 6))
+	     || ((reg_val == 11) && (count > 5))
+	     || ((reg_val == 12) && (count > 4))
+	     || ((reg_val == 13) && (count > 2))
+	     || ((reg_val == 14) && (count > 0)))
+           as_warn (_("RA register is saved twice."));
+
+         /* Check if the third operand is "RA" or "ra" */
+         if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA)))
+           as_bad (_("`%s' Illegal use of registers."), ins_parse);
+       }
+
+      if (insn->nargs > 1)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         /* If register is a register pair ie r12/r13/r14 in operand1, then
+            the count constant should be validated.  */
+         if (((reg_val == 11) && (count > 7))
+	     || ((reg_val == 12) && (count > 6))
+	     || ((reg_val == 13) && (count > 4))
+	     || ((reg_val == 14) && (count > 2))
+	     || ((reg_val == 15) && (count > 0)))
+           as_bad (_("`%s' Illegal count-register combination."), ins_parse);
+       }
+     else
+       {
+         /* Check if the operand is "RA" or "ra" */
+         if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA)))
+           as_bad (_("`%s' Illegal use of register."), ins_parse);
+       }
+    }
+
+  /* Some instruction assume the stack pointer as rptr operand.
+     Issue an error when the register to be loaded is also SP.  */
+  if (instruction->flags & NO_SP)
+    {
+      if (getreg_image (insn->arg[1].r) == getreg_image (sp))
+        as_bad (_("`%s' has undefined result"), ins_parse);
+    }
+
+  /* If the rptr register is specified as one of the registers to be loaded,
+     the final contents of rptr are undefined. Thus, we issue an error.  */
+  if (instruction->flags & NO_RPTR)
+    {
+      if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
+        as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
+                  getreg_image (insn->arg[0].r));
+    }
+}
+
+/* In some cases, we need to adjust the instruction pointer although a
+   match was already found. Here, we gather all these cases.
+   Returns 1 if instruction pointer was adjusted, otherwise 0.  */
+
+static int
+adjust_if_needed (ins *insn ATTRIBUTE_UNUSED)
+{
+  int ret_value = 0;
+
+  if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS)))
+    {
+      if ((instruction->operands[0].op_type == abs24)
+           && ((insn->arg[0].constant) > 0xF00000))
+        {
+          insn->arg[0].constant &= 0xFFFFF;
+          instruction--;
+          ret_value = 1;
+        }
+    }
+
+  return ret_value;
+}
+
+/* Assemble a single instruction:
+   INSN is already parsed (that is, all operand values and types are set).
+   For instruction to be assembled, we need to find an appropriate template in
+   the instruction table, meeting the following conditions:
+    1: Has the same number of operands.
+    2: Has the same operand types.
+    3: Each operand size is sufficient to represent the instruction's values.
+   Returns 1 upon success, 0 upon failure.  */
+
+static int
+assemble_insn (char *mnemonic, ins *insn)
+{
+  /* Type of each operand in the current template.  */
+  argtype cur_type[MAX_OPERANDS];
+  /* Size (in bits) of each operand in the current template.  */
+  unsigned int cur_size[MAX_OPERANDS];
+  /* Flags of each operand in the current template.  */
+  unsigned int cur_flags[MAX_OPERANDS];
+  /* Instruction type to match.  */
+  unsigned int ins_type;
+  /* Boolean flag to mark whether a match was found.  */
+  int match = 0;
+  int i;
+  /* Nonzero if an instruction with same number of operands was found.  */
+  int found_same_number_of_operands = 0;
+  /* Nonzero if an instruction with same argument types was found.  */
+  int found_same_argument_types = 0;
+  /* Nonzero if a constant was found within the required range.  */
+  int found_const_within_range  = 0;
+  /* Argument number of an operand with invalid type.  */
+  int invalid_optype = -1;
+  /* Argument number of an operand with invalid constant value.  */
+  int invalid_const  = -1;
+  /* Operand error (used for issuing various constant error messages).  */
+  op_err op_error, const_err = OP_LEGAL;
+
+/* Retrieve data (based on FUNC) for each operand of a given instruction.  */
+#define GET_CURRENT_DATA(FUNC, ARRAY)                           \
+  for (i = 0; i < insn->nargs; i++)                             \
+    ARRAY[i] = FUNC (instruction->operands[i].op_type)
+
+#define GET_CURRENT_TYPE    GET_CURRENT_DATA (get_optype, cur_type)
+#define GET_CURRENT_SIZE    GET_CURRENT_DATA (get_opbits, cur_size)
+#define GET_CURRENT_FLAGS   GET_CURRENT_DATA (get_opflags, cur_flags)
+
+  /* Instruction has no operands -> only copy the constant opcode.   */
+  if (insn->nargs == 0)
+    {
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+      return 1;
+    }
+
+  /* In some case, same mnemonic can appear with different instruction types.
+     For example, 'storb' is supported with 3 different types :
+     LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
+     We assume that when reaching this point, the instruction type was
+     pre-determined. We need to make sure that the type stays the same
+     during a search for matching instruction.  */
+  ins_type = CR16_INS_TYPE (instruction->flags);
+
+  while (/* Check that match is still not found.  */
+         match != 1
+         /* Check we didn't get to end of table.  */
+         && instruction->mnemonic != NULL
+         /* Check that the actual mnemonic is still available.  */
+         && IS_INSN_MNEMONIC (mnemonic)
+         /* Check that the instruction type wasn't changed.  */
+         && IS_INSN_TYPE (ins_type))
+    {
+      /* Check whether number of arguments is legal.  */
+      if (get_number_of_operands () != insn->nargs)
+        goto next_insn;
+      found_same_number_of_operands = 1;
+
+      /* Initialize arrays with data of each operand in current template.  */
+      GET_CURRENT_TYPE;
+      GET_CURRENT_SIZE;
+      GET_CURRENT_FLAGS;
+
+      /* Check for type compatibility.  */
+      for (i = 0; i < insn->nargs; i++)
+        {
+          if (cur_type[i] != insn->arg[i].type)
+            {
+              if (invalid_optype == -1)
+                invalid_optype = i + 1;
+              goto next_insn;
+            }
+        }
+      found_same_argument_types = 1;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          /* If 'bal' instruction size is '2' and reg operand is not 'ra'
+             then goto next instruction.  */
+          if (IS_INSN_MNEMONIC ("bal") && (i == 0)
+	      && (instruction->size == 2) && (insn->arg[i].rp != 14))
+            goto next_insn;
+
+          /* If 'storb' instruction with 'sp' reg and 16-bit disp of
+           * reg-pair, leads to undifined trap, so this should use
+           * 20-bit disp of reg-pair.  */
+          if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
+	      && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
+            goto next_insn;
+
+          /* Only check range - don't update the constant's value, since the
+             current instruction may not be the last we try to match.
+             The constant's value will be updated later, right before printing
+             it to the object file.  */
+          if ((insn->arg[i].X_op == O_constant)
+              && (op_error = check_range (&insn->arg[i].constant, cur_size[i],
+                                          cur_flags[i], 0)))
+            {
+              if (invalid_const == -1)
+                {
+                  invalid_const = i + 1;
+                  const_err = op_error;
+                }
+              goto next_insn;
+            }
+          /* For symbols, we make sure the relocation size (which was already
+             determined) is sufficient.  */
+          else if ((insn->arg[i].X_op == O_symbol)
+                   && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+		       > cur_size[i]))
+                  goto next_insn;
+        }
+      found_const_within_range = 1;
+
+      /* If we got till here -> Full match is found.  */
+      match = 1;
+      break;
+
+/* Try again with next instruction.  */
+next_insn:
+      instruction++;
+    }
+
+  if (!match)
+    {
+      /* We haven't found a match - instruction can't be assembled.  */
+      if (!found_same_number_of_operands)
+        as_bad (_("Incorrect number of operands"));
+      else if (!found_same_argument_types)
+        as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
+      else if (!found_const_within_range)
+        {
+          switch (const_err)
+            {
+	    case OP_OUT_OF_RANGE:
+	      as_bad (_("Operand out of range (arg %d)"), invalid_const);
+	      break;
+	    case OP_NOT_EVEN:
+	      as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
+	      break;
+	    default:
+	      as_bad (_("Illegal operand (arg %d)"), invalid_const);
+	      break;
+            }
+        }
+
+       return 0;
+    }
+  else
+    /* Full match - print the encoding to output file.  */
+    {
+      /* Make further checkings (such that couldn't be made earlier).
+         Warn the user if necessary.  */
+      warn_if_needed (insn);
+
+      /* Check whether we need to adjust the instruction pointer.  */
+      if (adjust_if_needed (insn))
+        /* If instruction pointer was adjusted, we need to update
+           the size of the current template operands.  */
+        GET_CURRENT_SIZE;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          int j = instruction->flags & REVERSE_MATCH ?
+                  i == 0 ? 1 :
+                  i == 1 ? 0 : i :
+                  i;
+
+          /* This time, update constant value before printing it.  */
+            if ((insn->arg[j].X_op == O_constant)
+               && (check_range (&insn->arg[j].constant, cur_size[j],
+                                cur_flags[j], 1) != OP_LEGAL))
+              as_fatal (_("Illegal operand (arg %d)"), j+1);
+        }
+
+      /* First, copy the instruction's opcode.  */
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+         /* For BAL (ra),disp17 instuction only. And also set the
+            DISP24a relocation type.  */
+         if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
+           {
+             insn->rtype = BFD_RELOC_CR16_DISP24a;
+             continue;
+           }
+          cur_arg_num = i;
+          print_operand (cur_size[i], instruction->operands[i].shift,
+                         &insn->arg[i]);
+        }
+    }
+
+  return 1;
+}
+
+/* Print the instruction.
+   Handle also cases where the instruction is relaxable/relocatable.  */
+
+static void
+print_insn (ins *insn)
+{
+  unsigned int i, j, insn_size;
+  char *this_frag;
+  unsigned short words[4];
+  int addr_mod;
+
+  /* Arrange the insn encodings in a WORD size array.  */
+  for (i = 0, j = 0; i < 2; i++)
+    {
+      words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
+      words[j++] = output_opcode[i] & 0xFFFF;
+    }
+
+    insn_size = instruction->size;
+    this_frag = frag_more (insn_size * 2);
+
+    /* Handle relocation.  */
+    if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
+      {
+         reloc_howto_type *reloc_howto;
+         int size;
+
+         reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
+
+         if (!reloc_howto)
+           abort ();
+
+         size = bfd_get_reloc_size (reloc_howto);
+
+         if (size < 1 || size > 4)
+           abort ();
+
+         fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                      size, &insn->exp, reloc_howto->pc_relative,
+                      insn->rtype);
+      }
+
+  /* Verify a 2-byte code alignment.  */
+  addr_mod = frag_now_fix () & 1;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 2"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
+  /* Write the instruction encoding to frag.  */
+  for (i = 0; i < insn_size; i++)
+    {
+      md_number_to_chars (this_frag, (valueT) words[i], 2);
+      this_frag += 2;
+    }
+}
+
+/* This is the guts of the machine-dependent assembler.  OP points to a
+   machine dependent instruction.  This function is supposed to emit
+   the frags/bytes it assembles to.  */
+
+void
+md_assemble (char *op)
+{
+  ins cr16_ins;
+  char *param, param1[32];
+  char c;
+
+  /* Reset global variables for a new instruction.  */
+  reset_vars (op);
+
+  /* Strip the mnemonic.  */
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param++ = '\0';
+
+  /* bCC instuctions and adjust the mnemonic by adding extra white spaces.  */
+  if (is_bcc_insn (op))
+    {
+      strcpy (param1, get_b_cc (op));
+      op = "b";
+      strcat (param1,",");
+      strcat (param1, param);
+      param = (char *) &param1;
+    }
+
+  /* Checking the cinv options and adjust the mnemonic by removing the
+     extra white spaces.  */
+  if (streq ("cinv", op))
+    {
+     /* Validate the cinv options.  */
+      check_cinv_options (param);
+      strcat (op, param);
+    }
+
+  /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
+     lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
+     as CR16 core doesn't support lsh[b/w] right shift operaions.  */
+  if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
+      && (param [0] == '$'))
+    {
+      strcpy (param1, param);
+      /* Find the instruction.  */
+      instruction = (const inst *) hash_find (cr16_inst_hash, op);
+       parse_operands (&cr16_ins, param1);
+      if (((&cr16_ins)->arg[0].type == arg_ic)
+	  && ((&cr16_ins)->arg[0].constant >= 0))
+        {
+           if (streq ("lshb", op))
+	     op = "ashub";
+           else if (streq ("lshd", op))
+	     op = "ashud";
+	   else
+	     op = "ashuw";
+        }
+    }
+
+  /* Find the instruction.  */
+  instruction = (const inst *) hash_find (cr16_inst_hash, op);
+  if (instruction == NULL)
+    {
+      as_bad (_("Unknown opcode: `%s'"), op);
+      return;
+    }
+
+  /* Tie dwarf2 debug info to the address at the start of the insn.  */
+  dwarf2_emit_insn (0);
+
+  /* Parse the instruction's operands.  */
+  parse_insn (&cr16_ins, param);
+
+  /* Assemble the instruction - return upon failure.  */
+  if (assemble_insn (op, &cr16_ins) == 0)
+    return;
+
+  /* Print the instruction.  */
+  print_insn (&cr16_ins);
+}
diff --git a/gas/config/tc-cr16.h b/gas/config/tc-cr16.h
new file mode 100644
index 0000000..6d06151
--- /dev/null
+++ b/gas/config/tc-cr16.h
@@ -0,0 +1,73 @@
+/* tc-cr16.h -- Header file for tc-cr16.c, the CR16 GAS port.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_CR16_H
+#define TC_CR16_H
+
+#define TC_CR16 1
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_FORMAT "elf32-cr16"
+#define TARGET_ARCH   bfd_arch_cr16
+
+#define WORKING_DOT_WORD
+#define LOCAL_LABEL_PREFIX '.'
+
+#define md_undefined_symbol(s)  0
+#define md_number_to_chars      number_to_chars_littleendian
+
+/* We do relaxing in the assembler as well as the linker.  */
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* We do not want to adjust any relocations to make implementation of
+   linker relaxations easier.  */
+#define tc_fix_adjustable(fixP)  0
+
+/* We need to force out some relocations when relaxing.  */
+#define TC_FORCE_RELOCATION(FIXP) cr16_force_relocation (FIXP)
+extern int cr16_force_relocation (struct fix *);
+
+/* Fixup debug sections since we will never relax them.  */
+#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
+
+/* CR16 instructions, with operands included, are a multiple
+   of two bytes long.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *);
+/* This is called by emit_expr when creating a reloc for a cons.
+   We could use the definition there, except that we want to handle 
+   the CR16 reloc type specially, rather than the BFD_RELOC type.  */
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
+  cr16_cons_fix_new (FRAG, OFF, LEN, EXP) 
+
+/* Give an error if a frag containing code is not aligned to a 2-byte 
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code                                                \
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 1) != 0)        \
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,                 \
+                  _("instruction address is not a multiple of 2"));
+
+#endif /* TC_CR16_H */
diff --git a/gas/configure.tgt b/gas/configure.tgt
index c77cf81..3b7fb19 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -35,6 +35,7 @@ case ${cpu} in
   arm*)			cpu_type=arm endian=little ;;
   bfin*)		cpu_type=bfin endian=little ;;
   c4x*)			cpu_type=tic4x ;;
+  cr16*)		cpu_type=cr16 endian=little ;;
   crisv32)		cpu_type=cris arch=crisv32 ;;
   crx*)			cpu_type=crx endian=little ;;
   fido)			cpu_type=m68k ;;
@@ -126,6 +127,7 @@ case ${generic_target} in
   avr-*-*)				fmt=elf bfd_gas=yes ;;
   bfin-*-*)				fmt=elf bfd_gas=yes ;;
   bfin-*elf)				fmt=elf ;;
+  cr16-*-elf*)	    			fmt=elf ;;
 
   cris-*-linux-* | crisv32-*-linux-*)
 					fmt=multi em=linux ;;
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 9616505..4f6ff92 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -34,6 +34,7 @@ CPU_DOCS = \
 	c-arm.texi \
 	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 791efb0..2481a50 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -237,6 +237,7 @@ CPU_DOCS = \
 	c-arm.texi \
 	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
@@ -294,9 +295,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  doc/Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  doc/Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --cygnus  doc/Makefile
+	  $(AUTOMAKE) --foreign  doc/Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index ddabb68..b4778bf 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -31,6 +31,7 @@
 @set ARM
 @set AVR
 @set BFIN
+@set CR16
 @set CRIS
 @set D10V
 @set D30V
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 2cc40aa..b6f7f32 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -6351,6 +6351,9 @@ subject, see the hardware manufacturer's manual.
 @ifset BFIN
 * BFIN-Dependent::		BFIN Dependent Features
 @end ifset
+@ifset CR16
+* CR16-Dependent::              CR16 Dependent Features
+@end ifset
 @ifset CRIS
 * CRIS-Dependent::              CRIS Dependent Features
 @end ifset
@@ -6472,6 +6475,10 @@ subject, see the hardware manufacturer's manual.
 @include c-bfin.texi
 @end ifset
 
+@ifset CR16
+@include c-cr16.texi
+@end ifset
+
 @ifset CRIS
 @include c-cris.texi
 @end ifset
diff --git a/gas/doc/c-cr16.texi b/gas/doc/c-cr16.texi
new file mode 100644
index 0000000..4748d56
--- /dev/null
+++ b/gas/doc/c-cr16.texi
@@ -0,0 +1,80 @@
+@c Copyright 2007 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node CR16-Dependent
+@chapter CR16 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter CR16 Dependent Features
+@end ifclear
+
+@cindex CR16 support
+@menu
+* CR16 Operand Qualifiers::     CR16 Machine Operand Qualifiers
+@end menu
+
+@node CR16 Operand Qualifiers
+@section CR16 Operand Qualifiers
+@cindex CR16 Operand Qualifiers
+
+The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.  
+
+Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
+
+@table @code
+@item  s 
+- @code{Specifies expression operand type as small}
+@item  m 
+- @code{Specifies expression operand type as medium}
+@item  l 
+- @code{Specifies expression operand type as large}
+@item  c 
+- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
+@end table
+
+CR16 target operand qualifiers and its size (in bits):
+
+@table @samp
+@item Immediate Operand
+- s ---- 4 bits
+@item 
+- m ---- 16 bits, for movb and movw instructions.
+@item 
+- m ---- 20 bits, movd instructions.
+@item 
+- l ---- 32 bits
+
+@item Absolute Operand
+- s ---- Illegal specifier for this operand.
+@item  
+- m ---- 20 bits, movd instructions.
+
+@item Displacement Operand
+- s ---- 8 bits
+@item
+- m ---- 16 bits
+@item 
+- l ---- 24 bits
+@end table
+
+For example:
+@example
+1   @code{movw $_myfun@@c,r1}
+
+    This loads the address of _myfun, shifted right by 1, into r1.
+
+2   @code{movd $_myfun@@c,(r2,r1)}
+
+    This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
+                
+3   @code{_myfun_ptr:}
+    @code{.long _myfun@@c}
+    @code{loadd _myfun_ptr, (r1,r0)}
+    @code{jal (r1,r0)}
+
+    This .long directive, the address of _myfunc, shifted right by 1 at link time.
+@end example
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0c7e228..4eea75c 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,45 @@
+2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
+
+	* gas/cr16: New directory
+	* gas/cr16.exp: New file
+	* add_test.d and  add_test.s: New files
+	* and_test.d and and_test.s: New files
+	* ash_test.d and ash_test.s: New files
+	* bal_test.d and bal_test.s: New files
+	* bcc_test.d and bcc_test.s: New files
+	* beq0_test.d and beq0_test.s: New files
+	* cbitb_test.d and cbitb_test.s: New files
+	* cbitw_test.d and cbitw_test.s: New files
+	* cinv_test.d and cinv_test.s: New files
+	* cmp_test.d and cmp_test.s: New files
+	* excp_test.d and excp_test.s: New files
+	* jal_test.d and jal_test.s: New files
+	* jcc_test.d and jcc_test.s: New files
+	* loadb_test.d and loadb_test.s: New files
+	* loadd_test.d and loadd_test.s: New files
+	* loadm_test.d and loadm_test.s: New files
+	* loadw_test.d and loadw_test.s: New files
+	* lpsp_test.d and lpsp_test.s: New files
+	* lsh_test.d and lsh_test.s: New files
+	* mov_test.d and mov_test.s: New files
+	* mul_test.d and mul_test.s: New files
+	* or_test.d and or_test.s: New files
+	* popret_test.d and popret_test.s: New files
+	* pop_test.d and pop_test.s: New files
+	* push_test.d and push_test.s: New files
+	* sbitb_test.d and sbitb_test.s: New files
+	* sbitw_test.d and sbitw_test.s: New files
+	* scc_test.d and scc_test.s: New files
+	* storb_test.d and storb_test.s: New files
+	* stord_test.d and stord_test.s: New files
+	* storm_test.d and storm_test.s: New files
+	* storw_test.d and storw_test.s: New files
+	* sub_test.d and sub_test.s: New files
+	* tbitb_test.d and tbitb_test.s: New files
+	* tbit_test.d and tbit_test.s: New files
+	* tbitw_test.d and tbitw_test.s: New files
+	* xor_test.d and xor_test.s: New files
+
 2007-06-26  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index 68eb282..cb8c677 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -89,12 +89,12 @@ case $target_triplet in {
 	#  symbol `sym' required but not present
 	setup_xfail "*c30*-*-*" "*c4x*-*-*" "*arm*-*-*aout*" "*arm*-*-*coff" \
 	    "*arm*-*-pe" "crx*-*-*" "h8300*-*-*" "m68hc*-*-*" "maxq-*-*" \
-	    "mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*"
+	    "mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*" "cr16-*-*"
 	run_dump_test redef2
 	setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \
 	    "bfin-*-*" "*c4x*-*-*" "crx*-*-*" "h8300*-*-*" "hppa*-*-hpux*" \
 	    "m68hc*-*-*" "maxq-*-*" "mn10300-*-*" "or32-*-*" "pdp11-*-*" \
-	    "vax*-*-*" "z8k-*-*"
+	    "vax*-*-*" "z8k-*-*" "cr16-*-*"
 	run_dump_test redef3
 	setup_xfail "*c4x*-*-*"
 	gas_test_error "redef4.s" "" ".set for symbol already used as label"
diff --git a/gas/testsuite/gas/cr16/add_test.d b/gas/testsuite/gas/cr16/add_test.d
new file mode 100644
index 0000000..c2a0fe0
--- /dev/null
+++ b/gas/testsuite/gas/cr16/add_test.d
@@ -0,0 +1,71 @@
+#as:
+#objdump:  -dr
+#name:  add_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 30       	addb	\$0xf:s,r1
+   2:	b2 30 ff 00 	addb	\$0xff:m,r2
+   6:	b1 30 ff 0f 	addb	\$0xfff:m,r1
+   a:	b1 30 14 00 	addb	\$0x14:m,r1
+   e:	a2 30       	addb	\$0xa:s,r2
+  10:	b2 30 0b 00 	addb	\$0xb:m,r2
+  14:	12 31       	addb	r1,r2
+  16:	23 31       	addb	r2,r3
+  18:	34 31       	addb	r3,r4
+  1a:	56 31       	addb	r5,r6
+  1c:	67 31       	addb	r6,r7
+  1e:	78 31       	addb	r7,r8
+  20:	f1 34       	addcb	\$0xf:s,r1
+  22:	b2 34 ff 00 	addcb	\$0xff:m,r2
+  26:	b1 34 ff 0f 	addcb	\$0xfff:m,r1
+  2a:	b1 34 14 00 	addcb	\$0x14:m,r1
+  2e:	a2 34       	addcb	\$0xa:s,r2
+  30:	b2 34 0b 00 	addcb	\$0xb:m,r2
+  34:	12 35       	addcb	r1,r2
+  36:	23 35       	addcb	r2,r3
+  38:	34 35       	addcb	r3,r4
+  3a:	56 35       	addcb	r5,r6
+  3c:	67 35       	addcb	r6,r7
+  3e:	78 35       	addcb	r7,r8
+  40:	f1 36       	addcw	\$0xf:s,r1
+  42:	b2 36 ff 00 	addcw	\$0xff:m,r2
+  46:	b1 36 ff 0f 	addcw	\$0xfff:m,r1
+  4a:	b1 36 14 00 	addcw	\$0x14:m,r1
+  4e:	a2 36       	addcw	\$0xa:s,r2
+  50:	b2 36 0b 00 	addcw	\$0xb:m,r2
+  54:	12 37       	addcw	r1,r2
+  56:	23 37       	addcw	r2,r3
+  58:	34 37       	addcw	r3,r4
+  5a:	56 37       	addcw	r5,r6
+  5c:	67 37       	addcw	r6,r7
+  5e:	78 37       	addcw	r7,r8
+  60:	f1 32       	addw	\$0xf:s,r1
+  62:	b2 32 ff 00 	addw	\$0xff:m,r2
+  66:	b1 32 ff 0f 	addw	\$0xfff:m,r1
+  6a:	b1 32 14 00 	addw	\$0x14:m,r1
+  6e:	a2 32       	addw	\$0xa:s,r2
+  70:	12 33       	addw	r1,r2
+  72:	23 33       	addw	r2,r3
+  74:	34 33       	addw	r3,r4
+  76:	56 33       	addw	r5,r6
+  78:	67 33       	addw	r6,r7
+  7a:	78 33       	addw	r7,r8
+  7c:	f1 60       	addd	\$0xf:s,\(r2,r1\)
+  7e:	b1 60 0b 00 	addd	\$0xb:m,\(r2,r1\)
+  82:	b1 60 ff 00 	addd	\$0xff:m,\(r2,r1\)
+  86:	b1 60 ff 0f 	addd	\$0xfff:m,\(r2,r1\)
+  8a:	10 04 ff ff 	addd	\$0xffff:m,\(r2,r1\)
+  8e:	1f 04 ff ff 	addd	\$0xfffff:m,\(r2,r1\)
+  92:	21 00 ff 0f 	addd	\$0xfffffff:l,\(r2,r1\)
+  96:	ff ff 
+  98:	91 60       	addd	\$-1:s,\(r2,r1\)
+  9a:	31 61       	addd	\(r4,r3\),\(r2,r1\)
+  9c:	31 61       	addd	\(r4,r3\),\(r2,r1\)
+  9e:	af 60       	addd	\$0xa:s,\(sp\)
+  a0:	ef 60       	addd	\$0xe:s,\(sp\)
+  a2:	bf 60 0b 00 	addd	\$0xb:m,\(sp\)
+  a6:	8f 60       	addd	\$0x8:s,\(sp\)
diff --git a/gas/testsuite/gas/cr16/add_test.s b/gas/testsuite/gas/cr16/add_test.s
new file mode 100644
index 0000000..de5270d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/add_test.s
@@ -0,0 +1,98 @@
+        .text
+        .global main
+main:
+        ###########
+	# ADDB imm4/imm16, reg
+        ###########
+	addb    $0xf,r1
+	addb    $0xff,r2
+	addb    $0xfff,r1
+	#addb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addb    $20,r1
+	addb    $10,r2
+	addb    $11,r2
+        ###########
+	# ADDB reg, reg
+        ###########
+	addb    r1,r2
+	addb    r2,r3
+	addb    r3,r4
+	addb    r5,r6
+	addb    r6,r7
+	addb    r7,r8
+        ###########
+	# ADDCB imm4/imm16, reg
+        ###########
+	addcb    $0xf,r1
+	addcb    $0xff,r2
+	addcb    $0xfff,r1
+	#addcb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addcb    $20,r1
+	addcb    $10,r2
+	addcb    $11,r2
+        ###########
+	# ADDCB reg, reg
+        ###########
+	addcb    r1,r2
+	addcb    r2,r3
+	addcb    r3,r4
+	addcb    r5,r6
+	addcb    r6,r7
+	addcb    r7,r8
+        ###########
+	# ADDCW imm4/imm16, reg
+        ###########
+	addcw    $0xf,r1
+	addcw    $0xff,r2
+	addcw    $0xfff,r1
+	#addcw    $0xffff,r2 # check with CRASM 4.1
+	addcw    $20,r1
+	addcw    $10,r2
+	addcw    $11,r2
+        ###########
+	# ADDCW reg, reg
+        ###########
+	addcw    r1,r2
+	addcw    r2,r3
+	addcw    r3,r4
+	addcw    r5,r6
+	addcw    r6,r7
+	addcw    r7,r8
+        ###########
+	# ADDW imm4/imm16, reg
+        ###########
+	addw    $0xf,r1
+	addw    $0xff,r2
+	addw    $0xfff,r1
+	#addw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addw    $20,r1
+	addw    $10,r2
+        ###########
+	# ADDW reg, reg
+        ###########
+	addw    r1,r2
+	addw    r2,r3
+	addw    r3,r4
+	addw    r5,r6
+	addw    r6,r7
+	addw    r7,r8
+        ###########
+	# ADDD imm4/imm16/imm20/imm32, regp
+        ###########
+	addd    $0xf,(r2,r1)
+	addd    $0xB,(r2,r1)
+	addd    $0xff,(r2,r1)
+	addd    $0xfff,(r2,r1)
+	addd    $0xffff,(r2,r1)
+	addd    $0xfffff,(r2,r1)
+	addd    $0xfffffff,(r2,r1)
+	addd    $0xffffffff,(r2,r1)
+        ###########
+	# ADDD regp, regp
+        ###########
+	addd    (r4,r3),(r2,r1)
+	addd    (r4,r3),(r2,r1)
+	addd    $10,(sp)
+	addd    $14,(sp)
+	addd    $11,(sp)
+	addd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/and_test.d b/gas/testsuite/gas/cr16/and_test.d
new file mode 100644
index 0000000..f8e1f27
--- /dev/null
+++ b/gas/testsuite/gas/cr16/and_test.d
@@ -0,0 +1,55 @@
+#as:
+#objdump:  -dr
+#name:  and_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 20       	andb	\$0xf:s,r1
+   2:	b2 20 ff 00 	andb	\$0xff:m,r2
+   6:	b1 20 ff 0f 	andb	\$0xfff:m,r1
+   a:	b2 20 ff ff 	andb	\$0xffff:m,r2
+   e:	b1 20 14 00 	andb	\$0x14:m,r1
+  12:	a2 20       	andb	\$0xa:s,r2
+  14:	12 21       	andb	r1,r2
+  16:	23 21       	andb	r2,r3
+  18:	34 21       	andb	r3,r4
+  1a:	56 21       	andb	r5,r6
+  1c:	67 21       	andb	r6,r7
+  1e:	78 21       	andb	r7,r8
+  20:	f1 22       	andw	\$0xf:s,r1
+  22:	b2 22 ff 00 	andw	\$0xff:m,r2
+  26:	b1 22 ff 0f 	andw	\$0xfff:m,r1
+  2a:	b2 22 ff ff 	andw	\$0xffff:m,r2
+  2e:	b1 22 14 00 	andw	\$0x14:m,r1
+  32:	a2 22       	andw	\$0xa:s,r2
+  34:	12 23       	andw	r1,r2
+  36:	23 23       	andw	r2,r3
+  38:	34 23       	andw	r3,r4
+  3a:	56 23       	andw	r5,r6
+  3c:	67 23       	andw	r6,r7
+  3e:	78 23       	andw	r7,r8
+  40:	41 00 00 00 	andd	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	41 00 00 00 	andd	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	41 00 00 00 	andd	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	41 00 00 00 	andd	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	41 00 0f 00 	andd	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	41 00 ff 0f 	andd	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	41 00 ff ff 	andd	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 b0 	andd	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 b0 	andd	\(r4,r3\),\(r2,r1\)
+  72:	4f 00 00 00 	andd	\$0xa:l,\(sp\)
+  76:	0a 00 
+  78:	4f 00 00 00 	andd	\$0xe:l,\(sp\)
+  7c:	0e 00 
+  7e:	4f 00 00 00 	andd	\$0x8:l,\(sp\)
+  82:	08 00 
diff --git a/gas/testsuite/gas/cr16/and_test.s b/gas/testsuite/gas/cr16/and_test.s
new file mode 100644
index 0000000..b21fdb7
--- /dev/null
+++ b/gas/testsuite/gas/cr16/and_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# ANDB imm4/imm16, reg
+        ###########
+	andb    $0xf,r1
+	andb    $0xff,r2
+	andb    $0xfff,r1
+	andb    $0xffff,r2
+	andb    $20,r1
+	andb    $10,r2
+        ###########
+	# ANDB reg, reg
+        ###########
+	andb    r1,r2
+	andb    r2,r3
+	andb    r3,r4
+	andb    r5,r6
+	andb    r6,r7
+	andb    r7,r8
+        ###########
+	# ANDW imm4/imm16, reg
+        ###########
+	andw    $0xf,r1
+	andw    $0xff,r2
+	andw    $0xfff,r1
+	andw    $0xffff,r2
+	andw    $20,r1
+	andw    $10,r2
+        ###########
+	# ANDW reg, reg
+        ###########
+	andw    r1,r2
+	andw    r2,r3
+	andw    r3,r4
+	andw    r5,r6
+	andw    r6,r7
+	andw    r7,r8
+        ###########
+	# ANDD imm4/imm16/imm32, regp
+        ###########
+	andd    $0xf,(r2,r1)
+	andd    $0xff,(r2,r1)
+	andd    $0xfff,(r2,r1)
+	andd    $0xffff,(r2,r1)
+	andd    $0xfffff,(r2,r1)
+	andd    $0xfffffff,(r2,r1)
+	andd    $0xffffffff,(r2,r1)
+        ###########
+	# ANDD regp, regp
+        ###########
+	andd    (r4,r3),(r2,r1)
+	andd    (r4,r3),(r2,r1)
+	andd    $10,(sp)
+	andd    $14,(sp)
+	andd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/ash_test.d b/gas/testsuite/gas/cr16/ash_test.d
new file mode 100644
index 0000000..2818012
--- /dev/null
+++ b/gas/testsuite/gas/cr16/ash_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  ash_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 40       	ashub	\$7:s,r1
+   2:	91 40       	ashub	\$-7:s,r1
+   4:	41 40       	ashub	\$4:s,r1
+   6:	c1 40       	ashub	\$-4:s,r1
+   8:	81 40       	ashub	\$-8:s,r1
+   a:	31 40       	ashub	\$3:s,r1
+   c:	d1 40       	ashub	\$-3:s,r1
+   e:	21 41       	ashub	r2,r1
+  10:	34 41       	ashub	r3,r4
+  12:	56 41       	ashub	r5,r6
+  14:	8a 41       	ashub	r8,r10
+  16:	71 42       	ashuw	\$7:s,r1
+  18:	91 43       	ashuw	\$-7:s,r1
+  1a:	41 42       	ashuw	\$4:s,r1
+  1c:	c1 43       	ashuw	\$-4:s,r1
+  1e:	81 42       	ashuw	\$8:s,r1
+  20:	81 43       	ashuw	\$-8:s,r1
+  22:	31 42       	ashuw	\$3:s,r1
+  24:	d1 43       	ashuw	\$-3:s,r1
+  26:	21 45       	ashuw	r2,r1
+  28:	34 45       	ashuw	r3,r4
+  2a:	56 45       	ashuw	r5,r6
+  2c:	8a 45       	ashuw	r8,r10
+  2e:	72 4c       	ashud	\$7:s,\(r3,r2\)
+  30:	92 4f       	ashud	\$-7:s,\(r3,r2\)
+  32:	82 4c       	ashud	\$8:s,\(r3,r2\)
+  34:	82 4f       	ashud	\$-8:s,\(r3,r2\)
+  36:	42 4c       	ashud	\$4:s,\(r3,r2\)
+  38:	c2 4f       	ashud	\$-4:s,\(r3,r2\)
+  3a:	c2 4c       	ashud	\$12:s,\(r3,r2\)
+  3c:	42 4f       	ashud	\$-12:s,\(r3,r2\)
+  3e:	31 4c       	ashud	\$3:s,\(r2,r1\)
+  40:	d1 4f       	ashud	\$-3:s,\(r2,r1\)
+  42:	41 48       	ashud	r4,\(r2,r1\)
+  44:	51 48       	ashud	r5,\(r2,r1\)
+  46:	61 48       	ashud	r6,\(r2,r1\)
+  48:	81 48       	ashud	r8,\(r2,r1\)
+  4a:	11 48       	ashud	r1,\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/ash_test.s b/gas/testsuite/gas/cr16/ash_test.s
new file mode 100644
index 0000000..dc3e794
--- /dev/null
+++ b/gas/testsuite/gas/cr16/ash_test.s
@@ -0,0 +1,59 @@
+        .text
+        .global main
+main:
+	#####################################
+	# ASHUB cnt(left +)/cnt (right -), reg
+	#####################################
+        ashub   $7,r1
+        ashub   $-7,r1
+        ashub   $4,r1
+        ashub   $-4,r1
+        ashub	$-8,r1
+        ashub   $3,r1
+        ashub   $-3,r1
+	#####################################
+	# ASHUB reg, reg
+	#####################################
+        ashub   r2,r1
+        ashub   r3,r4
+        ashub   r5,r6
+        ashub   r8,r10
+	#####################################
+	# ASHUW cnt(left +)/cnt (right -), reg
+	#####################################
+        ashuw   $7,r1
+        ashuw   $-7,r1
+        ashuw   $4,r1
+        ashuw   $-4,r1
+        ashuw	$8,r1
+        ashuw	$-8,r1
+        ashuw   $3,r1
+        ashuw   $-3,r1
+	#####################################
+	# ASHUW reg, reg
+	#####################################
+        ashuw   r2,r1
+        ashuw   r3,r4
+        ashuw   r5,r6
+        ashuw   r8,r10
+	#####################################
+	# ASHUD cnt(left +)/cnt (right -), regp
+	#####################################
+        ashud   $7, (r3,r2)
+        ashud   $-7, (r3,r2)
+        ashud   $8, (r3,r2)
+        ashud   $-8, (r3,r2)
+        ashud   $4, (r3,r2)
+        ashud   $-4, (r3,r2)
+        ashud   $12,(r3,r2)
+        ashud   $-12,(r3,r2)
+        ashud	$3,(r2,r1)
+        ashud	$-3,(r2,r1)
+	#####################################
+	# ASHUD reg, regp
+	#####################################
+        ashud   r4,(r2,r1)
+        ashud   r5,(r2,r1)
+        ashud   r6,(r2,r1)
+        ashud   r8,(r2,r1)
+        ashud   r1,(r2,r1)
diff --git a/gas/testsuite/gas/cr16/bal_test.d b/gas/testsuite/gas/cr16/bal_test.d
new file mode 100644
index 0000000..eb1558d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bal_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  bal_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	0f c0 22 f1 	bal	\(ra\),\*\+0xff122 <main\+0xff122>:m
+   4:	ff c0 26 f1 	bal	\(ra\),\*\+0xfff12a <main\+0xfff12a>:m
+   8:	00 c0 22 00 	bal	\(ra\),\*\+0x2a <main\+0x2a>:m
+   c:	00 c0 22 01 	bal	\(ra\),\*\+0x12e <main\+0x12e>:m
+  10:	00 c0 22 f1 	bal	\(ra\),\*\+0xf132 <main\+0xf132>:m
+  14:	00 c0 2a 81 	bal	\(ra\),\*\+0x813e <main\+0x813e>:m
+  18:	10 00 00 20 	bal	\(r1,r0\),\*\+0x13a <main\+0x13a>:l
+  1c:	22 01 
+  1e:	10 00 ac 2f 	bal	\(r11,r10\),\*\+0xcff140 <main\+0xcff140>:l
+  22:	22 f1 
+  24:	10 00 6a 2f 	bal	\(r7,r6\),\*\+0xaff146 <main\+0xaff146>:l
+  28:	22 f1 
+  2a:	10 00 38 2f 	bal	\(r4,r3\),\*\+0x8ff14c <main\+0x8ff14c>:l
+  2e:	22 f1 
+  30:	10 00 7f 2f 	bal	\(r8,r7\),\*\+0xfff152 <main\+0xfff152>:l
+  34:	22 f1 
diff --git a/gas/testsuite/gas/cr16/bal_test.s b/gas/testsuite/gas/cr16/bal_test.s
new file mode 100644
index 0000000..b89f1f6
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bal_test.s
@@ -0,0 +1,14 @@
+        .text

+        .global main

+main:

+bal     (ra),*+0xff122

+bal     (ra),*+0xfff126

+bal     (ra),*+0x22

+bal     (ra),*+0x122

+bal     (ra),*+0xf122

+bal     (ra),*+0x812a

+bal	(r1,r0),*+0x122

+bal	(r11,r10),*+0xcff122

+bal	(r7,r6),*+0xaff122

+bal	(r4,r3),*+0x8ff122

+bal	(r8,r7),*+0xfff122

diff --git a/gas/testsuite/gas/cr16/bcc_test.d b/gas/testsuite/gas/cr16/bcc_test.d
new file mode 100644
index 0000000..4613edf
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bcc_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  bcc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	01 11       	beq	\*\+0x22 <main\+0x22>:s
+   2:	19 11       	bne	\*\+0x34 <main\+0x34>:s
+   4:	32 12       	bcc	\*\+0x48 <main\+0x48>:s
+   6:	3a 12       	bcc	\*\+0x5a <main\+0x5a>:s
+   8:	43 13       	bhi	\*\+0x6e <main\+0x6e>:s
+   a:	cb 13       	blt	\*\+0x80 <main\+0x80>:s
+   c:	64 14       	bgt	\*\+0x94 <main\+0x94>:s
+   e:	8d 14       	bfs	\*\+0xa8 <main\+0xa8>:s
+  10:	95 15       	bfc	\*\+0xba <main\+0xba>:s
+  12:	a0 18 bc 01 	blo	\*\+0x1ce <main\+0x1ce>:m
+  16:	40 18 cc 01 	bhi	\*\+0x1e2 <main\+0x1e2>:m
+  1a:	c0 18 d6 01 	blt	\*\+0x1f0 <main\+0x1f0>:m
+  1e:	d0 18 e6 01 	bge	\*\+0x204 <main\+0x204>:m
+  22:	eb 17       	br	\*\+0x118 <main\+0x118>:s
+  24:	00 18 12 01 	beq	\*\+0x136 <main\+0x136>:m
+  28:	00 18 12 1f 	beq	\*\+0x1f3a <main\+0x1f3a>:m
+  2c:	00 18 22 0f 	beq	\*\+0xf4e <main\+0xf4e>:m
+  30:	10 18 34 0f 	bne	\*\+0xf64 <main\+0xf64>:m
+  34:	30 18 44 0f 	bcc	\*\+0xf78 <main\+0xf78>:m
+  38:	30 18 56 0f 	bcc	\*\+0xf8e <main\+0xf8e>:m
+  3c:	40 18 66 0f 	bhi	\*\+0xfa2 <main\+0xfa2>:m
+  40:	c0 18 78 0f 	blt	\*\+0xfb8 <main\+0xfb8>:m
+  44:	60 18 88 0f 	bgt	\*\+0xfcc <main\+0xfcc>:m
+  48:	80 18 9a 0f 	bfs	\*\+0xfe2 <main\+0xfe2>:m
+  4c:	90 18 aa 0f 	bfc	\*\+0xff6 <main\+0xff6>:m
+  50:	a0 18 bc 1f 	blo	\*\+0x200c <main\+0x200c>:m
+  54:	40 18 cc 1f 	bhi	\*\+0x2020 <main\+0x2020>:m
+  58:	c0 18 da 1f 	blt	\*\+0x2032 <main\+0x2032>:m
+  5c:	d0 18 ea 1f 	bge	\*\+0x2046 <main\+0x2046>:m
+  60:	e0 18 fa ff 	br	\*\+0x1005a <main\+0x1005a>:m
+  64:	10 00 0f 0f 	beq	\*\+0xff1f76 <main\+0xff1f76>:l
+  68:	12 1f 
+  6a:	10 00 0a 0a 	beq	\*\+0xaa0f8c <main\+0xaa0f8c>:l
+  6e:	22 0f 
+  70:	10 00 1b 0b 	bne	\*\+0xbb0fa4 <main\+0xbb0fa4>:l
+  74:	34 0f 
+  76:	10 00 3c 0c 	bcc	\*\+0xcc0fba <main\+0xcc0fba>:l
+  7a:	44 0f 
+  7c:	10 00 3d 0d 	bcc	\*\+0xdd0fd2 <main\+0xdd0fd2>:l
+  80:	56 0f 
+  82:	10 00 49 09 	bhi	\*\+0x990fe8 <main\+0x990fe8>:l
+  86:	66 0f 
+  88:	10 00 c8 08 	blt	\*\+0x881000 <main\+0x881000>:l
+  8c:	78 0f 
+  8e:	10 00 67 07 	bgt	\*\+0x771016 <main\+0x771016>:l
+  92:	88 0f 
+  94:	10 00 86 06 	bfs	\*\+0x66102e <main\+0x66102e>:l
+  98:	9a 0f 
+  9a:	10 00 95 05 	bfc	\*\+0x551044 <main\+0x551044>:l
+  9e:	aa 0f 
+  a0:	10 00 a4 04 	blo	\*\+0x44205c <main\+0x44205c>:l
+  a4:	bc 1f 
+  a6:	10 00 43 03 	bhi	\*\+0x332072 <main\+0x332072>:l
+  aa:	cc 1f 
+  ac:	10 00 c2 02 	blt	\*\+0x22208a <main\+0x22208a>:l
+  b0:	de 1f 
+  b2:	10 00 d1 01 	bge	\*\+0x1120a0 <main\+0x1120a0>:l
+  b6:	ee 1f 
+  b8:	10 00 e0 0f 	br	\*\+0x1000b6 <main\+0x1000b6>:l
+  bc:	fe ff 
diff --git a/gas/testsuite/gas/cr16/bcc_test.s b/gas/testsuite/gas/cr16/bcc_test.s
new file mode 100644
index 0000000..50f3fbe
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bcc_test.s
@@ -0,0 +1,59 @@
+        .text

+        .global main

+main:

+	###################

+	# bcc disp9/disp17/disp25

+	###################

+	# bcc disp9

+	###################

+	beq	*+0x022

+	bne	*+0x032

+	bcc	*+0x044

+	bcc	*+0x054

+	bhi	*+0x066

+	blt	*+0x076

+	bgt	*+0x088

+	bfs	*+0x09a

+	bfc	*+0x0aa

+	blo	*+0x1bc

+	bhi	*+0x1cc

+	blt	*+0x1d6

+	bge	*+0x1e6

+	br	*+0x0f6

+	###################

+	# bcc disp17

+	###################

+	beq	*+0x112

+	beq	*+0x1f12

+	beq	*+0x0f22

+	bne	*+0x0f34

+	bcc	*+0x0f44

+	bcc	*+0x0f56

+	bhi	*+0x0f66

+	blt	*+0x0f78

+	bgt	*+0x0f88

+	bfs	*+0x0f9a

+	bfc	*+0x0faa

+	blo	*+0x1fbc

+	bhi	*+0x1fcc

+	blt	*+0x1fda

+	bge	*+0x1fea

+	br	*+0xfffa

+	###################

+	# bcc disp25

+	###################

+	beq	*+0xff1f12

+	beq	*+0xaa0f22

+	bne	*+0xbb0f34

+	bcc	*+0xcc0f44

+	bcc	*+0xdd0f56

+	bhi	*+0x990f66

+	blt	*+0x880f78

+	bgt	*+0x770f88

+	bfs	*+0x660f9a

+	bfc	*+0x550faa

+	blo	*+0x441fbc

+	bhi	*+0x331fcc

+	blt	*+0x221fde

+	bge	*+0x111fee

+	br	*+0x0ffffe

diff --git a/gas/testsuite/gas/cr16/beq0_test.d b/gas/testsuite/gas/cr16/beq0_test.d
new file mode 100644
index 0000000..82f923c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/beq0_test.d
@@ -0,0 +1,15 @@
+#as:
+#objdump:  -dr
+#name:  beq0_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 0c       	beq0b	r1,\*\+0x10 <main\+0x10>:s
+   2:	b1 0c       	beq0b	r1,\*\+0x18 <main\+0x18>:s
+   4:	e1 0c       	beq0b	r1,\*\+0x1e <main\+0x1e>:s
+   6:	71 0e       	beq0w	r1,\*\+0x10 <main\+0x10>:s
+   8:	b1 0e       	beq0w	r1,\*\+0x18 <main\+0x18>:s
+   a:	e1 0e       	beq0w	r1,\*\+0x1e <main\+0x1e>:s
diff --git a/gas/testsuite/gas/cr16/beq0_test.s b/gas/testsuite/gas/cr16/beq0_test.s
new file mode 100644
index 0000000..70e9f6a
--- /dev/null
+++ b/gas/testsuite/gas/cr16/beq0_test.s
@@ -0,0 +1,15 @@
+        .text
+        .global main
+main:
+	###################
+	# beq0b reg, dispu5
+	###################
+	beq0b	r1,*+16
+	beq0b	r1,*+24
+	beq0b	r1,*+30
+	###################
+	# beq0w reg, dispu5
+	###################
+	beq0w	r1,*+16
+	beq0w	r1,*+24
+	beq0w	r1,*+30
diff --git a/gas/testsuite/gas/cr16/cbitb_test.d b/gas/testsuite/gas/cr16/cbitb_test.d
new file mode 100644
index 0000000..bbb382e
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  cbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 6b cd 0b 	cbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 6b cd ab 	cbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f 7a 	cbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 68 14 00 	cbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 68 fc ab 	cbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 68 34 12 	cbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 68 34 12 	cbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 68 34 00 	cbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 6a 5a 4b 	cbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 6a 1a 41 	cbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 6a 14 01 	cbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 6a 	cbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e 60 	cbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 60 	cbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f 60 	cbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 40 	cbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 6b 34 00 	cbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 6b ab 00 	cbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 40 	cbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 40 	cbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 40 	cbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 40 	cbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 6b ff 0f 	cbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 6b ff 0f 	cbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 6b ff ff 	cbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 6b 43 23 	cbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 41 	cbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 44 	cbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d 5f 	cbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 4f 	cbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 4f 	cbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 44 	cbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 6a       	cbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 6b 01 00 	cbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 6b 34 12 	cbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 6b 34 12 	cbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 51 	cbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 6b 23 01 	cbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 51 	cbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/cbitb_test.s b/gas/testsuite/gas/cr16/cbitb_test.s
new file mode 100644
index 0000000..1e65ef3
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	cbitb $4,0xbcd
+	cbitb $5,0xaabcd
+	cbitb $3,0xfaabcd
+
+	cbitb $5,[r12]0x14
+	cbitb $4,[r13]0xabfc
+	cbitb $3,[r12]0x1234
+	cbitb $3,[r13]0x1234
+	cbitb $3,[r12]0x34
+
+	cbitb $3,[r12]0xa7a(r1,r0)
+	cbitb $3,[r12]0xa7a(r3,r2)
+	cbitb $3,[r12]0xa7a(r4,r3)
+	cbitb $3,[r12]0xa7a(r5,r4)
+	cbitb $3,[r12]0xa7a(r6,r5)
+	cbitb $3,[r12]0xa7a(r7,r6)
+	cbitb $3,[r12]0xa7a(r9,r8)
+	cbitb $3,[r12]0xa7a(r11,r10)
+	cbitb $3,[r13]0xa7a(r1,r0)
+	cbitb $3,[r13]0xa7a(r3,r2)
+	cbitb $3,[r13]0xa7a(r4,r3)
+	cbitb $3,[r13]0xa7a(r5,r4)
+	cbitb $3,[r13]0xa7a(r6,r5)
+	cbitb $3,[r13]0xa7a(r7,r6)
+	cbitb $3,[r13]0xa7a(r9,r8)
+	cbitb $3,[r13]0xa7a(r11,r10)
+	cbitb $5,[r13]0xb7a(r4,r3)
+	cbitb $1,[r12]0x17a(r6,r5)
+	cbitb $1,[r13]0x134(r6,r5)
+	cbitb $3,[r12]0xabcde(r4,r3)
+	cbitb $5,[r13]0xabcd(r4,r3)
+	cbitb $3,[r12]0xabcd(r6,r5)
+	cbitb $3,[r13]0xbcde(r6,r5)
+
+	cbitb $5,0x0(r2)
+	cbitb $3,0x34(r12)
+	cbitb $3,0xab(r13)
+	cbitb $5,0xad(r1)
+	cbitb $5,0xcd(r2)
+	cbitb $5,0xfff(r0)
+	cbitb $3,0xbcd(r4)
+	cbitb $3,0xfff(r12)
+	cbitb $3,0xfff(r13)
+	cbitb $3,0xffff(r13)
+	cbitb $3,0x2343(r12)
+	cbitb $3,0x12345(r2)
+	cbitb $3,0x4abcd(r8)
+	cbitb $3,0xfabcd(r13)
+	cbitb $3,0xfabcd(r8)
+	cbitb $3,0xfabcd(r9)
+	cbitb $3,0x4abcd(r9)
+
+	cbitb $3,0x0(r2,r1)
+	cbitb $5,0x1(r2,r1)
+	cbitb $4,0x1234(r2,r1)
+	cbitb $3,0x1234(r2,r1)
+	cbitb $3,0x12345(r2,r1)
+	cbitb $3,0x123(r2,r1)
+	cbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/cbitw_test.d b/gas/testsuite/gas/cr16/cbitw_test.d
new file mode 100644
index 0000000..55e1543
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  cbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 6f cd 0b 	cbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 6f cd ab 	cbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f 7a 	cbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 6f cd 0b 	cbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 6f cd ab 	cbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef 7a 	cbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 6c 14 00 	cbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 6d fc ab 	cbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 6c 34 12 	cbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 6d 34 12 	cbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 6c 34 00 	cbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 6c 14 00 	cbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 6d fc ab 	cbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 6c 34 12 	cbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 6d 34 12 	cbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 6c 34 00 	cbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 6a 5a 4b 	cbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 6a 1a 41 	cbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 6a 14 01 	cbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 6a 	cbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e 60 	cbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 60 	cbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f 60 	cbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 6a fa 4b 	cbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 6a ba 41 	cbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 6a b4 01 	cbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 6a 	cbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe 60 	cbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 60 	cbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df 60 	cbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 40 	cbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 69 34 00 	cbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 69 ab 00 	cbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 40 	cbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 40 	cbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 40 	cbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 40 	cbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 69 ff 0f 	cbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 69 ff 0f 	cbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 69 ff ff 	cbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 69 43 23 	cbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 41 	cbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 44 	cbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d 5f 	cbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 4f 	cbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 4f 	cbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 44 	cbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 40 	cbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 69 34 00 	cbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 69 ab 00 	cbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 40 	cbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 40 	cbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 40 	cbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 40 	cbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 69 ff 0f 	cbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 69 ff 0f 	cbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 69 ff ff 	cbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 69 43 23 	cbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 41 	cbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 44 	cbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd 5f 	cbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 4f 	cbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 4f 	cbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 44 	cbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 6e       	cbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 69 01 00 	cbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 69 34 12 	cbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 69 34 12 	cbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 51 	cbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 69 23 01 	cbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 51 	cbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 6e       	cbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 69 01 00 	cbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 69 34 12 	cbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 69 34 12 	cbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 51 	cbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 69 23 01 	cbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 51 	cbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/cbitw_test.s b/gas/testsuite/gas/cr16/cbitw_test.s
new file mode 100644
index 0000000..61bda08
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	cbitw $4,0xbcd
+	cbitw $5,0xaabcd
+	cbitw $3,0xfaabcd
+	cbitw $10,0xbcd
+	cbitw $15,0xaabcd
+	cbitw $14,0xfaabcd
+
+	cbitw $5,[r12]0x14
+	cbitw $4,[r13]0xabfc
+	cbitw $3,[r12]0x1234
+	cbitw $3,[r13]0x1234
+	cbitw $3,[r12]0x34
+	cbitw $15,[r12]0x14
+	cbitw $14,[r13]0xabfc
+	cbitw $13,[r12]0x1234
+	cbitw $13,[r13]0x1234
+	cbitw $11,[r12]0x34
+
+	cbitw $3,[r12]0xa7a(r1,r0)
+	cbitw $3,[r12]0xa7a(r3,r2)
+	cbitw $3,[r12]0xa7a(r4,r3)
+	cbitw $3,[r12]0xa7a(r5,r4)
+	cbitw $3,[r12]0xa7a(r6,r5)
+	cbitw $3,[r12]0xa7a(r7,r6)
+	cbitw $3,[r12]0xa7a(r9,r8)
+	cbitw $3,[r12]0xa7a(r11,r10)
+	cbitw $3,[r13]0xa7a(r1,r0)
+	cbitw $3,[r13]0xa7a(r3,r2)
+	cbitw $3,[r13]0xa7a(r4,r3)
+	cbitw $3,[r13]0xa7a(r5,r4)
+	cbitw $3,[r13]0xa7a(r6,r5)
+	cbitw $3,[r13]0xa7a(r7,r6)
+	cbitw $3,[r13]0xa7a(r9,r8)
+	cbitw $3,[r13]0xa7a(r11,r10)
+	cbitw $5,[r13]0xb7a(r4,r3)
+	cbitw $1,[r12]0x17a(r6,r5)
+	cbitw $1,[r13]0x134(r6,r5)
+	cbitw $3,[r12]0xabcde(r4,r3)
+	cbitw $5,[r13]0xabcd(r4,r3)
+	cbitw $3,[r12]0xabcd(r6,r5)
+	cbitw $3,[r13]0xbcde(r6,r5)
+	cbitw $13,[r12]0xa7a(r1,r0)
+	cbitw $13,[r12]0xa7a(r3,r2)
+	cbitw $13,[r12]0xa7a(r4,r3)
+	cbitw $13,[r12]0xa7a(r5,r4)
+	cbitw $13,[r12]0xa7a(r6,r5)
+	cbitw $13,[r12]0xa7a(r7,r6)
+	cbitw $13,[r12]0xa7a(r9,r8)
+	cbitw $13,[r12]0xa7a(r11,r10)
+	cbitw $13,[r13]0xa7a(r1,r0)
+	cbitw $13,[r13]0xa7a(r3,r2)
+	cbitw $13,[r13]0xa7a(r4,r3)
+	cbitw $13,[r13]0xa7a(r5,r4)
+	cbitw $13,[r13]0xa7a(r6,r5)
+	cbitw $13,[r13]0xa7a(r7,r6)
+	cbitw $13,[r13]0xa7a(r9,r8)
+	cbitw $13,[r13]0xa7a(r11,r10)
+	cbitw $15,[r13]0xb7a(r4,r3)
+	cbitw $11,[r12]0x17a(r6,r5)
+	cbitw $11,[r13]0x134(r6,r5)
+	cbitw $13,[r12]0xabcde(r4,r3)
+	cbitw $15,[r13]0xabcd(r4,r3)
+	cbitw $13,[r12]0xabcd(r6,r5)
+	cbitw $13,[r13]0xbcde(r6,r5)
+
+	cbitw $5,0x0(r2)
+	cbitw $3,0x34(r12)
+	cbitw $3,0xab(r13)
+	cbitw $5,0xad(r1)
+	cbitw $5,0xcd(r2)
+	cbitw $5,0xfff(r0)
+	cbitw $3,0xbcd(r4)
+	cbitw $3,0xfff(r12)
+	cbitw $3,0xfff(r13)
+	cbitw $3,0xffff(r13)
+	cbitw $3,0x2343(r12)
+	cbitw $3,0x12345(r2)
+	cbitw $3,0x4abcd(r8)
+	cbitw $3,0xfabcd(r13)
+	cbitw $3,0xfabcd(r8)
+	cbitw $3,0xfabcd(r9)
+	cbitw $3,0x4abcd(r9)
+	cbitw $15,0x0(r2)
+	cbitw $13,0x34(r12)
+	cbitw $13,0xab(r13)
+	cbitw $15,0xad(r1)
+	cbitw $15,0xcd(r2)
+	cbitw $15,0xfff(r0)
+	cbitw $13,0xbcd(r4)
+	cbitw $13,0xfff(r12)
+	cbitw $13,0xfff(r13)
+	cbitw $13,0xffff(r13)
+	cbitw $13,0x2343(r12)
+	cbitw $13,0x12345(r2)
+	cbitw $13,0x4abcd(r8)
+	cbitw $13,0xfabcd(r13)
+	cbitw $13,0xfabcd(r8)
+	cbitw $13,0xfabcd(r9)
+	cbitw $13,0x4abcd(r9)
+
+	cbitw $3,0x0(r2,r1)
+	cbitw $5,0x1(r2,r1)
+	cbitw $4,0x1234(r2,r1)
+	cbitw $3,0x1234(r2,r1)
+	cbitw $3,0x12345(r2,r1)
+	cbitw $3,0x123(r2,r1)
+	cbitw $3,0x12345(r2,r1)
+	cbitw $13,0x0(r2,r1)
+	cbitw $15,0x1(r2,r1)
+	cbitw $14,0x1234(r2,r1)
+	cbitw $13,0x1234(r2,r1)
+	cbitw $13,0x12345(r2,r1)
+	cbitw $13,0x123(r2,r1)
+	cbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/cinv_test.d b/gas/testsuite/gas/cr16/cinv_test.d
new file mode 100644
index 0000000..f1e2f25
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cinv_test.d
@@ -0,0 +1,15 @@
+#as:
+#objdump:  -dr
+#name:  cinv_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	0a 00       	cinv    \[i\]
+   2:	0b 00       	cinv    \[i,u\]
+   4:	0c 00       	cinv    \[d\]
+   6:	0d 00       	cinv    \[d,u\]
+   8:	0e 00       	cinv    \[d,i\]
+   a:	0f 00       	cinv    \[d,i,u\]
diff --git a/gas/testsuite/gas/cr16/cinv_test.s b/gas/testsuite/gas/cr16/cinv_test.s
new file mode 100644
index 0000000..eda4b97
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cinv_test.s
@@ -0,0 +1,12 @@
+        .text

+        .global main

+main:

+	##############################

+	# cin [i/i,u/d/d,u/d,i/d,i,u]

+	##############################

+	cinv   [i]

+	cinv   [i,u]

+	cinv   [d]

+	cinv   [d,u]

+	cinv   [d,i]

+	cinv   [d,i,u]

diff --git a/gas/testsuite/gas/cr16/cmp_test.d b/gas/testsuite/gas/cr16/cmp_test.d
new file mode 100644
index 0000000..6c3e101
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cmp_test.d
@@ -0,0 +1,51 @@
+#as:
+#objdump:  -dr
+#name:  cmp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 50       	cmpb	\$0xf:s,r1
+   2:	b2 50 ff 00 	cmpb	\$0xff:m,r2
+   6:	b1 50 ff 0f 	cmpb	\$0xfff:m,r1
+   a:	b1 50 14 00 	cmpb	\$0x14:m,r1
+   e:	a2 50       	cmpb	\$0xa:s,r2
+  10:	b2 50 0b 00 	cmpb	\$0xb:m,r2
+  14:	12 51       	cmpb	r1,r2
+  16:	23 51       	cmpb	r2,r3
+  18:	34 51       	cmpb	r3,r4
+  1a:	56 51       	cmpb	r5,r6
+  1c:	67 51       	cmpb	r6,r7
+  1e:	78 51       	cmpb	r7,r8
+  20:	f1 52       	cmpw	\$0xf:s,r1
+  22:	b1 52 0b 00 	cmpw	\$0xb:m,r1
+  26:	b2 52 ff 00 	cmpw	\$0xff:m,r2
+  2a:	b1 52 ff 0f 	cmpw	\$0xfff:m,r1
+  2e:	b1 52 14 00 	cmpw	\$0x14:m,r1
+  32:	a2 52       	cmpw	\$0xa:s,r2
+  34:	b2 52 0b 00 	cmpw	\$0xb:m,r2
+  38:	12 53       	cmpw	r1,r2
+  3a:	23 53       	cmpw	r2,r3
+  3c:	34 53       	cmpw	r3,r4
+  3e:	56 53       	cmpw	r5,r6
+  40:	67 53       	cmpw	r6,r7
+  42:	78 53       	cmpw	r7,r8
+  44:	f1 56       	cmpd	\$0xf:s,\(r2,r1\)
+  46:	b1 56 0b 00 	cmpd	\$0xb:m,\(r2,r1\)
+  4a:	b1 56 ff 00 	cmpd	\$0xff:m,\(r2,r1\)
+  4e:	b1 56 ff 0f 	cmpd	\$0xfff:m,\(r2,r1\)
+  52:	91 00 00 00 	cmpd	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	91 00 0f 00 	cmpd	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	91 00 ff 0f 	cmpd	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	91 56       	cmpd	\$-1:s,\(r2,r1\)
+  66:	31 57       	cmpd	\(r4,r3\),\(r2,r1\)
+  68:	31 57       	cmpd	\(r4,r3\),\(r2,r1\)
+  6a:	af 56       	cmpd	\$0xa:s,\(sp\)
+  6c:	ef 56       	cmpd	\$0xe:s,\(sp\)
+  6e:	bf 56 0b 00 	cmpd	\$0xb:m,\(sp\)
+  72:	8f 56       	cmpd	\$0x8:s,\(sp\)
diff --git a/gas/testsuite/gas/cr16/cmp_test.s b/gas/testsuite/gas/cr16/cmp_test.s
new file mode 100644
index 0000000..2d0af3b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cmp_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+        ###########
+	# CMPB imm4/imm16, reg
+        ###########
+	cmpb    $0xf,r1
+	cmpb    $0xff,r2
+	cmpb    $0xfff,r1
+	#cmpb    $0xffff,r2 // CHCEFK WITH CRASM 4.1
+	cmpb    $20,r1
+	cmpb    $10,r2
+	cmpb    $11,r2
+        ###########
+	# CMPB reg, reg
+        ###########
+	cmpb    r1,r2
+	cmpb    r2,r3
+	cmpb    r3,r4
+	cmpb    r5,r6
+	cmpb    r6,r7
+	cmpb    r7,r8
+        ###########
+	# CMPW imm4/imm16, reg
+        ###########
+	cmpw    $0xf,r1
+	cmpw    $0xB,r1
+	cmpw    $0xff,r2
+	cmpw    $0xfff,r1
+	#cmpw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	cmpw    $20,r1
+	cmpw    $10,r2
+	cmpw    $11,r2
+        ###########
+	# CMPW reg, reg
+        ###########
+	cmpw    r1,r2
+	cmpw    r2,r3
+	cmpw    r3,r4
+	cmpw    r5,r6
+	cmpw    r6,r7
+	cmpw    r7,r8
+        ###########
+	# CMPD imm4/imm16/imm32, regp
+        ###########
+	cmpd    $0xf,(r2,r1)
+	cmpd    $0xB,(r2,r1)
+	cmpd    $0xff,(r2,r1)
+	cmpd    $0xfff,(r2,r1)
+	cmpd    $0xffff,(r2,r1)
+	cmpd    $0xfffff,(r2,r1)
+	cmpd    $0xfffffff,(r2,r1)
+	cmpd    $0xffffffff,(r2,r1)
+        ###########
+	# CMPD regp, regp
+        ###########
+	cmpd    (r4,r3),(r2,r1)
+	cmpd    (r4,r3),(r2,r1)
+	cmpd    $10,(sp)
+	cmpd    $14,(sp)
+	cmpd    $11,(sp)
+	cmpd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/cr16.exp b/gas/testsuite/gas/cr16/cr16.exp
new file mode 100644
index 0000000..6697c33
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cr16.exp
@@ -0,0 +1,27 @@
+#
+# Driver for CR16 assembler testsuite
+#
+
+proc run_list_test { name opts } {
+  global srcdir subdir
+  set testname "cr16 $name"
+  set file $srcdir/$subdir/$name
+  gas_run ${name}.s $opts ">&dump.out"
+  if {[regexp_diff "dump.out" "${file}.l"] } {
+    fail $testname
+    verbose "output is [file_contents "dump.out"]" 2
+    return
+  }
+  pass $testname
+}
+
+if ![istarget cr16-*-*] {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach test $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $test]
+    run_dump_test [file rootname $test]
+}
diff --git a/gas/testsuite/gas/cr16/excp_test.d b/gas/testsuite/gas/cr16/excp_test.d
new file mode 100644
index 0000000..7c4053b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/excp_test.d
@@ -0,0 +1,18 @@
+#as:
+#objdump:  -dr
+#name:  excp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c5 00       	excp	svc
+   2:	c6 00       	excp	dvz
+   4:	c7 00       	excp	flg
+   6:	c8 00       	excp	bpt
+   8:	c9 00       	excp	trc
+   a:	ca 00       	excp	und
+   c:	cc 00       	excp	iad
+   e:	ce 00       	excp	dbg
+  10:	cf 00       	excp	ise
diff --git a/gas/testsuite/gas/cr16/excp_test.s b/gas/testsuite/gas/cr16/excp_test.s
new file mode 100644
index 0000000..4984a74
--- /dev/null
+++ b/gas/testsuite/gas/cr16/excp_test.s
@@ -0,0 +1,15 @@
+        .text
+        .global main
+main:
+	##########################################
+	# excp svc/dvz/flg/bpt/trc/und/iad/dbg/ise
+	##########################################
+	excp	svc
+	excp	dvz
+	excp	flg
+	excp	bpt
+	excp	trc
+	excp	und
+	excp	iad
+	excp	dbg
+	excp	ise
diff --git a/gas/testsuite/gas/cr16/jal_test.d b/gas/testsuite/gas/cr16/jal_test.d
new file mode 100644
index 0000000..51a4e76
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jal_test.d
@@ -0,0 +1,14 @@
+#as:
+#objdump:  -dr
+#name:  jal_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	d1 00       	jal	\(r2,r1\)
+   2:	14 00 15 80 	jal	\(r6,r5\),\(r2,r1\)
+   6:	14 00 32 80 	jal	\(r3,r2\),\(r4,r3\)
+   a:	14 00 30 80 	jal	\(r1,r0\),\(r4,r3\)
+   e:	14 00 72 80 	jal	\(r3,r2\),\(r8,r7\)
diff --git a/gas/testsuite/gas/cr16/jal_test.s b/gas/testsuite/gas/cr16/jal_test.s
new file mode 100644
index 0000000..2a4715b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jal_test.s
@@ -0,0 +1,11 @@
+        .text
+        .global main
+main:
+	################
+	# JAL regp regp
+	################
+	jal (r2,r1)
+	jal (r6,r5),(r2,r1)
+	jal (r3,r2),(r4,r3)
+	jal (r1,r0), (r4,r3)
+	jal (r3,r2), (r8,r7)
diff --git a/gas/testsuite/gas/cr16/jcc_test.d b/gas/testsuite/gas/cr16/jcc_test.d
new file mode 100644
index 0000000..e192c9d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jcc_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  jcc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 0a       	jeq	\(r1,r0\)
+   2:	11 0a       	jne	\(r2,r1\)
+   4:	32 0a       	jcc	\(r3,r2\)
+   6:	33 0a       	jcc	\(r4,r3\)
+   8:	44 0a       	jhi	\(r5,r4\)
+   a:	c5 0a       	jlt	\(r6,r5\)
+   c:	66 0a       	jgt	\(r7,r6\)
+   e:	87 0a       	jfs	\(r8,r7\)
+  10:	98 0a       	jfc	\(r9,r8\)
+  12:	a9 0a       	jlo	\(r10,r9\)
+  14:	4a 0a       	jhi	\(r11,r10\)
+  16:	c0 0a       	jlt	\(r1,r0\)
+  18:	d2 0a       	jge	\(r3,r2\)
+  1a:	e5 0a       	jump	\(r6,r5\)
+  1c:	f5 0a       	jusr	\(r6,r5\)
diff --git a/gas/testsuite/gas/cr16/jcc_test.s b/gas/testsuite/gas/cr16/jcc_test.s
new file mode 100644
index 0000000..c384e1a
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jcc_test.s
@@ -0,0 +1,21 @@
+        .text
+        .global main
+main:
+	##########
+	# JCond regp
+	##########
+	jeq	(r1,r0)
+	jne	(r2,r1)
+	jcc	(r3,r2)
+	jcc	(r4,r3)
+	jhi	(r5,r4)
+	jlt	(r6,r5)
+	jgt	(r7,r6)
+	jfs	(r8,r7)
+	jfc	(r9,r8)
+	jlo	(r10,r9)
+	jhi	(r11,r10)
+	jlt	(r1,r0)
+	jge	(r3,r2)
+	jump	(r6,r5)
+	jusr	(r6,r5)
diff --git a/gas/testsuite/gas/cr16/loadb_test.d b/gas/testsuite/gas/cr16/loadb_test.d
new file mode 100644
index 0000000..0e22d57
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadb_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadd_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 88 00 00 	loadb	0x0 <main>:m,r0
+   4:	10 88 ff 00 	loadb	0xff <main\+0xff>:m,r1
+   8:	30 88 ff 0f 	loadb	0xfff <main\+0xfff>:m,r3
+   c:	40 88 34 12 	loadb	0x1234 <main\+0x1234>:m,r4
+  10:	50 88 34 12 	loadb	0x1234 <main\+0x1234>:m,r5
+  14:	12 00 07 7a 	loadb	0x7a1234 <main\+0x7a1234>:l,r0
+  18:	34 12 
+  1a:	12 00 1b 7a 	loadb	0xba1234 <main\+0xba1234>:l,r1
+  1e:	34 12 
+  20:	2f 88 ff ff 	loadb	0xfffff <main\+0xfffff>:m,r2
+  24:	00 8a 00 00 	loadb	\[r12\]0x0:m,r0
+  28:	00 8b 00 00 	loadb	\[r12\]0x0:m,r0
+  2c:	10 8a ff 00 	loadb	\[r12\]0xff:m,r1
+  30:	10 8b ff 00 	loadb	\[r12\]0xff:m,r1
+  34:	30 8a ff 0f 	loadb	\[r12\]0xfff:m,r3
+  38:	30 8b ff 0f 	loadb	\[r12\]0xfff:m,r3
+  3c:	40 8a 34 12 	loadb	\[r13\]0x1234:m,r4
+  40:	40 8b 34 12 	loadb	\[r13\]0x1234:m,r4
+  44:	50 8a 34 12 	loadb	\[r13\]0x1234:m,r5
+  48:	50 8b 34 12 	loadb	\[r13\]0x1234:m,r5
+  4c:	20 8a 67 45 	loadb	\[r12\]0x4567:m,r2
+  50:	2a 8b 34 12 	loadb	\[r12\]0xa1234:m,r2
+  54:	10 b4       	loadb	0x4:s\(r1,r0\),r1
+  56:	32 b4       	loadb	0x4:s\(r3,r2\),r3
+  58:	40 bf 34 12 	loadb	0x1234:m\(r1,r0\),r4
+  5c:	52 bf 34 12 	loadb	0x1234:m\(r3,r2\),r5
+  60:	12 00 60 5a 	loadb	0xa1234:l\(r1,r0\),r6
+  64:	34 12 
+  66:	18 00 10 5f 	loadb	0xffffc:l\(r1,r0\),r1
+  6a:	fc ff 
+  6c:	18 00 32 5f 	loadb	0xffffc:l\(r3,r2\),r3
+  70:	fc ff 
+  72:	18 00 40 5f 	loadb	0xfedcc:l\(r1,r0\),r4
+  76:	cc ed 
+  78:	18 00 52 5f 	loadb	0xfedcc:l\(r3,r2\),r5
+  7c:	cc ed 
+  7e:	18 00 60 55 	loadb	0x5edcc:l\(r1,r0\),r6
+  82:	cc ed 
+  84:	00 b0       	loadb	0x0:s\(r1,r0\),r0
+  86:	10 b0       	loadb	0x0:s\(r1,r0\),r1
+  88:	00 bf 0f 00 	loadb	0xf:m\(r1,r0\),r0
+  8c:	10 bf 0f 00 	loadb	0xf:m\(r1,r0\),r1
+  90:	20 bf 34 12 	loadb	0x1234:m\(r1,r0\),r2
+  94:	32 bf cd ab 	loadb	0xabcd:m\(r3,r2\),r3
+  98:	43 bf ff af 	loadb	0xafff:m\(r4,r3\),r4
+  9c:	12 00 55 5a 	loadb	0xa1234:l\(r6,r5\),r5
+  a0:	34 12 
+  a2:	18 00 00 5f 	loadb	0xffff1:l\(r1,r0\),r0
+  a6:	f1 ff 
+  a8:	18 00 10 5f 	loadb	0xffff1:l\(r1,r0\),r1
+  ac:	f1 ff 
+  ae:	18 00 20 5f 	loadb	0xfedcc:l\(r1,r0\),r2
+  b2:	cc ed 
+  b4:	18 00 32 5f 	loadb	0xf5433:l\(r3,r2\),r3
+  b8:	33 54 
+  ba:	18 00 43 5f 	loadb	0xf5001:l\(r4,r3\),r4
+  be:	01 50 
+  c0:	18 00 55 55 	loadb	0x5edcc:l\(r6,r5\),r5
+  c4:	cc ed 
+  c6:	00 be       	loadb	\[r12\]0x0:s\(r1,r0\),r0
+  c8:	18 be       	loadb	\[r13\]0x0:s\(r1,r0\),r1
+  ca:	70 86 04 12 	loadb	\[r12\]0x234:m\(r1,r0\),r7
+  ce:	12 00 38 61 	loadb	\[r13\]0x1abcd:l\(r1,r0\),r3
+  d2:	cd ab 
+  d4:	12 00 40 6a 	loadb	\[r12\]0xa1234:l\(r1,r0\),r4
+  d8:	34 12 
+  da:	12 00 58 6b 	loadb	\[r13\]0xb1234:l\(r1,r0\),r5
+  de:	34 12 
+  e0:	12 00 68 6f 	loadb	\[r13\]0xfffff:l\(r1,r0\),r6
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadb_test.s b/gas/testsuite/gas/cr16/loadb_test.s
new file mode 100644
index 0000000..258e3b3
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadb_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadb abs20/24 reg

+	######################

+	loadb 0x0,r0

+	loadb 0xff,r1

+	loadb 0xfff,r3

+	loadb 0x1234,r4

+	loadb 0x1234,r5

+	loadb 0x7A1234,r0

+	loadb 0xBA1234,r1

+	loadb 0xffffff,r2

+	######################

+	#  loadb abs20 rel reg

+	######################

+	loadb [r12]0x0,r0

+	loadb [r13]0x0,r0

+	loadb [r12]0xff,r1

+	loadb [r13]0xff,r1

+	loadb [r12]0xfff,r3

+	loadb [r13]0xfff,r3

+	loadb [r12]0x1234,r4

+	loadb [r13]0x1234,r4

+	loadb [r12]0x1234,r5

+	loadb [r13]0x1234,r5

+	loadb [r12]0x4567,r2

+	loadb [r13]0xA1234,r2

+	###################################

+	#  loadb rbase(disp20/-disp20)  reg

+	###################################

+	loadb 0x4(r1,r0),r1

+	loadb 0x4(r3,r2),r3

+	loadb 0x1234(r1,r0),r4

+	loadb 0x1234(r3,r2),r5

+	loadb 0xA1234(r1,r0),r6

+	loadb -0x4(r1,r0),r1

+	loadb -0x4(r3,r2),r3

+	loadb -0x1234(r1,r0),r4

+	loadb -0x1234(r3,r2),r5

+	loadb -0xA1234(r1,r0),r6

+	#################################################

+	#  loadb rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadb 0x0(r1,r0),r0

+	loadb 0x0(r1,r0),r1

+	loadb 0xf(r1,r0),r0

+	loadb 0xf(r1,r0),r1

+	loadb 0x1234(r1,r0),r2

+	loadb 0xabcd(r3,r2),r3

+	loadb 0xAfff(r4,r3),r4

+	loadb 0xA1234(r6,r5),r5

+	loadb -0xf(r1,r0),r0

+	loadb -0xf(r1,r0),r1

+	loadb -0x1234(r1,r0),r2

+	loadb -0xabcd(r3,r2),r3

+	loadb -0xAfff(r4,r3),r4

+	loadb -0xA1234(r6,r5),r5

+	####################################

+	#  loadb rbase(disp0/disp14) rel reg

+	####################################

+	loadb [r12]0x0(r1,r0),r0

+	loadb [r13]0x0(r1,r0),r1

+	loadb [r12]0x1234(r1,r0),r2

+	loadb [r13]0x1abcd(r1,r0),r3

+	#################################

+	#  loadb rpbase(disp20) rel reg

+	#################################

+	loadb [r12]0xA1234(r1,r0),r4

+	loadb [r13]0xB1234(r1,r0),r5

+	loadb [r13]0xfffff(r1,r0),r6

diff --git a/gas/testsuite/gas/cr16/loadd_test.d b/gas/testsuite/gas/cr16/loadd_test.d
new file mode 100644
index 0000000..77ea45f
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadd_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadd_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 87 00 00 	loadd	0x0 <main>:m,\(r1,r0\)
+   4:	00 87 ff 00 	loadd	0xff <main\+0xff>:m,\(r1,r0\)
+   8:	20 87 ff 0f 	loadd	0xfff <main\+0xfff>:m,\(r3,r2\)
+   c:	30 87 34 12 	loadd	0x1234 <main\+0x1234>:m,\(r4,r3\)
+  10:	40 87 34 12 	loadd	0x1234 <main\+0x1234>:m,\(r5,r4\)
+  14:	12 00 07 ba 	loadd	0x7a1234 <main\+0x7a1234>:l,\(r1,r0\)
+  18:	34 12 
+  1a:	12 00 0b ba 	loadd	0xba1234 <main\+0xba1234>:l,\(r1,r0\)
+  1e:	34 12 
+  20:	1f 87 ff ff 	loadd	0xfffff <main\+0xfffff>:m,\(r2,r1\)
+  24:	00 8c 00 00 	loadd	\[r12\]0x0:m,\(r1,r0\)
+  28:	00 8d 00 00 	loadd	\[r12\]0x0:m,\(r1,r0\)
+  2c:	00 8c ff 00 	loadd	\[r12\]0xff:m,\(r1,r0\)
+  30:	00 8d ff 00 	loadd	\[r12\]0xff:m,\(r1,r0\)
+  34:	20 8c ff 0f 	loadd	\[r12\]0xfff:m,\(r3,r2\)
+  38:	20 8d ff 0f 	loadd	\[r12\]0xfff:m,\(r3,r2\)
+  3c:	30 8c 34 12 	loadd	\[r12\]0x1234:m,\(r4,r3\)
+  40:	30 8d 34 12 	loadd	\[r12\]0x1234:m,\(r4,r3\)
+  44:	40 8c 34 12 	loadd	\[r13\]0x1234:m,\(r5,r4\)
+  48:	40 8d 34 12 	loadd	\[r13\]0x1234:m,\(r5,r4\)
+  4c:	10 8c 67 45 	loadd	\[r12\]0x4567:m,\(r2,r1\)
+  50:	1a 8d 34 12 	loadd	\[r12\]0xa1234:m,\(r2,r1\)
+  54:	10 a2       	loadd	0x4:s\(r1,r0\),\(r2,r1\)
+  56:	22 a2       	loadd	0x4:s\(r3,r2\),\(r3,r2\)
+  58:	30 af 34 12 	loadd	0x1234:m\(r1,r0\),\(r4,r3\)
+  5c:	42 af 34 12 	loadd	0x1234:m\(r3,r2\),\(r5,r4\)
+  60:	12 00 50 9a 	loadd	0xa1234:l\(r1,r0\),\(r6,r5\)
+  64:	34 12 
+  66:	18 00 10 9f 	loadd	0xffffc:l\(r1,r0\),\(r2,r1\)
+  6a:	fc ff 
+  6c:	18 00 22 9f 	loadd	0xffffc:l\(r3,r2\),\(r3,r2\)
+  70:	fc ff 
+  72:	18 00 30 9f 	loadd	0xfedcc:l\(r1,r0\),\(r4,r3\)
+  76:	cc ed 
+  78:	18 00 42 9f 	loadd	0xfedcc:l\(r3,r2\),\(r5,r4\)
+  7c:	cc ed 
+  7e:	18 00 50 95 	loadd	0x5edcc:l\(r1,r0\),\(r6,r5\)
+  82:	cc ed 
+  84:	00 a0       	loadd	0x0:s\(r1,r0\),\(r1,r0\)
+  86:	00 a0       	loadd	0x0:s\(r1,r0\),\(r1,r0\)
+  88:	00 af 0f 00 	loadd	0xf:m\(r1,r0\),\(r1,r0\)
+  8c:	00 af 0f 00 	loadd	0xf:m\(r1,r0\),\(r1,r0\)
+  90:	10 af 34 12 	loadd	0x1234:m\(r1,r0\),\(r2,r1\)
+  94:	22 af cd ab 	loadd	0xabcd:m\(r3,r2\),\(r3,r2\)
+  98:	33 af ff af 	loadd	0xafff:m\(r4,r3\),\(r4,r3\)
+  9c:	12 00 65 9a 	loadd	0xa1234:l\(r6,r5\),\(r7,r6\)
+  a0:	34 12 
+  a2:	18 00 00 9f 	loadd	0xffff1:l\(r1,r0\),\(r1,r0\)
+  a6:	f1 ff 
+  a8:	18 00 00 9f 	loadd	0xffff1:l\(r1,r0\),\(r1,r0\)
+  ac:	f1 ff 
+  ae:	18 00 10 9f 	loadd	0xfedcc:l\(r1,r0\),\(r2,r1\)
+  b2:	cc ed 
+  b4:	18 00 22 9f 	loadd	0xf5433:l\(r3,r2\),\(r3,r2\)
+  b8:	33 54 
+  ba:	18 00 43 9f 	loadd	0xf5001:l\(r4,r3\),\(r5,r4\)
+  be:	01 50 
+  c0:	18 00 45 95 	loadd	0x5edcc:l\(r6,r5\),\(r5,r4\)
+  c4:	cc ed 
+  c6:	00 ae       	loadd	\[r12\]0x0:s\(r1,r0\),\(r1,r0\)
+  c8:	08 ae       	loadd	\[r13\]0x0:s\(r1,r0\),\(r1,r0\)
+  ca:	b0 86 04 12 	loadd	\[r12\]0x234:m\(r1,r0\),\(r12,r11\)
+  ce:	12 00 28 a1 	loadd	\[r13\]0x1abcd:l\(r1,r0\),\(r3,r2\)
+  d2:	cd ab 
+  d4:	12 00 20 aa 	loadd	\[r12\]0xa1234:l\(r1,r0\),\(r3,r2\)
+  d8:	34 12 
+  da:	12 00 38 ab 	loadd	\[r13\]0xb1234:l\(r1,r0\),\(r4,r3\)
+  de:	34 12 
+  e0:	12 00 48 af 	loadd	\[r13\]0xfffff:l\(r1,r0\),\(r5,r4\)
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadd_test.s b/gas/testsuite/gas/cr16/loadd_test.s
new file mode 100644
index 0000000..677752d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadd_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadd abs20/24 regp

+	######################

+	loadd 0x0,(r1,r0)

+	loadd 0xff,(r1,r0)

+	loadd 0xfff,(r3,r2)

+	loadd 0x1234,(r4,r3)

+	loadd 0x1234,(r5,r4)

+	loadd 0x7A1234,(r1,r0)

+	loadd 0xBA1234,(r1,r0)

+	loadd 0xffffff,(r2,r1)

+	######################

+	#  loadd abs20 rel regp

+	######################

+	loadd [r12]0x0,(r1,r0)

+	loadd [r13]0x0,(r1,r0)

+	loadd [r12]0xff,(r1,r0)

+	loadd [r13]0xff,(r1,r0)

+	loadd [r12]0xfff,(r3,r2)

+	loadd [r13]0xfff,(r3,r2)

+	loadd [r12]0x1234,(r4,r3)

+	loadd [r13]0x1234,(r4,r3)

+	loadd [r12]0x1234,(r5,r4)

+	loadd [r13]0x1234,(r5,r4)

+	loadd [r12]0x4567,(r2,r1)

+	loadd [r13]0xA1234,(r2,r1)

+	###################################

+	#  loadd rbase(disp20/-disp20)  regp

+	###################################

+	loadd 0x4(r1,r0),(r2,r1)

+	loadd 0x4(r3,r2),(r3,r2)

+	loadd 0x1234(r1,r0),(r4,r3)

+	loadd 0x1234(r3,r2),(r5,r4)

+	loadd 0xA1234(r1,r0),(r6,r5)

+	loadd -0x4(r1,r0),(r2,r1)

+	loadd -0x4(r3,r2),(r3,r2)

+	loadd -0x1234(r1,r0),(r4,r3)

+	loadd -0x1234(r3,r2),(r5,r4)

+	loadd -0xA1234(r1,r0),(r6,r5)

+	#################################################

+	#  loadd rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadd 0x0(r1,r0),(r1,r0)

+	loadd 0x0(r1,r0),(r1,r0)

+	loadd 0xf(r1,r0),(r1,r0)

+	loadd 0xf(r1,r0),(r1,r0)

+	loadd 0x1234(r1,r0),(r2,r1)

+	loadd 0xabcd(r3,r2),(r3,r2)

+	loadd 0xAfff(r4,r3),(r4,r3)

+	loadd 0xA1234(r6,r5),(r7,r6)

+	loadd -0xf(r1,r0),(r1,r0)

+	loadd -0xf(r1,r0),(r1,r0)

+	loadd -0x1234(r1,r0),(r2,r1)

+	loadd -0xabcd(r3,r2),(r3,r2)

+	loadd -0xAfff(r4,r3),(r5,r4)

+	loadd -0xA1234(r6,r5),(r5,r4)

+	####################################

+	#  loadd rbase(disp0/disp14) rel reg

+	####################################

+	loadd [r12]0x0(r1,r0),(r1,r0)

+	loadd [r13]0x0(r1,r0),(r1,r0)

+	loadd [r12]0x1234(r1,r0),(r2,r1)

+	loadd [r13]0x1abcd(r1,r0),(r3,r2)

+	#################################

+	#  loadd rpbase(disp20) rel reg

+	#################################

+	loadd [r12]0xA1234(r1,r0),(r3,r2)

+	loadd [r13]0xB1234(r1,r0),(r4,r3)

+	loadd [r13]0xfffff(r1,r0),(r5,r4)

diff --git a/gas/testsuite/gas/cr16/loadm_test.d b/gas/testsuite/gas/cr16/loadm_test.d
new file mode 100644
index 0000000..7d7ff3e
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadm_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  loadm_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	a0 00       	loadm	\$0x1,r0
+   2:	a1 00       	loadm	\$0x2,r0
+   4:	a2 00       	loadm	\$0x3,r0
+   6:	a3 00       	loadm	\$0x4,r0
+   8:	a4 00       	loadm	\$0x5,r0
+   a:	a5 00       	loadm	\$0x6,r0
+   c:	a6 00       	loadm	\$0x7,r0
+   e:	a7 00       	loadm	\$0x8,r0
+  10:	a8 00       	loadmp	\$0x1,r0
+  12:	a9 00       	loadmp	\$0x2,r0
+  14:	aa 00       	loadmp	\$0x3,r0
+  16:	ab 00       	loadmp	\$0x4,r0
+  18:	ac 00       	loadmp	\$0x5,r0
+  1a:	ad 00       	loadmp	\$0x6,r0
+  1c:	ae 00       	loadmp	\$0x7,r0
+  1e:	af 00       	loadmp	\$0x8,r0
diff --git a/gas/testsuite/gas/cr16/loadm_test.s b/gas/testsuite/gas/cr16/loadm_test.s
new file mode 100644
index 0000000..3549e20
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadm_test.s
@@ -0,0 +1,25 @@
+        .text
+        .global main
+main:
+	##############
+	# loadm cnt
+	##############
+ 	loadm $1
+ 	loadm $2
+ 	loadm $3
+ 	loadm $4
+ 	loadm $5
+ 	loadm $6
+ 	loadm $7
+ 	loadm $8
+	##############
+	# loadmp cnt
+	##############
+ 	loadmp $1
+ 	loadmp $2
+ 	loadmp $3
+ 	loadmp $4
+ 	loadmp $5
+ 	loadmp $6
+ 	loadmp $7
+ 	loadmp $8
diff --git a/gas/testsuite/gas/cr16/loadw_test.d b/gas/testsuite/gas/cr16/loadw_test.d
new file mode 100644
index 0000000..cc4f311
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadw_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 89 00 00 	loadw	0x0 <main>:m,r0
+   4:	10 89 ff 00 	loadw	0xff <main\+0xff>:m,r1
+   8:	30 89 ff 0f 	loadw	0xfff <main\+0xfff>:m,r3
+   c:	40 89 34 12 	loadw	0x1234 <main\+0x1234>:m,r4
+  10:	50 89 34 12 	loadw	0x1234 <main\+0x1234>:m,r5
+  14:	12 00 07 fa 	loadw	0x7a1234 <main\+0x7a1234>:l,r0
+  18:	34 12 
+  1a:	12 00 1b fa 	loadw	0xba1234 <main\+0xba1234>:l,r1
+  1e:	34 12 
+  20:	2f 89 ff ff 	loadw	0xfffff <main\+0xfffff>:m,r2
+  24:	00 8e 00 00 	loadw	\[r12\]0x0:m,r0
+  28:	00 8f 00 00 	loadw	\[r12\]0x0:m,r0
+  2c:	10 8e ff 00 	loadw	\[r12\]0xff:m,r1
+  30:	10 8f ff 00 	loadw	\[r12\]0xff:m,r1
+  34:	30 8e ff 0f 	loadw	\[r12\]0xfff:m,r3
+  38:	30 8f ff 0f 	loadw	\[r12\]0xfff:m,r3
+  3c:	40 8e 34 12 	loadw	\[r13\]0x1234:m,r4
+  40:	40 8f 34 12 	loadw	\[r13\]0x1234:m,r4
+  44:	50 8e 34 12 	loadw	\[r13\]0x1234:m,r5
+  48:	50 8f 34 12 	loadw	\[r13\]0x1234:m,r5
+  4c:	20 8e 67 45 	loadw	\[r12\]0x4567:m,r2
+  50:	2a 8f 34 12 	loadw	\[r12\]0xa1234:m,r2
+  54:	10 92       	loadw	0x4:s\(r1,r0\),r1
+  56:	32 92       	loadw	0x4:s\(r3,r2\),r3
+  58:	40 9f 34 12 	loadw	0x1234:m\(r1,r0\),r4
+  5c:	52 9f 34 12 	loadw	0x1234:m\(r3,r2\),r5
+  60:	12 00 60 da 	loadw	0xa1234:l\(r1,r0\),r6
+  64:	34 12 
+  66:	18 00 10 df 	loadw	0xffffc:l\(r1,r0\),r1
+  6a:	fc ff 
+  6c:	18 00 32 df 	loadw	0xffffc:l\(r3,r2\),r3
+  70:	fc ff 
+  72:	18 00 40 df 	loadw	0xfedcc:l\(r1,r0\),r4
+  76:	cc ed 
+  78:	18 00 52 df 	loadw	0xfedcc:l\(r3,r2\),r5
+  7c:	cc ed 
+  7e:	18 00 60 d5 	loadw	0x5edcc:l\(r1,r0\),r6
+  82:	cc ed 
+  84:	00 90       	loadw	0x0:s\(r1,r0\),r0
+  86:	10 90       	loadw	0x0:s\(r1,r0\),r1
+  88:	00 9f 0f 00 	loadw	0xf:m\(r1,r0\),r0
+  8c:	10 9f 0f 00 	loadw	0xf:m\(r1,r0\),r1
+  90:	20 9f 34 12 	loadw	0x1234:m\(r1,r0\),r2
+  94:	32 9f cd ab 	loadw	0xabcd:m\(r3,r2\),r3
+  98:	43 9f ff af 	loadw	0xafff:m\(r4,r3\),r4
+  9c:	12 00 55 da 	loadw	0xa1234:l\(r6,r5\),r5
+  a0:	34 12 
+  a2:	18 00 00 df 	loadw	0xffff1:l\(r1,r0\),r0
+  a6:	f1 ff 
+  a8:	18 00 10 df 	loadw	0xffff1:l\(r1,r0\),r1
+  ac:	f1 ff 
+  ae:	18 00 20 df 	loadw	0xfedcc:l\(r1,r0\),r2
+  b2:	cc ed 
+  b4:	18 00 32 df 	loadw	0xf5433:l\(r3,r2\),r3
+  b8:	33 54 
+  ba:	18 00 43 df 	loadw	0xf5001:l\(r4,r3\),r4
+  be:	01 50 
+  c0:	18 00 55 d5 	loadw	0x5edcc:l\(r6,r5\),r5
+  c4:	cc ed 
+  c6:	00 9e       	loadw	\[r12\]0x0:s\(r1,r0\),r0
+  c8:	18 9e       	loadw	\[r13\]0x0:s\(r1,r0\),r1
+  ca:	f0 86 04 12 	loadw	\[r12\]0x234:m\(r1,r0\),r15
+  ce:	12 00 38 e1 	loadw	\[r13\]0x1abcd:l\(r1,r0\),r3
+  d2:	cd ab 
+  d4:	12 00 40 ea 	loadw	\[r12\]0xa1234:l\(r1,r0\),r4
+  d8:	34 12 
+  da:	12 00 58 eb 	loadw	\[r13\]0xb1234:l\(r1,r0\),r5
+  de:	34 12 
+  e0:	12 00 68 ef 	loadw	\[r13\]0xfffff:l\(r1,r0\),r6
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadw_test.s b/gas/testsuite/gas/cr16/loadw_test.s
new file mode 100644
index 0000000..bd9a2bb
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadw_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadw abs20/24 reg

+	######################

+	loadw 0x0,r0

+	loadw 0xff,r1

+	loadw 0xfff,r3

+	loadw 0x1234,r4

+	loadw 0x1234,r5

+	loadw 0x7A1234,r0

+	loadw 0xBA1234,r1

+	loadw 0xffffff,r2

+	######################

+	#  loadw abs20 rel reg

+	######################

+	loadw [r12]0x0,r0

+	loadw [r13]0x0,r0

+	loadw [r12]0xff,r1

+	loadw [r13]0xff,r1

+	loadw [r12]0xfff,r3

+	loadw [r13]0xfff,r3

+	loadw [r12]0x1234,r4

+	loadw [r13]0x1234,r4

+	loadw [r12]0x1234,r5

+	loadw [r13]0x1234,r5

+	loadw [r12]0x4567,r2

+	loadw [r13]0xA1234,r2

+	###################################

+	#  loadw rbase(disp20/-disp20)  reg

+	###################################

+	loadw 0x4(r1,r0),r1

+	loadw 0x4(r3,r2),r3

+	loadw 0x1234(r1,r0),r4

+	loadw 0x1234(r3,r2),r5

+	loadw 0xA1234(r1,r0),r6

+	loadw -0x4(r1,r0),r1

+	loadw -0x4(r3,r2),r3

+	loadw -0x1234(r1,r0),r4

+	loadw -0x1234(r3,r2),r5

+	loadw -0xA1234(r1,r0),r6

+	#################################################

+	#  loadw rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadw 0x0(r1,r0),r0

+	loadw 0x0(r1,r0),r1

+	loadw 0xf(r1,r0),r0

+	loadw 0xf(r1,r0),r1

+	loadw 0x1234(r1,r0),r2

+	loadw 0xabcd(r3,r2),r3

+	loadw 0xAfff(r4,r3),r4

+	loadw 0xA1234(r6,r5),r5

+	loadw -0xf(r1,r0),r0

+	loadw -0xf(r1,r0),r1

+	loadw -0x1234(r1,r0),r2

+	loadw -0xabcd(r3,r2),r3

+	loadw -0xAfff(r4,r3),r4

+	loadw -0xA1234(r6,r5),r5

+	####################################

+	#  loadw rbase(disp0/disp14) rel reg

+	####################################

+	loadw [r12]0x0(r1,r0),r0

+	loadw [r13]0x0(r1,r0),r1

+	loadw [r12]0x1234(r1,r0),r2

+	loadw [r13]0x1abcd(r1,r0),r3

+	#################################

+	#  loadw rpbase(disp20) rel reg

+	#################################

+	loadw [r12]0xA1234(r1,r0),r4

+	loadw [r13]0xB1234(r1,r0),r5

+	loadw [r13]0xfffff(r1,r0),r6

diff --git a/gas/testsuite/gas/cr16/lpsp_test.d b/gas/testsuite/gas/cr16/lpsp_test.d
new file mode 100644
index 0000000..66ca8e2
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lpsp_test.d
@@ -0,0 +1,57 @@
+#as:
+#objdump:  -dr
+#name:  lpsp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	14 00 91 00 	lpr	r1,psr
+   4:	14 00 82 00 	lpr	r2,cfg
+   8:	14 00 a2 00 	lpr	r2,intbasel
+   c:	14 00 b3 00 	lpr	r3,intbaseh
+  10:	14 00 c4 00 	lpr	r4,ispl
+  14:	14 00 d5 00 	lpr	r5,isph
+  18:	14 00 e6 00 	lpr	r6,uspl
+  1c:	14 00 f7 00 	lpr	r7,usph
+  20:	14 00 18 00 	lpr	r8,dsr
+  24:	14 00 29 00 	lpr	r9,dcrl
+  28:	14 00 3a 00 	lpr	r10,dcrh
+  2c:	14 00 4b 00 	lpr	r11,car0l
+  30:	14 00 50 00 	lpr	r0,car0h
+  34:	14 00 61 00 	lpr	r1,car1l
+  38:	14 00 73 00 	lpr	r3,car1h
+  3c:	14 00 90 10 	lprd	\(r1,r0\),psr
+  40:	14 00 81 10 	lprd	\(r2,r1\),cfg
+  44:	14 00 a2 10 	lprd	\(r3,r2\),intbase
+  48:	14 00 c3 10 	lprd	\(r4,r3\),isp
+  4c:	14 00 e4 10 	lprd	\(r5,r4\),usp
+  50:	14 00 15 10 	lprd	\(r6,r5\),dsr
+  54:	14 00 26 10 	lprd	\(r7,r6\),dcr
+  58:	14 00 47 10 	lprd	\(r8,r7\),car0
+  5c:	14 00 68 10 	lprd	\(r9,r8\),car1
+  60:	14 00 90 20 	spr	psr,r0
+  64:	14 00 81 20 	spr	cfg,r1
+  68:	14 00 a2 20 	spr	intbasel,r2
+  6c:	14 00 b3 20 	spr	intbaseh,r3
+  70:	14 00 c4 20 	spr	ispl,r4
+  74:	14 00 d5 20 	spr	isph,r5
+  78:	14 00 e6 20 	spr	uspl,r6
+  7c:	14 00 f7 20 	spr	usph,r7
+  80:	14 00 18 20 	spr	dsr,r8
+  84:	14 00 29 20 	spr	dcrl,r9
+  88:	14 00 3a 20 	spr	dcrh,r10
+  8c:	14 00 4b 20 	spr	car0l,r11
+  90:	14 00 50 20 	spr	car0h,r0
+  94:	14 00 61 20 	spr	car1l,r1
+  98:	14 00 72 20 	spr	car1h,r2
+  9c:	14 00 90 30 	sprd	psr,\(r1,r0\)
+  a0:	14 00 81 30 	sprd	cfg,\(r2,r1\)
+  a4:	14 00 a2 30 	sprd	intbase,\(r3,r2\)
+  a8:	14 00 c3 30 	sprd	isp,\(r4,r3\)
+  ac:	14 00 e4 30 	sprd	usp,\(r5,r4\)
+  b0:	14 00 15 30 	sprd	dsr,\(r6,r5\)
+  b4:	14 00 26 30 	sprd	dcr,\(r7,r6\)
+  b8:	14 00 47 30 	sprd	car0,\(r8,r7\)
+  bc:	14 00 68 30 	sprd	car1,\(r9,r8\)
diff --git a/gas/testsuite/gas/cr16/lpsp_test.s b/gas/testsuite/gas/cr16/lpsp_test.s
new file mode 100644
index 0000000..8e9d459
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lpsp_test.s
@@ -0,0 +1,63 @@
+        .text

+        .global main

+main:

+	################

+	# lpr reg, preg

+	################

+	lpr	r1,psr

+	lpr	r2,cfg

+	lpr	r2,intbasel

+	lpr	r3,intbaseh

+	lpr	r4,ispl

+	lpr	r5,isph

+	lpr	r6,uspl

+	lpr	r7,usph

+	lpr	r8,dsr

+	lpr	r9,dcrl

+	lpr	r10,dcrh

+	lpr	r11,car0l

+	lpr	r0,car0h

+	lpr	r1,car1l

+	lpr	r3,car1h

+	#################

+	# lprd regp, preg

+	#################

+	lprd	(r1,r0),psr

+	lprd	(r2,r1),cfg

+	lprd	(r3,r2),intbase

+	lprd	(r4,r3),isp

+	lprd	(r5,r4),usp

+	lprd	(r6,r5),dsr

+	lprd	(r7,r6),dcr

+	lprd	(r8,r7),car0

+	lprd	(r9,r8),car1

+	#################

+	# spr preg, reg

+	#################

+	spr	psr,r0

+	spr	cfg,r1

+	spr	intbasel,r2

+	spr	intbaseh,r3

+	spr	ispl,r4

+	spr	isph,r5

+	spr	uspl,r6

+	spr	usph,r7

+	spr	dsr,r8

+	spr	dcrl,r9

+	spr	dcrh,r10

+	spr	car0l,r11

+	spr	car0h,r0

+	spr	car1l,r1

+	spr	car1h,r2

+	#################

+	# sprd preg, regp

+	#################

+	sprd	psr,(r1,r0)

+	sprd	cfg,(r2,r1)

+	sprd	intbase,(r3,r2)

+	sprd	isp,(r4,r3)

+	sprd	usp,(r5,r4)

+	sprd	dsr,(r6,r5)

+	sprd	dcr,(r7,r6)

+	sprd	car0,(r8,r7)

+	sprd	car1,(r9,r8)

diff --git a/gas/testsuite/gas/cr16/lsh_test.d b/gas/testsuite/gas/cr16/lsh_test.d
new file mode 100644
index 0000000..aba1cda
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lsh_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  lsh_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 40       	ashub	\$7:s,r1
+   2:	91 09       	lshb	\$-7:s,r1
+   4:	41 40       	ashub	\$4:s,r1
+   6:	c1 09       	lshb	\$-4:s,r1
+   8:	81 09       	lshb	\$-8:s,r1
+   a:	31 40       	ashub	\$3:s,r1
+   c:	d1 09       	lshb	\$-3:s,r1
+   e:	21 44       	lshb	r2,r1
+  10:	34 44       	lshb	r3,r4
+  12:	56 44       	lshb	r5,r6
+  14:	8a 44       	lshb	r8,r10
+  16:	71 42       	ashuw	\$7:s,r1
+  18:	91 49       	lshw	\$-7:s,r1
+  1a:	41 42       	ashuw	\$4:s,r1
+  1c:	c1 49       	lshw	\$-4:s,r1
+  1e:	81 42       	ashuw	\$8:s,r1
+  20:	81 49       	lshw	\$-8:s,r1
+  22:	31 42       	ashuw	\$3:s,r1
+  24:	d1 49       	lshw	\$-3:s,r1
+  26:	21 46       	lshw	r2,r1
+  28:	34 46       	lshw	r3,r4
+  2a:	56 46       	lshw	r5,r6
+  2c:	8a 46       	lshw	r8,r10
+  2e:	72 4c       	ashud	\$7:s,\(r3,r2\)
+  30:	92 4b       	lshd	\$-7:s,\(r3,r2\)
+  32:	82 4c       	ashud	\$8:s,\(r3,r2\)
+  34:	82 4b       	lshd	\$-8:s,\(r3,r2\)
+  36:	42 4c       	ashud	\$4:s,\(r3,r2\)
+  38:	c2 4b       	lshd	\$-4:s,\(r3,r2\)
+  3a:	c2 4c       	ashud	\$12:s,\(r3,r2\)
+  3c:	42 4b       	lshd	\$-12:s,\(r3,r2\)
+  3e:	31 4c       	ashud	\$3:s,\(r2,r1\)
+  40:	d1 4b       	lshd	\$-3:s,\(r2,r1\)
+  42:	41 47       	lshd	r4,\(r2,r1\)
+  44:	51 47       	lshd	r5,\(r2,r1\)
+  46:	61 47       	lshd	r6,\(r2,r1\)
+  48:	81 47       	lshd	r8,\(r2,r1\)
+  4a:	11 47       	lshd	r1,\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/lsh_test.s b/gas/testsuite/gas/cr16/lsh_test.s
new file mode 100644
index 0000000..3236cbd
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lsh_test.s
@@ -0,0 +1,59 @@
+        .text
+        .global main
+main:
+	###########################
+	# LSHB cnt(right -), reg
+	###########################
+        lshb   $7,r1
+        lshb   $-7,r1
+        lshb   $4,r1
+        lshb   $-4,r1
+        lshb	$-8,r1
+        lshb   $3,r1
+        lshb   $-3,r1
+	###########################
+	# LSHB reg, reg
+	###########################
+        lshb   r2,r1
+        lshb   r3,r4
+        lshb   r5,r6
+        lshb   r8,r10
+	###########################
+	# LSHW cnt (right -), reg
+	###########################
+        lshw   $7,r1
+        lshw   $-7,r1
+        lshw   $4,r1
+        lshw   $-4,r1
+        lshw	$8,r1
+        lshw	$-8,r1
+        lshw   $3,r1
+        lshw   $-3,r1
+	##########################
+	# LSHW reg, reg
+	##########################
+        lshw   r2,r1
+        lshw   r3,r4
+        lshw   r5,r6
+        lshw   r8,r10
+	###########################
+	# LSHD cnt (right -), regp
+	############################
+        lshd   $7, (r3,r2)
+        lshd   $-7, (r3,r2)
+        lshd   $8, (r3,r2)
+        lshd   $-8, (r3,r2)
+        lshd   $4, (r3,r2)
+        lshd   $-4, (r3,r2)
+        lshd   $12,(r3,r2)
+        lshd   $-12,(r3,r2)
+        lshd	$3,(r2,r1)
+        lshd	$-3,(r2,r1)
+	#################
+	# LSHD reg, regp
+	#################
+        lshd   r4,(r2,r1)
+        lshd   r5,(r2,r1)
+        lshd   r6,(r2,r1)
+        lshd   r8,(r2,r1)
+        lshd   r1,(r2,r1)
diff --git a/gas/testsuite/gas/cr16/mov_test.d b/gas/testsuite/gas/cr16/mov_test.d
new file mode 100644
index 0000000..ce253e7
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mov_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  mov_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 58       	movb	\$0xf:s,r1
+   2:	b2 58 ff 00 	movb	\$0xff:m,r2
+   6:	b1 58 ff 0f 	movb	\$0xfff:m,r1
+   a:	b1 58 14 00 	movb	\$0x14:m,r1
+   e:	a2 58       	movb	\$0xa:s,r2
+  10:	b2 58 0b 00 	movb	\$0xb:m,r2
+  14:	12 59       	movb	r1,r2
+  16:	23 59       	movb	r2,r3
+  18:	34 59       	movb	r3,r4
+  1a:	56 59       	movb	r5,r6
+  1c:	67 59       	movb	r6,r7
+  1e:	78 59       	movb	r7,r8
+  20:	f1 5a       	movw	\$0xf:s,r1
+  22:	b1 5a 0b 00 	movw	\$0xb:m,r1
+  26:	b2 5a ff 00 	movw	\$0xff:m,r2
+  2a:	b1 5a ff 0f 	movw	\$0xfff:m,r1
+  2e:	b1 5a 14 00 	movw	\$0x14:m,r1
+  32:	a2 5a       	movw	\$0xa:s,r2
+  34:	b2 5a 0b 00 	movw	\$0xb:m,r2
+  38:	12 5b       	movw	r1,r2
+  3a:	23 5b       	movw	r2,r3
+  3c:	34 5b       	movw	r3,r4
+  3e:	56 5b       	movw	r5,r6
+  40:	67 5b       	movw	r6,r7
+  42:	78 5b       	movw	r7,r8
+  44:	f1 54       	movd	\$0xf:s,\(r2,r1\)
+  46:	b1 54 0b 00 	movd	\$0xb:m,\(r2,r1\)
+  4a:	b1 54 ff 00 	movd	\$0xff:m,\(r2,r1\)
+  4e:	b1 54 ff 0f 	movd	\$0xfff:m,\(r2,r1\)
+  52:	10 05 ff ff 	movd	\$0xffff:m,\(r2,r1\)
+  56:	1f 05 ff ff 	movd	\$0xfffff:m,\(r2,r1\)
+  5a:	71 00 ff 0f 	movd	\$0xfffffff:l,\(r2,r1\)
+  5e:	ff ff 
+  60:	91 54       	movd	\$-1:s,\(r2,r1\)
+  62:	31 55       	movd	\(r4,r3\),\(r2,r1\)
+  64:	31 55       	movd	\(r4,r3\),\(r2,r1\)
+  66:	af 54       	movd	\$0xa:s,\(sp\)
+  68:	ef 54       	movd	\$0xe:s,\(sp\)
+  6a:	bf 54 0b 00 	movd	\$0xb:m,\(sp\)
+  6e:	8f 54       	movd	\$0x8:s,\(sp\)
+  70:	12 5c       	movxb	r1,r2
+  72:	34 5c       	movxb	r3,r4
+  74:	56 5c       	movxb	r5,r6
+  76:	78 5c       	movxb	r7,r8
+  78:	9a 5c       	movxb	r9,r10
+  7a:	12 5e       	movxw	r1,\(r3,r2\)
+  7c:	33 5e       	movxw	r3,\(r4,r3\)
+  7e:	55 5e       	movxw	r5,\(r6,r5\)
+  80:	77 5e       	movxw	r7,\(r8,r7\)
+  82:	98 5e       	movxw	r9,\(r9,r8\)
+  84:	12 5d       	movzb	r1,r2
+  86:	34 5d       	movzb	r3,r4
+  88:	56 5d       	movzb	r5,r6
+  8a:	78 5d       	movzb	r7,r8
+  8c:	9a 5d       	movzb	r9,r10
+  8e:	12 5f       	movzw	r1,\(r3,r2\)
+  90:	33 5f       	movzw	r3,\(r4,r3\)
+  92:	55 5f       	movzw	r5,\(r6,r5\)
+  94:	77 5f       	movzw	r7,\(r8,r7\)
+  96:	98 5f       	movzw	r9,\(r9,r8\)
diff --git a/gas/testsuite/gas/cr16/mov_test.s b/gas/testsuite/gas/cr16/mov_test.s
new file mode 100644
index 0000000..20fdf4d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mov_test.s
@@ -0,0 +1,94 @@
+        .text
+        .global main
+main:
+        ###########
+	# MOVB imm4/imm16, reg
+        ###########
+	movb    $0xf,r1
+	movb    $0xff,r2
+	movb    $0xfff,r1
+	#movb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	movb    $20,r1
+	movb    $10,r2
+	movb    $11,r2
+        ###########
+	# MOVB reg, reg
+        ###########
+	movb    r1,r2
+	movb    r2,r3
+	movb    r3,r4
+	movb    r5,r6
+	movb    r6,r7
+	movb    r7,r8
+        ###########
+	# MOVW imm4/imm16, reg
+        ###########
+	movw    $0xf,r1
+	movw    $0xB,r1
+	movw    $0xff,r2
+	movw    $0xfff,r1
+	#movw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	movw    $20,r1
+	movw    $10,r2
+	movw    $11,r2
+        ###########
+	# MOVW reg, reg
+        ###########
+	movw    r1,r2
+	movw    r2,r3
+	movw    r3,r4
+	movw    r5,r6
+	movw    r6,r7
+	movw    r7,r8
+        ###########
+	# MOVD imm4/imm16/imm20/imm32, regp
+        ###########
+	movd    $0xf,(r2,r1)
+	movd    $0xB,(r2,r1)
+	movd    $0xff,(r2,r1)
+	movd    $0xfff,(r2,r1)
+	movd    $0xffff,(r2,r1)
+	movd    $0xfffff,(r2,r1)
+	movd    $0xfffffff,(r2,r1)
+	movd    $0xffffffff,(r2,r1)
+        ###########
+	# MOVD regp, regp
+        ###########
+	movd    (r4,r3),(r2,r1)
+	movd    (r4,r3),(r2,r1)
+	movd    $10,(sp)
+	movd    $14,(sp)
+	movd    $11,(sp)
+	movd    $8,(sp)
+        ###########
+	# MOVXB reg, reg
+        ###########
+	movxb	r1,r2
+	movxb	r3,r4
+	movxb	r5,r6
+	movxb	r7,r8
+	movxb	r9,r10
+        ###########
+	# MOVXW reg, regp
+        ###########
+	movxw	r1,(r3,r2)
+	movxw	r3,(r4,r3)
+	movxw	r5,(r6,r5)
+	movxw	r7,(r8,r7)
+	movxw	r9,(r9,r8)
+        ###########
+	# MOVZB reg, reg
+        ###########
+	movzb	r1,r2
+	movzb	r3,r4
+	movzb	r5,r6
+	movzb	r7,r8
+	movzb	r9,r10
+        ###########
+	# MOVZW reg, regp
+        ###########
+	movzw	r1,(r3,r2)
+	movzw	r3,(r4,r3)
+	movzw	r5,(r6,r5)
+	movzw	r7,(r8,r7)
+	movzw	r9,(r9,r8)
diff --git a/gas/testsuite/gas/cr16/mul_test.d b/gas/testsuite/gas/cr16/mul_test.d
new file mode 100644
index 0000000..6e5755d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mul_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  mul_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 64       	mulb	\$0xf:s,r1
+   2:	b2 64 ff 00 	mulb	\$0xff:m,r2
+   6:	b1 64 ff 0f 	mulb	\$0xfff:m,r1
+   a:	b1 64 14 00 	mulb	\$0x14:m,r1
+   e:	a2 64       	mulb	\$0xa:s,r2
+  10:	12 65       	mulb	r1,r2
+  12:	23 65       	mulb	r2,r3
+  14:	34 65       	mulb	r3,r4
+  16:	56 65       	mulb	r5,r6
+  18:	67 65       	mulb	r6,r7
+  1a:	78 65       	mulb	r7,r8
+  1c:	f1 66       	mulw	\$0xf:s,r1
+  1e:	b2 66 ff 00 	mulw	\$0xff:m,r2
+  22:	b1 66 ff 0f 	mulw	\$0xfff:m,r1
+  26:	b1 66 14 00 	mulw	\$0x14:m,r1
+  2a:	a2 66       	mulw	\$0xa:s,r2
+  2c:	12 67       	mulw	r1,r2
+  2e:	23 67       	mulw	r2,r3
+  30:	34 67       	mulw	r3,r4
+  32:	56 67       	mulw	r5,r6
+  34:	67 67       	mulw	r6,r7
+  36:	78 67       	mulw	r7,r8
+  38:	12 0b       	mulsb	r1,r2
+  3a:	34 0b       	mulsb	r3,r4
+  3c:	56 0b       	mulsb	r5,r6
+  3e:	78 0b       	mulsb	r7,r8
+  40:	9a 0b       	mulsb	r9,r10
+  42:	12 62       	mulsw	r1,\(r3,r2\)
+  44:	33 62       	mulsw	r3,\(r4,r3\)
+  46:	55 62       	mulsw	r5,\(r6,r5\)
+  48:	77 62       	mulsw	r7,\(r8,r7\)
+  4a:	98 62       	mulsw	r9,\(r9,r8\)
+  4c:	14 00 12 d2 	macqw	r1,r2,\(r3,r2\)
+  50:	14 00 45 d4 	macqw	r4,r5,\(r5,r4\)
+  54:	14 00 12 e2 	macuw	r1,r2,\(r3,r2\)
+  58:	14 00 45 e7 	macuw	r4,r5,\(r8,r7\)
+  5c:	14 00 12 f2 	macsw	r1,r2,\(r3,r2\)
+  60:	14 00 45 f6 	macsw	r4,r5,\(r7,r6\)
diff --git a/gas/testsuite/gas/cr16/mul_test.s b/gas/testsuite/gas/cr16/mul_test.s
new file mode 100644
index 0000000..c2b960c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mul_test.s
@@ -0,0 +1,64 @@
+        .text
+        .global main
+main:
+        ###########
+	# MULB imm4/imm16, reg
+        ###########
+	mulb    $0xf,r1
+	mulb    $0xff,r2
+	mulb    $0xfff,r1
+	#mulb    $0xffff,r2 // CHCEK WITH CRASM 4.1
+	mulb    $20,r1
+	mulb    $10,r2
+        ###########
+	# MULB reg, reg
+        ###########
+	mulb    r1,r2
+	mulb    r2,r3
+	mulb    r3,r4
+	mulb    r5,r6
+	mulb    r6,r7
+	mulb    r7,r8
+        ###########
+	# MULW imm4/imm16, reg
+        ###########
+	mulw    $0xf,r1
+	mulw    $0xff,r2
+	mulw    $0xfff,r1
+	#mulw    $0xffff,r2 // CHCEK WITH CRASM 4.1
+	mulw    $20,r1
+	mulw    $10,r2
+        ###########
+	# MULW reg, reg
+        ###########
+	mulw    r1,r2
+	mulw    r2,r3
+	mulw    r3,r4
+	mulw    r5,r6
+	mulw    r6,r7
+	mulw    r7,r8
+        ###########
+	# MULSB reg, reg
+        ###########
+	mulsb	r1,r2
+	mulsb	r3,r4
+	mulsb	r5,r6
+	mulsb	r7,r8
+	mulsb	r9,r10
+        ###########
+	# MULSW reg, regp
+        ###########
+	mulsw	r1,(r3,r2)
+	mulsw	r3,(r4,r3)
+	mulsw	r5,(r6,r5)
+	mulsw	r7,(r8,r7)
+	mulsw	r9,(r9,r8)
+        #############################
+	# MUC[q/u/s/]w reg, reg, regp
+        #############################
+	macqw   r1,r2,(r3,r2)
+	macqw   r4,r5,(r5,r4)
+	macuw   r1,r2,(r3,r2)
+	macuw   r4,r5,(r8,r7)
+	macsw   r1,r2,(r3,r2)
+	macsw   r4,r5,(r7,r6)
diff --git a/gas/testsuite/gas/cr16/or_test.d b/gas/testsuite/gas/cr16/or_test.d
new file mode 100644
index 0000000..73d95d0
--- /dev/null
+++ b/gas/testsuite/gas/cr16/or_test.d
@@ -0,0 +1,49 @@
+#as:
+#objdump:  -dr
+#name:  or_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 24       	orb	\$0xf:s,r1
+   2:	b2 24 ff 00 	orb	\$0xff:m,r2
+   6:	b1 24 ff 0f 	orb	\$0xfff:m,r1
+   a:	b2 24 ff ff 	orb	\$0xffff:m,r2
+   e:	b1 24 14 00 	orb	\$0x14:m,r1
+  12:	a2 24       	orb	\$0xa:s,r2
+  14:	12 25       	orb	r1,r2
+  16:	23 25       	orb	r2,r3
+  18:	34 25       	orb	r3,r4
+  1a:	56 25       	orb	r5,r6
+  1c:	67 25       	orb	r6,r7
+  1e:	78 25       	orb	r7,r8
+  20:	f1 26       	orw	\$0xf:s,r1
+  22:	b2 26 ff 00 	orw	\$0xff:m,r2
+  26:	b1 26 ff 0f 	orw	\$0xfff:m,r1
+  2a:	b2 26 ff ff 	orw	\$0xffff:m,r2
+  2e:	b1 26 14 00 	orw	\$0x14:m,r1
+  32:	a2 26       	orw	\$0xa:s,r2
+  34:	12 27       	orw	r1,r2
+  36:	23 27       	orw	r2,r3
+  38:	34 27       	orw	r3,r4
+  3a:	56 27       	orw	r5,r6
+  3c:	67 27       	orw	r6,r7
+  3e:	78 27       	orw	r7,r8
+  40:	51 00 00 00 	ord	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	51 00 00 00 	ord	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	51 00 00 00 	ord	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	51 00 00 00 	ord	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	51 00 0f 00 	ord	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	51 00 ff 0f 	ord	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	51 00 ff ff 	ord	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 90 	ord	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 90 	ord	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/or_test.s b/gas/testsuite/gas/cr16/or_test.s
new file mode 100644
index 0000000..df140c1
--- /dev/null
+++ b/gas/testsuite/gas/cr16/or_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# ORB imm4/imm16, reg
+        ###########
+	orb    $0xf,r1
+	orb    $0xff,r2
+	orb    $0xfff,r1
+	orb    $0xffff,r2
+	orb    $20,r1
+	orb    $10,r2
+        ###########
+	# ORB reg, reg
+        ###########
+	orb    r1,r2
+	orb    r2,r3
+	orb    r3,r4
+	orb    r5,r6
+	orb    r6,r7
+	orb    r7,r8
+        ###########
+	# ORW imm4/imm16, reg
+        ###########
+	orw    $0xf,r1
+	orw    $0xff,r2
+	orw    $0xfff,r1
+	orw    $0xffff,r2
+	orw    $20,r1
+	orw    $10,r2
+        ###########
+	# ORW reg, reg
+        ###########
+	orw    r1,r2
+	orw    r2,r3
+	orw    r3,r4
+	orw    r5,r6
+	orw    r6,r7
+	orw    r7,r8
+        ###########
+	# ORD imm32, regp
+        ###########
+	ord    $0xf,(r2,r1)
+	ord    $0xff,(r2,r1)
+	ord    $0xfff,(r2,r1)
+	ord    $0xffff,(r2,r1)
+	ord    $0xfffff,(r2,r1)
+	ord    $0xfffffff,(r2,r1)
+	ord    $0xffffffff,(r2,r1)
+        ###########
+	# ORD regp, regp
+        ###########
+	ord    (r4,r3),(r2,r1)
+	ord    (r4,r3),(r2,r1)
+	#ord    $10,(sp)
+	#ord    $14,(sp)
+	#ord    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/pop_test.d b/gas/testsuite/gas/cr16/pop_test.d
new file mode 100644
index 0000000..1ed8c43
--- /dev/null
+++ b/gas/testsuite/gas/cr16/pop_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  pop_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 02       	pop	\$0x1,r7,RA
+   2:	96 02       	pop	\$0x2,r6,RA
+   4:	a5 02       	pop	\$0x3,r5,RA
+   6:	b4 02       	pop	\$0x4,r4,RA
+   8:	c3 02       	pop	\$0x5,r3,RA
+   a:	d2 02       	pop	\$0x6,r2,RA
+   c:	e1 02       	pop	\$0x7,r1,RA
+   e:	07 02       	pop	\$0x1,r7
+  10:	16 02       	pop	\$0x2,r6
+  12:	25 02       	pop	\$0x3,r5
+  14:	34 02       	pop	\$0x4,r4
+  16:	43 02       	pop	\$0x5,r3
+  18:	52 02       	pop	\$0x6,r2
+  1a:	61 02       	pop	\$0x7,r1
+  1c:	1e 02       	pop	RA
diff --git a/gas/testsuite/gas/cr16/pop_test.s b/gas/testsuite/gas/cr16/pop_test.s
new file mode 100644
index 0000000..e88acff
--- /dev/null
+++ b/gas/testsuite/gas/cr16/pop_test.s
@@ -0,0 +1,27 @@
+        .text
+        .global main
+main:
+	####################
+	# pop uimm3 regr RA
+	####################
+	pop $1,r7,RA
+	pop $2,r6,RA
+	pop $3,r5,RA
+	pop $4,r4,RA
+	pop $5,r3,RA
+	pop $6,r2,RA
+	pop $7,r1,RA
+	#################
+	# pop uimm3 regr
+	#################
+	pop $1,r7
+	pop $2,r6
+	pop $3,r5
+	pop $4,r4
+	pop $5,r3
+	pop $6,r2
+	pop $7,r1
+	##########
+	# pop RA
+	##########
+	pop RA
diff --git a/gas/testsuite/gas/cr16/popret_test.d b/gas/testsuite/gas/cr16/popret_test.d
new file mode 100644
index 0000000..cbc8f85
--- /dev/null
+++ b/gas/testsuite/gas/cr16/popret_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  popret_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 03       	popret	\$0x1,r7,RA
+   2:	96 03       	popret	\$0x2,r6,RA
+   4:	a5 03       	popret	\$0x3,r5,RA
+   6:	b4 03       	popret	\$0x4,r4,RA
+   8:	c3 03       	popret	\$0x5,r3,RA
+   a:	d2 03       	popret	\$0x6,r2,RA
+   c:	e1 03       	popret	\$0x7,r1,RA
+   e:	07 03       	popret	\$0x1,r7
+  10:	16 03       	popret	\$0x2,r6
+  12:	25 03       	popret	\$0x3,r5
+  14:	34 03       	popret	\$0x4,r4
+  16:	43 03       	popret	\$0x5,r3
+  18:	52 03       	popret	\$0x6,r2
+  1a:	61 03       	popret	\$0x7,r1
+  1c:	1e 03       	popret	RA
diff --git a/gas/testsuite/gas/cr16/popret_test.s b/gas/testsuite/gas/cr16/popret_test.s
new file mode 100644
index 0000000..f88bf28
--- /dev/null
+++ b/gas/testsuite/gas/cr16/popret_test.s
@@ -0,0 +1,27 @@
+        .text
+        .global main
+main:
+	####################
+	# popret uimm3 regr RA
+	####################
+	popret $1,r7,RA
+	popret $2,r6,RA
+	popret $3,r5,RA
+	popret $4,r4,RA
+	popret $5,r3,RA
+	popret $6,r2,RA
+	popret $7,r1,RA
+	#################
+	# popret uimm3 regr
+	#################
+	popret $1,r7
+	popret $2,r6
+	popret $3,r5
+	popret $4,r4
+	popret $5,r3
+	popret $6,r2
+	popret $7,r1
+	##########
+	# popret RA
+	##########
+	popret RA
diff --git a/gas/testsuite/gas/cr16/push_test.d b/gas/testsuite/gas/cr16/push_test.d
new file mode 100644
index 0000000..0a8afab
--- /dev/null
+++ b/gas/testsuite/gas/cr16/push_test.d
@@ -0,0 +1,26 @@
+#as:
+#objdump:  -dr
+#name:  push_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 01       	push	\$0x1,r7,RA
+   2:	96 01       	push	\$0x2,r6,RA
+   4:	a5 01       	push	\$0x3,r5,RA
+   6:	b4 01       	push	\$0x4,r4,RA
+   8:	c3 01       	push	\$0x5,r3,RA
+   a:	d2 01       	push	\$0x6,r2,RA
+   c:	e1 01       	push	\$0x7,r1,RA
+   e:	07 01       	push	\$0x1,r7
+  10:	16 01       	push	\$0x2,r6
+  12:	25 01       	push	\$0x3,r5
+  14:	34 01       	push	\$0x4,r4
+  16:	43 01       	push	\$0x5,r3
+  18:	52 01       	push	\$0x6,r2
+  1a:	61 01       	push	\$0x7,r1
+  1c:	5c 01       	push	\$0x6,r12
+  1e:	1e 01       	push	RA
+  20:	1e 01       	push	RA
diff --git a/gas/testsuite/gas/cr16/push_test.s b/gas/testsuite/gas/cr16/push_test.s
new file mode 100644
index 0000000..804419c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/push_test.s
@@ -0,0 +1,40 @@
+        .text
+        .global main
+main:
+	####################
+	# push uimm3 regr RA
+	####################
+	push $1,r7,RA
+	push $2,r6,RA
+	push $3,r5,RA
+	push $4,r4,RA
+	push $5,r3,RA
+	push $6,r2,RA
+	push $7,r1,RA
+#push $6,r12,RA
+	#push $7,r13,RA
+	#push $7,r12,RA
+	#push $8,r12,RA
+	#################
+	# push uimm3 regr
+	#################
+	push $1,r7
+	push $2,r6
+	push $3,r5
+	push $4,r4
+	push $5,r3
+	push $6,r2
+	push $7,r1
+	push $6,r12
+	#push $7,r13
+	#push $7,r12
+	#push $8,r12
+	#push $6,r13
+	##########
+	# push RA
+	##########
+	#push r1
+	#push r4
+	#push r9
+	push ra
+	push RA
diff --git a/gas/testsuite/gas/cr16/sbitb_test.d b/gas/testsuite/gas/cr16/sbitb_test.d
new file mode 100644
index 0000000..e04ddde
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  sbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 73 cd 0b 	sbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 73 cd ab 	sbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f ba 	sbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 70 14 00 	sbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 70 fc ab 	sbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 70 34 12 	sbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 70 34 12 	sbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 70 34 00 	sbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 72 5a 4b 	sbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 72 1a 41 	sbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 72 14 01 	sbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 aa 	sbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e a0 	sbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 a0 	sbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f a0 	sbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 80 	sbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 73 34 00 	sbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 73 ab 00 	sbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 80 	sbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 80 	sbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 80 	sbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 80 	sbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 73 ff 0f 	sbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 73 ff 0f 	sbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 73 ff ff 	sbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 73 43 23 	sbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 81 	sbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 84 	sbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d 9f 	sbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 8f 	sbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 8f 	sbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 84 	sbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 72       	sbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 73 01 00 	sbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 73 34 12 	sbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 73 34 12 	sbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 91 	sbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 73 23 01 	sbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 91 	sbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/sbitb_test.s b/gas/testsuite/gas/cr16/sbitb_test.s
new file mode 100644
index 0000000..937e6c6
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	sbitb $4,0xbcd
+	sbitb $5,0xaabcd
+	sbitb $3,0xfaabcd
+
+	sbitb $5,[r12]0x14
+	sbitb $4,[r13]0xabfc
+	sbitb $3,[r12]0x1234
+	sbitb $3,[r13]0x1234
+	sbitb $3,[r12]0x34
+
+	sbitb $3,[r12]0xa7a(r1,r0)
+	sbitb $3,[r12]0xa7a(r3,r2)
+	sbitb $3,[r12]0xa7a(r4,r3)
+	sbitb $3,[r12]0xa7a(r5,r4)
+	sbitb $3,[r12]0xa7a(r6,r5)
+	sbitb $3,[r12]0xa7a(r7,r6)
+	sbitb $3,[r12]0xa7a(r9,r8)
+	sbitb $3,[r12]0xa7a(r11,r10)
+	sbitb $3,[r13]0xa7a(r1,r0)
+	sbitb $3,[r13]0xa7a(r3,r2)
+	sbitb $3,[r13]0xa7a(r4,r3)
+	sbitb $3,[r13]0xa7a(r5,r4)
+	sbitb $3,[r13]0xa7a(r6,r5)
+	sbitb $3,[r13]0xa7a(r7,r6)
+	sbitb $3,[r13]0xa7a(r9,r8)
+	sbitb $3,[r13]0xa7a(r11,r10)
+	sbitb $5,[r13]0xb7a(r4,r3)
+	sbitb $1,[r12]0x17a(r6,r5)
+	sbitb $1,[r13]0x134(r6,r5)
+	sbitb $3,[r12]0xabcde(r4,r3)
+	sbitb $5,[r13]0xabcd(r4,r3)
+	sbitb $3,[r12]0xabcd(r6,r5)
+	sbitb $3,[r13]0xbcde(r6,r5)
+
+	sbitb $5,0x0(r2)
+	sbitb $3,0x34(r12)
+	sbitb $3,0xab(r13)
+	sbitb $5,0xad(r1)
+	sbitb $5,0xcd(r2)
+	sbitb $5,0xfff(r0)
+	sbitb $3,0xbcd(r4)
+	sbitb $3,0xfff(r12)
+	sbitb $3,0xfff(r13)
+	sbitb $3,0xffff(r13)
+	sbitb $3,0x2343(r12)
+	sbitb $3,0x12345(r2)
+	sbitb $3,0x4abcd(r8)
+	sbitb $3,0xfabcd(r13)
+	sbitb $3,0xfabcd(r8)
+	sbitb $3,0xfabcd(r9)
+	sbitb $3,0x4abcd(r9)
+
+	sbitb $3,0x0(r2,r1)
+	sbitb $5,0x1(r2,r1)
+	sbitb $4,0x1234(r2,r1)
+	sbitb $3,0x1234(r2,r1)
+	sbitb $3,0x12345(r2,r1)
+	sbitb $3,0x123(r2,r1)
+	sbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/sbitw_test.d b/gas/testsuite/gas/cr16/sbitw_test.d
new file mode 100644
index 0000000..afc75f4
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  sbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 77 cd 0b 	sbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 77 cd ab 	sbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f ba 	sbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 77 cd 0b 	sbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 77 cd ab 	sbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef ba 	sbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 74 14 00 	sbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 75 fc ab 	sbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 74 34 12 	sbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 75 34 12 	sbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 74 34 00 	sbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 74 14 00 	sbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 75 fc ab 	sbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 74 34 12 	sbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 75 34 12 	sbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 74 34 00 	sbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 72 5a 4b 	sbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 72 1a 41 	sbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 72 14 01 	sbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 aa 	sbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e a0 	sbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 a0 	sbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f a0 	sbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 72 fa 4b 	sbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 72 ba 41 	sbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 72 b4 01 	sbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 aa 	sbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe a0 	sbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 a0 	sbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df a0 	sbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 80 	sbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 71 34 00 	sbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 71 ab 00 	sbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 80 	sbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 80 	sbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 80 	sbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 80 	sbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 71 ff 0f 	sbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 71 ff 0f 	sbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 71 ff ff 	sbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 71 43 23 	sbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 81 	sbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 84 	sbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d 9f 	sbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 8f 	sbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 8f 	sbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 84 	sbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 80 	sbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 71 34 00 	sbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 71 ab 00 	sbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 80 	sbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 80 	sbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 80 	sbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 80 	sbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 71 ff 0f 	sbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 71 ff 0f 	sbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 71 ff ff 	sbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 71 43 23 	sbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 81 	sbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 84 	sbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd 9f 	sbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 8f 	sbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 8f 	sbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 84 	sbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 76       	sbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 71 01 00 	sbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 71 34 12 	sbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 71 34 12 	sbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 91 	sbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 71 23 01 	sbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 91 	sbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 76       	sbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 71 01 00 	sbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 71 34 12 	sbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 71 34 12 	sbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 91 	sbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 71 23 01 	sbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 91 	sbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/sbitw_test.s b/gas/testsuite/gas/cr16/sbitw_test.s
new file mode 100644
index 0000000..334d033
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	sbitw $4,0xbcd
+	sbitw $5,0xaabcd
+	sbitw $3,0xfaabcd
+	sbitw $10,0xbcd
+	sbitw $15,0xaabcd
+	sbitw $14,0xfaabcd
+
+	sbitw $5,[r12]0x14
+	sbitw $4,[r13]0xabfc
+	sbitw $3,[r12]0x1234
+	sbitw $3,[r13]0x1234
+	sbitw $3,[r12]0x34
+	sbitw $15,[r12]0x14
+	sbitw $14,[r13]0xabfc
+	sbitw $13,[r12]0x1234
+	sbitw $13,[r13]0x1234
+	sbitw $11,[r12]0x34
+
+	sbitw $3,[r12]0xa7a(r1,r0)
+	sbitw $3,[r12]0xa7a(r3,r2)
+	sbitw $3,[r12]0xa7a(r4,r3)
+	sbitw $3,[r12]0xa7a(r5,r4)
+	sbitw $3,[r12]0xa7a(r6,r5)
+	sbitw $3,[r12]0xa7a(r7,r6)
+	sbitw $3,[r12]0xa7a(r9,r8)
+	sbitw $3,[r12]0xa7a(r11,r10)
+	sbitw $3,[r13]0xa7a(r1,r0)
+	sbitw $3,[r13]0xa7a(r3,r2)
+	sbitw $3,[r13]0xa7a(r4,r3)
+	sbitw $3,[r13]0xa7a(r5,r4)
+	sbitw $3,[r13]0xa7a(r6,r5)
+	sbitw $3,[r13]0xa7a(r7,r6)
+	sbitw $3,[r13]0xa7a(r9,r8)
+	sbitw $3,[r13]0xa7a(r11,r10)
+	sbitw $5,[r13]0xb7a(r4,r3)
+	sbitw $1,[r12]0x17a(r6,r5)
+	sbitw $1,[r13]0x134(r6,r5)
+	sbitw $3,[r12]0xabcde(r4,r3)
+	sbitw $5,[r13]0xabcd(r4,r3)
+	sbitw $3,[r12]0xabcd(r6,r5)
+	sbitw $3,[r13]0xbcde(r6,r5)
+	sbitw $13,[r12]0xa7a(r1,r0)
+	sbitw $13,[r12]0xa7a(r3,r2)
+	sbitw $13,[r12]0xa7a(r4,r3)
+	sbitw $13,[r12]0xa7a(r5,r4)
+	sbitw $13,[r12]0xa7a(r6,r5)
+	sbitw $13,[r12]0xa7a(r7,r6)
+	sbitw $13,[r12]0xa7a(r9,r8)
+	sbitw $13,[r12]0xa7a(r11,r10)
+	sbitw $13,[r13]0xa7a(r1,r0)
+	sbitw $13,[r13]0xa7a(r3,r2)
+	sbitw $13,[r13]0xa7a(r4,r3)
+	sbitw $13,[r13]0xa7a(r5,r4)
+	sbitw $13,[r13]0xa7a(r6,r5)
+	sbitw $13,[r13]0xa7a(r7,r6)
+	sbitw $13,[r13]0xa7a(r9,r8)
+	sbitw $13,[r13]0xa7a(r11,r10)
+	sbitw $15,[r13]0xb7a(r4,r3)
+	sbitw $11,[r12]0x17a(r6,r5)
+	sbitw $11,[r13]0x134(r6,r5)
+	sbitw $13,[r12]0xabcde(r4,r3)
+	sbitw $15,[r13]0xabcd(r4,r3)
+	sbitw $13,[r12]0xabcd(r6,r5)
+	sbitw $13,[r13]0xbcde(r6,r5)
+
+	sbitw $5,0x0(r2)
+	sbitw $3,0x34(r12)
+	sbitw $3,0xab(r13)
+	sbitw $5,0xad(r1)
+	sbitw $5,0xcd(r2)
+	sbitw $5,0xfff(r0)
+	sbitw $3,0xbcd(r4)
+	sbitw $3,0xfff(r12)
+	sbitw $3,0xfff(r13)
+	sbitw $3,0xffff(r13)
+	sbitw $3,0x2343(r12)
+	sbitw $3,0x12345(r2)
+	sbitw $3,0x4abcd(r8)
+	sbitw $3,0xfabcd(r13)
+	sbitw $3,0xfabcd(r8)
+	sbitw $3,0xfabcd(r9)
+	sbitw $3,0x4abcd(r9)
+	sbitw $15,0x0(r2)
+	sbitw $13,0x34(r12)
+	sbitw $13,0xab(r13)
+	sbitw $15,0xad(r1)
+	sbitw $15,0xcd(r2)
+	sbitw $15,0xfff(r0)
+	sbitw $13,0xbcd(r4)
+	sbitw $13,0xfff(r12)
+	sbitw $13,0xfff(r13)
+	sbitw $13,0xffff(r13)
+	sbitw $13,0x2343(r12)
+	sbitw $13,0x12345(r2)
+	sbitw $13,0x4abcd(r8)
+	sbitw $13,0xfabcd(r13)
+	sbitw $13,0xfabcd(r8)
+	sbitw $13,0xfabcd(r9)
+	sbitw $13,0x4abcd(r9)
+
+	sbitw $3,0x0(r2,r1)
+	sbitw $5,0x1(r2,r1)
+	sbitw $4,0x1234(r2,r1)
+	sbitw $3,0x1234(r2,r1)
+	sbitw $3,0x12345(r2,r1)
+	sbitw $3,0x123(r2,r1)
+	sbitw $3,0x12345(r2,r1)
+	sbitw $13,0x0(r2,r1)
+	sbitw $15,0x1(r2,r1)
+	sbitw $14,0x1234(r2,r1)
+	sbitw $13,0x1234(r2,r1)
+	sbitw $13,0x12345(r2,r1)
+	sbitw $13,0x123(r2,r1)
+	sbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/scc_test.d b/gas/testsuite/gas/cr16/scc_test.d
new file mode 100644
index 0000000..308e755
--- /dev/null
+++ b/gas/testsuite/gas/cr16/scc_test.d
@@ -0,0 +1,22 @@
+#as:
+#objdump:  -dr
+#name:  scc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	02 08       	seq	r2
+   2:	13 08       	sne	r3
+   4:	23 08       	scs	r3
+   6:	34 08       	scc	r4
+   8:	45 08       	shi	r5
+   a:	56 08       	sls	r6
+   c:	67 08       	sgt	r7
+   e:	88 08       	sfs	r8
+  10:	99 08       	sfc	r9
+  12:	aa 08       	slo	r10
+  14:	b1 08       	shs	r1
+  16:	cb 08       	slt	r11
+  18:	d0 08       	sge	r0
diff --git a/gas/testsuite/gas/cr16/scc_test.s b/gas/testsuite/gas/cr16/scc_test.s
new file mode 100644
index 0000000..9b9d01c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/scc_test.s
@@ -0,0 +1,19 @@
+        .text
+        .global main
+main:
+	##########
+	# SCond reg
+	##########
+	seq	r2
+	sne	r3
+	scs	r3
+	scc	r4
+	shi	r5
+	sls	r6
+	sgt	r7
+	sfs	r8
+	sfc	r9
+	slo	r10
+	shs	r1
+	slt	r11
+	sge	r0
diff --git a/gas/testsuite/gas/cr16/storb_test.d b/gas/testsuite/gas/cr16/storb_test.d
new file mode 100644
index 0000000..dc2a9c2
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storb_test.d
@@ -0,0 +1,153 @@
+#as:
+#objdump:  -dr
+#name:  storb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c8 00 00 	storb	r0,0x0 <main>:m
+   4:	10 c8 ff 00 	storb	r1,0xff <main\+0xff>:m
+   8:	30 c8 ff 0f 	storb	r3,0xfff <main\+0xfff>:m
+   c:	40 c8 34 12 	storb	r4,0x1234 <main\+0x1234>:m
+  10:	50 c8 34 12 	storb	r5,0x1234 <main\+0x1234>:m
+  14:	13 00 07 7a 	storb	r0,0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 1b 7a 	storb	r1,0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 2f 7f 	storb	r2,0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 ca 00 00 	storb	r0,\[r12\]0x0:m
+  2a:	00 cb 00 00 	storb	r0,\[r12\]0x0:m
+  2e:	10 ca ff 00 	storb	r1,\[r12\]0xff:m
+  32:	10 cb ff 00 	storb	r1,\[r12\]0xff:m
+  36:	30 ca ff 0f 	storb	r3,\[r12\]0xfff:m
+  3a:	30 cb ff 0f 	storb	r3,\[r12\]0xfff:m
+  3e:	40 ca 34 12 	storb	r4,\[r13\]0x1234:m
+  42:	40 cb 34 12 	storb	r4,\[r13\]0x1234:m
+  46:	50 ca 34 12 	storb	r5,\[r13\]0x1234:m
+  4a:	50 cb 34 12 	storb	r5,\[r13\]0x1234:m
+  4e:	20 ca 67 45 	storb	r2,\[r12\]0x4567:m
+  52:	2a cb 34 12 	storb	r2,\[r12\]0xa1234:m
+  56:	10 f4       	storb	r1,0x4:s\(r1,r0\)
+  58:	32 f4       	storb	r3,0x4:s\(r3,r2\)
+  5a:	40 ff 34 12 	storb	r4,0x1234:m\(r1,r0\)
+  5e:	52 ff 34 12 	storb	r5,0x1234:m\(r3,r2\)
+  62:	13 00 60 5a 	storb	r6,0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 5f 	storb	r1,0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 32 5f 	storb	r3,0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 40 5f 	storb	r4,0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 52 5f 	storb	r5,0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 60 55 	storb	r6,0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 f0       	storb	r0,0x0:s\(r1,r0\)
+  88:	00 f0       	storb	r0,0x0:s\(r1,r0\)
+  8a:	00 ff 0f 00 	storb	r0,0xf:m\(r1,r0\)
+  8e:	10 ff 0f 00 	storb	r1,0xf:m\(r1,r0\)
+  92:	20 ff 34 12 	storb	r2,0x1234:m\(r1,r0\)
+  96:	32 ff cd ab 	storb	r3,0xabcd:m\(r3,r2\)
+  9a:	43 ff ff af 	storb	r4,0xafff:m\(r4,r3\)
+  9e:	13 00 55 5a 	storb	r5,0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 5f 	storb	r0,0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 10 5f 	storb	r1,0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 20 5f 	storb	r2,0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 32 5f 	storb	r3,0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 5f 	storb	r4,0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 55 55 	storb	r5,0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 fe       	storb	r0,\[r12\]0x0:s\(r1,r0\)
+  ca:	18 fe       	storb	r1,\[r13\]0x0:s\(r1,r0\)
+  cc:	70 c6 04 12 	storb	r7,\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 38 61 	storb	r3,\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 40 6a 	storb	r4,\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 58 6b 	storb	r5,\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 68 6f 	storb	r6,\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
+  e8:	40 81 cd 0b 	storb	\$0x4:s,0xbcd <main\+0xbcd>:m
+  ec:	5a 81 cd ab 	storb	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+  f0:	12 00 3f 3a 	storb	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+  f4:	cd ab 
+  f6:	50 84 14 00 	storb	\$0x5:s,\[r13\]0x14:m
+  fa:	40 85 fc ab 	storb	\$0x4:s,\[r13\]0xabfc:m
+  fe:	30 84 34 12 	storb	\$0x3:s,\[r12\]0x1234:m
+ 102:	30 85 34 12 	storb	\$0x3:s,\[r12\]0x1234:m
+ 106:	30 84 34 00 	storb	\$0x3:s,\[r12\]0x34:m
+ 10a:	30 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+ 10e:	31 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+ 112:	36 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+ 116:	32 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+ 11a:	37 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+ 11e:	33 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+ 122:	34 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+ 126:	35 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+ 12a:	38 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+ 12e:	39 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+ 132:	3e 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+ 136:	3a 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+ 13a:	3f 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+ 13e:	3b 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+ 142:	3c 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+ 146:	3d 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+ 14a:	3e 86 5a 4b 	storb	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+ 14e:	37 86 1a 41 	storb	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+ 152:	3f 86 14 01 	storb	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+ 156:	12 00 36 2a 	storb	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+ 15a:	de bc 
+ 15c:	12 00 5e 20 	storb	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+ 160:	cd ab 
+ 162:	12 00 37 20 	storb	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+ 166:	cd ab 
+ 168:	12 00 3f 20 	storb	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+ 16c:	de bc 
+ 16e:	12 00 52 00 	storb	\$0x5:s,0x0:l\(r2\)
+ 172:	00 00 
+ 174:	3c 83 34 00 	storb	\$0x3:s,0x34:m\(r12\)
+ 178:	3d 83 ab 00 	storb	\$0x3:s,0xab:m\(r13\)
+ 17c:	12 00 51 00 	storb	\$0x5:s,0xad:l\(r1\)
+ 180:	ad 00 
+ 182:	12 00 52 00 	storb	\$0x5:s,0xcd:l\(r2\)
+ 186:	cd 00 
+ 188:	12 00 50 00 	storb	\$0x5:s,0xfff:l\(r0\)
+ 18c:	ff 0f 
+ 18e:	12 00 34 00 	storb	\$0x3:s,0xbcd:l\(r4\)
+ 192:	cd 0b 
+ 194:	3c 83 ff 0f 	storb	\$0x3:s,0xfff:m\(r12\)
+ 198:	3d 83 ff 0f 	storb	\$0x3:s,0xfff:m\(r13\)
+ 19c:	3d 83 ff ff 	storb	\$0x3:s,0xffff:m\(r13\)
+ 1a0:	3c 83 43 23 	storb	\$0x3:s,0x2343:m\(r12\)
+ 1a4:	12 00 32 01 	storb	\$0x3:s,0x2345:l\(r2\)
+ 1a8:	45 23 
+ 1aa:	12 00 38 04 	storb	\$0x3:s,0xabcd:l\(r8\)
+ 1ae:	cd ab 
+ 1b0:	12 00 3d 1f 	storb	\$0x3:s,0xfabcd:l\(r13\)
+ 1b4:	cd ab 
+ 1b6:	12 00 38 0f 	storb	\$0x3:s,0xabcd:l\(r8\)
+ 1ba:	cd ab 
+ 1bc:	12 00 39 0f 	storb	\$0x3:s,0xabcd:l\(r9\)
+ 1c0:	cd ab 
+ 1c2:	12 00 39 04 	storb	\$0x3:s,0xabcd:l\(r9\)
+ 1c6:	cd ab 
+ 1c8:	31 82       	storb	\$0x3:s,0x0:s\(r2,r1\)
+ 1ca:	51 83 01 00 	storb	\$0x5:s,0x1:m\(r2,r1\)
+ 1ce:	41 83 34 12 	storb	\$0x4:s,0x1234:m\(r2,r1\)
+ 1d2:	31 83 34 12 	storb	\$0x3:s,0x1234:m\(r2,r1\)
+ 1d6:	12 00 31 11 	storb	\$0x3:s,0x12345:l\(r2,r1\)
+ 1da:	45 23 
+ 1dc:	31 83 23 01 	storb	\$0x3:s,0x123:m\(r2,r1\)
+ 1e0:	12 00 31 11 	storb	\$0x3:s,0x12345:l\(r2,r1\)
+ 1e4:	45 23 
diff --git a/gas/testsuite/gas/cr16/storb_test.s b/gas/testsuite/gas/cr16/storb_test.s
new file mode 100644
index 0000000..2cd2706
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storb_test.s
@@ -0,0 +1,143 @@
+        .text

+        .global main

+main:

+	######################

+	#  storb reg abs20/24 

+	######################

+	storb r0,0x0

+	storb r1,0xff

+	storb r3,0xfff

+	storb r4,0x1234

+	storb r5,0x1234

+	storb r0,0x7A1234

+	storb r1,0xBA1234

+	storb r2,0xffffff

+	######################

+	#  storb abs20 rel reg

+	######################

+	storb r0,[r12]0x0

+	storb r0,[r13]0x0

+	storb r1,[r12]0xff

+	storb r1,[r13]0xff

+	storb r3,[r12]0xfff

+	storb r3,[r13]0xfff

+	storb r4,[r12]0x1234

+	storb r4,[r13]0x1234

+	storb r5,[r12]0x1234

+	storb r5,[r13]0x1234

+	storb r2,[r12]0x4567

+	storb r2,[r13]0xA1234

+	###################################

+	#  storb reg rbase(disp20/-disp20) 

+	###################################

+	storb r1,0x4(r1,r0)

+	storb r3,0x4(r3,r2)

+	storb r4,0x1234(r1,r0)

+	storb r5,0x1234(r3,r2)

+	storb r6,0xA1234(r1,r0)

+	storb r1,-0x4(r1,r0)

+	storb r3,-0x4(r3,r2)

+	storb r4,-0x1234(r1,r0)

+	storb r5,-0x1234(r3,r2)

+	storb r6,-0xA1234(r1,r0)

+	#################################################

+	#  storb reg rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	storb r0,0x0(r1,r0)

+	storb r0,0x0(r1,r0)

+	storb r0,0xf(r1,r0)

+	storb r1,0xf(r1,r0)

+	storb r2,0x1234(r1,r0)

+	storb r3,0xabcd(r3,r2)

+	storb r4,0xAfff(r4,r3)

+	storb r5,0xA1234(r6,r5)

+	storb r0,-0xf(r1,r0)

+	storb r1,-0xf(r1,r0)

+	storb r2,-0x1234(r1,r0)

+	storb r3,-0xabcd(r3,r2)

+	storb r4,-0xAfff(r4,r3)

+	storb r5,-0xA1234(r6,r5)

+	####################################

+	#  storb rbase(disp0/disp14) rel reg

+	####################################

+	storb r0,[r12]0x0(r1,r0)

+	storb r1,[r13]0x0(r1,r0)

+	storb r2,[r12]0x1234(r1,r0)

+	storb r3,[r13]0x1abcd(r1,r0)

+	#################################

+	#  storb reg rpbase(disp20) rel

+	#################################

+	storb r4,[r12]0xA1234(r1,r0)

+	storb r5,[r13]0xB1234(r1,r0)

+	storb r6,[r13]0xfffff(r1,r0)

+	#######################

+	# storb reg, uimm16/20

+	######################

+	storb $4,0xbcd

+	storb $5,0xaabcd

+	storb $3,0xfaabcd

+

+	#######################

+	# storb reg, uimm16/20

+	######################

+	storb $5,[r12]0x14

+	storb $4,[r13]0xabfc

+	storb $3,[r12]0x1234

+	storb $3,[r13]0x1234

+	storb $3,[r12]0x34

+	#######################

+	# storb imm, index-rbase

+	######################

+	storb $3,[r12]0xa7a(r1,r0)

+	storb $3,[r12]0xa7a(r3,r2)

+	storb $3,[r12]0xa7a(r4,r3)

+	storb $3,[r12]0xa7a(r5,r4)

+	storb $3,[r12]0xa7a(r6,r5)

+	storb $3,[r12]0xa7a(r7,r6)

+	storb $3,[r12]0xa7a(r9,r8)

+	storb $3,[r12]0xa7a(r11,r10)

+	storb $3,[r13]0xa7a(r1,r0)

+	storb $3,[r13]0xa7a(r3,r2)

+	storb $3,[r13]0xa7a(r4,r3)

+	storb $3,[r13]0xa7a(r5,r4)

+	storb $3,[r13]0xa7a(r6,r5)

+	storb $3,[r13]0xa7a(r7,r6)

+	storb $3,[r13]0xa7a(r9,r8)

+	storb $3,[r13]0xa7a(r11,r10)

+	storb $5,[r13]0xb7a(r4,r3)

+	storb $1,[r12]0x17a(r6,r5)

+	storb $1,[r13]0x134(r6,r5)

+	storb $3,[r12]0xabcde(r4,r3)

+	storb $5,[r13]0xabcd(r4,r3)

+	storb $3,[r12]0xabcd(r6,r5)

+	storb $3,[r13]0xbcde(r6,r5)

+	#######################

+	# storb imm4, rbase(disp)

+	######################

+	storb $5,0x0(r2)

+	storb $3,0x34(r12)

+	storb $3,0xab(r13)

+	storb $5,0xad(r1)

+	storb $5,0xcd(r2)

+	storb $5,0xfff(r0)

+	storb $3,0xbcd(r4)

+	storb $3,0xfff(r12)

+	storb $3,0xfff(r13)

+	storb $3,0xffff(r13)

+	storb $3,0x2343(r12)

+	storb $3,0x12345(r2)

+	storb $3,0x4abcd(r8)

+	storb $3,0xfabcd(r13)

+	storb $3,0xfabcd(r8)

+	storb $3,0xfabcd(r9)

+	storb $3,0x4abcd(r9)

+	##########################

+	# storb imm, disp20(rpbase)

+	#########################

+	storb $3,0x0(r2,r1)

+	storb $5,0x1(r2,r1)

+	storb $4,0x1234(r2,r1)

+	storb $3,0x1234(r2,r1)

+	storb $3,0x12345(r2,r1)

+	storb $3,0x123(r2,r1)

+	storb $3,0x12345(r2,r1)

diff --git a/gas/testsuite/gas/cr16/stord_test.d b/gas/testsuite/gas/cr16/stord_test.d
new file mode 100644
index 0000000..9e31b7a
--- /dev/null
+++ b/gas/testsuite/gas/cr16/stord_test.d
@@ -0,0 +1,80 @@
+#as:
+#objdump:  -dr
+#name:  stord_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c7 00 00 	stord	\(r1,r0\),0x0 <main>:m
+   4:	00 c7 ff 00 	stord	\(r1,r0\),0xff <main\+0xff>:m
+   8:	20 c7 ff 0f 	stord	\(r3,r2\),0xfff <main\+0xfff>:m
+   c:	30 c7 34 12 	stord	\(r4,r3\),0x1234 <main\+0x1234>:m
+  10:	40 c7 34 12 	stord	\(r5,r4\),0x1234 <main\+0x1234>:m
+  14:	13 00 07 ba 	stord	\(r1,r0\),0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 0b ba 	stord	\(r1,r0\),0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 1f bf 	stord	\(r2,r1\),0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 cc 00 00 	stord	\(r1,r0\),\[r12\]0x0:m
+  2a:	00 cd 00 00 	stord	\(r1,r0\),\[r12\]0x0:m
+  2e:	00 cc ff 00 	stord	\(r1,r0\),\[r12\]0xff:m
+  32:	00 cd ff 00 	stord	\(r1,r0\),\[r12\]0xff:m
+  36:	20 cc ff 0f 	stord	\(r3,r2\),\[r12\]0xfff:m
+  3a:	20 cd ff 0f 	stord	\(r3,r2\),\[r12\]0xfff:m
+  3e:	30 cc 34 12 	stord	\(r4,r3\),\[r12\]0x1234:m
+  42:	30 cd 34 12 	stord	\(r4,r3\),\[r12\]0x1234:m
+  46:	40 cc 34 12 	stord	\(r5,r4\),\[r13\]0x1234:m
+  4a:	40 cd 34 12 	stord	\(r5,r4\),\[r13\]0x1234:m
+  4e:	10 cc 67 45 	stord	\(r2,r1\),\[r12\]0x4567:m
+  52:	1a cd 34 12 	stord	\(r2,r1\),\[r12\]0xa1234:m
+  56:	10 e2       	stord	\(r2,r1\),0x4:s\(r1,r0\)
+  58:	22 e2       	stord	\(r3,r2\),0x4:s\(r3,r2\)
+  5a:	30 ef 34 12 	stord	\(r4,r3\),0x1234:m\(r1,r0\)
+  5e:	42 ef 34 12 	stord	\(r5,r4\),0x1234:m\(r3,r2\)
+  62:	13 00 50 9a 	stord	\(r6,r5\),0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 9f 	stord	\(r2,r1\),0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 22 9f 	stord	\(r3,r2\),0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 30 9f 	stord	\(r4,r3\),0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 42 9f 	stord	\(r5,r4\),0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 50 95 	stord	\(r6,r5\),0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 e0       	stord	\(r1,r0\),0x0:s\(r1,r0\)
+  88:	00 e0       	stord	\(r1,r0\),0x0:s\(r1,r0\)
+  8a:	00 ef 0f 00 	stord	\(r1,r0\),0xf:m\(r1,r0\)
+  8e:	00 ef 0f 00 	stord	\(r1,r0\),0xf:m\(r1,r0\)
+  92:	10 ef 34 12 	stord	\(r2,r1\),0x1234:m\(r1,r0\)
+  96:	22 ef cd ab 	stord	\(r3,r2\),0xabcd:m\(r3,r2\)
+  9a:	33 ef ff af 	stord	\(r4,r3\),0xafff:m\(r4,r3\)
+  9e:	13 00 65 9a 	stord	\(r7,r6\),0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 9f 	stord	\(r1,r0\),0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 00 9f 	stord	\(r1,r0\),0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 10 9f 	stord	\(r2,r1\),0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 22 9f 	stord	\(r3,r2\),0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 9f 	stord	\(r5,r4\),0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 45 95 	stord	\(r5,r4\),0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 ee       	stord	\(r1,r0\),\[r12\]0x0:s\(r1,r0\)
+  ca:	08 ee       	stord	\(r1,r0\),\[r13\]0x0:s\(r1,r0\)
+  cc:	b0 c6 04 12 	stord	\(r12,r11\),\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 28 a1 	stord	\(r3,r2\),\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 20 aa 	stord	\(r3,r2\),\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 38 ab 	stord	\(r4,r3\),\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 48 af 	stord	\(r5,r4\),\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
diff --git a/gas/testsuite/gas/cr16/stord_test.s b/gas/testsuite/gas/cr16/stord_test.s
new file mode 100644
index 0000000..dcac741
--- /dev/null
+++ b/gas/testsuite/gas/cr16/stord_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  stord abs20/24 regp

+	######################

+	stord (r1,r0),0x0

+	stord (r1,r0),0xff

+	stord (r3,r2),0xfff

+	stord (r4,r3),0x1234

+	stord (r5,r4),0x1234

+	stord (r1,r0),0x7A1234

+	stord (r1,r0),0xBA1234

+	stord (r2,r1),0xffffff

+	######################

+	#  stord abs20 rel regp

+	######################

+	stord (r1,r0),[r12]0x0

+	stord (r1,r0),[r13]0x0

+	stord (r1,r0),[r12]0xff

+	stord (r1,r0),[r13]0xff

+	stord (r3,r2),[r12]0xfff

+	stord (r3,r2),[r13]0xfff

+	stord (r4,r3),[r12]0x1234

+	stord (r4,r3),[r13]0x1234

+	stord (r5,r4),[r12]0x1234

+	stord (r5,r4),[r13]0x1234

+	stord (r2,r1),[r12]0x4567

+	stord (r2,r1),[r13]0xA1234

+	###################################

+	#  stord regp rbase(disp20/-disp20)  

+	###################################

+	stord (r2,r1),0x4(r1,r0)

+	stord (r3,r2),0x4(r3,r2)

+	stord (r4,r3),0x1234(r1,r0)

+	stord (r5,r4),0x1234(r3,r2)

+	stord (r6,r5),0xA1234(r1,r0)

+	stord (r2,r1),-0x4(r1,r0)

+	stord (r3,r2),-0x4(r3,r2)

+	stord (r4,r3),-0x1234(r1,r0)

+	stord (r5,r4),-0x1234(r3,r2)

+	stord (r6,r5),-0xA1234(r1,r0)

+	#################################################

+	#  stord regp rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	stord (r1,r0),0x0(r1,r0)

+	stord (r1,r0),0x0(r1,r0)

+	stord (r1,r0),0xf(r1,r0)

+	stord (r1,r0),0xf(r1,r0)

+	stord (r2,r1),0x1234(r1,r0)

+	stord (r3,r2),0xabcd(r3,r2)

+	stord (r4,r3),0xAfff(r4,r3)

+	stord (r7,r6),0xA1234(r6,r5)

+	stord (r1,r0),-0xf(r1,r0)

+	stord (r1,r0),-0xf(r1,r0)

+	stord (r2,r1),-0x1234(r1,r0)

+	stord (r3,r2),-0xabcd(r3,r2)

+	stord (r5,r4),-0xAfff(r4,r3)

+	stord (r5,r4),-0xA1234(r6,r5)

+	####################################

+	#  stord rbase(disp0/disp14) rel reg

+	####################################

+	stord (r1,r0),[r12]0x0(r1,r0)

+	stord (r1,r0),[r13]0x0(r1,r0)

+	stord (r2,r1),[r12]0x1234(r1,r0)

+	stord (r3,r2),[r13]0x1abcd(r1,r0)

+	#################################

+	#  stord rpbase(disp20) rel reg

+	#################################

+	stord (r3,r2),[r12]0xA1234(r1,r0)

+	stord (r4,r3),[r13]0xB1234(r1,r0)

+	stord (r5,r4),[r13]0xfffff(r1,r0)

diff --git a/gas/testsuite/gas/cr16/storm_test.d b/gas/testsuite/gas/cr16/storm_test.d
new file mode 100644
index 0000000..8e103ba
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storm_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  storm_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	b0 00       	storm	\$0x1,r0
+   2:	b1 00       	storm	\$0x2,r0
+   4:	b2 00       	storm	\$0x3,r0
+   6:	b3 00       	storm	\$0x4,r0
+   8:	b4 00       	storm	\$0x5,r0
+   a:	b5 00       	storm	\$0x6,r0
+   c:	b6 00       	storm	\$0x7,r0
+   e:	b7 00       	storm	\$0x8,r0
+  10:	b8 00       	stormp	\$0x1,r0
+  12:	b9 00       	stormp	\$0x2,r0
+  14:	ba 00       	stormp	\$0x3,r0
+  16:	bb 00       	stormp	\$0x4,r0
+  18:	bc 00       	stormp	\$0x5,r0
+  1a:	bd 00       	stormp	\$0x6,r0
+  1c:	be 00       	stormp	\$0x7,r0
+  1e:	bf 00       	stormp	\$0x8,r0
diff --git a/gas/testsuite/gas/cr16/storm_test.s b/gas/testsuite/gas/cr16/storm_test.s
new file mode 100644
index 0000000..ad5de61
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storm_test.s
@@ -0,0 +1,25 @@
+        .text
+        .global main
+main:
+	##############
+	# storm cnt
+	##############
+ 	storm $1
+ 	storm $2
+ 	storm $3
+ 	storm $4
+ 	storm $5
+ 	storm $6
+ 	storm $7
+ 	storm $8
+	##############
+	# stormp cnt
+	##############
+ 	stormp $1
+ 	stormp $2
+ 	stormp $3
+ 	stormp $4
+ 	stormp $5
+ 	stormp $6
+ 	stormp $7
+ 	stormp $8
diff --git a/gas/testsuite/gas/cr16/storw_test.d b/gas/testsuite/gas/cr16/storw_test.d
new file mode 100644
index 0000000..02b1b65
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storw_test.d
@@ -0,0 +1,153 @@
+#as:
+#objdump:  -dr
+#name:  storw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c9 00 00 	storw	r0,0x0 <main>:m
+   4:	10 c9 ff 00 	storw	r1,0xff <main\+0xff>:m
+   8:	30 c9 ff 0f 	storw	r3,0xfff <main\+0xfff>:m
+   c:	40 c9 34 12 	storw	r4,0x1234 <main\+0x1234>:m
+  10:	50 c9 34 12 	storw	r5,0x1234 <main\+0x1234>:m
+  14:	13 00 07 fa 	storw	r0,0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 1b fa 	storw	r1,0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 2f ff 	storw	r2,0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 ce 00 00 	storw	r0,\[r12\]0x0:m
+  2a:	00 cf 00 00 	storw	r0,\[r12\]0x0:m
+  2e:	10 ce ff 00 	storw	r1,\[r12\]0xff:m
+  32:	10 cf ff 00 	storw	r1,\[r12\]0xff:m
+  36:	30 ce ff 0f 	storw	r3,\[r12\]0xfff:m
+  3a:	30 cf ff 0f 	storw	r3,\[r12\]0xfff:m
+  3e:	40 ce 34 12 	storw	r4,\[r13\]0x1234:m
+  42:	40 cf 34 12 	storw	r4,\[r13\]0x1234:m
+  46:	50 ce 34 12 	storw	r5,\[r13\]0x1234:m
+  4a:	50 cf 34 12 	storw	r5,\[r13\]0x1234:m
+  4e:	20 ce 67 45 	storw	r2,\[r12\]0x4567:m
+  52:	2a cf 34 12 	storw	r2,\[r12\]0xa1234:m
+  56:	10 d2       	storw	r1,0x4:s\(r1,r0\)
+  58:	32 d2       	storw	r3,0x4:s\(r3,r2\)
+  5a:	40 df 34 12 	storw	r4,0x1234:m\(r1,r0\)
+  5e:	52 df 34 12 	storw	r5,0x1234:m\(r3,r2\)
+  62:	13 00 60 da 	storw	r6,0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 df 	storw	r1,0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 32 df 	storw	r3,0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 40 df 	storw	r4,0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 52 df 	storw	r5,0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 60 d5 	storw	r6,0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 d0       	storw	r0,0x0:s\(r1,r0\)
+  88:	00 d0       	storw	r0,0x0:s\(r1,r0\)
+  8a:	00 df 0f 00 	storw	r0,0xf:m\(r1,r0\)
+  8e:	10 df 0f 00 	storw	r1,0xf:m\(r1,r0\)
+  92:	20 df 34 12 	storw	r2,0x1234:m\(r1,r0\)
+  96:	32 df cd ab 	storw	r3,0xabcd:m\(r3,r2\)
+  9a:	43 df ff af 	storw	r4,0xafff:m\(r4,r3\)
+  9e:	13 00 55 da 	storw	r5,0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 df 	storw	r0,0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 10 df 	storw	r1,0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 20 df 	storw	r2,0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 32 df 	storw	r3,0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 df 	storw	r4,0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 55 d5 	storw	r5,0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 de       	storw	r0,\[r12\]0x0:s\(r1,r0\)
+  ca:	18 de       	storw	r1,\[r13\]0x0:s\(r1,r0\)
+  cc:	f0 c6 04 12 	storw	r15,\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 38 e1 	storw	r3,\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 40 ea 	storw	r4,\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 58 eb 	storw	r5,\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 68 ef 	storw	r6,\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
+  e8:	40 c1 cd 0b 	storw	\$0x4:s,0xbcd <main\+0xbcd>:m
+  ec:	5a c1 cd ab 	storw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+  f0:	13 00 3f 3a 	storw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+  f4:	cd ab 
+  f6:	50 c4 14 00 	storw	\$0x5:s,\[r13\]0x14:m
+  fa:	40 c5 fc ab 	storw	\$0x4:s,\[r13\]0xabfc:m
+  fe:	30 c4 34 12 	storw	\$0x3:s,\[r12\]0x1234:m
+ 102:	30 c5 34 12 	storw	\$0x3:s,\[r12\]0x1234:m
+ 106:	30 c4 34 00 	storw	\$0x3:s,\[r12\]0x34:m
+ 10a:	30 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+ 10e:	31 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+ 112:	36 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+ 116:	32 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+ 11a:	37 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+ 11e:	33 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+ 122:	34 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+ 126:	35 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+ 12a:	38 c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+ 12e:	39 c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+ 132:	3e c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+ 136:	3a c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+ 13a:	3f c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+ 13e:	3b c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+ 142:	3c c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+ 146:	3d c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+ 14a:	3e c6 5a 4b 	storw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+ 14e:	37 c6 1a 41 	storw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+ 152:	3f c6 14 01 	storw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+ 156:	13 00 36 2a 	storw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+ 15a:	de bc 
+ 15c:	13 00 5e 20 	storw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+ 160:	cd ab 
+ 162:	13 00 37 20 	storw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+ 166:	cd ab 
+ 168:	13 00 3f 20 	storw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+ 16c:	de bc 
+ 16e:	13 00 52 00 	storw	\$0x5:s,0x0:l\(r2\)
+ 172:	00 00 
+ 174:	3c c3 34 00 	storw	\$0x3:s,0x34:m\(r12\)
+ 178:	3d c3 ab 00 	storw	\$0x3:s,0xab:m\(r13\)
+ 17c:	13 00 51 00 	storw	\$0x5:s,0xad:l\(r1\)
+ 180:	ad 00 
+ 182:	13 00 52 00 	storw	\$0x5:s,0xcd:l\(r2\)
+ 186:	cd 00 
+ 188:	13 00 50 00 	storw	\$0x5:s,0xfff:l\(r0\)
+ 18c:	ff 0f 
+ 18e:	13 00 34 00 	storw	\$0x3:s,0xbcd:l\(r4\)
+ 192:	cd 0b 
+ 194:	3c c3 ff 0f 	storw	\$0x3:s,0xfff:m\(r12\)
+ 198:	3d c3 ff 0f 	storw	\$0x3:s,0xfff:m\(r13\)
+ 19c:	3d c3 ff ff 	storw	\$0x3:s,0xffff:m\(r13\)
+ 1a0:	3c c3 43 23 	storw	\$0x3:s,0x2343:m\(r12\)
+ 1a4:	13 00 32 01 	storw	\$0x3:s,0x2345:l\(r2\)
+ 1a8:	45 23 
+ 1aa:	13 00 38 04 	storw	\$0x3:s,0xabcd:l\(r8\)
+ 1ae:	cd ab 
+ 1b0:	13 00 3d 1f 	storw	\$0x3:s,0xfabcd:l\(r13\)
+ 1b4:	cd ab 
+ 1b6:	13 00 38 0f 	storw	\$0x3:s,0xabcd:l\(r8\)
+ 1ba:	cd ab 
+ 1bc:	13 00 39 0f 	storw	\$0x3:s,0xabcd:l\(r9\)
+ 1c0:	cd ab 
+ 1c2:	13 00 39 04 	storw	\$0x3:s,0xabcd:l\(r9\)
+ 1c6:	cd ab 
+ 1c8:	31 c2       	storw	\$0x3:s,0x0:s\(r2,r1\)
+ 1ca:	51 c3 01 00 	storw	\$0x5:s,0x1:m\(r2,r1\)
+ 1ce:	41 c3 34 12 	storw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1d2:	31 c3 34 12 	storw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1d6:	13 00 31 11 	storw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1da:	45 23 
+ 1dc:	31 c3 23 01 	storw	\$0x3:s,0x123:m\(r2,r1\)
+ 1e0:	13 00 31 11 	storw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1e4:	45 23 
diff --git a/gas/testsuite/gas/cr16/storw_test.s b/gas/testsuite/gas/cr16/storw_test.s
new file mode 100644
index 0000000..6adee5c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storw_test.s
@@ -0,0 +1,144 @@
+        .text

+        .global main

+main:

+	######################

+	#  storw reg abs20/24 

+	######################

+	storw r0,0x0

+	storw r1,0xff

+	storw r3,0xfff

+	storw r4,0x1234

+	storw r5,0x1234

+	storw r0,0x7A1234

+	storw r1,0xBA1234

+	storw r2,0xffffff

+	######################

+	#  storw abs20 rel reg

+	######################

+	storw r0,[r12]0x0

+	storw r0,[r13]0x0

+	storw r1,[r12]0xff

+	storw r1,[r13]0xff

+	storw r3,[r12]0xfff

+	storw r3,[r13]0xfff

+	storw r4,[r12]0x1234

+	storw r4,[r13]0x1234

+	storw r5,[r12]0x1234

+	storw r5,[r13]0x1234

+	storw r2,[r12]0x4567

+	storw r2,[r13]0xA1234

+	###################################

+	#  storw reg rbase(disp20/-disp20) 

+	###################################

+	storw r1,0x4(r1,r0)

+	storw r3,0x4(r3,r2)

+	storw r4,0x1234(r1,r0)

+	storw r5,0x1234(r3,r2)

+	storw r6,0xA1234(r1,r0)

+	storw r1,-0x4(r1,r0)

+	storw r3,-0x4(r3,r2)

+	storw r4,-0x1234(r1,r0)

+	storw r5,-0x1234(r3,r2)

+	storw r6,-0xA1234(r1,r0)

+	#################################################

+	#  storw reg rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	storw r0,0x0(r1,r0)

+	storw r0,0x0(r1,r0)

+	storw r0,0xf(r1,r0)

+	storw r1,0xf(r1,r0)

+	storw r2,0x1234(r1,r0)

+	storw r3,0xabcd(r3,r2)

+	storw r4,0xAfff(r4,r3)

+	storw r5,0xA1234(r6,r5)

+	storw r0,-0xf(r1,r0)

+	storw r1,-0xf(r1,r0)

+	storw r2,-0x1234(r1,r0)

+	storw r3,-0xabcd(r3,r2)

+	storw r4,-0xAfff(r4,r3)

+	storw r5,-0xA1234(r6,r5)

+	####################################

+	#  storw rbase(disp0/disp14) rel reg

+	####################################

+	storw r0,[r12]0x0(r1,r0)

+	storw r1,[r13]0x0(r1,r0)

+	storw r2,[r12]0x1234(r1,r0)

+	storw r3,[r13]0x1abcd(r1,r0)

+	#################################

+	#  storw reg rpbase(disp20) rel

+	#################################

+	storw r4,[r12]0xA1234(r1,r0)

+	storw r5,[r13]0xB1234(r1,r0)

+	storw r6,[r13]0xfffff(r1,r0)

+	#######################

+	# storw reg, uimm16/20

+	######################

+	storw $4,0xbcd

+	storw $5,0xaabcd

+	storw $3,0xfaabcd

+

+	#######################

+	# storw reg, uimm16/20

+	######################

+	storw $5,[r12]0x14

+	storw $4,[r13]0xabfc

+	storw $3,[r12]0x1234

+	storw $3,[r13]0x1234

+	storw $3,[r12]0x34

+	#######################

+	# storw imm, index-rbase

+	######################

+	storw $3,[r12]0xa7a(r1,r0)

+	storw $3,[r12]0xa7a(r3,r2)

+	storw $3,[r12]0xa7a(r4,r3)

+	storw $3,[r12]0xa7a(r5,r4)

+	storw $3,[r12]0xa7a(r6,r5)

+	storw $3,[r12]0xa7a(r7,r6)

+	storw $3,[r12]0xa7a(r9,r8)

+	storw $3,[r12]0xa7a(r11,r10)

+	storw $3,[r13]0xa7a(r1,r0)

+	storw $3,[r13]0xa7a(r3,r2)

+	storw $3,[r13]0xa7a(r4,r3)

+	storw $3,[r13]0xa7a(r5,r4)

+	storw $3,[r13]0xa7a(r6,r5)

+	storw $3,[r13]0xa7a(r7,r6)

+	storw $3,[r13]0xa7a(r9,r8)

+	storw $3,[r13]0xa7a(r11,r10)

+	storw $5,[r13]0xb7a(r4,r3)

+	storw $1,[r12]0x17a(r6,r5)

+	storw $1,[r13]0x134(r6,r5)

+	storw $3,[r12]0xabcde(r4,r3)

+	storw $5,[r13]0xabcd(r4,r3)

+	storw $3,[r12]0xabcd(r6,r5)

+	storw $3,[r13]0xbcde(r6,r5)

+	#######################

+	# storw imm4, rbase(disp)

+	######################

+	storw $5,0x0(r2)

+	storw $3,0x34(r12)

+	storw $3,0xab(r13)

+	storw $5,0xad(r1)

+	storw $5,0xcd(r2)

+	storw $5,0xfff(r0)

+	storw $3,0xbcd(r4)

+	storw $3,0xfff(r12)

+	storw $3,0xfff(r13)

+	storw $3,0xffff(r13)

+	storw $3,0x2343(r12)

+	storw $3,0x12345(r2)

+	storw $3,0x4abcd(r8)

+	storw $3,0xfabcd(r13)

+	storw $3,0xfabcd(r8)

+	storw $3,0xfabcd(r9)

+	storw $3,0x4abcd(r9)

+	##########################

+	# storw imm, disp20(rpbase)

+	#########################

+	storw $3,0x0(r2,r1)

+	storw $5,0x1(r2,r1)

+	storw $4,0x1234(r2,r1)

+	storw $3,0x1234(r2,r1)

+	storw $3,0x12345(r2,r1)

+	storw $3,0x123(r2,r1)

+	storw $3,0x12345(r2,r1)

+

diff --git a/gas/testsuite/gas/cr16/sub_test.d b/gas/testsuite/gas/cr16/sub_test.d
new file mode 100644
index 0000000..1744836
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sub_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  sub_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 38       	subb	\$0xf:s,r1
+   2:	b2 38 ff 00 	subb	\$0xff:m,r2
+   6:	b1 38 ff 0f 	subb	\$0xfff:m,r1
+   a:	b1 38 14 00 	subb	\$0x14:m,r1
+   e:	a2 38       	subb	\$0xa:s,r2
+  10:	12 39       	subb	r1,r2
+  12:	23 39       	subb	r2,r3
+  14:	34 39       	subb	r3,r4
+  16:	56 39       	subb	r5,r6
+  18:	67 39       	subb	r6,r7
+  1a:	78 39       	subb	r7,r8
+  1c:	f1 3c       	subcb	\$0xf:s,r1
+  1e:	b2 3c ff 00 	subcb	\$0xff:m,r2
+  22:	b1 3c ff 0f 	subcb	\$0xfff:m,r1
+  26:	b1 3c 14 00 	subcb	\$0x14:m,r1
+  2a:	a2 3c       	subcb	\$0xa:s,r2
+  2c:	12 3d       	subcb	r1,r2
+  2e:	23 3d       	subcb	r2,r3
+  30:	34 3d       	subcb	r3,r4
+  32:	56 3d       	subcb	r5,r6
+  34:	67 3d       	subcb	r6,r7
+  36:	78 3d       	subcb	r7,r8
+  38:	f1 3e       	subcw	\$0xf:s,r1
+  3a:	b2 3e ff 00 	subcw	\$0xff:m,r2
+  3e:	b1 3e ff 0f 	subcw	\$0xfff:m,r1
+  42:	b1 3e 14 00 	subcw	\$0x14:m,r1
+  46:	a2 3e       	subcw	\$0xa:s,r2
+  48:	12 3f       	subcw	r1,r2
+  4a:	23 3f       	subcw	r2,r3
+  4c:	34 3f       	subcw	r3,r4
+  4e:	56 3f       	subcw	r5,r6
+  50:	67 3f       	subcw	r6,r7
+  52:	78 3f       	subcw	r7,r8
+  54:	f1 3a       	subw	\$0xf:s,r1
+  56:	b2 3a ff 00 	subw	\$0xff:m,r2
+  5a:	b1 3a ff 0f 	subw	\$0xfff:m,r1
+  5e:	b1 3a 14 00 	subw	\$0x14:m,r1
+  62:	a2 3a       	subw	\$0xa:s,r2
+  64:	12 3b       	subw	r1,r2
+  66:	23 3b       	subw	r2,r3
+  68:	34 3b       	subw	r3,r4
+  6a:	56 3b       	subw	r5,r6
+  6c:	67 3b       	subw	r6,r7
+  6e:	78 3b       	subw	r7,r8
+  70:	31 00 00 00 	subd	\$0xf:l,\(r2,r1\)
+  74:	0f 00 
+  76:	31 00 00 00 	subd	\$0xff:l,\(r2,r1\)
+  7a:	ff 00 
+  7c:	31 00 00 00 	subd	\$0xfff:l,\(r2,r1\)
+  80:	ff 0f 
+  82:	31 00 00 00 	subd	\$0xffff:l,\(r2,r1\)
+  86:	ff ff 
+  88:	31 00 0f 00 	subd	\$0xfffff:l,\(r2,r1\)
+  8c:	ff ff 
+  8e:	31 00 ff 0f 	subd	\$0xfffffff:l,\(r2,r1\)
+  92:	ff ff 
+  94:	31 00 ff ff 	subd	\$0xffffffff:l,\(r2,r1\)
+  98:	ff ff 
+  9a:	14 00 31 c0 	subd	\(r4,r3\),\(r2,r1\)
+  9e:	14 00 31 c0 	subd	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/sub_test.s b/gas/testsuite/gas/cr16/sub_test.s
new file mode 100644
index 0000000..ad0ac07
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sub_test.s
@@ -0,0 +1,93 @@
+        .text
+        .global main
+main:
+        ###########
+	# SUBB imm4/imm16, reg
+        ###########
+	subb    $0xf,r1
+	subb    $0xff,r2
+	subb    $0xfff,r1
+	#subb    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subb    $20,r1
+	subb    $10,r2
+        ###########
+	# SUBB reg, reg
+        ###########
+	subb    r1,r2
+	subb    r2,r3
+	subb    r3,r4
+	subb    r5,r6
+	subb    r6,r7
+	subb    r7,r8
+        ###########
+	# SUBCB imm4/imm16, reg
+        ###########
+	subcb    $0xf,r1
+	subcb    $0xff,r2
+	subcb    $0xfff,r1
+	#subcb    $0xffff,r2   // CHECK WITH CRASM 4.1
+	subcb    $20,r1
+	subcb    $10,r2
+        ###########
+	# SUBCB reg, reg
+        ###########
+	subcb    r1,r2
+	subcb    r2,r3
+	subcb    r3,r4
+	subcb    r5,r6
+	subcb    r6,r7
+	subcb    r7,r8
+        ###########
+	# SUBCW imm4/imm16, reg
+        ###########
+	subcw    $0xf,r1
+	subcw    $0xff,r2
+	subcw    $0xfff,r1
+	#subcw    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subcw    $20,r1
+	subcw    $10,r2
+        ###########
+	# SUBCW reg, reg
+        ###########
+	subcw    r1,r2
+	subcw    r2,r3
+	subcw    r3,r4
+	subcw    r5,r6
+	subcw    r6,r7
+	subcw    r7,r8
+        ###########
+	# SUBW imm4/imm16, reg
+        ###########
+	subw    $0xf,r1
+	subw    $0xff,r2
+	subw    $0xfff,r1
+	#subw    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subw    $20,r1
+	subw    $10,r2
+        ###########
+	# SUBW reg, reg
+        ###########
+	subw    r1,r2
+	subw    r2,r3
+	subw    r3,r4
+	subw    r5,r6
+	subw    r6,r7
+	subw    r7,r8
+        ###########
+	# SUBD imm4/imm16/imm32, regp
+        ###########
+	subd    $0xf,(r2,r1)
+	subd    $0xff,(r2,r1)
+	subd    $0xfff,(r2,r1)
+	subd    $0xffff,(r2,r1)
+	subd    $0xfffff,(r2,r1)
+	subd    $0xfffffff,(r2,r1)
+	subd    $0xffffffff,(r2,r1)
+        ###########
+	# SUBD regp, regp
+        ###########
+	subd    (r4,r3),(r2,r1)
+	subd    (r4,r3),(r2,r1)
+	#subd    $10,(sp)
+	#subd    $14,(sp)
+	#subd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/tbit_test.d b/gas/testsuite/gas/cr16/tbit_test.d
new file mode 100644
index 0000000..cf5b499
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbit_test.d
@@ -0,0 +1,37 @@
+#as:
+#objdump:  -dr
+#name:  tbit_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 06       	tbit	\$0x0:s,r0
+   2:	11 06       	tbit	\$0x1:s,r1
+   4:	22 06       	tbit	\$0x2:s,r2
+   6:	33 06       	tbit	\$0x3:s,r3
+   8:	44 06       	tbit	\$0x4:s,r4
+   a:	55 06       	tbit	\$0x5:s,r5
+   c:	66 06       	tbit	\$0x6:s,r6
+   e:	77 06       	tbit	\$0x7:s,r7
+  10:	88 06       	tbit	\$0x8:s,r8
+  12:	99 06       	tbit	\$0x9:s,r9
+  14:	aa 06       	tbit	\$0xa:s,r10
+  16:	bb 06       	tbit	\$0xb:s,r11
+  18:	cc 06       	tbit	\$0xc:s,r12
+  1a:	dd 06       	tbit	\$0xd:s,r13
+  1c:	00 07       	tbit	r0,r0
+  1e:	11 07       	tbit	r1,r1
+  20:	22 07       	tbit	r2,r2
+  22:	33 07       	tbit	r3,r3
+  24:	44 07       	tbit	r4,r4
+  26:	55 07       	tbit	r5,r5
+  28:	66 07       	tbit	r6,r6
+  2a:	77 07       	tbit	r7,r7
+  2c:	88 07       	tbit	r8,r8
+  2e:	99 07       	tbit	r9,r9
+  30:	aa 07       	tbit	r10,r10
+  32:	bb 07       	tbit	r11,r11
+  34:	cc 07       	tbit	r12,r12
+  36:	dd 07       	tbit	r13,r13
diff --git a/gas/testsuite/gas/cr16/tbit_test.s b/gas/testsuite/gas/cr16/tbit_test.s
new file mode 100644
index 0000000..aec7923
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbit_test.s
@@ -0,0 +1,41 @@
+        .text
+        .global main
+main:
+	##################
+	# tbit uimm4, reg
+	#################
+	tbit	$0,r0
+	tbit	$1,r1
+	tbit	$2,r2
+	tbit	$3,r3
+	tbit	$4,r4
+	tbit	$5,r5
+	tbit	$6,r6
+	tbit	$7,r7
+	tbit	$8,r8
+	tbit	$9,r9
+	tbit	$10,r10
+	tbit	$11,r11
+	tbit	$12,r12
+	tbit	$13,r13
+#	tbit	$14,r14 // Add error check for these INST
+#	tbit	$15,r15 // Add error check for these INST
+	##################
+	# tbit reg, reg
+	#################
+	tbit	r0,r0
+	tbit	r1,r1
+	tbit	r2,r2
+	tbit	r3,r3
+	tbit	r4,r4
+	tbit	r5,r5
+	tbit	r6,r6
+	tbit	r7,r7
+	tbit	r8,r8
+	tbit	r9,r9
+	tbit	r10,r10
+	tbit	r11,r11
+	tbit	r12,r12
+	tbit	r13,r13
+#	tbit	r14,r14 // Add error check for these INST
+#	tbit	r15,r15 // Add error check for these INST
diff --git a/gas/testsuite/gas/cr16/tbitb_test.d b/gas/testsuite/gas/cr16/tbitb_test.d
new file mode 100644
index 0000000..9965fac
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  tbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 7b cd 0b 	tbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 7b cd ab 	tbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f fa 	tbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 78 14 00 	tbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 78 fc ab 	tbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 78 34 12 	tbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 78 34 12 	tbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 78 34 00 	tbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 7a 5a 4b 	tbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 7a 1a 41 	tbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 7a 14 01 	tbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 ea 	tbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e e0 	tbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 e0 	tbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f e0 	tbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 c0 	tbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 7b 34 00 	tbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 7b ab 00 	tbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 c0 	tbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 c0 	tbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 c0 	tbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 c0 	tbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 7b ff 0f 	tbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 7b ff 0f 	tbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 7b ff ff 	tbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 7b 43 23 	tbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 c1 	tbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 c4 	tbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d df 	tbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 cf 	tbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 cf 	tbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 c4 	tbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 7a       	tbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 7b 01 00 	tbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 7b 34 12 	tbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 7b 34 12 	tbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 d1 	tbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 7b 23 01 	tbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 d1 	tbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/tbitb_test.s b/gas/testsuite/gas/cr16/tbitb_test.s
new file mode 100644
index 0000000..7fe427e
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	tbitb $4,0xbcd
+	tbitb $5,0xaabcd
+	tbitb $3,0xfaabcd
+
+	tbitb $5,[r12]0x14
+	tbitb $4,[r13]0xabfc
+	tbitb $3,[r12]0x1234
+	tbitb $3,[r13]0x1234
+	tbitb $3,[r12]0x34
+
+	tbitb $3,[r12]0xa7a(r1,r0)
+	tbitb $3,[r12]0xa7a(r3,r2)
+	tbitb $3,[r12]0xa7a(r4,r3)
+	tbitb $3,[r12]0xa7a(r5,r4)
+	tbitb $3,[r12]0xa7a(r6,r5)
+	tbitb $3,[r12]0xa7a(r7,r6)
+	tbitb $3,[r12]0xa7a(r9,r8)
+	tbitb $3,[r12]0xa7a(r11,r10)
+	tbitb $3,[r13]0xa7a(r1,r0)
+	tbitb $3,[r13]0xa7a(r3,r2)
+	tbitb $3,[r13]0xa7a(r4,r3)
+	tbitb $3,[r13]0xa7a(r5,r4)
+	tbitb $3,[r13]0xa7a(r6,r5)
+	tbitb $3,[r13]0xa7a(r7,r6)
+	tbitb $3,[r13]0xa7a(r9,r8)
+	tbitb $3,[r13]0xa7a(r11,r10)
+	tbitb $5,[r13]0xb7a(r4,r3)
+	tbitb $1,[r12]0x17a(r6,r5)
+	tbitb $1,[r13]0x134(r6,r5)
+	tbitb $3,[r12]0xabcde(r4,r3)
+	tbitb $5,[r13]0xabcd(r4,r3)
+	tbitb $3,[r12]0xabcd(r6,r5)
+	tbitb $3,[r13]0xbcde(r6,r5)
+
+	tbitb $5,0x0(r2)
+	tbitb $3,0x34(r12)
+	tbitb $3,0xab(r13)
+	tbitb $5,0xad(r1)
+	tbitb $5,0xcd(r2)
+	tbitb $5,0xfff(r0)
+	tbitb $3,0xbcd(r4)
+	tbitb $3,0xfff(r12)
+	tbitb $3,0xfff(r13)
+	tbitb $3,0xffff(r13)
+	tbitb $3,0x2343(r12)
+	tbitb $3,0x12345(r2)
+	tbitb $3,0x4abcd(r8)
+	tbitb $3,0xfabcd(r13)
+	tbitb $3,0xfabcd(r8)
+	tbitb $3,0xfabcd(r9)
+	tbitb $3,0x4abcd(r9)
+
+	tbitb $3,0x0(r2,r1)
+	tbitb $5,0x1(r2,r1)
+	tbitb $4,0x1234(r2,r1)
+	tbitb $3,0x1234(r2,r1)
+	tbitb $3,0x12345(r2,r1)
+	tbitb $3,0x123(r2,r1)
+	tbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/tbitw_test.d b/gas/testsuite/gas/cr16/tbitw_test.d
new file mode 100644
index 0000000..81022b1
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  tbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 7f cd 0b 	tbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 7f cd ab 	tbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f fa 	tbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 7f cd 0b 	tbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 7f cd ab 	tbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef fa 	tbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 7c 14 00 	tbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 7d fc ab 	tbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 7c 34 12 	tbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 7d 34 12 	tbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 7c 34 00 	tbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 7c 14 00 	tbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 7d fc ab 	tbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 7c 34 12 	tbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 7d 34 12 	tbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 7c 34 00 	tbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 7a 5a 4b 	tbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 7a 1a 41 	tbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 7a 14 01 	tbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 ea 	tbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e e0 	tbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 e0 	tbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f e0 	tbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 7a fa 4b 	tbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 7a ba 41 	tbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 7a b4 01 	tbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 ea 	tbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe e0 	tbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 e0 	tbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df e0 	tbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 c0 	tbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 79 34 00 	tbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 79 ab 00 	tbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 c0 	tbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 c0 	tbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 c0 	tbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 c0 	tbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 79 ff 0f 	tbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 79 ff 0f 	tbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 79 ff ff 	tbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 79 43 23 	tbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 c1 	tbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 c4 	tbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d df 	tbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 cf 	tbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 cf 	tbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 c4 	tbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 c0 	tbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 79 34 00 	tbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 79 ab 00 	tbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 c0 	tbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 c0 	tbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 c0 	tbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 c0 	tbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 79 ff 0f 	tbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 79 ff 0f 	tbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 79 ff ff 	tbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 79 43 23 	tbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 c1 	tbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 c4 	tbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd df 	tbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 cf 	tbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 cf 	tbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 c4 	tbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 7e       	tbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 79 01 00 	tbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 79 34 12 	tbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 79 34 12 	tbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 d1 	tbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 79 23 01 	tbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 d1 	tbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 7e       	tbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 79 01 00 	tbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 79 34 12 	tbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 79 34 12 	tbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 d1 	tbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 79 23 01 	tbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 d1 	tbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/tbitw_test.s b/gas/testsuite/gas/cr16/tbitw_test.s
new file mode 100644
index 0000000..939804c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	tbitw $4,0xbcd
+	tbitw $5,0xaabcd
+	tbitw $3,0xfaabcd
+	tbitw $10,0xbcd
+	tbitw $15,0xaabcd
+	tbitw $14,0xfaabcd
+
+	tbitw $5,[r12]0x14
+	tbitw $4,[r13]0xabfc
+	tbitw $3,[r12]0x1234
+	tbitw $3,[r13]0x1234
+	tbitw $3,[r12]0x34
+	tbitw $15,[r12]0x14
+	tbitw $14,[r13]0xabfc
+	tbitw $13,[r12]0x1234
+	tbitw $13,[r13]0x1234
+	tbitw $11,[r12]0x34
+
+	tbitw $3,[r12]0xa7a(r1,r0)
+	tbitw $3,[r12]0xa7a(r3,r2)
+	tbitw $3,[r12]0xa7a(r4,r3)
+	tbitw $3,[r12]0xa7a(r5,r4)
+	tbitw $3,[r12]0xa7a(r6,r5)
+	tbitw $3,[r12]0xa7a(r7,r6)
+	tbitw $3,[r12]0xa7a(r9,r8)
+	tbitw $3,[r12]0xa7a(r11,r10)
+	tbitw $3,[r13]0xa7a(r1,r0)
+	tbitw $3,[r13]0xa7a(r3,r2)
+	tbitw $3,[r13]0xa7a(r4,r3)
+	tbitw $3,[r13]0xa7a(r5,r4)
+	tbitw $3,[r13]0xa7a(r6,r5)
+	tbitw $3,[r13]0xa7a(r7,r6)
+	tbitw $3,[r13]0xa7a(r9,r8)
+	tbitw $3,[r13]0xa7a(r11,r10)
+	tbitw $5,[r13]0xb7a(r4,r3)
+	tbitw $1,[r12]0x17a(r6,r5)
+	tbitw $1,[r13]0x134(r6,r5)
+	tbitw $3,[r12]0xabcde(r4,r3)
+	tbitw $5,[r13]0xabcd(r4,r3)
+	tbitw $3,[r12]0xabcd(r6,r5)
+	tbitw $3,[r13]0xbcde(r6,r5)
+	tbitw $13,[r12]0xa7a(r1,r0)
+	tbitw $13,[r12]0xa7a(r3,r2)
+	tbitw $13,[r12]0xa7a(r4,r3)
+	tbitw $13,[r12]0xa7a(r5,r4)
+	tbitw $13,[r12]0xa7a(r6,r5)
+	tbitw $13,[r12]0xa7a(r7,r6)
+	tbitw $13,[r12]0xa7a(r9,r8)
+	tbitw $13,[r12]0xa7a(r11,r10)
+	tbitw $13,[r13]0xa7a(r1,r0)
+	tbitw $13,[r13]0xa7a(r3,r2)
+	tbitw $13,[r13]0xa7a(r4,r3)
+	tbitw $13,[r13]0xa7a(r5,r4)
+	tbitw $13,[r13]0xa7a(r6,r5)
+	tbitw $13,[r13]0xa7a(r7,r6)
+	tbitw $13,[r13]0xa7a(r9,r8)
+	tbitw $13,[r13]0xa7a(r11,r10)
+	tbitw $15,[r13]0xb7a(r4,r3)
+	tbitw $11,[r12]0x17a(r6,r5)
+	tbitw $11,[r13]0x134(r6,r5)
+	tbitw $13,[r12]0xabcde(r4,r3)
+	tbitw $15,[r13]0xabcd(r4,r3)
+	tbitw $13,[r12]0xabcd(r6,r5)
+	tbitw $13,[r13]0xbcde(r6,r5)
+
+	tbitw $5,0x0(r2)
+	tbitw $3,0x34(r12)
+	tbitw $3,0xab(r13)
+	tbitw $5,0xad(r1)
+	tbitw $5,0xcd(r2)
+	tbitw $5,0xfff(r0)
+	tbitw $3,0xbcd(r4)
+	tbitw $3,0xfff(r12)
+	tbitw $3,0xfff(r13)
+	tbitw $3,0xffff(r13)
+	tbitw $3,0x2343(r12)
+	tbitw $3,0x12345(r2)
+	tbitw $3,0x4abcd(r8)
+	tbitw $3,0xfabcd(r13)
+	tbitw $3,0xfabcd(r8)
+	tbitw $3,0xfabcd(r9)
+	tbitw $3,0x4abcd(r9)
+	tbitw $15,0x0(r2)
+	tbitw $13,0x34(r12)
+	tbitw $13,0xab(r13)
+	tbitw $15,0xad(r1)
+	tbitw $15,0xcd(r2)
+	tbitw $15,0xfff(r0)
+	tbitw $13,0xbcd(r4)
+	tbitw $13,0xfff(r12)
+	tbitw $13,0xfff(r13)
+	tbitw $13,0xffff(r13)
+	tbitw $13,0x2343(r12)
+	tbitw $13,0x12345(r2)
+	tbitw $13,0x4abcd(r8)
+	tbitw $13,0xfabcd(r13)
+	tbitw $13,0xfabcd(r8)
+	tbitw $13,0xfabcd(r9)
+	tbitw $13,0x4abcd(r9)
+
+	tbitw $3,0x0(r2,r1)
+	tbitw $5,0x1(r2,r1)
+	tbitw $4,0x1234(r2,r1)
+	tbitw $3,0x1234(r2,r1)
+	tbitw $3,0x12345(r2,r1)
+	tbitw $3,0x123(r2,r1)
+	tbitw $3,0x12345(r2,r1)
+	tbitw $13,0x0(r2,r1)
+	tbitw $15,0x1(r2,r1)
+	tbitw $14,0x1234(r2,r1)
+	tbitw $13,0x1234(r2,r1)
+	tbitw $13,0x12345(r2,r1)
+	tbitw $13,0x123(r2,r1)
+	tbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/xor_test.d b/gas/testsuite/gas/cr16/xor_test.d
new file mode 100644
index 0000000..57f7e23
--- /dev/null
+++ b/gas/testsuite/gas/cr16/xor_test.d
@@ -0,0 +1,49 @@
+#as:
+#objdump:  -dr
+#name:  xor_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 28       	xorb	\$0xf:s,r1
+   2:	b2 28 ff 00 	xorb	\$0xff:m,r2
+   6:	b1 28 ff 0f 	xorb	\$0xfff:m,r1
+   a:	b2 28 ff ff 	xorb	\$0xffff:m,r2
+   e:	b1 28 14 00 	xorb	\$0x14:m,r1
+  12:	a2 28       	xorb	\$0xa:s,r2
+  14:	12 29       	xorb	r1,r2
+  16:	23 29       	xorb	r2,r3
+  18:	34 29       	xorb	r3,r4
+  1a:	56 29       	xorb	r5,r6
+  1c:	67 29       	xorb	r6,r7
+  1e:	78 29       	xorb	r7,r8
+  20:	f1 2a       	xorw	\$0xf:s,r1
+  22:	b2 2a ff 00 	xorw	\$0xff:m,r2
+  26:	b1 2a ff 0f 	xorw	\$0xfff:m,r1
+  2a:	b2 2a ff ff 	xorw	\$0xffff:m,r2
+  2e:	b1 2a 14 00 	xorw	\$0x14:m,r1
+  32:	a2 2a       	xorw	\$0xa:s,r2
+  34:	12 2b       	xorw	r1,r2
+  36:	23 2b       	xorw	r2,r3
+  38:	34 2b       	xorw	r3,r4
+  3a:	56 2b       	xorw	r5,r6
+  3c:	67 2b       	xorw	r6,r7
+  3e:	78 2b       	xorw	r7,r8
+  40:	61 00 00 00 	xord	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	61 00 00 00 	xord	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	61 00 00 00 	xord	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	61 00 00 00 	xord	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	61 00 0f 00 	xord	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	61 00 ff 0f 	xord	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	61 00 ff ff 	xord	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 a0 	xord	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 a0 	xord	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/xor_test.s b/gas/testsuite/gas/cr16/xor_test.s
new file mode 100644
index 0000000..b99d103
--- /dev/null
+++ b/gas/testsuite/gas/cr16/xor_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# XORB imm4/imm16, reg
+        ###########
+	xorb    $0xf,r1
+	xorb    $0xff,r2
+	xorb    $0xfff,r1
+	xorb    $0xffff,r2
+	xorb    $20,r1
+	xorb    $10,r2
+        ###########
+	# XORB reg, reg
+        ###########
+	xorb    r1,r2
+	xorb    r2,r3
+	xorb    r3,r4
+	xorb    r5,r6
+	xorb    r6,r7
+	xorb    r7,r8
+        ###########
+	# XORW imm4/imm16, reg
+        ###########
+	xorw    $0xf,r1
+	xorw    $0xff,r2
+	xorw    $0xfff,r1
+	xorw    $0xffff,r2
+	xorw    $20,r1
+	xorw    $10,r2
+        ###########
+	# XORW reg, reg
+        ###########
+	xorw    r1,r2
+	xorw    r2,r3
+	xorw    r3,r4
+	xorw    r5,r6
+	xorw    r6,r7
+	xorw    r7,r8
+        ###########
+	# XORD imm32, regp
+        ###########
+	xord    $0xf,(r2,r1)
+	xord    $0xff,(r2,r1)
+	xord    $0xfff,(r2,r1)
+	xord    $0xffff,(r2,r1)
+	xord    $0xfffff,(r2,r1)
+	xord    $0xfffffff,(r2,r1)
+	xord    $0xffffffff,(r2,r1)
+        ###########
+	# XORD regp, regp
+        ###########
+	xord    (r4,r3),(r2,r1)
+	xord    (r4,r3),(r2,r1)
+	#xord    $10,(sp)
+	#xord    $14,(sp)
+	#xord    $8,(sp)