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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-14 21:18:16 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-14 22:04:39 +0000 |
| commit | 353abf7c10561aab3e8e7ffce6e270c3743376f0 (patch) | |
| tree | 8c3e3381198a36dacbb46cd30ce3c774e7cc803b /gas | |
| parent | 63e014fccdd91a89873554f6b33d7128d7112813 (diff) | |
| download | gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.zip gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.tar.gz gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.tar.bz2 | |
MIPS16: Fix SP-relative SD instruction annotation
Fix the annotation of SP-relative SD instructions incorrectly marked as
reading from the PC rather than SP, which in turn prevented their 16-bit
forms from being scheduled into jump delay slots. This bug has been
there since forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
`pinfo2' with SP-relative "sd" entries.
gas/
* testsuite/gas/mips/mips16-sprel-swap.d: New test.
* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips16-sprel-swap.d | 20 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips16-sprel-swap.s | 24 |
4 files changed, 51 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index b2eaa8d..742da3e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2016-12-14 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/gas/mips/mips16-sprel-swap.d: New test. + * testsuite/gas/mips/mips16-sprel-swap.s: New test source. + * testsuite/gas/mips/mips.exp: Run the new test. + 2016-12-13 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 38c57f4..da8d569 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1296,6 +1296,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "mips16e-64" "-march=mips32 -32" run_dump_test "mips16-intermix" run_dump_test "mips16-extend" + run_dump_test "mips16-sprel-swap" run_dump_test "vxworks1" run_dump_test "vxworks1-xgot" diff --git a/gas/testsuite/gas/mips/mips16-sprel-swap.d b/gas/testsuite/gas/mips/mips16-sprel-swap.d new file mode 100644 index 0000000..3b34fc8 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-sprel-swap.d @@ -0,0 +1,20 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS16 jump delay slot scheduling for SP-relative instructions +#as: -32 + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> d204 sw v0,16\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> 6206 sw ra,24\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> f944 sd v0,32\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> fa05 sd ra,40\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> 920c lw v0,48\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> f847 ld v0,56\(sp\) + \.\.\. diff --git a/gas/testsuite/gas/mips/mips16-sprel-swap.s b/gas/testsuite/gas/mips/mips16-sprel-swap.s new file mode 100644 index 0000000..3538158 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-sprel-swap.s @@ -0,0 +1,24 @@ + .module mips3 + .set mips16 +foo: + sw $2, 0x10($29) + jr $3 + + sw $31, 0x18($29) + jr $3 + + sd $2, 0x20($29) + jr $3 + + sd $31, 0x28($29) + jr $3 + + lw $2, 0x30($29) + jr $3 + + ld $2, 0x38($29) + jr $3 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 |