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authorThiemo Seufer <ths@networkno.de>2006-11-06 14:28:21 +0000
committerThiemo Seufer <ths@networkno.de>2006-11-06 14:28:21 +0000
commita360e743fba30ffcd20ca3878b16bc28b5634629 (patch)
tree4483e232ad8c5b8c5b049cd595cadcc316dfb34c /gas
parent7d0317c40ffffb902c5661b7cf62758831ed62d5 (diff)
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* config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
34k always has DSP ASE.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-mips.c13
2 files changed, 12 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cb43b84..eccd265 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2006-11-06 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
+ 34k always has DSP ASE.
+
2006-11-03 Thiemo Seufer <ths@mips.com>
* config/tc-mips.c (md_pcrel_from_section): Disallow PC relative
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index e9657c1..d3ed818 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -14580,19 +14580,20 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 24ke is a 24k with DSP ASE, other ASEs are optional. */
- { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- /* 34k is a 24k with MT ASE, other ASEs are optional. */
- { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* 34k is a 24k with DSP and MT ASE, other ASEs are optional. */
+ { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
/* MIPS 64 */
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },