Add MIPS V and MIPS 64 machine numbers

4 files changed, 71 insertions, 18 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8de2b35..bd23387 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -52,6 +52,21 @@
         4Kp entries with a single mips32-4k entry.  Note that you can
         use ".set mips32".
 
+        * tc-mips.c (ISA_HAS_64BIT_REGS): Add checks for ISA_MIPS5 and
+        ISA_MIPS64.
+        (md_longopts, OPTION_MIPS5, OPTION_MIPS64): Add options for
+        -mips5 and -mips64.
+        (md_parse_option): Add cases for OPTION_MIPS5 and
+        OPTION_MIPS64.
+        (md_show_usage): Mention -mips5 and -mips64 arguments.
+        (s_mipsset): Add cases for MIPS5 and MIPS64.
+        (mips_cpu_info_table): Add entries for MIPS5 and MIPS64 ISAs
+        and pseudo-CPUs.
+        * doc/as.texinfo: Mention -mips5 and -mips64 options
+        and their meanings.
+        * doc/c-mips.texi: Likewise.  Also update introduction
+        and ".set" usage information.
+
 2000-12-01      Joel Sherrill <joel@OARcorp.com>
 
 	* configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index fb8c5e6..f4f1130 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -238,6 +238,8 @@ static int mips_gp32 = 0;
 #define ISA_HAS_64BIT_REGS(ISA) (    \
    (ISA) == ISA_MIPS3                \
    || (ISA) == ISA_MIPS4             \
+   || (ISA) == ISA_MIPS5             \
+   || (ISA) == ISA_MIPS32            \
    )
 
 /* Whether the processor uses hardware interlocks to protect
@@ -8884,6 +8886,10 @@ struct option md_longopts[] =
   {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
   {"mips32", no_argument, NULL, OPTION_MIPS32},
+#define OPTION_MIPS5 (OPTION_MD_BASE + 29)
+  {"mips5", no_argument, NULL, OPTION_MIPS5},
+#define OPTION_MIPS64 (OPTION_MD_BASE + 30)
+  {"mips64", no_argument, NULL, OPTION_MIPS64},
 #ifdef OBJ_ELF
 #define OPTION_ELF_BASE    (OPTION_MD_BASE + 35)
 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
@@ -8969,10 +8975,18 @@ md_parse_option (c, arg)
       mips_opts.isa = ISA_MIPS4;
       break;
 
+    case OPTION_MIPS5:
+      mips_opts.isa = ISA_MIPS5;
+      break;
+
     case OPTION_MIPS32:
       mips_opts.isa = ISA_MIPS32;
       break;
 
+    case OPTION_MIPS64:
+      mips_opts.isa = ISA_MIPS64;
+      break;
+
     case OPTION_MCPU:
       {
 	/* Identify the processor type.  */
@@ -9206,7 +9220,9 @@ MIPS options:\n\
 -mips2			generate MIPS ISA II instructions\n\
 -mips3			generate MIPS ISA III instructions\n\
 -mips4			generate MIPS ISA IV instructions\n\
+-mips5                  generate MIPS ISA V instructions\n\
 -mips32                 generate MIPS32 ISA instructions\n\
+-mips64                 generate MIPS64 ISA instructions\n\
 -mcpu=CPU		generate code for CPU, where CPU is one of:\n"));
 
   first = 1;
@@ -10234,15 +10250,15 @@ s_mipsset (x)
       isa = atoi (name + 4);
       switch (isa)
       {
-      case  0: mips_opts.isa = file_mips_isa; break;
-      case  1: mips_opts.isa = ISA_MIPS1;     break;
-      case  2: mips_opts.isa = ISA_MIPS2;     break;
-      case  3: mips_opts.isa = ISA_MIPS3;     break;
-      case  4: mips_opts.isa = ISA_MIPS4;     break;
-      case 32: mips_opts.isa = ISA_MIPS32;    break;
-      default:
-        as_bad (_("unknown ISA level"));
-        break;
+      case  0: mips_opts.isa = file_mips_isa;   break;
+      case  1: mips_opts.isa = ISA_MIPS1;       break;
+      case  2: mips_opts.isa = ISA_MIPS2;       break;
+      case  3: mips_opts.isa = ISA_MIPS3;       break;
+      case  5: mips_opts.isa = ISA_MIPS5;       break;
+      case  4: mips_opts.isa = ISA_MIPS4;       break;
+      case 32: mips_opts.isa = ISA_MIPS32;      break;
+      case 64: mips_opts.isa = ISA_MIPS64;      break;
+      default: as_bad (_("unknown ISA level")); break;
       }
     }
   else if (strcmp (name, "autoextend") == 0)
@@ -11914,12 +11930,23 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   /* MIPS4 ISA */
   { "MIPS4",          1,      ISA_MIPS4,      CPU_R8000, },
 
+  /* MIPS5 ISA */
+  { "MIPS5",          1,      ISA_MIPS5,      CPU_MIPS5, },
+  { "Generic-MIPS5",  0,      ISA_MIPS5,      CPU_MIPS5, },
+
   /* MIPS32 ISA */
   { "MIPS32",         1,      ISA_MIPS32,     CPU_MIPS32, },
   { "Generic-MIPS32", 0,      ISA_MIPS32,     CPU_MIPS32, },
 
+#if 1
   /* XXX for now, MIPS64 -> MIPS3 because of history */
   { "MIPS64",         1,      ISA_MIPS3,      CPU_R4000 }, /* XXX! */
+#else
+  /* MIPS64 ISA */
+  { "MIPS64",         1,      ISA_MIPS64,     CPU_MIPS64 },
+#endif
+  { "mips64isa",      1,      ISA_MIPS64,     CPU_MIPS64 },
+  { "Generic-MIPS64", 0,      ISA_MIPS64,     CPU_MIPS64, },
 
   /* R2000 CPU */
   { "R2000",          0,      ISA_MIPS1,      CPU_R2000, },
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index a59ae1d..3988d00 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -276,7 +276,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}.  For details,
 @end ifset
 @ifset MIPS
  [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
- [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
+ [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
+ [ -mips32 ] [ -mips64 ]
  [ -m4650 ] [ -no-m4650 ]
  [ --trap ] [ --break ]
  [ --emulation=@var{name} ]
@@ -674,8 +675,11 @@ Generate ``little endian'' format output.
 @itemx -mips32
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
-@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
-processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
+@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
+processor.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
 
 @item -m4650
 @itemx -no-m4650
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index e56156e..b9902ff 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -13,7 +13,8 @@
 
 @cindex MIPS processor
 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
-different @sc{mips} processors, and MIPS ISA levels I through IV.  For
+different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
+and MIPS64.  For
 information about the @sc{mips} instruction set, see @cite{MIPS RISC
 Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
@@ -60,13 +61,18 @@ to select big-endian output, and @samp{-EL} for little-endian.
 @itemx -mips2
 @itemx -mips3
 @itemx -mips4
+@itemx -mips5
 @itemx -mips32
+@itemx -mips64
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
-@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
-processor.  You can also switch instruction sets during the
+@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
+@sc{r10000} processors.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
+You can also switch instruction sets during the
 assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
 
 @item -mgp32
@@ -239,8 +245,9 @@ assembly language programmers!
 @kindex @code{.set mips@var{n}}
 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}.  @var{n} should be a number from 0 to 4, or 32.  The values 1
-to 4 and 32 make the assembler accept instructions for the corresponding
+mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32 or 64.
+The values 1 to 5, 32, and 64 make the assembler accept instructions
+for the corresponding
 @sc{isa} level, from that point on in the assembly.  @code{.set
 mips@var{n}} affects not only which instructions are permitted, but also
 how certain macros are expanded.  @code{.set mips0} restores the