diff options
| author | Ian Lance Taylor <ian@airs.com> | 1998-10-20 14:51:09 +0000 |
|---|---|---|
| committer | Ian Lance Taylor <ian@airs.com> | 1998-10-20 14:51:09 +0000 |
| commit | f5003e7d628285d7d578ae4b1149ce23dbe12694 (patch) | |
| tree | f61db2fddb491b141bc95eba2929b04df6c06e44 /gas | |
| parent | d10fb38c2b56cc15f3037a4d73e857827b7dd3dc (diff) | |
| download | gdb-f5003e7d628285d7d578ae4b1149ce23dbe12694.zip gdb-f5003e7d628285d7d578ae4b1149ce23dbe12694.tar.gz gdb-f5003e7d628285d7d578ae4b1149ce23dbe12694.tar.bz2 | |
* config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc
for BFD_ASSEMBLER to only change value when COFF if TE_PE.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 29 |
2 files changed, 32 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 6ca1306..11a9721 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +Tue Oct 20 10:49:42 1998 Ian Lance Taylor <ian@cygnus.com> + + * config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc + for BFD_ASSEMBLER to only change value when COFF if TE_PE. + Mon Oct 19 20:20:42 1998 Catherine Moore <clm@cygnus.com> * config/tc-sh.h (obj_fix_adjustable): Define. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 49d2a7f..b4f5c76 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1511,6 +1511,28 @@ md_assemble (line) } } + if (i.tm.base_opcode == AMD_3DNOW_OPCODE) + { + /* These AMD specific instructions have an opcode suffix which + is coded in the same place as an 8-bit immediate field + would be. Here we fake an 8-bit immediate operand from the + opcode suffix stored in tm.extension_opcode. + Note: this "opcode suffix" has nothing to do with what gas + calls opcode suffixes. gas opcode suffixes should really + be called instruction mnemonic suffixes. FIXME maybe. */ + + expressionS *exp; + + assert(i.imm_operands == 0 && i.operands <= 2); + + exp = &im_expressions[i.imm_operands++]; + i.imms[i.operands] = exp; + i.types[i.operands++] = Imm8; + exp->X_op = O_constant; + exp->X_add_number = i.tm.extension_opcode; + i.tm.extension_opcode = None; + } + /* For insns with operands there are more diddles to do to the opcode. */ if (i.operands) { @@ -2283,7 +2305,7 @@ i386_operand (operand_string) op_string = end_op; if (is_space_char (*op_string)) ++op_string; - if (*op_string) + if (*op_string == ':') { if (r->reg_type & (SReg2 | SReg3)) { @@ -3090,7 +3112,10 @@ md_apply_fix3 (fixP, valp, seg) { #ifndef OBJ_AOUT if (OUTPUT_FLAVOR == bfd_target_elf_flavour - || OUTPUT_FLAVOR == bfd_target_coff_flavour) +#ifdef TE_PE + || OUTPUT_FLAVOR == bfd_target_coff_flavour +#endif + ) value += fixP->fx_where + fixP->fx_frag->fr_address; #endif #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |