[BINUTILS, AArch64] Enable Transactional Memory Extension

This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.

We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
   * tstart <Xt>
   * ttest <Xt>
   * tcommit
   * tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order

*** gas/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_features): Add "tme".
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/tme-invalid.d: New test.
	* testsuite/gas/aarch64/tme-invalid.l: New test.
	* testsuite/gas/aarch64/tme-invalid.s: New test.
	* testsuite/gas/aarch64/tme.d: New test.
	* testsuite/gas/aarch64/tme.s: New test.

*** include/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
	(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.

*** opcodes/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_IMM_NIL): New.
	(TME): New.
	(_TME_INSN): New.
	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.

8 files changed, 111 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9f5e9ba..2dd2cf3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2019-05-01  Sudakshina Das  <sudi.das@arm.com>
+
+	* config/tc-aarch64.c (parse_operands): Add case for
+	AARCH64_OPND_TME_UIMM16.
+	(aarch64_features): Add "tme".
+	* doc/c-aarch64.texi: Document the same.
+	* testsuite/gas/aarch64/tme-invalid.d: New test.
+	* testsuite/gas/aarch64/tme-invalid.l: New test.
+	* testsuite/gas/aarch64/tme-invalid.s: New test.
+	* testsuite/gas/aarch64/tme.d: New test.
+	* testsuite/gas/aarch64/tme.s: New test.
+
 2019-04-29  John Darrington <john@darrington.wattle.id.au>
 
         * testsuite/gas/s12z/truncated.d: New file.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0f03a28..7b5f1b1 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5752,6 +5752,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_CCMP_IMM:
 	case AARCH64_OPND_SIMM5:
 	case AARCH64_OPND_FBITS:
+	case AARCH64_OPND_TME_UIMM16:
 	case AARCH64_OPND_UIMM4:
 	case AARCH64_OPND_UIMM4_ADDG:
 	case AARCH64_OPND_UIMM10:
@@ -8845,6 +8846,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (AARCH64_FEATURE_F16
 					 | AARCH64_FEATURE_SIMD
 					 | AARCH64_FEATURE_COMPNUM, 0)},
+  {"tme",		AARCH64_FEATURE (AARCH64_FEATURE_TME, 0),
+			AARCH64_ARCH_NONE},
   {"compnum",		AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
 			AARCH64_FEATURE (AARCH64_FEATURE_F16
 					 | AARCH64_FEATURE_SIMD, 0)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 445fb2f..3614deb 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -194,6 +194,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{memtag} @tab ARMv8.5-A @tab No
  @tab Enable ARMv8.5-A Memory Tagging Extensions.
+@item @code{tme} @tab ARMv8-A @tab No
+ @tab Enable Transactional Memory Extensions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/tme-invalid.d b/gas/testsuite/gas/aarch64/tme-invalid.d
new file mode 100644
index 0000000..6ff73e9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-invalid.d
@@ -0,0 +1,4 @@
+#name: Invalid TME instructions
+#as: -march=armv8-a+tme
+#source: tme-invalid.s
+#error_output: tme-invalid.l
diff --git a/gas/testsuite/gas/aarch64/tme-invalid.l b/gas/testsuite/gas/aarch64/tme-invalid.l
new file mode 100644
index 0000000..22f60c5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-invalid.l
@@ -0,0 +1,26 @@
+[^:]*: Assembler messages:
+.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel -1'
+.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel 65536'
+.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel 0x10000'
+.*: Error: constant expression required at operand 1 -- `tcancel 1b'
+.*: Error: immediate operand required at operand 1 -- `tcancel w1'
+.*: Error: immediate operand required at operand 1 -- `tcancel x1'
+.*: Error: immediate operand required at operand 1 -- `tcancel w23'
+.*: Error: immediate operand required at operand 1 -- `tcancel x23'
+.*: Error: immediate operand required at operand 1 -- `tcancel wzr'
+.*: Error: immediate operand required at operand 1 -- `tcancel xzr'
+.*: Error: constant expression required at operand 1 -- `tcancel wsp'
+.*: Error: constant expression required at operand 1 -- `tcancel xsp'
+.*: Error: constant expression required at operand 1 -- `tcancel sp'
+.*: Error: operand 1 must be an integer register -- `tstart'
+.*: Error: operand mismatch -- `tstart w1'
+.*: Info:    did you mean this\?
+.*: Info:    	tstart x1
+.*: Error: operand mismatch -- `tstart w17'
+.*: Info:    did you mean this\?
+.*: Info:    	tstart x17
+.*: Error: operand mismatch -- `tstart wzr'
+.*: Info:    did you mean this\?
+.*: Info:    	tstart xzr
+.*: Error: operand 1 must be an integer register -- `tstart wsp'
+.*: Error: operand 1 must be an integer register -- `tstart xsp'
diff --git a/gas/testsuite/gas/aarch64/tme-invalid.s b/gas/testsuite/gas/aarch64/tme-invalid.s
new file mode 100644
index 0000000..13d8e3b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-invalid.s
@@ -0,0 +1,28 @@
+// Instructions in this file are invalid.
+// Other files provide more extensive testing of valid instructions;
+
+# tcancel only accept 16bit unsigned constant immediate.
+1:
+	tcancel	-1
+	tcancel	65536
+	tcancel	0x10000
+	tcancel	1b
+
+# tcancel doesn't accept any register.
+	tcancel w1
+	tcancel x1
+	tcancel w23
+	tcancel x23
+	tcancel wzr
+	tcancel xzr
+	tcancel wsp
+	tcancel xsp
+	tcancel sp
+
+# tstart must has one X register operand.
+	tstart
+	tstart w1
+	tstart w17
+	tstart wzr
+	tstart wsp
+	tstart xsp
diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
new file mode 100644
index 0000000..24d34ea
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme.d
@@ -0,0 +1,22 @@
+#as: -march=armv8-a+tme
+#objdump: -dr
+
+.* file format .*
+
+Disassembly of section .*:
+
+.* <.*>:
+.*:	d5233060 	tstart	x0
+.*:	d5233060 	tstart	x0
+.*:	d523306f 	tstart	x15
+.*:	d523306f 	tstart	x15
+.*:	d523307e 	tstart	x30
+.*:	d523307e 	tstart	x30
+.*:	d503307f 	tcommit
+.*:	d503307f 	tcommit
+.*:	d5233160 	ttest	x0
+.*:	d523317e 	ttest	x30
+.*:	d4600000 	tcancel	#0
+.*:	d47fffe0 	tcancel	#65535
+.*:	d47fffe0 	tcancel	#65535
+.*:	d4600140 	tcancel	#10
diff --git a/gas/testsuite/gas/aarch64/tme.s b/gas/testsuite/gas/aarch64/tme.s
new file mode 100644
index 0000000..45c861e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme.s
@@ -0,0 +1,14 @@
+	tstart	x0
+	TSTART	X0
+	tstart	x15
+	TSTART	X15
+	tstart	x30
+	TSTART	X30
+	tcommit
+	TCOMMIT
+	ttest	x0
+	TTEST	X30
+	tcancel	0
+	TCANCEL	65535
+	tcancel	0xffff
+	TCANCEL	0XA