diff options
author | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
---|---|---|
committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
commit | 875ac09b1217981fcd8d72908f45ecd9540fe8b5 (patch) | |
tree | e598634538e908e65ca5dc97ce67caf6da4cb0dc /gas | |
parent | 5dd9c473f6bf04f12ec93182ccfa165e962e3500 (diff) | |
download | gdb-875ac09b1217981fcd8d72908f45ecd9540fe8b5.zip gdb-875ac09b1217981fcd8d72908f45ecd9540fe8b5.tar.gz gdb-875ac09b1217981fcd8d72908f45ecd9540fe8b5.tar.bz2 |
MIPS/GAS: Handle --trap command-line option dynamically
We have an ISA check for the '--trap' command-line option that reports
its incompatibility with the MIPS I architecture. It doesn't prevent
trap instructions from being enabled though, so when attempt is made to
emit one in an expansion of one of the division or multiplication macros
an assertion failure triggers:
.../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages:
.../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1
.../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero
.../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064.
Please report this bug.
The same assertion failure triggers without an earlier error message
when the initial ISA is compatible with the '--trap', however at the
time an attempt is made to emit a trap instruction from a division or
multiplication macro the ISA has been changed by a '.set' pseudo-op to
an incompatible one.
With the way the situations are mishandled it seems unlikely that anyone
relies on the current semantics and a sane approach is to decide on the
fly according to the currently selected ISA as to whether to emit trap
or breakpoint instructions in the case where '--trap' has been used.
Change our code to do so then and clarify that in the manual, which is
not explicit about how '--trap' is handled with a changing ISA. Mention
the change in NEWS too since it's a applies to a user option.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/NEWS | 7 | ||||
-rw-r--r-- | gas/config/tc-mips.c | 36 | ||||
-rw-r--r-- | gas/doc/c-mips.texi | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/allegrex@trap-opt.d | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/break-opt.d | 115 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/brtr-opt.l | 7 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/brtr-opt.s | 46 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/micromips@break-opt.d | 134 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/micromips@trap-opt.d | 94 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/mips1@trap-opt.d | 107 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/r3000@trap-opt.d | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/r3900@trap-opt.d | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/trap-opt.d | 99 |
14 files changed, 663 insertions, 15 deletions
@@ -1,5 +1,12 @@ -*- text -*- +* The MIPS '--trap' command-line option now causes GAS to dynamically + track the ISA setting as code is assembled and to emit either trap or + breakpoint instructions according to whether the currently selected ISA + permits the use of trap instructions or not. Previously the ISA was + only checked at startup and GAS bailed out if the initial ISA was + incompatible with the '--trap' option. + * Support CFCMOV feature in Intel APX. Now, APX_F is fully supportted. * Support CCMP and CTEST feature in Intel APX. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 8f54cb8..d551b47 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -399,6 +399,12 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS64R5 \ || (ISA) == ISA_MIPS64R6) +/* Return true if the ISA and CPU support trap instructions. */ +#define ISA_HAS_TRAPS(ISA, CPU) \ + (((ISA) != ISA_MIPS1 \ + && (CPU) != CPU_ALLEGREX) \ + || mips_opts.micromips) \ + /* Return true if ISA supports 64-bit right rotate (dror et al.) instructions. */ #define ISA_HAS_DROR(ISA) \ @@ -4153,9 +4159,6 @@ file_mips_check_options (void) || mips_abi == O32_ABI)) mips_32bitmode = 1; - if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) - as_bad (_("trap exception not supported at ISA 1")); - /* If the selected architecture includes support for ASEs, enable generation of code for them. */ if (file_mips_opts.mips16 == -1) @@ -10269,6 +10272,16 @@ small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) return false; } +/* Return true if the ISA, CPU, and --trap settings imply using trap + rather than breakpoint instructions in the expansion of multiply + and divide macros. */ + +static bool +mips_use_trap (void) +{ + return ISA_HAS_TRAPS (mips_opts.isa, mips_opts.arch) && mips_trap; +} + /* * Build macros * This routine implements the seemingly endless macro or synthesized @@ -10787,7 +10800,7 @@ macro (struct mips_cl_insn *ip, char *str) if (op[2] == 0) { as_warn (_("divide by zero")); - if (mips_trap) + if (mips_use_trap ()) macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); else macro_build (NULL, "break", BRK_FMT, 7); @@ -10795,7 +10808,7 @@ macro (struct mips_cl_insn *ip, char *str) } start_noreorder (); - if (mips_trap) + if (mips_use_trap ()) { macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); @@ -10818,7 +10831,8 @@ macro (struct mips_cl_insn *ip, char *str) if (mips_opts.micromips) micromips_label_expr (&label_expr); else - label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); + label_expr.X_add_number = (mips_use_trap () + ? (dbl ? 12 : 8) : (dbl ? 20 : 16)); macro_build (&label_expr, "bne", "s,t,p", op[2], AT); if (dbl) { @@ -10831,7 +10845,7 @@ macro (struct mips_cl_insn *ip, char *str) expr1.X_add_number = 0x80000000; macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); } - if (mips_trap) + if (mips_use_trap ()) { macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); /* We want to close the noreorder block as soon as possible, so @@ -10897,7 +10911,7 @@ macro (struct mips_cl_insn *ip, char *str) if (imm_expr.X_add_number == 0) { as_warn (_("divide by zero")); - if (mips_trap) + if (mips_use_trap ()) macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); else macro_build (NULL, "break", BRK_FMT, 7); @@ -10943,7 +10957,7 @@ macro (struct mips_cl_insn *ip, char *str) s2 = "mfhi"; do_divu3: start_noreorder (); - if (mips_trap) + if (mips_use_trap ()) { macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); macro_build (NULL, s, "z,s,t", op[1], op[2]); @@ -13308,7 +13322,7 @@ macro (struct mips_cl_insn *ip, char *str) macro_build (NULL, "mflo", MFHL_FMT, op[0]); macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); macro_build (NULL, "mfhi", MFHL_FMT, AT); - if (mips_trap) + if (mips_use_trap ()) macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); else { @@ -13346,7 +13360,7 @@ macro (struct mips_cl_insn *ip, char *str) op[1], imm ? AT : op[2]); macro_build (NULL, "mfhi", MFHL_FMT, AT); macro_build (NULL, "mflo", MFHL_FMT, op[0]); - if (mips_trap) + if (mips_use_trap ()) macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); else { diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index f3c1f66..4181aa3 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -588,10 +588,12 @@ directive to the beginning of the source file. @xref{MIPS NaN Encodings}. @c FIXME! (1) reflect these options (next item too) in option summaries; @c (2) stop teasing, say _which_ instructions expanded _how_. @code{@value{AS}} automatically macro expands certain division and -multiplication instructions to check for overflow and division by zero. This -option causes @code{@value{AS}} to generate code to take a trap exception -rather than a break exception when an error is detected. The trap instructions -are only supported at Instruction Set Architecture level 2 and higher. +multiplication instructions to check for overflow and division by zero. +This option causes @code{@value{AS}} to generate code to take a trap +exception rather than a break exception when an error is detected and the +ISA selected for assembly at the originating place in source code permits +the use of trap instructions. The trap instructions are only supported at +Instruction Set Architecture level 2 and higher. @item --break @itemx --no-trap diff --git a/gas/testsuite/gas/mips/allegrex@trap-opt.d b/gas/testsuite/gas/mips/allegrex@trap-opt.d new file mode 100644 index 0000000..c6e7d67 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@trap-opt.d @@ -0,0 +1,6 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s +#dump: mips1@trap-opt.d diff --git a/gas/testsuite/gas/mips/break-opt.d b/gas/testsuite/gas/mips/break-opt.d new file mode 100644 index 0000000..86e0639 --- /dev/null +++ b/gas/testsuite/gas/mips/break-opt.d @@ -0,0 +1,115 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --break +#as: -32 --break +#warning_output: brtr-opt.l +#source: brtr-opt.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 + \.\.\. diff --git a/gas/testsuite/gas/mips/brtr-opt.l b/gas/testsuite/gas/mips/brtr-opt.l new file mode 100644 index 0000000..7f7cc0a --- /dev/null +++ b/gas/testsuite/gas/mips/brtr-opt.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:9: Warning: divide by zero +.*:10: Warning: divide by zero +.*:21: Warning: divide by zero +.*:22: Warning: divide by zero +.*:33: Warning: divide by zero +.*:34: Warning: divide by zero diff --git a/gas/testsuite/gas/mips/brtr-opt.s b/gas/testsuite/gas/mips/brtr-opt.s new file mode 100644 index 0000000..0b06277 --- /dev/null +++ b/gas/testsuite/gas/mips/brtr-opt.s @@ -0,0 +1,46 @@ +# We use XOR placeholders to avoid implicit NOPs causing output variation. + .text + .set nodsp + .set noeva + .set nomips16e2 + .set nomt + .set novirt +foo: + div $6, $4, $0 + divu $6, $4, 0 + rem $6, $4, $2 + xor $16, $16 + remu $6, $4, $2 + xor $16, $16 + xor $17, $17 + mulo $6, $4, $2 + xor $16, $16 + mulou $6, $4, 2 + + .set mips1 + div $6, $4, $0 + divu $6, $4, 0 + rem $6, $4, $2 + xor $16, $16 + remu $6, $4, $2 + xor $16, $16 + xor $17, $17 + mulo $6, $4, $2 + xor $16, $16 + mulou $6, $4, 2 + + .set mips2 + div $6, $4, $0 + divu $6, $4, 0 + rem $6, $4, $2 + xor $16, $16 + remu $6, $4, $2 + xor $16, $16 + xor $17, $17 + mulo $6, $4, $2 + xor $16, $16 + mulou $6, $4, 2 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/gas/testsuite/gas/mips/micromips@break-opt.d b/gas/testsuite/gas/mips/micromips@break-opt.d new file mode 100644 index 0000000..0516b5e --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@break-opt.d @@ -0,0 +1,134 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --break +#as: -32 --break +#warning_output: brtr-opt.l +#source: brtr-opt.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_0 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_0> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_1 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> b424 fffe bne a0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_1 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_1> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_2 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_2> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 9426 fffe beq a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_3 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_3> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 9401 fffe beqz at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_4 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_4> 4687 break 0x7 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_5 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_5> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_6 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> b424 fffe bne a0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_6 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_6> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_7 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_7> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 9426 fffe beq a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_8 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_8> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 9401 fffe beqz at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_9 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_9> 4687 break 0x7 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_10 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_10> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_11 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> b424 fffe bne a0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_11 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_11> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> b402 fffe bnez v0,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_12 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4687 break 0x7 +[0-9a-f]+ <\.L\^_12> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 9426 fffe beq a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_13 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 +[0-9a-f]+ <\.L\^_13> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 9401 fffe beqz at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_14 +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 4686 break 0x6 + \.\.\. + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@trap-opt.d b/gas/testsuite/gas/mips/micromips@trap-opt.d new file mode 100644 index 0000000..dcf2a5a --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@trap-opt.d @@ -0,0 +1,94 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_0 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0024 603c teq a0,at,0x6 +[0-9a-f]+ <\.L\^_0> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 0026 6c3c tne a2,at,0x6 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 0001 6c3c tne at,zero,0x6 +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_1 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0024 603c teq a0,at,0x6 +[0-9a-f]+ <\.L\^_1> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 0026 6c3c tne a2,at,0x6 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 0001 6c3c tne at,zero,0x6 +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0000 703c teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 ab3c div zero,a0,v0 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b422 fffe bne v0,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_2 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0024 603c teq a0,at,0x6 +[0-9a-f]+ <\.L\^_2> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 0002 703c teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0044 bb3c divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 4606 mfhi a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 4449 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 0044 8b3c mult a0,v0 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 00c6 f880 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 0026 6c3c tne a2,at,0x6 +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 9b3c multu a0,at +[0-9a-f]+ <[^>]*> 4601 mfhi at +[0-9a-f]+ <[^>]*> 4646 mflo a2 +[0-9a-f]+ <[^>]*> 0001 6c3c tne at,zero,0x6 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index ae39614..a211e02 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -2182,4 +2182,9 @@ if { [istarget mips*-*-vxworks*] } { if [istarget *-*-irix*] { run_dump_test "irix-no-pdr" } + + run_dump_test_arches "break-opt" [mips_arch_list_matching mips1 \ + !mips32r6] + run_dump_test_arches "trap-opt" [mips_arch_list_matching mips1 \ + !mips32r6] } diff --git a/gas/testsuite/gas/mips/mips1@trap-opt.d b/gas/testsuite/gas/mips/mips1@trap-opt.d new file mode 100644 index 0000000..e484636 --- /dev/null +++ b/gas/testsuite/gas/mips/mips1@trap-opt.d @@ -0,0 +1,107 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 000001f4 \.word 0x1f4 +[0-9a-f]+ <[^>]*> 000001f4 \.word 0x1f4 +[0-9a-f]+ <[^>]*> 004001f4 \.word 0x4001f4 +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410002 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 008101b4 \.word 0x8101b4 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 004001f4 \.word 0x4001f4 +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00c101b6 \.word 0xc101b6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 002001b6 \.word 0x2001b6 + \.\.\. diff --git a/gas/testsuite/gas/mips/r3000@trap-opt.d b/gas/testsuite/gas/mips/r3000@trap-opt.d new file mode 100644 index 0000000..c6e7d67 --- /dev/null +++ b/gas/testsuite/gas/mips/r3000@trap-opt.d @@ -0,0 +1,6 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s +#dump: mips1@trap-opt.d diff --git a/gas/testsuite/gas/mips/r3900@trap-opt.d b/gas/testsuite/gas/mips/r3900@trap-opt.d new file mode 100644 index 0000000..c6e7d67 --- /dev/null +++ b/gas/testsuite/gas/mips/r3900@trap-opt.d @@ -0,0 +1,6 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s +#dump: mips1@trap-opt.d diff --git a/gas/testsuite/gas/mips/trap-opt.d b/gas/testsuite/gas/mips/trap-opt.d new file mode 100644 index 0000000..58754ec --- /dev/null +++ b/gas/testsuite/gas/mips/trap-opt.d @@ -0,0 +1,99 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS divide and multiply macros with --trap +#as: -32 --trap +#warning_output: brtr-opt.l +#source: brtr-opt.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 000001f4 teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 000001f4 teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 004001f4 teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410002 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 008101b4 teq a0,at,0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 004001f4 teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00c101b6 tne a2,at,0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 002001b6 tne at,zero,0x6 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410004 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 14810002 bne a0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 14400002 bnez v0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 0007000d break 0x7 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 10c10002 beq a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 10200002 beqz at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0006000d break 0x6 +[0-9a-f]+ <[^>]*> 000001f4 teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 000001f4 teq zero,zero,0x7 +[0-9a-f]+ <[^>]*> 004001f4 teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0082001a div zero,a0,v0 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14410002 bne v0,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 008101b4 teq a0,at,0x6 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 004001f4 teq v0,zero,0x7 +[0-9a-f]+ <[^>]*> 0082001b divu zero,a0,v0 +[0-9a-f]+ <[^>]*> 00003010 mfhi a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 02318826 xor s1,s1,s1 +[0-9a-f]+ <[^>]*> 00820018 mult a0,v0 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 000637c3 sra a2,a2,0x1f +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00c101b6 tne a2,at,0x6 +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00810019 multu a0,at +[0-9a-f]+ <[^>]*> 00000810 mfhi at +[0-9a-f]+ <[^>]*> 00003012 mflo a2 +[0-9a-f]+ <[^>]*> 002001b6 tne at,zero,0x6 + \.\.\. |