RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions

bfd/
	* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.

gas/
	* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
	(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
	* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
	* testsuite/gas/riscv/b-ext-64.d: Likewise.
	* testsuite/gas/riscv/b-ext.s: Likewise.
	* testsuite/gas/riscv/b-ext.d: Likewise.

include/
	* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
	* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.

opcodes/
	* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.

6 files changed, 170 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 79332f0..f759c93 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
+	(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
+	* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
+	* testsuite/gas/riscv/b-ext-64.d: Likewise.
+	* testsuite/gas/riscv/b-ext.s: Likewise.
+	* testsuite/gas/riscv/b-ext.d: Likewise.
+
 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
 	* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index bbf7052..429732f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -139,6 +139,10 @@ static const struct riscv_ext_version ext_version_table[] =
 
   {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
 
+  {"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+  {"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+  {"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+
   /* Terminate the list.  */
   {NULL, 0, 0, 0}
 };
@@ -330,6 +334,15 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
     case INSN_CLASS_ZIHINTPAUSE:
       return riscv_subset_supports ("zihintpause");
 
+    case INSN_CLASS_ZBB:
+      return riscv_subset_supports ("zbb");
+
+    case INSN_CLASS_ZBA:
+      return riscv_subset_supports ("zba");
+
+    case INSN_CLASS_ZBC:
+      return riscv_subset_supports ("zbc");
+
     default:
       as_fatal ("internal: unreachable");
       return FALSE;
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
new file mode 100644
index 0000000..f4a7abf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -0,0 +1,48 @@
+#as: -march=rv64i_zba_zbb_zbc
+#source: b-ext-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
+[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
+[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
+[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
+[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
+[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
+[ 	]+24:[ 	]+0805453b[ 	]+zext.h[ 	]+a0,a0
+[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+44:[ 	]+6b855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
+[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
+[ 	]+64:[ 	]+6005151b[ 	]+clzw[ 	]+a0,a0
+[ 	]+68:[ 	]+6015151b[ 	]+ctzw[ 	]+a0,a0
+[ 	]+6c:[ 	]+6025151b[ 	]+cpopw[ 	]+a0,a0
+[ 	]+70:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
+[ 	]+74:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
+[ 	]+78:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+7c:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+80:[ 	]+20c5a53b[ 	]+sh1add.uw[ 	]+a0,a1,a2
+[ 	]+84:[ 	]+20c5c53b[ 	]+sh2add.uw[ 	]+a0,a1,a2
+[ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
+[ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
+[ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+[ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
new file mode 100644
index 0000000..c3ac377
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -0,0 +1,39 @@
+target:
+	clz	a0, a0
+	ctz	a0, a0
+	cpop	a0, a0
+	min	a0, a1, a2
+	minu	a0, a1, a2
+	max	a0, a1, a2
+	maxu	a0, a1, a2
+	sext.b	a0, a0
+	sext.h	a0, a0
+	zext.h	a0, a0
+	andn	a0, a1, a2
+	orn	a0, a1, a2
+	xnor	a0, a1, a2
+	rol	a0, a1, a2
+	ror	a0, a1, a2
+	ror	a0, a1, 2
+	rori	a0, a1, 2
+	rev8	a0, a0
+	orc.b	a0, a0
+	sh1add	a0, a1, a2
+	sh2add	a0, a1, a2
+	sh3add	a0, a1, a2
+	clmul	a0, a1, a2
+	clmulh	a0, a1, a2
+	clmulr	a0, a1, a2
+	clzw	a0, a0
+	ctzw	a0, a0
+	cpopw	a0, a0
+	rolw	a0, a1, a2
+	rorw	a0, a1, a2
+	rorw	a0, a1, 2
+	roriw	a0, a1, 2
+	sh1add.uw	a0, a1, a2
+	sh2add.uw	a0, a1, a2
+	sh3add.uw	a0, a1, a2
+	add.uw	a0, a1, a2
+	zext.w	a0, a1
+	slli.uw	a0, a1, 2
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
new file mode 100644
index 0000000..7410796
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -0,0 +1,35 @@
+#as: -march=rv32i_zba_zbb_zbc
+#source: b-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
+[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
+[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
+[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
+[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
+[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
+[ 	]+24:[ 	]+08054533[ 	]+zext.h[ 	]+a0,a0
+[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+44:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
+[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
new file mode 100644
index 0000000..051dafd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -0,0 +1,26 @@
+target:
+	clz	a0, a0
+	ctz	a0, a0
+	cpop	a0, a0
+	min	a0, a1, a2
+	minu	a0, a1, a2
+	max	a0, a1, a2
+	maxu	a0, a1, a2
+	sext.b	a0, a0
+	sext.h	a0, a0
+	zext.h	a0, a0
+	andn	a0, a1, a2
+	orn	a0, a1, a2
+	xnor	a0, a1, a2
+	rol	a0, a1, a2
+	ror	a0, a1, a2
+	ror	a0, a1, 2
+	rori	a0, a1, 2
+	rev8	a0, a0
+	orc.b	a0, a0
+	sh1add	a0, a1, a2
+	sh2add	a0, a1, a2
+	sh3add	a0, a1, a2
+	clmul	a0, a1, a2
+	clmulh	a0, a1, a2
+	clmulr	a0, a1, a2