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| author | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
| commit | 5dd9c473f6bf04f12ec93182ccfa165e962e3500 (patch) | |
| tree | 3c96b753809591600cf3bcb9eb40baea4bc28762 /gas | |
| parent | 71ddc7006b9f37d0934031b4d81940644aec89ca (diff) | |
| download | gdb-5dd9c473f6bf04f12ec93182ccfa165e962e3500.zip gdb-5dd9c473f6bf04f12ec93182ccfa165e962e3500.tar.gz gdb-5dd9c473f6bf04f12ec93182ccfa165e962e3500.tar.bz2 | |
MIPS/GAS/testsuite: Add R10000 CPU architecture
Add a fully interlocked MIPS IV CPU so that we can have coverage for
MIPS IV instruction sequences with and without instruction separation
required for a HI/LO data anti-dependency.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r10000@c0.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r10000@c1.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r10000@cp0c.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r10000@save-sub.d | 5 |
5 files changed, 22 insertions, 0 deletions
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index e388bb7..ae39614 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -522,6 +522,8 @@ mips_arch_create r4000 64 mips3 {} \ mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat nollsc } \ { -march=r5900 -mtune=r5900 } { -mmips:5900 } \ { mipsr5900el-*-* mips64r5900el-*-* } +mips_arch_create r10000 64 mips4 {} \ + { -march=r10000 -mtune=r10000 } { -mmips:10000 } mips_arch_create vr5400 64 mips4 { ror } \ { -march=vr5400 -mtune=vr5400 } { -mmips:5400 } mips_arch_create interaptiv-mr2 32 mips32r3 {} \ diff --git a/gas/testsuite/gas/mips/r10000@c0.d b/gas/testsuite/gas/mips/r10000@c0.d new file mode 100644 index 0000000..7771a42 --- /dev/null +++ b/gas/testsuite/gas/mips/r10000@c0.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS C0/COP0 instructions +#as: -32 +#source: c0.s +#dump: mips3@c0.d diff --git a/gas/testsuite/gas/mips/r10000@c1.d b/gas/testsuite/gas/mips/r10000@c1.d new file mode 100644 index 0000000..e445db9 --- /dev/null +++ b/gas/testsuite/gas/mips/r10000@c1.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS C1/COP1 instructions +#as: -32 +#source: c1.s +#dump: mips4@c1.d diff --git a/gas/testsuite/gas/mips/r10000@cp0c.d b/gas/testsuite/gas/mips/r10000@cp0c.d new file mode 100644 index 0000000..cf8dc94 --- /dev/null +++ b/gas/testsuite/gas/mips/r10000@cp0c.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP0 control register move instructions +#as: -32 +#source: cp0c.s +#dump: mips1@cp0c.d diff --git a/gas/testsuite/gas/mips/r10000@save-sub.d b/gas/testsuite/gas/mips/r10000@save-sub.d new file mode 100644 index 0000000..047d323 --- /dev/null +++ b/gas/testsuite/gas/mips/r10000@save-sub.d @@ -0,0 +1,5 @@ +#objdump: -dr +#as: -32 -I$srcdir/$subdir +#name: SAVE/RESTORE instruction subset disassembly +#source: save-sub.s +#dump: mips1@save-sub.d |