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| author | Nick Clifton <nickc@redhat.com> | 2001-05-23 17:26:40 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2001-05-23 17:26:40 +0000 |
| commit | d1cf510e5e1ab5cb49de51ae96ef011ec0ab7510 (patch) | |
| tree | 9189d3cd2efd6281a0ee083401bc11fa84863dbb /gas | |
| parent | 6c426cf36e042f2ef86fdb7d6c7e5e6a7ddb0e1c (diff) | |
| download | gdb-d1cf510e5e1ab5cb49de51ae96ef011ec0ab7510.zip gdb-d1cf510e5e1ab5cb49de51ae96ef011ec0ab7510.tar.gz gdb-d1cf510e5e1ab5cb49de51ae96ef011ec0ab7510.tar.bz2 | |
Add MIPS r12k support
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 9 |
2 files changed, 15 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index d412c44..07cb17a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * config/tc-mips.c (ISA_HAS_64BIT_REGS): Add ISA_MIPS64 as 64 bit + architecture, remove erraneous ISA_MIPS32. + (md_show_usage): Add MIPS r12k support. + (mips_cpu_info_table): Add MIPS r12k support. + 2001-05-22 Alan Modra <amodra@one.net.au> * config/tc-arc.c (md_assemble): Use is_end_of_line instead of diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 0e1ad87..15c4f87 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -241,7 +241,7 @@ static int mips_gp32 = 0; (ISA) == ISA_MIPS3 \ || (ISA) == ISA_MIPS4 \ || (ISA) == ISA_MIPS5 \ - || (ISA) == ISA_MIPS32 \ + || (ISA) == ISA_MIPS64 \ ) /* Whether the processor uses hardware interlocks to protect @@ -9273,6 +9273,7 @@ MIPS options:\n\ show (stream, "6000", &column, &first); show (stream, "8000", &column, &first); show (stream, "10000", &column, &first); + show (stream, "12000", &column, &first); show (stream, "mips32-4k", &column, &first); show (stream, "sb-1", &column, &first); fputc ('\n', stream); @@ -12038,6 +12039,12 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "10k", 0, ISA_MIPS4, CPU_R10000, }, { "r10k", 0, ISA_MIPS4, CPU_R10000, }, + /* R12000 CPU */ + { "R12000", 0, ISA_MIPS4, CPU_R12000, }, + { "12000", 0, ISA_MIPS4, CPU_R12000, }, + { "12k", 0, ISA_MIPS4, CPU_R12000, }, + { "r12k", 0, ISA_MIPS4, CPU_R12000, }, + /* VR4100 CPU */ { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, { "4100", 0, ISA_MIPS3, CPU_VR4100, }, |