Add support for V850E3V5 architecture

5 files changed, 493 insertions, 137 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5aa4438..e89e8b4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-v850.c: Add support for e3v5 architecture.
+	* doc/c-v850.texi: Mention new support.
+
 2013-01-23  Nick Clifton  <nickc@redhat.com>
 
 	PR gas/15039
diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index ad1fb30..276756a 100644
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -1,6 +1,5 @@
 /* tc-v850.c -- Assembler code for the NEC V850
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
-   2006, 2007, 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+   Copyright 1996-2013 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -127,6 +126,10 @@ const relax_typeS md_relax_table[] =
   {0xfffe, -0x10000,	4, SUBYPTE_SA_9_17_22_32 + 2},
   {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
   {0x7ffffffe, -0x80000000, 10, 0},
+  /* Loop.  (V850E2V4_UP, max 22-bit).  */
+#define SUBYPTE_LOOP_16_22	29
+  {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1},
+  {0x1ffffe + 2, -0x200000 + 2, 6, 0},
 };
 
 static int v850_relax = 0;
@@ -528,6 +531,7 @@ set_machine (int number)
     case bfd_mach_v850e1:  SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);   break;
     case bfd_mach_v850e2:  SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);  break;
     case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
+    case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break;
     }
 }
 
@@ -588,6 +592,8 @@ const pseudo_typeS md_pseudo_table[] =
   { "v850e1",		set_machine,		bfd_mach_v850e1         },
   { "v850e2",		set_machine,		bfd_mach_v850e2 	},
   { "v850e2v3",		set_machine,		bfd_mach_v850e2v3 	},
+  { "v850e2v4",		set_machine,		bfd_mach_v850e3v5 	},
+  { "v850e3v5",		set_machine,		bfd_mach_v850e3v5 	},
   { "longcall",		v850_longcode,		1			},
   { "longjump",		v850_longcode,		2			},
   { NULL,		NULL,			0			}
@@ -651,97 +657,97 @@ static const struct reg_name system_registers[] =
   { "bpc",         22, PROCESSOR_NOT_V850 },
   { "bpdm",        27, PROCESSOR_NOT_V850 },
   { "bpdv",        26, PROCESSOR_NOT_V850 },
-  { "bsel",        31, PROCESSOR_V850E2_ALL },
-  { "cfg",          7, PROCESSOR_V850E2V3 },
+  { "bsel",        31, PROCESSOR_V850E2_UP },
+  { "cfg",          7, PROCESSOR_V850E2V3_UP },
   { "ctbp",        20, PROCESSOR_NOT_V850 },
   { "ctpc",        16, PROCESSOR_NOT_V850 },
   { "ctpsw",       17, PROCESSOR_NOT_V850 },
-  { "dbic",        15, PROCESSOR_V850E2_ALL },
+  { "dbic",        15, PROCESSOR_V850E2_UP },
   { "dbpc",        18, PROCESSOR_NOT_V850 },
   { "dbpsw",       19, PROCESSOR_NOT_V850 },
-  { "dbwr",        30, PROCESSOR_V850E2_ALL },
+  { "dbwr",        30, PROCESSOR_V850E2_UP },
   { "dir",         21, PROCESSOR_NOT_V850 },
-  { "dpa0l",       16, PROCESSOR_V850E2V3 },
-  { "dpa0u",       17, PROCESSOR_V850E2V3 },
-  { "dpa1l",       18, PROCESSOR_V850E2V3 },
-  { "dpa1u",       19, PROCESSOR_V850E2V3 },
-  { "dpa2l",       20, PROCESSOR_V850E2V3 },
-  { "dpa2u",       21, PROCESSOR_V850E2V3 },
-  { "dpa3l",       22, PROCESSOR_V850E2V3 },
-  { "dpa3u",       23, PROCESSOR_V850E2V3 },
-  { "dpa4l",       24, PROCESSOR_V850E2V3 },
-  { "dpa4u",       25, PROCESSOR_V850E2V3 },
-  { "dpa5l",       26, PROCESSOR_V850E2V3 },
-  { "dpa5u",       27, PROCESSOR_V850E2V3 },
+  { "dpa0l",       16, PROCESSOR_V850E2V3_UP },
+  { "dpa0u",       17, PROCESSOR_V850E2V3_UP },
+  { "dpa1l",       18, PROCESSOR_V850E2V3_UP },
+  { "dpa1u",       19, PROCESSOR_V850E2V3_UP },
+  { "dpa2l",       20, PROCESSOR_V850E2V3_UP },
+  { "dpa2u",       21, PROCESSOR_V850E2V3_UP },
+  { "dpa3l",       22, PROCESSOR_V850E2V3_UP },
+  { "dpa3u",       23, PROCESSOR_V850E2V3_UP },
+  { "dpa4l",       24, PROCESSOR_V850E2V3_UP },
+  { "dpa4u",       25, PROCESSOR_V850E2V3_UP },
+  { "dpa5l",       26, PROCESSOR_V850E2V3_UP },
+  { "dpa5u",       27, PROCESSOR_V850E2V3_UP },
   { "ecr",          4, PROCESSOR_ALL },
-  { "eh_base",      3, PROCESSOR_V850E2V3 },
-  { "eh_cfg",       1, PROCESSOR_V850E2V3 },
-  { "eh_reset",     2, PROCESSOR_V850E2V3 },
-  { "eiic",        13, PROCESSOR_V850E2_ALL },
+  { "eh_base",      3, PROCESSOR_V850E2V3_UP },
+  { "eh_cfg",       1, PROCESSOR_V850E2V3_UP },
+  { "eh_reset",     2, PROCESSOR_V850E2V3_UP },
+  { "eiic",        13, PROCESSOR_V850E2_UP },
   { "eipc",         0, PROCESSOR_ALL },
   { "eipsw",        1, PROCESSOR_ALL },
-  { "eiwr",        28, PROCESSOR_V850E2_ALL },
-  { "feic",        14, PROCESSOR_V850E2_ALL },
+  { "eiwr",        28, PROCESSOR_V850E2_UP },
+  { "feic",        14, PROCESSOR_V850E2_UP },
   { "fepc",         2, PROCESSOR_ALL },
   { "fepsw",        3, PROCESSOR_ALL },
-  { "fewr",        29, PROCESSOR_V850E2_ALL },
-  { "fpcc",         9, PROCESSOR_V850E2V3 },
-  { "fpcfg",       10, PROCESSOR_V850E2V3 },
-  { "fpec",        11, PROCESSOR_V850E2V3 },
-  { "fpepc",        7, PROCESSOR_V850E2V3 },
-  { "fpspc",       27, PROCESSOR_V850E2V3 },
-  { "fpsr",         6, PROCESSOR_V850E2V3 },
-  { "fpst",         8, PROCESSOR_V850E2V3 },
-  { "ipa0l",        6, PROCESSOR_V850E2V3 },
-  { "ipa0u",        7, PROCESSOR_V850E2V3 },
-  { "ipa1l",        8, PROCESSOR_V850E2V3 },
-  { "ipa1u",        9, PROCESSOR_V850E2V3 },
-  { "ipa2l",       10, PROCESSOR_V850E2V3 },
-  { "ipa2u",       11, PROCESSOR_V850E2V3 },
-  { "ipa3l",       12, PROCESSOR_V850E2V3 },
-  { "ipa3u",       13, PROCESSOR_V850E2V3 },
-  { "ipa4l",       14, PROCESSOR_V850E2V3 },
-  { "ipa4u",       15, PROCESSOR_V850E2V3 },
-  { "mca",         24, PROCESSOR_V850E2V3 },
-  { "mcc",         26, PROCESSOR_V850E2V3 },
-  { "mcr",         27, PROCESSOR_V850E2V3 },
-  { "mcs",         25, PROCESSOR_V850E2V3 },
-  { "mpc",          1, PROCESSOR_V850E2V3 },
-  { "mpm",          0, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3 },
-  { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa0l",  6, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa0u",  7, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa1l",  8, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa1u",  9, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3 },
-  { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3 },
-  { "mpu10_mpc",    1, PROCESSOR_V850E2V3 },
-  { "mpu10_mpm",    0, PROCESSOR_V850E2V3 },
-  { "mpu10_tid",    2, PROCESSOR_V850E2V3 },
-  { "mpu10_vmadr",  5, PROCESSOR_V850E2V3 },
-  { "mpu10_vmecr",  3, PROCESSOR_V850E2V3 },
-  { "mpu10_vmtid",  4, PROCESSOR_V850E2V3 },
-  { "pid",          6, PROCESSOR_V850E2V3 },
-  { "pmcr0",        4, PROCESSOR_V850E2V3 },
-  { "pmis2",       14, PROCESSOR_V850E2V3 },
+  { "fewr",        29, PROCESSOR_V850E2_UP },
+  { "fpcc",         9, PROCESSOR_V850E2V3_UP },
+  { "fpcfg",       10, PROCESSOR_V850E2V3_UP },
+  { "fpec",        11, PROCESSOR_V850E2V3_UP },
+  { "fpepc",        7, PROCESSOR_V850E2V3_UP },
+  { "fpspc",       27, PROCESSOR_V850E2V3_UP },
+  { "fpsr",         6, PROCESSOR_V850E2V3_UP },
+  { "fpst",         8, PROCESSOR_V850E2V3_UP },
+  { "ipa0l",        6, PROCESSOR_V850E2V3_UP },
+  { "ipa0u",        7, PROCESSOR_V850E2V3_UP },
+  { "ipa1l",        8, PROCESSOR_V850E2V3_UP },
+  { "ipa1u",        9, PROCESSOR_V850E2V3_UP },
+  { "ipa2l",       10, PROCESSOR_V850E2V3_UP },
+  { "ipa2u",       11, PROCESSOR_V850E2V3_UP },
+  { "ipa3l",       12, PROCESSOR_V850E2V3_UP },
+  { "ipa3u",       13, PROCESSOR_V850E2V3_UP },
+  { "ipa4l",       14, PROCESSOR_V850E2V3_UP },
+  { "ipa4u",       15, PROCESSOR_V850E2V3_UP },
+  { "mca",         24, PROCESSOR_V850E2V3_UP },
+  { "mcc",         26, PROCESSOR_V850E2V3_UP },
+  { "mcr",         27, PROCESSOR_V850E2V3_UP },
+  { "mcs",         25, PROCESSOR_V850E2V3_UP },
+  { "mpc",          1, PROCESSOR_V850E2V3_UP },
+  { "mpm",          0, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
+  { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa0l",  6, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa0u",  7, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa1l",  8, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa1u",  9, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
+  { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
+  { "mpu10_mpc",    1, PROCESSOR_V850E2V3_UP },
+  { "mpu10_mpm",    0, PROCESSOR_V850E2V3_UP },
+  { "mpu10_tid",    2, PROCESSOR_V850E2V3_UP },
+  { "mpu10_vmadr",  5, PROCESSOR_V850E2V3_UP },
+  { "mpu10_vmecr",  3, PROCESSOR_V850E2V3_UP },
+  { "mpu10_vmtid",  4, PROCESSOR_V850E2V3_UP },
+  { "pid",          6, PROCESSOR_V850E2V3_UP },
+  { "pmcr0",        4, PROCESSOR_V850E2V3_UP },
+  { "pmis2",       14, PROCESSOR_V850E2V3_UP },
   { "psw",          5, PROCESSOR_ALL },
-  { "scbp",        12, PROCESSOR_V850E2V3 },
-  { "sccfg",       11, PROCESSOR_V850E2V3 },
+  { "scbp",        12, PROCESSOR_V850E2V3_UP },
+  { "sccfg",       11, PROCESSOR_V850E2V3_UP },
   { "sr0",          0, PROCESSOR_ALL },
   { "sr1",          1, PROCESSOR_ALL },
   { "sr10",        10, PROCESSOR_ALL },
@@ -774,16 +780,16 @@ static const struct reg_name system_registers[] =
   { "sr7",          7, PROCESSOR_ALL },
   { "sr8",          8, PROCESSOR_ALL },
   { "sr9",          9, PROCESSOR_ALL },
-  { "sw_base",      3, PROCESSOR_V850E2V3 },
-  { "sw_cfg",       1, PROCESSOR_V850E2V3 },
-  { "sw_ctl",       0, PROCESSOR_V850E2V3 },
-  { "tid",          2, PROCESSOR_V850E2V3 },
-  { "vmadr",        6, PROCESSOR_V850E2V3 },
-  { "vmecr",        4, PROCESSOR_V850E2V3 },
-  { "vmtid",        5, PROCESSOR_V850E2V3 },
-  { "vsadr",        2, PROCESSOR_V850E2V3 },
-  { "vsecr",        0, PROCESSOR_V850E2V3 },
-  { "vstid",        1, PROCESSOR_V850E2V3 },
+  { "sw_base",      3, PROCESSOR_V850E2V3_UP },
+  { "sw_cfg",       1, PROCESSOR_V850E2V3_UP },
+  { "sw_ctl",       0, PROCESSOR_V850E2V3_UP },
+  { "tid",          2, PROCESSOR_V850E2V3_UP },
+  { "vmadr",        6, PROCESSOR_V850E2V3_UP },
+  { "vmecr",        4, PROCESSOR_V850E2V3_UP },
+  { "vmtid",        5, PROCESSOR_V850E2V3_UP },
+  { "vsadr",        2, PROCESSOR_V850E2V3_UP },
+  { "vsecr",        0, PROCESSOR_V850E2V3_UP },
+  { "vstid",        1, PROCESSOR_V850E2V3_UP },
 };
 
 #define SYSREG_NAME_CNT						\
@@ -822,43 +828,113 @@ static const struct reg_name cc_names[] =
 
 static const struct reg_name float_cc_names[] =
 {
-  { "eq",  0x2, PROCESSOR_V850E2V3 },	/* true.  */
-  { "f",   0x0, PROCESSOR_V850E2V3 },	/* true.  */
-  { "ge",  0xd, PROCESSOR_V850E2V3 },	/* false.  */
-  { "gl",  0xb, PROCESSOR_V850E2V3 },	/* false.  */
-  { "gle", 0x9, PROCESSOR_V850E2V3 },	/* false.  */
-  { "gt",  0xf, PROCESSOR_V850E2V3 },	/* false.  */
-  { "le",  0xe, PROCESSOR_V850E2V3 },	/* true.  */
-  { "lt",  0xc, PROCESSOR_V850E2V3 },	/* true.  */
-  { "neq", 0x2, PROCESSOR_V850E2V3 },	/* false.  */
-  { "nge", 0xd, PROCESSOR_V850E2V3 },	/* true.  */
-  { "ngl", 0xb, PROCESSOR_V850E2V3 },	/* true.  */
-  { "ngle",0x9, PROCESSOR_V850E2V3 },	/* true.  */
-  { "ngt", 0xf, PROCESSOR_V850E2V3 },	/* true.  */
-  { "nle", 0xe, PROCESSOR_V850E2V3 },	/* false.  */
-  { "nlt", 0xc, PROCESSOR_V850E2V3 },	/* false.  */
-  { "oge", 0x5, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ogl", 0x3, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ogt", 0x7, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ole", 0x6, PROCESSOR_V850E2V3 },	/* true.  */
-  { "olt", 0x4, PROCESSOR_V850E2V3 },	/* true.  */
-  { "or",  0x1, PROCESSOR_V850E2V3 },	/* false.  */
-  { "seq", 0xa, PROCESSOR_V850E2V3 },	/* true.  */
-  { "sf",  0x8, PROCESSOR_V850E2V3 },	/* true.  */
-  { "sne", 0xa, PROCESSOR_V850E2V3 },	/* false.  */
-  { "st",  0x8, PROCESSOR_V850E2V3 },	/* false.  */
-  { "t",   0x0, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ueq", 0x3, PROCESSOR_V850E2V3 },	/* true.  */
-  { "uge", 0x4, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ugt", 0x6, PROCESSOR_V850E2V3 },	/* false.  */
-  { "ule", 0x7, PROCESSOR_V850E2V3 },	/* true.  */
-  { "ult", 0x5, PROCESSOR_V850E2V3 },	/* true.  */
-  { "un",  0x1, PROCESSOR_V850E2V3 },	/* true.  */
+  { "eq",  0x2, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "f",   0x0, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "ge",  0xd, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "gl",  0xb, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "gle", 0x9, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "gt",  0xf, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "le",  0xe, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "lt",  0xc, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "neq", 0x2, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "nge", 0xd, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "ngl", 0xb, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "ngle",0x9, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "ngt", 0xf, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "nle", 0xe, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "nlt", 0xc, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "oge", 0x5, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ogl", 0x3, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ogt", 0x7, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ole", 0x6, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "olt", 0x4, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "or",  0x1, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "seq", 0xa, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "sf",  0x8, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "sne", 0xa, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "st",  0x8, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "t",   0x0, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ueq", 0x3, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "uge", 0x4, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ugt", 0x6, PROCESSOR_V850E2V3_UP },	/* false.  */
+  { "ule", 0x7, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "ult", 0x5, PROCESSOR_V850E2V3_UP },	/* true.  */
+  { "un",  0x1, PROCESSOR_V850E2V3_UP },	/* true.  */
 };
 
 #define FLOAT_CC_NAME_CNT					\
   (sizeof (float_cc_names) / sizeof (struct reg_name))
 
+
+static const struct reg_name cacheop_names[] =
+{
+  { "cfald",   0x44, PROCESSOR_V850E3V5_UP },
+  { "cfali",   0x40, PROCESSOR_V850E3V5_UP },
+  { "chbid",   0x04, PROCESSOR_V850E3V5_UP },
+  { "chbii",   0x00, PROCESSOR_V850E3V5_UP },
+  { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
+  { "chbwbd",  0x07, PROCESSOR_V850E3V5_UP },
+  { "cibid",   0x24, PROCESSOR_V850E3V5_UP },
+  { "cibii",   0x20, PROCESSOR_V850E3V5_UP },
+  { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
+  { "cibwbd",  0x27, PROCESSOR_V850E3V5_UP },
+  { "cildd",   0x65, PROCESSOR_V850E3V5_UP },
+  { "cildi",   0x61, PROCESSOR_V850E3V5_UP },
+  { "cistd",   0x64, PROCESSOR_V850E3V5_UP },
+  { "cisti",   0x60, PROCESSOR_V850E3V5_UP },
+};
+
+#define CACHEOP_NAME_CNT					\
+  (sizeof (cacheop_names) / sizeof (struct reg_name))
+
+static const struct reg_name prefop_names[] =
+{
+  { "prefd",   0x04, PROCESSOR_V850E3V5_UP },
+  { "prefi",   0x00, PROCESSOR_V850E3V5_UP },
+};
+
+#define PREFOP_NAME_CNT					\
+  (sizeof (prefop_names) / sizeof (struct reg_name))
+
+static const struct reg_name vector_registers[] =
+{
+  { "vr0",   0, PROCESSOR_V850E3V5_UP },
+  { "vr1",   1, PROCESSOR_V850E3V5_UP },
+  { "vr10", 10, PROCESSOR_V850E3V5_UP },
+  { "vr11", 11, PROCESSOR_V850E3V5_UP },
+  { "vr12", 12, PROCESSOR_V850E3V5_UP },
+  { "vr13", 13, PROCESSOR_V850E3V5_UP },
+  { "vr14", 14, PROCESSOR_V850E3V5_UP },
+  { "vr15", 15, PROCESSOR_V850E3V5_UP },
+  { "vr16", 16, PROCESSOR_V850E3V5_UP },
+  { "vr17", 17, PROCESSOR_V850E3V5_UP },
+  { "vr18", 18, PROCESSOR_V850E3V5_UP },
+  { "vr19", 19, PROCESSOR_V850E3V5_UP },
+  { "vr2",   2, PROCESSOR_V850E3V5_UP },
+  { "vr20", 20, PROCESSOR_V850E3V5_UP },
+  { "vr21", 21, PROCESSOR_V850E3V5_UP },
+  { "vr22", 22, PROCESSOR_V850E3V5_UP },
+  { "vr23", 23, PROCESSOR_V850E3V5_UP },
+  { "vr24", 24, PROCESSOR_V850E3V5_UP },
+  { "vr25", 25, PROCESSOR_V850E3V5_UP },
+  { "vr26", 26, PROCESSOR_V850E3V5_UP },
+  { "vr27", 27, PROCESSOR_V850E3V5_UP },
+  { "vr28", 28, PROCESSOR_V850E3V5_UP },
+  { "vr29", 29, PROCESSOR_V850E3V5_UP },
+  { "vr3",   3, PROCESSOR_V850E3V5_UP },
+  { "vr30", 30, PROCESSOR_V850E3V5_UP },
+  { "vr31", 31, PROCESSOR_V850E3V5_UP },
+  { "vr4",   4, PROCESSOR_V850E3V5_UP },
+  { "vr5",   5, PROCESSOR_V850E3V5_UP },
+  { "vr6",   6, PROCESSOR_V850E3V5_UP },
+  { "vr7",   7, PROCESSOR_V850E3V5_UP },
+  { "vr8",   8, PROCESSOR_V850E3V5_UP },
+  { "vr9",   9, PROCESSOR_V850E3V5_UP },
+};
+
+#define VREG_NAME_CNT						\
+  (sizeof (vector_registers) / sizeof (struct reg_name))
+
 /* Do a binary search of the given register table to see if NAME is a
    valid regiter name.  Return the register number from the array on
    success, or -1 on failure.  */
@@ -1134,6 +1210,143 @@ float_cc_name (expressionS *expressionP,
   return FALSE;
 }
 
+static bfd_boolean
+cacheop_name (expressionS * expressionP,
+	      bfd_boolean accept_numbers)
+{
+  int reg_number;
+  char *name;
+  char *start;
+  char c;
+
+  /* Find the spelling of the operand.  */
+  start = name = input_line_pointer;
+
+  c = get_symbol_end ();
+  reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers);
+
+  /* Put back the delimiting char.  */
+  *input_line_pointer = c;
+
+  if (reg_number < 0
+      && accept_numbers)
+    {
+      /* Reset input_line pointer.  */
+      input_line_pointer = start;
+
+      if (ISDIGIT (*input_line_pointer))
+	reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
+    }
+
+  expressionP->X_add_symbol = NULL;
+  expressionP->X_op_symbol  = NULL;
+
+  /* Look to see if it's in the register table.  */
+  if (reg_number >= 0)
+    {
+      expressionP->X_op		= O_constant;
+      expressionP->X_add_number = reg_number;
+
+      return TRUE;
+    }
+
+  /* Reset the line as if we had not done anything.  */
+  input_line_pointer = start;
+
+  expressionP->X_op = O_illegal;
+  expressionP->X_add_number = 0;
+
+  return FALSE;
+}
+
+static bfd_boolean
+prefop_name (expressionS * expressionP,
+	     bfd_boolean accept_numbers)
+{
+  int reg_number;
+  char *name;
+  char *start;
+  char c;
+
+  /* Find the spelling of the operand.  */
+  start = name = input_line_pointer;
+
+  c = get_symbol_end ();
+  reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers);
+
+  /* Put back the delimiting char.  */
+  *input_line_pointer = c;
+
+  if (reg_number < 0
+      && accept_numbers)
+    {
+      /* Reset input_line pointer.  */
+      input_line_pointer = start;
+
+      if (ISDIGIT (*input_line_pointer))
+	reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
+    }
+
+  expressionP->X_add_symbol = NULL;
+  expressionP->X_op_symbol  = NULL;
+
+  /* Look to see if it's in the register table.  */
+  if (reg_number >= 0)
+    {
+      expressionP->X_op		= O_constant;
+      expressionP->X_add_number = reg_number;
+
+      return TRUE;
+    }
+
+  /* Reset the line as if we had not done anything.  */
+  input_line_pointer = start;
+
+  expressionP->X_op = O_illegal;
+  expressionP->X_add_number = 0;
+
+  return FALSE;
+}
+
+static bfd_boolean
+vector_register_name (expressionS *expressionP)
+{
+  int reg_number;
+  char *name;
+  char *start;
+  char c;
+
+  /* Find the spelling of the operand.  */
+  start = name = input_line_pointer;
+
+  c = get_symbol_end ();
+
+  reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
+				name, FALSE);
+
+  /* Put back the delimiting char.  */
+  *input_line_pointer = c;
+
+  expressionP->X_add_symbol = NULL;
+  expressionP->X_op_symbol  = NULL;
+
+  /* Look to see if it's in the register table.  */
+  if (reg_number >= 0)
+    {
+      expressionP->X_op		= O_register;
+      expressionP->X_add_number = reg_number;
+
+      return TRUE;
+    }
+
+  /* Reset the line as if we had not done anything.  */
+  input_line_pointer = start;
+
+  expressionP->X_op = O_illegal;
+
+  return FALSE;
+}
+
 static void
 skip_white_space (void)
 {
@@ -1338,6 +1551,8 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("  -mv850e1                  The code is targeted at the v850e1\n"));
   fprintf (stream, _("  -mv850e2                  The code is targeted at the v850e2\n"));
   fprintf (stream, _("  -mv850e2v3                The code is targeted at the v850e2v3\n"));
+  fprintf (stream, _("  -mv850e2v4                Alias for -mv850e3v5\n"));
+  fprintf (stream, _("  -mv850e3v5                The code is targeted at the v850e3v5\n"));
   fprintf (stream, _("  -mrelax                   Enable relaxation\n"));
   fprintf (stream, _("  --disp-size-default-22    branch displacement with unknown size is 22 bits (default)\n"));
   fprintf (stream, _("  --disp-size-default-32    branch displacement with unknown size is 32 bits\n"));
@@ -1399,6 +1614,16 @@ md_parse_option (int c, char *arg)
       machine = bfd_mach_v850e2v3;
       SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
     }
+  else if (strcmp (arg, "v850e2v4") == 0)
+    {
+      machine = bfd_mach_v850e3v5;
+      SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
+    }
+  else if (strcmp (arg, "v850e3v5") == 0)
+    {
+      machine = bfd_mach_v850e3v5;
+      SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
+    }
   else if (strcmp (arg, "extension") == 0)
     {
       processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
@@ -1464,8 +1689,31 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
 
   subseg_change (sec, 0);
 
+  if (fragP->fr_subtype == SUBYPTE_LOOP_16_22)
+    {
+      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+	       fragP->fr_offset, 1,
+	       BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
+      fragP->fr_fix += 4;
+    }
+  else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1)
+    {
+      unsigned char * buffer =
+	(unsigned char *) (fragP->fr_fix + fragP->fr_literal);
+      int loop_reg = (buffer[0] & 0x1f);
+
+      /* Add -1.reg.  */
+      md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2);
+      /* Now create the conditional branch + fixup to the final target.  */
+      /* 0x000107ea = bne LBL(disp17).  */
+      md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4);
+      fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol,
+	       fragP->fr_offset, 1,
+	       BFD_RELOC_V850_17_PCREL);
+      fragP->fr_fix += 6;
+    }
   /* In range conditional or unconditional branch.  */
-  if (fragP->fr_subtype == SUBYPTE_COND_9_22
+  else if (fragP->fr_subtype == SUBYPTE_COND_9_22
       || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
       || fragP->fr_subtype == SUBYPTE_COND_9_22_32
       || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
@@ -1634,7 +1882,23 @@ md_begin (void)
   char *prev_name = "";
   const struct v850_opcode *op;
 
-  if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
+  if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0)
+    {
+      if (machine == -1)
+	machine = bfd_mach_v850e3v5;
+
+      if (!processor_mask)
+	SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
+    }
+  else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0)
+    {
+      if (machine == -1)
+	machine = bfd_mach_v850e3v5;
+
+      if (!processor_mask)
+	SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
+    }
+  else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
     {
       if (machine == -1)
         machine = bfd_mach_v850e2v3;
@@ -2129,6 +2393,12 @@ md_assemble (char *str)
 	  while (*str == ' ')
 	    ++str;
 
+	  if (   (strcmp (opcode->name, "pushsp") == 0
+	       || strcmp (opcode->name, "popsp") == 0
+	       || strcmp (opcode->name, "dbpush") == 0)
+	      && (*str == '-'))
+	    ++str;
+
 	  if (operand->flags & V850_OPERAND_RELAX)
 	    relaxable = 1;
 
@@ -2206,8 +2476,7 @@ md_assemble (char *str)
 		      break;
 
 		    default:
-		      fprintf (stderr, "reloc: %d\n", reloc);
-		      as_bad (_("AAARG -> unhandled constant reloc"));
+		      as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc);
 		      break;
 		    }
 
@@ -2350,8 +2619,8 @@ md_assemble (char *str)
 		    }
 		  if (operand->flags & V850E_IMMEDIATE16)
 		    {
-		      if ((ex.X_add_number & 0xffff0000)
-			  && ((ex.X_add_number & 0xffff0000) != 0xffff0000))
+		      if ((ex.X_add_number & 0xffff8000)
+			  && ((ex.X_add_number & 0xffff8000) != 0xffff8000))
 			{
 			  errmsg = _("constant too big to fit into instruction");
 			  goto error;
@@ -2540,6 +2809,21 @@ md_assemble (char *str)
 		      errmsg = _("invalid condition code name");
 		    }
 		}
+	      else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
+		{
+		  if (!cacheop_name (&ex, TRUE))
+		    errmsg = _("invalid cache oparation name");
+		}
+	      else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
+		{
+		  if (!prefop_name (&ex, TRUE))
+		    errmsg = _("invalid pref oparation name");
+		}
+	      else if ((operand->flags & V850_OPERAND_VREG) != 0)
+		{
+		  if (!vector_register_name (&ex))
+		    errmsg = _("invalid vector register name");
+		}
 	      else if ((register_name (&ex)
 			&& (operand->flags & V850_OPERAND_REG) == 0))
 		{
@@ -2603,6 +2887,11 @@ md_assemble (char *str)
 		{
 		  errmsg = _("syntax error: condition code not expected");
 		}
+	      else if (vector_register_name (&ex)
+		       && (operand->flags & V850_OPERAND_VREG) == 0)
+		{
+		  errmsg = _("syntax error: vector register not expected");
+		}
 	      else
 		{
 		  expression (&ex);
@@ -2637,6 +2926,18 @@ md_assemble (char *str)
 		    {
 		      errmsg = _("immediate operand is not match");
 		    }
+
+                  /* Special case2 :
+                     If we are assembling a ld/st instruction and the immediate
+                     value does not fit into the bits available then create a
+                     fake error so that the next ld/st instruction will be
+                     selected.  */
+                  if ( (  (strncmp (opcode->name, "st.", 3) == 0)
+		       || (strncmp (opcode->name, "ld.", 3) == 0))
+                      && ex.X_op == O_constant
+                      && (ex.X_add_number < (-(1 << (operand->bits - 1)))
+			  || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
+		    errmsg = _("displacement is too large");
 		}
 
 	      if (errmsg)
@@ -2753,10 +3054,27 @@ md_assemble (char *str)
       insn_size = 2;
       fc = 0;
 
-      if (strcmp (opcode->name, "br") == 0
-	  || strcmp (opcode->name, "jbr") == 0)
+      if (strcmp (opcode->name, "loop") == 0)
+	{
+	  if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
+	    {
+	      insn_size = 4;
+	      f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22,
+			    fixups[0].exp.X_add_symbol,
+			    fixups[0].exp.X_add_number,
+			    (char *)(size_t) fixups[0].opindex);
+	      md_number_to_chars (f, insn, insn_size);
+	      md_number_to_chars (f+4, 0, 4);
+	    }
+	  else
+	    {
+	      as_bad (_("loop: 32-bit displacement not supported"));
+	    }
+	}
+      else if (strcmp (opcode->name, "br") == 0
+	       || strcmp (opcode->name, "jbr") == 0)
 	{
-	  if ((processor_mask & PROCESSOR_V850E2_ALL) == 0 || default_disp_size == 22)
+	  if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
 	    {
 	      f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
 			    fixups[0].exp.X_add_symbol,
@@ -2778,9 +3096,9 @@ md_assemble (char *str)
       else /* b<cond>, j<cond>.  */
 	{
 	  if (default_disp_size == 22
-	      || (processor_mask & PROCESSOR_V850E2_ALL) == 0)
+	      || (processor_mask & PROCESSOR_V850E2_UP) == 0)
 	    {
-	      if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
+	      if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
 		{
 		  if (strcmp (opcode->name, "bsa") == 0)
 		    {
@@ -2825,7 +3143,7 @@ md_assemble (char *str)
 	    }
 	  else
 	    {
-	      if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
+	      if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
 		{
 		  if (strcmp (opcode->name, "bsa") == 0)
 		    {
@@ -2888,6 +3206,12 @@ md_assemble (char *str)
 	  || (insn & 0x1ffff) == 0x2e0)	/* JR.  */
 	insn_size = 2;
 
+      if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len))
+	{
+          frag_wane (frag_now);
+          frag_new (0);
+	}
+
       f = frag_more (insn_size);
       md_number_to_chars (f, insn, insn_size);
 
@@ -2975,6 +3299,7 @@ md_assemble (char *str)
 	}
       else
 	{
+	  gas_assert (f != NULL);
 	  fix_new_exp (frag_now,
 		       f - frag_now->fr_literal, 4,
 		       & fixups[i].exp,
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 3752606..2516a83 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -1,4 +1,4 @@
-@c Copyright 1997, 2002, 2003, 2006, 2011, 2012 Free Software Foundation, Inc.
+@c Copyright 1997-2013 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -80,6 +80,16 @@ Specifies that the assembled code should be marked as being targeted at
 the V850E2V3 processor.  This allows the linker to detect attempts to link
 such code with code assembled for other processors.
 
+@cindex @code{-mv850e2v4} command line option, V850
+@item -mv850e2v4
+This is an alias for @option{-mv850e3v5}.
+
+@cindex @code{-mv850e3v5} command line option, V850
+@item -mv850e3v5
+Specifies that the assembled code should be marked as being targeted at
+the V850E3V5 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
 @cindex @code{-mrelax} command line option, V850
 @item -mrelax
 Enables relaxation.  This allows the .longcall and .longjump pseudo
@@ -302,6 +312,18 @@ Specifies that the assembled code should be marked as being targeted at
 the V850E2V3 processor.  This allows the linker to detect attempts to link
 such code with code assembled for other processors.
 
+@cindex @code{.v850e2v4} directive, V850
+@item .v850e2v4
+Specifies that the assembled code should be marked as being targeted at
+the V850E3V5 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{.v850e3v5} directive, V850
+@item .v850e3v5
+Specifies that the assembled code should be marked as being targeted at
+the V850E3V5 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
 @end table
 
 @node V850 Opcodes
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 73c96e9..2545ce1 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* gas/elf/warn-2.s: Skip for all V850 variants.
+
 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* gas/aarch64/diagnostic.l: Update.
diff --git a/gas/testsuite/gas/elf/warn-2.s b/gas/testsuite/gas/elf/warn-2.s
index 7783f9d..6f4454f 100644
--- a/gas/testsuite/gas/elf/warn-2.s
+++ b/gas/testsuite/gas/elf/warn-2.s
@@ -20,4 +20,4 @@
  .endif
  .endif
 
-;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* openrisc-*-* or32-*-* v850-*-* } 0 }
+;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* openrisc-*-* or32-*-* v850*-*-* } 0 }