MIPS: Fix microMIPS instruction size determination

Fix a bug in `micromips_insn_at_pc_has_delay_slot' in instruction size
determination via `mips_insn_size'.  In the microMIPS case the latter
function expects a lone 16-bit instruction word containing the major
opcode regardless of whether the opcode requires another 16-bit word to
follow, to form a complete 32-bit instruction.  Code however passes the
16-bit word previously retrieved shifted left by 16 bits.  Consequently
`mips_insn_size', which examines the low 16-bit only, always sees 0.

By pure coincidence a major opcode of 0 denotes a 32-bit instruction in
the microMIPS instruction set, so the size of 4 is always returned here,
and the following 16-bit word is then merged in the low 16 bits of the
instruction previously shifted by 16 bits.  The resulting 32-bit value
is then passed to `micromips_instruction_has_delay_slot' for delay slot
presence determination.  This function in turn first examines the high
16 bits of the instruction word received and ignores the low 16 bits for
16-bit instructions.

Consequently the only effect of this bug is an extraneous memory read
issued to retrieve a subsequent 16-bit word where a 16-bit instruction
is being examined.  Which in turn may fail if the instruction is located
right at the end of a readable memory area, in which case the lack of a
delay slot will be reported to the caller, which may be incorrect.

This code is used in breakpoint maintenance, for delay slot avoidance,
so the bug would only trigger for the unlikely case of someone placing
a breakpoint in a delay slot of an instruction which is at the end of
readable memory.  Which explains why the bug remained unnoticed so long.

	gdb/
	* mips-tdep.c (micromips_insn_at_pc_has_delay_slot): Pass
	unshifted 16-bit microMIPS instruction word to `mips_insn_size'.

0 files changed, 0 insertions, 0 deletions