bfd:

	Add ms2.
	* archures.c (bfd_mach_ms2): Define.
	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
	correct merging logic, with workaround.
	(ms1_elf_print_private_bfd_data): Add ms2 case.
	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.

cpu:
	Add ms2
	* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
	model.
	(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
	f-cb2incr, f-rc3): New fields.
	(LOOP): New instruction.
	(JAL-HAZARD): New hazard.
	(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
	New operands.
	(mul, muli, dbnz, iflush): Enable for ms2
	(jal, reti): Has JAL-HAZARD.
	(ldctxt, ldfb, stfb): Only ms1.
	(fbcb): Only ms1,ms1-003.
	(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
	fbcbincrs, mfbcbincrs): Enable for ms2.
	(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
	* ms1.opc (parse_loopsize): New.
	(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
	(print_pcrel): New.

gas:
	Add ms2.
	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
	(ms1_architectures): Add ms2.
	(md_parse_option): Add ms2.
	(md_show_usage): Add ms2.
	(md_assemble): Add JAL_HAZARD detection logic.
	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
	* doc/c-ms1.texi: New.
	* doc/all.texi: Add MS1.
	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
	* doc/Makefile.in: Rebuilt.
	* doc/Makefile: Rebuilt.

gas/testsuite:
	Add ms2.
	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
	* gas/ms1/errors.exp: Fix target triplet.
	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
	* gas/ms1/ms1-16-003.s: Tweak label.
	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
	disassembly.
	* gas/ms1/relocs.exp: Adjust target triplet.

include:
	Add ms2.
	* elf/ms1.h (EF_MS1_CPU_MS2): New.


opcodes:
	Add ms2.
	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
	ms1-opc.c, ms1-opc.h: Regenerated.

16 files changed, 161 insertions, 19 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4556e03..cfbd519 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2 support.
+	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
+	(ms1_architectures): Add ms2.
+	(md_parse_option): Add ms2.
+	(md_show_usage): Add ms2.
+	(md_assemble): Add JAL_HAZARD detection logic.
+	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
+	* doc/c-ms1.texi: New.
+	* doc/all.texi: Add MS1.
+	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
+	* doc/Makefile.in: Rebuilt.
+	* doc/Makefile: Rebuilt.
+
 2005-11-07  Steve Ellcey  <sje@cup.hp.com>
 
 	* configure: Regenerate after modifying bfd/warning.m4.
diff --git a/gas/config/tc-ms1.c b/gas/config/tc-ms1.c
index e459bc8..7e2e685 100644
--- a/gas/config/tc-ms1.c
+++ b/gas/config/tc-ms1.c
@@ -84,7 +84,7 @@ const char * md_shortopts = "";
 
 /* Mach selected from command line.  */
 static int ms1_mach = bfd_mach_ms1;
-static unsigned ms1_mach_bitmask = 0;
+static unsigned ms1_mach_bitmask = 1 << MACH_MS1;
 
 /* Flags to set in the elf header */
 static flagword ms1_flags = EF_MS1_CPU_MRISC;
@@ -94,7 +94,8 @@ enum ms1_architectures
   {
     ms1_64_001,
     ms1_16_002,
-    ms1_16_003
+    ms1_16_003,
+    ms2
   };
 
 /* MS1 architecture we are using for this output file.  */
@@ -127,6 +128,13 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
  	  ms1_mach_bitmask = 1 << MACH_MS1_003;
  	  ms1_arch = ms1_16_003;
  	}
+      else if (strcasecmp (arg, "MS2") == 0)
+ 	{
+ 	  ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2;
+ 	  ms1_mach = bfd_mach_mrisc2;
+ 	  ms1_mach_bitmask = 1 << MACH_MS2;
+ 	  ms1_arch = ms2;
+ 	}
     case OPTION_NO_SCHED_REST:
       no_scheduling_restrictions = 1;
       break;
@@ -145,6 +153,7 @@ md_show_usage (FILE * stream)
   fprintf (stream, _("  -march=ms1-64-001         allow ms1-64-001 instructions (default) \n"));
   fprintf (stream, _("  -march=ms1-16-002         allow ms1-16-002 instructions \n"));
   fprintf (stream, _("  -march=ms1-16-003         allow ms1-16-003 instructions \n"));
+  fprintf (stream, _("  -march=ms2                allow ms2 instructions \n"));
   fprintf (stream, _("  -nosched                  disable scheduling restrictions \n"));
 }
 
@@ -176,6 +185,7 @@ void
 md_assemble (char * str)
 {
   static long delayed_load_register = 0;
+  static long prev_delayed_load_register = 0;
   static int last_insn_had_delay_slot = 0;
   static int last_insn_in_noncond_delay_slot = 0;
   static int last_insn_has_load_delay = 0;
@@ -241,6 +251,24 @@ md_assemble (char * str)
 		     insn.fields.f_sr2);
 	}
 
+      /* Detect JAL/RETI hazard */
+      if (ms1_mach == ms2
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
+	{
+	  if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	       && insn.fields.f_sr1 == delayed_load_register)
+	      || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		  && insn.fields.f_sr2 == delayed_load_register))
+	    as_warn (_("operand references R%ld of previous instrutcion."),
+		     delayed_load_register);
+	  else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+		    && insn.fields.f_sr1 == prev_delayed_load_register)
+		   || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		       && insn.fields.f_sr2 == prev_delayed_load_register))
+	    as_warn (_("operand references R%ld of instructcion before previous."),
+		     prev_delayed_load_register);
+	}
+      
       /* Detect data dependency between conditional branch instruction
          and an immediately preceding arithmetic or logical instruction.  */
       if (last_insn_was_arithmetic_or_logic
@@ -287,6 +315,8 @@ md_assemble (char * str)
   CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
     && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
   
+  prev_delayed_load_register = delayed_load_register;
+  
   if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
      delayed_load_register = insn.fields.f_dr; 
   else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
@@ -381,6 +411,12 @@ md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
         result = fixP->fx_cgen.opinfo;
       fixP->fx_no_overflow = 1;
       break;
+    case MS1_OPERAND_LOOPSIZE:
+      result = BFD_RELOC_MS1_PCINSN8;
+      fixP->fx_pcrel = 1;
+      /* Adjust for the delay slot, which is not part of the loop  */
+      fixP->fx_offset -= 8;
+      break;
     default:
       result = BFD_RELOC_NONE;
       break;
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 14770d5..a2785d4 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -42,6 +42,7 @@ CPU_DOCS = \
 	c-m68k.texi \
 	c-mips.texi \
 	c-mmix.texi \
+	c-ms1.texi \
 	c-msp430.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index d8d4419..0fae527 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -234,6 +234,7 @@ CPU_DOCS = \
 	c-m68k.texi \
 	c-mips.texi \
 	c-mmix.texi \
+	c-ms1.texi \
 	c-msp430.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index c10ec08..2476b2e 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -48,6 +48,7 @@
 @set MCORE
 @set MIPS
 @set MMIX
+@set MS1
 @set MSP430
 @set PDP11
 @set PJ
diff --git a/gas/doc/c-ms1.texi b/gas/doc/c-ms1.texi
new file mode 100644
index 0000000..854d411
--- /dev/null
+++ b/gas/doc/c-ms1.texi
@@ -0,0 +1,44 @@
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node MS1-Dependent
+@chapter MS1 Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter MS1 Dependent Features
+@end ifclear
+
+@cindex MS1 support
+@menu
+* MS1 Options::              Options
+@end menu
+
+@node MS1 Options
+@section Options
+@cindex MS1 options (none)
+@cindex options for MS1 (none)
+
+@table @code
+
+@cindex @code{-march=} command line option, MS1
+@item -march=@var{processor}
+This option specifies the target processor.  The assembler will issue an
+error message if an attempt is made to assemble an instruction which
+will not execute on the target processor.  The following processor names are
+recognized: 
+@code{ms1-64-001},
+@code{ms1-16-002},
+@code{ms1-16-003},
+and @code{ms2}.
+
+@cindex @code{-nosched} command line option, MS1
+@item -nosched
+This option disables scheduling restriction checking.
+
+@end table
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d9a47c5..8bd4ffc 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2.
+	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
+	* gas/ms1/errors.exp: Fix target triplet.
+	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
+	* gas/ms1/ms1-16-003.s: Tweak label.
+	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
+	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
+	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
+	disassembly. 
+	* gas/ms1/relocs.exp: Adjust target triplet.
+
 2005-11-07  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/all/redef2.[sd]: New.
diff --git a/gas/testsuite/gas/ms1/allinsn.d b/gas/testsuite/gas/ms1/allinsn.d
index d992c58..03db93d 100644
--- a/gas/testsuite/gas/ms1/allinsn.d
+++ b/gas/testsuite/gas/ms1/allinsn.d
@@ -88,16 +88,16 @@ Disassembly of section .text:
   68:	25 00 00 00 	asri R0,R0,#\$0
 
 0000006c <brlt>:
-  6c:	31 00 00 00 	brlt R0,R0,\$0
+  6c:	31 00 00 00 	brlt R0,R0,6c <brlt>
 
 00000070 <brle>:
-  70:	33 00 00 00 	brle R0,R0,\$0
+  70:	33 00 00 00 	brle R0,R0,70 <brle>
 
 00000074 <breq>:
-  74:	35 00 00 00 	breq R0,R0,\$0
+  74:	35 00 00 00 	breq R0,R0,74 <breq>
 
 00000078 <jmp>:
-  78:	37 00 00 00 	jmp \$0
+  78:	37 00 00 00 	jmp 78 <jmp>
 
 0000007c <jal>:
   7c:	38 00 00 00 	jal R0,R0
@@ -121,7 +121,7 @@ Disassembly of section .text:
   94:	64 00 00 00 	si R0
 
 00000098 <brne>:
-  98:	3b 00 00 00 	brne R0,R0,\$0
+  98:	3b 00 00 00 	brne R0,R0,98 <brne>
 
 0000009c <break>:
   9c:	68 00 00 00 	break
diff --git a/gas/testsuite/gas/ms1/errors.exp b/gas/testsuite/gas/ms1/errors.exp
index 90a8976..dd47d43 100644
--- a/gas/testsuite/gas/ms1/errors.exp
+++ b/gas/testsuite/gas/ms1/errors.exp
@@ -27,7 +27,7 @@ proc mrisc1_error_test { file testname {warnpattern ""} } {
     }
 }
 
-if [istarget mrisc1*-*-*] {
+if [istarget ms1-*-*] {
     foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] {
 	set file [file tail $file]
 	switch -- $file {
diff --git a/gas/testsuite/gas/ms1/ms1-16-003.d b/gas/testsuite/gas/ms1/ms1-16-003.d
index 0233d85..f855696 100644
--- a/gas/testsuite/gas/ms1/ms1-16-003.d
+++ b/gas/testsuite/gas/ms1/ms1-16-003.d
@@ -12,8 +12,8 @@ Disassembly of section .text:
    4:	08 00 00 00 	mul R0,R0,R0
 00000008 <muli>:
    8:	09 00 00 00 	muli R0,R0,#\$0
-0000000c <dbnz>:
-   c:	3d 00 00 00 	dbnz R0,\$0
+0000000c <dbnz_>:
+   c:	3d 00 00 00 	dbnz R0,c <dbnz_>
 [ 	]*c: R_MS1_PC16	dbnz
 00000010 <fbcbincs>:
   10:	f0 00 00 00 	fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
diff --git a/gas/testsuite/gas/ms1/ms1-16-003.s b/gas/testsuite/gas/ms1/ms1-16-003.s
index ec1dd7b..516fff5 100644
--- a/gas/testsuite/gas/ms1/ms1-16-003.s
+++ b/gas/testsuite/gas/ms1/ms1-16-003.s
@@ -12,7 +12,7 @@ muli:
 	muli R0, R0, #0
 
 	.global dbnz
-dbnz:
+dbnz_:
 	dbnz	r0, dbnz
 
 	.global fbcbincs
diff --git a/gas/testsuite/gas/ms1/ms1.exp b/gas/testsuite/gas/ms1/ms1.exp
index 49aea81..1960f0d 100644
--- a/gas/testsuite/gas/ms1/ms1.exp
+++ b/gas/testsuite/gas/ms1/ms1.exp
@@ -1,10 +1,11 @@
 # MRISC1 assembler testsuite.
 
-if { [istarget mrisc1*-*-*] || [istarget ms1-*-*]} then {
+if [istarget ms1*-*-*] {
     #
     run_dump_test "allinsn"
     run_dump_test "misc"
     run_dump_test "msys"
     run_dump_test "ms1-16-003"
+    run_dump_test "ms2"
     #
 }
diff --git a/gas/testsuite/gas/ms1/ms2.d b/gas/testsuite/gas/ms1/ms2.d
new file mode 100644
index 0000000..8771052
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ms2.d
@@ -0,0 +1,18 @@
+#as: -march=ms2
+#objdump: -dr
+#name: ms2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <code>:
+   0:	3e 10 00 05 	loop R1,1c <label>
+   4:	3f 00 10 04 	loopi #\$10,1c <label>
+   8:	83 ff ff ff 	dfbc #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+   c:	87 ff ff 7f 	dwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$3f
+  10:	8b ff ff ff 	fbwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+  14:	8f f0 ff ff 	dfbr #\$7,#\$7,R0,#\$7,#\$7,#\$7,#\$1,#\$3f
+  18:	12 00 00 00 	nop
+0000001c <label>:
+  1c:	f0 00 00 00 	fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
diff --git a/gas/testsuite/gas/ms1/ms2.s b/gas/testsuite/gas/ms1/ms2.s
new file mode 100644
index 0000000..37efbf0
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ms2.s
@@ -0,0 +1,11 @@
+
+code:	
+	loop R1, label
+	loopi #16,label
+	dfbc #7,#7,#-1,#-1,#1,#1,#63
+	dwfb #7,#7,#-1,#-1,#1,#63
+	fbwfb #7,#7,#-1,#-1,#1,#1,#63
+	dfbr #7,#7,R0,#7,#7,#7,#1,#63
+	nop
+label:	 
+	fbcbincs  #0,#0,#0,#0,#0,#0,#0,#0,#0,#0
diff --git a/gas/testsuite/gas/ms1/relocs.d b/gas/testsuite/gas/ms1/relocs.d
index a9a66e9..2a752ba 100644
--- a/gas/testsuite/gas/ms1/relocs.d
+++ b/gas/testsuite/gas/ms1/relocs.d
@@ -1,8 +1,8 @@
 
-relocs.x:     file format elf32-mrisc1
+relocs.x:     file format elf32-(mrisc1|ms1)
 
 Contents of section .text:
- 2000 00131000 37000004 12000000 3700fff8  ....7.......7...
+ 2000 00131000 3700dffc 12000000 3700fff8  ....7.......7...
  2010 03210000 03212215 03210001 03210000  .!...!"..!...!..
  2020 0321ffff 0321eeee 03210005 03210006  .!...!...!...!..
  2030 00675000                             .gP.            
@@ -38,18 +38,19 @@ Contents of section .data:
  22f4 00000000 00000000 00000000 00000000  ................
  2304 00000000 00000000 00000000 00000000  ................
  2314 000003                               ...             
-Contents of section .sbss:
+Contents of section .stack:
+ 7ffff0 deaddead                             ....            
 Disassembly of section .text:
 
 00002000 <_start>:
     2000:	00 13 10 00 	add R1,R1,R3
 
 00002004 <local>:
-    2004:	37 00 00 04 	jmp \$4
+    2004:	37 00 df fc 	jmp 0 <_start-0x2000>
 
 00002008 <none>:
-    2008:	12 00 00 00 	or R0,R0,R0
-    200c:	37 00 ff f8 	jmp \$fffffff8
+    2008:	12 00 00 00 	nop
+    200c:	37 00 ff f8 	jmp 2004 <local>
     2010:	03 21 00 00 	addui R1,R2,#\$0
     2014:	03 21 22 15 	addui R1,R2,#\$2215
     2018:	03 21 00 01 	addui R1,R2,#\$1
diff --git a/gas/testsuite/gas/ms1/relocs.exp b/gas/testsuite/gas/ms1/relocs.exp
index b02e208..41c84e2 100644
--- a/gas/testsuite/gas/ms1/relocs.exp
+++ b/gas/testsuite/gas/ms1/relocs.exp
@@ -20,7 +20,7 @@ proc regexp_test { file1 file2 test } {
 
 
 global srcdir subdir
-if [istarget mrisc1*-*-* || istarget ms1-*] {
+if [istarget ms1-*] {
     gas_test "relocs1.s" {-o relocs1.o} {} {assembling relocs1}
 
     #    gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}