Revert 2 June 1994 changes (Alpha 21164 support), for lack of assignment

paperwork.

2 files changed, 43 insertions, 177 deletions

diff --git a/gas/config/alpha-opcode.h b/gas/config/alpha-opcode.h
index 7c691e3..6e736eb 100644
--- a/gas/config/alpha-opcode.h
+++ b/gas/config/alpha-opcode.h
@@ -86,7 +86,7 @@ Kinds of operands:
    e    fa floating point register.
    f    fb floating point register.
    g    fc floating point register.
-   I	26 bit immediate (PALcode function #)
+   I	26 bit immediate
    l	16 low bits of immediate
    h	16 high(er) bits of immediate		[Never used. KR]
    L	22 bit PC relative immediate.
@@ -173,33 +173,6 @@ static const struct alpha_opcode alpha_opcodes[] =
 { "stq_c",      0xbc000000, 0, "1,l(2)" },
 { "stq_c",      0xbc000000, 0, "1,P" },		/* regbase macro */
 
-{ "ldb",	0, 0,		"1,l(2)Bd" },
-{ "ldb",	0, 0,		"1,PBd" },
-{ "ldbu",	0, 0,		"1,l(2)Bd" },
-{ "ldbu",	0, 0,		"1,PBd" },
-{ "ldw",	0, 0,		"1,l(2)Bd" },
-{ "ldw",	0, 0,		"1,PBd" },
-{ "ldwu",	0, 0,		"1,l(2)Bd" },
-{ "ldwu",	0, 0,		"1,PBd" },
-{ "stb",	0, 0,		"1,l(2)Bd" },
-{ "stb",	0, 0,		"1,PBd" },
-{ "stw",	0, 0,		"1,l(2)Bd" },
-{ "stw",	0, 0,		"1,PBd" },
-{ "ustw",	0, 0,		"1,l(2)Bd" },
-{ "ustw",	0, 0,		"1,PBd" },
-{ "ustl",	0, 0,		"1,l(2)Bd" },
-{ "ustl",	0, 0,		"1,PBd" },
-{ "ustq",	0, 0,		"1,l(2)Bd" },
-{ "ustq",	0, 0,		"1,PBd" },
-{ "uldw",	0, 0,		"1,l(2)Bd" },
-{ "uldw",	0, 0,		"1,PBd" },
-{ "uldwu",	0, 0,		"1,l(2)Bd" },
-{ "uldwu",	0, 0,		"1,PBd" },
-{ "uldl",	0, 0,		"1,l(2)Bd" },
-{ "uldl",	0, 0,		"1,PBd" },
-{ "uldq",	0, 0,		"1,l(2)Bd" },
-{ "uldq",	0, 0,		"1,PBd" },
-
 { "beq",        0xe4000000, 0, "1,L" },		/* 6o+5a+21d */
 { "bne",        0xf4000000, 0, "1,L" },
 { "blt",        0xe8000000, 0, "1,L" },
@@ -758,7 +731,7 @@ static const struct alpha_opcode alpha_opcodes[] =
 { "mult/suid",  0x5800fc40, 1, "e,f,g" },
 
 /*
- * Miscellaneous, including standard PAL instructions.
+ * Miscellaneous
  */
 { "pal",        0x00000000, 0, "I" },		/* 6o+26f */
 { "call_pal",   0x00000000, 0, "I" },		/* alias */
@@ -778,19 +751,8 @@ static const struct alpha_opcode alpha_opcodes[] =
 { "rs",         0x6000f000, 0, "1" },
 
 /*
- * More macros
- */
-{ "nop",         0x47ff041f, 0, "" },		/* or zero,zero,zero */
-{ "mov",         0x47e00400, 0, "2,3" },		/* or zero,r2,r3 */
-};
-
-#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0]))
-
-/*
- * PAL instructions for 21064 (and 21066/68)
+ * PAL instructions
  */
-static const struct alpha_opcode alpha_pal21064_opcodes[] =
-{
 { "hw_ld",	0x6c000000, 0, "1,t(2)" },
 { "hw_ld/p",	0x6c008000, 0, "1,t(2)" },
 { "hw_ld/a",	0x6c004000, 0, "1,t(2)" },
@@ -862,42 +824,11 @@ static const struct alpha_opcode alpha_pal21064_opcodes[] =
 { "hw_mtpr", 	0x74000000, 0, "R,8" },
 
 { "hw_rei",	0x7bff8000, 0, "" },
-};
-
-#define NUM21064OPCODES ((sizeof alpha_pal21064_opcodes)/(sizeof alpha_pal21064_opcodes[0]))
-
 /*
- * 21164 (and 21166/68) specific PAL instructions.
+ * More macros
  */
-static const struct alpha_opcode alpha_pal21164_opcodes[] =
-{
-{ "hw_ld",	0x6c000000, 0, "1,l(2)" },      /* RA, 16 bit displacement (RB) */
-{ "hw_st",	0x7c000000, 0, "1,l(2)" },      /* RA, 16 bit displacement (RB) */
-
-{ "hw_ldl/a",	0x6c004000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_ldq/a",	0x6c005000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_stl/a",	0x7c004000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_stq/a",	0x7c005000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-
-{ "hw_ldl/p",	0x6c008000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_ldq/p",	0x6c009000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_stl/p",	0x7c008000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_stq/p",	0x7c009000, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-
-{ "hw_ldq/v",	0x6c001800, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-
-{ "hw_ldl/l",	0x6c000400, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_ldq/l",	0x6c001400, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-
-{ "hw_stl/c",	0x7c000400, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-{ "hw_stq/c",	0x7c001400, 0, "1,t(2)" },      /* RA, 12 bit displacement (RB) */
-
-{ "hw_mfpr",	0x64000000, 0, "R,l" },         /* RA,RB,16 bits displacement */
-{ "hw_mtpr", 	0x74000000, 0, "R,l" },         /* RA,RB,16 bits displacement */
-
-{ "hw_rei",	0x7bff8000, 0, "" },
-
-{ "hw_rei_stall",	0x7bffc000, 0, "" },
+{ "nop",         0x47ff041f, 0, "" },		/* or zero,zero,zero */
+{ "mov",         0x47e00400, 0, "2,3" },		/* or zero,r2,r3 */
 };
 
-#define NUM21164OPCODES ((sizeof alpha_pal21164_opcodes)/(sizeof alpha_pal21164_opcodes[0]))
+#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0]))
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index 81453c9..25de02d 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -63,10 +63,6 @@
 /* @@ Will a simple 0x8000 work here?  If not, why not?  */
 #define GP_ADJUSTMENT	(0x8000 - 0x10)
 
-/* Which machine type is this?  Currently stores an integer for the
-   model, one of: 21064, 21066, 21164.  */
-static unsigned long machine;
-
 /* These are exported to relaxing code, even though we don't do any
    relaxing on this processor currently.  */
 const relax_typeS md_relax_table[1];
@@ -554,100 +550,64 @@ get_lit4_offset (val)
   return retval;
 }
 
-#define load_insn(NAME, OP)	(hash_insert (op_hash, (NAME), (PTR) (OP)))
+static struct alpha_it clear_insn;
 
-static void
-load_insn_table (ops, size)
-     struct alpha_opcode *ops;
-     int size;
+/* This function is called once, at assembler startup time.  It should
+   set up all the tables, etc. that the MD part of the assembler will
+   need, that can be determined before arguments are parsed.  */
+void
+md_begin ()
 {
-  struct alpha_opcode *end = ops + size;
-  struct alpha_opcode *op;
-  const char *name;
-
-  for (op = ops; op < end; )
-    {
-      const char *retval;
+  const char *retval, *name;
+  unsigned int i = 0;
 
-      name = op->name;
+  op_hash = hash_new ();
 
-      retval = load_insn (op->name, op);
+  for (i = 0; i < NUMOPCODES; )
+    {
+      const char *name = alpha_opcodes[i].name;
+      retval = hash_insert (op_hash, name, (PTR) &alpha_opcodes[i]);
       if (retval)
 	as_fatal ("internal error: can't hash opcode `%s': %s",
-		  op->name, retval);
+		  name, retval);
 
       do
-	op++;
-      while (op < end
-	     && (op->name == name
-		 || !strcmp (op->name, name)));
+	i++;
+      while (i < NUMOPCODES
+	     && (alpha_opcodes[i].name == name
+		 || !strcmp (alpha_opcodes[i].name, name)));
     }
   /* Some opcodes include modifiers of various sorts with a "/mod"
      syntax, like the architecture documentation suggests.  However,
      for use with gcc at least, we also need to access those same
      opcodes without the "/".  */
-  for (op = ops; op < end; )
+  for (i = 0; i < NUMOPCODES; )
     {
-      name = op->name;
+      name = alpha_opcodes[i].name;
 
       if (strchr (name, '/'))
 	{
-	  char *name2, *p;
-	  const char *q;
-
-	  name2 = xmalloc (strlen (name));
-	  p = name2;
-	  q = name;
-
-	  while (*q)
-	    if (*q == '/')
-	      q++;
-	    else
-	      *p++ = *q++;
-	  *p = 0;
+	  char *p = xmalloc (strlen (name));
+	  const char *q = name;
+	  char *q2 = p;
+
+	  for (; *q; q++)
+	    if (*q /= '/')
+	      *q2++ = *q;
+
+	  *q2++ = 0;
+	  retval = hash_insert (op_hash, p, (PTR) &alpha_opcodes[i]);
 	  /* Ignore failures -- the opcode table does duplicate some
 	     variants in different forms, like "hw_stq" and "hw_st/q".
-	     Maybe the variants can be eliminated, and this error checking
-	     restored.  */
-	  load_insn (name2, op);
+	     Maybe the variants can be eliminated, and this error
+	     checking restored.  */
 	}
 
       do
-	op++;
-      while (op < end
-	     && (op->name == name
-		 || !strcmp (op->name, name)));
-    }
-}
-
-static struct alpha_it clear_insn;
-
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc. that the MD part of the assembler will
-   need, that can be determined before arguments are parsed.  */
-void
-md_begin ()
-{
-  int i;
-
-  op_hash = hash_new ();
-  load_insn_table (alpha_opcodes, NUMOPCODES);
-
-  /* Default to 21064 PAL instructions.  */
-  if (machine == 0)
-    machine = 21064;
-
-  switch (machine)
-    {
-    case 21064:
-    case 21066:
-      load_insn_table (alpha_pal21064_opcodes, NUM21064OPCODES);
-      break;
-    case 21164:
-      load_insn_table (alpha_pal21164_opcodes, NUM21164OPCODES);
-      break;
-    default:
-      as_fatal ("palcode set unknown (internal error)");
+	i++;
+      while (i < NUMOPCODES
+	     && (alpha_opcodes[i].name == name
+		 || !strcmp (alpha_opcodes[i].name, name)));
     }
 
   lituse_basereg.X_op = O_constant;
@@ -2263,31 +2223,6 @@ md_parse_option (c, arg)
       addr32 = 1;
       break;
 
-    case 'm':
-      {
-	unsigned long mach;
-
-	if (!strcmp (arg, "21064"))
-	  mach = 21064;
-	else if (!strcmp (arg, "21066"))
-	  mach = 21066;
-	else if (!strcmp (arg, "21164"))
-	  mach = 21164;
-	else
-	  {
-	    as_bad ("invalid architecture %s", arg);
-	    return 0;
-	  }
-
-	if (machine != 0 && machine != mach)
-	  {
-	    as_warn ("machine type %lu already chosen, overriding with %lu",
-		     machine, mach);
-	  }
-	machine = mach;
-      }
-      break;
-
     default:
       return 0;
     }