Document M32Rx warnings and errors.

Document --warn-explicit-parallel-conflicts.

3 files changed, 149 insertions, 9 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 88d8aaf..ade2fbc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+start-sanitize-m32rx
+Wed Feb 11 10:32:28 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* doc/c-m32r.texi: Document warning and error messages.  Add
+	descriptions of --warn-explicit-parallel-conflicts.
+
+	* doc/as.texinfo: Add more m32rx command line options.
+end-sanitize-m32rx
+Tue Feb 10 18:31:31 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/tc-i386.c (i386_operand): Change error added Jan 2 1998
+	from as_bad to as_warn.
+
 start-sanitize-sky
 Tue Feb 10 15:15:40 1998  Doug Evans  <devans@canuck.cygnus.com>
 
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 199ee24..a24a590 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -1,5 +1,6 @@
 \input texinfo @c                               -*-Texinfo-*-
-@c  Copyright (c) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+@c  Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 1998
+@c  Free Software Foundation, Inc.
 @c UPDATE!!  On future updates--
 @c   (1)   check for new machine-dep cmdline options in
 @c         md_parse_option definitions in config/tc-*.c
@@ -85,7 +86,7 @@ END-INFO-DIR-ENTRY
 @ifinfo
 This file documents the GNU Assembler "@value{AS}".
 
-Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
 
 Permission is granted to make and distribute verbatim copies of
 this manual provided the copyright notice and this permission notice
@@ -140,7 +141,7 @@ done.
 @end tex
 
 @vskip 0pt plus 1filll
-Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
 
 Permission is granted to make and distribute verbatim copies of
 this manual provided the copyright notice and this permission notice
@@ -246,7 +247,7 @@ Here is a brief summary of how to invoke @code{@value{AS}}.  For details,
 @end ifset
 @c start-sanitize-m32rx
 @ifset M32R
- [ --m32rx ]
+ [ --m32rx | --[no-]warn-explicit-parallel-conflicts ]
 @end ifset
 @c end-sanitize-m32rx
 @ifset M680X0
@@ -470,6 +471,14 @@ Mitsubishi M32R series.
 Specify which processor in the M32R family is the target.  The default
 is normally the M32R, but this option changes it to the M32RX.
 
+@item --warn-explicit-parallel-conflicts
+Produce warning messages when questionable parallel constructs are
+encountered. 
+
+@item --no-warn-explicit-parallel-conflicts
+Do not produce warning messages when questionable parallel constructs are 
+encountered. 
+
 @end table
 @end ifset
 @c end-sanitize-m32rx
@@ -974,6 +983,7 @@ assembler.)
 * o::             -o to name the object file
 * R::             -R to join data and text sections
 * statistics::    --statistics to see statistics about assembly
+* traditional-format:: --traditional-format for compatible output
 * v::             -v to announce version
 * W::             -W to suppress warnings
 * Z::             -Z to make object file even after errors
@@ -1328,6 +1338,17 @@ Use @samp{--statistics} to display two statistics about the resources used by
 (in bytes), and the total execution time taken for the assembly (in @sc{cpu}
 seconds).
 
+@node traditional-format
+@section Compatible output: @code{--traditional-format}
+
+@kindex --traditional-format
+For some targets, the output of @code{@value{AS}} is different in some ways
+from the output of some existing assembler.  This switch requests
+@code{@value{AS}} to use the traditional format instead.
+
+For example, it disables the exception frame optimizations which
+@code{@value{AS}} normally does by default on @code{@value{GCC}} output.
+
 @node v
 @section Announce Version: @code{-v}
 
@@ -4721,9 +4742,11 @@ subject, see the hardware manufacturer's manual.
 @ifset I960
 * i960-Dependent::              Intel 80960 Dependent Features
 @end ifset
+@c start-sanitize-m32rx
 @ifset M32R
 * M32R-Dependent::              M32R Dependent Features
 @end ifset
+@c end-sanitize-m32rx
 @ifset M680X0
 * M68K-Dependent::              M680x0 Dependent Features
 @end ifset
@@ -4892,9 +4915,11 @@ family.
 @include c-i960.texi
 @end ifset
 
+@c start-sanitize-m32rx
 @ifset M32R
 @include c-m32r.texi
 @end ifset
+@c end-sanitize-m32rx
 
 @ifset M680X0
 @include c-m68k.texi
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi
index 55ed269..082820b 100644
--- a/gas/doc/c-m32r.texi
+++ b/gas/doc/c-m32r.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+@c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -11,9 +11,12 @@
 @chapter M32R Dependent Features
 @end ifclear
 
+@c start-sanitize-m32rx
+
 @cindex M32R support
 @menu
 * M32R-Opts::                   M32R Options
+* M32R-Warnings::               M32R Warnings
 @end menu
 
 @node M32R-Opts
@@ -21,17 +24,116 @@
 
 @cindex options, M32R
 @cindex M32R options
+
 The Mitsubishi M32R version of @code{@value{AS}} has a few machine
-dependent options.
+dependent options:
 
-@cindex @samp{--m32rx} option, M32R
-@cindex architecture options, M32R
+@table @code
+@item --m32rx
+@cindex @samp{--m32rx} option, M32RX
+@cindex architecture options, M32RX
 @cindex M32R architecture options
 @code{@value{AS}} can assemble code for several different members of the
 Mitsubishi M32R family.  Normally the default is to assemble code for
 the M32R microprocessor.  This option may be used to change the default
 to the M32RX microprocessor, which adds some more instructions to the
-basic M32R instruction set.
+basic M32R instruction set, and some additional parameters to some of
+the original instructions.
+
+@item --warn-explicit-parallel-conflicts
+@cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX
+Instructs @code{@value{AS}} to produce warning messages when
+questionable parallel instructions are encountered.  This option is
+enabled by default, but @code{@value{GCC}} disables it when it invokes
+@code{@value{AS}} directly.  Questionable instructions are those whoes
+behaviour would be different if they were executed sequentially.  For
+example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
+different result from @samp{mv r1, r2 \n mv r3, r1} since the former
+moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
+and r3.
+
+@item --no-warn-explicit-parallel-conflicts
+@cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX
+Instructs @code{@value{AS}} not to produce warning messages when
+questionable parallel instructions are encountered.
+
+@end table
+
+@node M32R-Warnings
+@section M32R Warnings
+
+@cindex warnings, M32R
+@cindex M32R warnings
+
+There are several warning and error messages that can be produced by
+@code{@value{AS}} which are specific to the M32R:
+
+@table @code
+
+@item output of first instruction is the same as the input of second instruction - is this intentional ?
+This message is only produced if warnings for explicit parallel
+conflicts have been enabled.  It indicates that the assembler has
+encountered a parallel instruction in which the destination register of
+the left hand instruction is used as an input register in the right hand
+instruction.  For example in this code fragment
+@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
+move instruction and the input to the neg instruction.
+
+@item output of second instruction is the same as the input of first instruction - is this intentional ?
+This message is only produced if warnings for explicit parallel
+conflicts have been enabled.  It indicates that the assembler has
+encountered a parallel instruction in which the destination register of
+the right hand instruction is used as an input register in the left hand
+instruction.  For example in this code fragment
+@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
+neg instruction and the input to the move instruction.
+
+@item instruction @samp{...} is for the M32RX only
+This message is produced when the assembler encounters an instruction
+which is only supported by the M32Rx processor, and the @samp{--m32rx}
+command line flag has not been specified to allow assembly of such
+instructions. 
+
+@item only the NOP instruction can be issued in parallel on the m32r
+This message is produced when the assembler encounters a parallel
+instruction which does not involve a NOP instruction and the
+@samp{--m32rx} command line flag has not been specified.  Only the M32Rx
+processor is able to execute two instructions in parallel.
+
+@item instruction @samp{...} cannot be executed in parallel.
+This message is produced when the assembler encounters a parallel
+instruction which is made up of one or two instructions which cannot be
+executed in parallel.
+
+@item Instructions share the same execution pipeline
+This message is produced when the assembler encounters a parallel
+instruction whoes components both use the same execution pipeline.
+
+@item Both instructions write to the link register
+This message is produced when the assembler encounters a parallel
+instruction whoes components both write to the link register, one of
+them as a side effect.  For example this code fragment will produce this
+message:  @samp{jl r0 || mv r14, r1}
+
+@item Destination of first instruction written to by side effect of second instruction.
+This message is produced when the assembler encounters a parallel
+instruction whoes right hand component has a side effect which modifes a
+register used as the destination by the left hand component.  For
+example this code fragment will produce this message:
+@samp{mv r1, r2 || ld r0, @@r1+} 
 
+@item Destination of second instruction written to by side effect of first instruction.
+This message is produced when the assembler encounters a parallel
+instruction whoes left hand component has a side effect which modifes a
+register used as the destination by the right hand component.  For
+example this code fragment will produce this message:
+@samp{st r2, @@-r1 || mv r1, r3} 
 
+@item Instructions write to the same destination register.
+This message is produced when the assembler encounters a parallel
+instruction where both components attempt to modify the same register.
+For example this code fragment will produce this message:
+@samp{mv r1, r2 || neg r1, r3}
 
+@end table
+@c end-sanitize-m32rx