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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:57:16 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | af4bcb4ce6939da1738c847a06789d2223b67ca4 (patch) | |
| tree | c97aeb157e74b8884981ab2852c2b3ec38e1756b /gas | |
| parent | 3fd229a447cd28a70bfd921f617bc6c3553b8fdd (diff) | |
| download | gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.zip gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.tar.gz gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 2 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sysreg-4.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-4.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-4.s | 2 |
6 files changed, 19 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index f958277..dab1a01 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,13 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * config/tc-aarch64.c (aarch64_features): New "rng" option. + * doc/c-aarch64.texi: Document the same. + * testsuite/gas/aarch64/sysreg-4.s: Test both instructions. + * testsuite/gas/aarch64/sysreg-4.d: Likewise. + * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8621a33..b09c416 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8773,6 +8773,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SHA3, 0), AARCH64_ARCH_NONE}, + {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0), + AARCH64_ARCH_NONE}, {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index dd5fbf4..009a379 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -185,6 +185,8 @@ automatically cause those extensions to be disabled. @tab Enable the speculation barrier instruction sb. @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable the Execution and Data and Prediction instructions. +@item @code{rng} @tab ARMv8.5-A @tab No + @tab Enable ARMv8.5-A random number instructions. @end multitable @node AArch64 Syntax diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l index f3167e3..2e0851c 100644 --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l @@ -6,3 +6,5 @@ [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx' [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3' [^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp' +[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndr' +[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndrrs' diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d index 1c14016..3ce7501 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg-4.d @@ -1,5 +1,5 @@ #source: sysreg-4.s -#as: -march=armv8.5-a +#as: -march=armv8.5-a+rng #objdump: -dr .*: file format .* @@ -11,3 +11,5 @@ Disassembly of section \.text: .*: d50b73a2 dvp rctx, x2 .*: d50b73e3 cpp rctx, x3 .*: d50b7d24 dc cvadp, x4 +.*: d53b2405 mrs x5, rndr +.*: d53b2426 mrs x6, rndrrs diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s index 49907c0..30decbd 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.s +++ b/gas/testsuite/gas/aarch64/sysreg-4.s @@ -4,3 +4,5 @@ func: dvp rctx, x2 cpp rctx, x3 dc cvadp, x4 + mrs x5, rndr + mrs x6, rndrrs |