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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:55:25 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:55:25 +0800 |
| commit | 9108bc33b1ca0b2e930c0cce5b1a0394e33e86be (patch) | |
| tree | adb7aaf17163d449da228c09b5f7c94b80e3163d /gas | |
| parent | bd782c07b914f28fd927cec42eacd8adcf556dca (diff) | |
| download | gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.zip gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.tar.gz gdb-9108bc33b1ca0b2e930c0cce5b1a0394e33e86be.tar.bz2 | |
[MIPS] Add Loongson 2K1000 proccessor support.
bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs264e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS264E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs264e to
bfd_mach_mips_gs464e extension.
binutils/
* NEWS: Mention Loongson 2K1000 proccessor support.
* readelf.c (get_machine_flags): Handle gs264e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
(mips_cpu_info_table): Add gs264e descriptors.
* doc/as.texi (march table): Add gs264e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
* opcode/mips.h (CPU_XXX): New CPU_GS264E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs264e and gs464e.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 5 | ||||
| -rw-r--r-- | gas/doc/c-mips.texi | 1 |
3 files changed, 11 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index a9413fa..8bb6ae8 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. + (mips_cpu_info_table): Add gs264e descriptors. + * doc/as.texi (march table): Add gs264e. + +2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 9c0a1fd..c9fc6c6 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -423,7 +423,8 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS64R6 \ || (CPU) == CPU_R5900) \ && ((CPU) != CPU_GS464 \ - || (CPU) != CPU_GS464E)) + || (CPU) != CPU_GS464E \ + || (CPU) != CPU_GS264E)) /* Return true if ISA supports move to/from high part of a 64-bit floating-point register. */ @@ -19817,6 +19818,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = ISA_MIPS64R2, CPU_GS464 }, { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, + { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT + | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, /* Cavium Networks Octeon CPU core */ { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 2682e36..7751ce0 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -439,6 +439,7 @@ loongson2e, loongson2f, gs464, gs464e, +gs264e, octeon, octeon+, octeon2, |