[binutils, Arm] Add support for shift instructions in MVE

This patch adds the following instructions which are part of
Armv8.1-M MVE:
ASRL (imm)
ASRL (reg)
LSLL (imm)
LSLL (reg)
LSRL
SQRSHRL
SRQSHR
SQSHLL
SQSHL
SRSHRL
SRSHR
UQRSHLL
UQRSHL
UQSHLL
UQSHL
URSHLL
URSHL

*** gas/ChangeLog ***

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (operand_parse_code): New entries for
	OP_RRnpcsp_I32 (register or integer operands).
	(do_mve_scalar_shift): New.
	(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
	sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
	* testsuite/gas/arm/mve-shift.d: New.
	* testsuite/gas/arm/mve-shift.s: New.
	* testsuite/gas/arm/mve-shift-bad.d: New.
	* testsuite/gas/arm/mve-shift-bad.s: New.
	* testsuite/gas/arm/mve-shift-bad.l: New.

*** opcodes/ChangeLog ***

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (emun mve_instructions): Updated for new instructions.
	(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
	sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
	uqshl, urshrl and urshr.
	(is_mve_okay_in_it): Add new instructions to TRUE list.
	(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
	(print_insn_mve): Updated to accept new %j,
	%<bitfield>m and %<bitfield>n patterns.

7 files changed, 142 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f25c2dc..34fee55 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+2019-05-21  Sudakshina Das  <sudi.das@arm.com>
+
+	* config/tc-arm.c (operand_parse_code): New entries for
+	OP_RRnpcsp_I32 (register or integer operands).
+	(do_mve_scalar_shift): New.
+	(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
+	sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
+	* testsuite/gas/arm/mve-shift.d: New.
+	* testsuite/gas/arm/mve-shift.s: New.
+	* testsuite/gas/arm/mve-shift-bad.d: New.
+	* testsuite/gas/arm/mve-shift-bad.s: New.
+	* testsuite/gas/arm/mve-shift-bad.l: New.
+
 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 
 	* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 136df33..8826119 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7559,6 +7559,9 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0);   break;
 	I0:		  po_imm_or_fail (0, 0, FALSE);	      break;
 
+	case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32);	break;
+	I32:		     po_imm_or_fail (1, 32, FALSE);	break;
+
 	case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
 	IF:
 	  if (!is_immediate_prefix (*str))
@@ -7818,6 +7821,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 
 	case OP_oRRnpcsp:
 	case OP_RRnpcsp:
+	case OP_RRnpcsp_I32:
 	  if (inst.operands[i].isreg)
 	    {
 	      if (inst.operands[i].reg == REG_PC)
@@ -14123,6 +14127,37 @@ v8_1_loop_reloc (int is_le)
     }
 }
 
+/* For shifts in MVE.  */
+static void
+do_mve_scalar_shift (void)
+{
+  if (!inst.operands[2].present)
+    {
+      inst.operands[2] = inst.operands[1];
+      inst.operands[1].reg = 0xf;
+    }
+
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg << 8;
+
+  if (inst.operands[2].isreg)
+    {
+      /* Assuming Rm is already checked not to be 11x1.  */
+      constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
+      constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
+      inst.instruction |= inst.operands[2].reg << 12;
+    }
+  else
+    {
+      /* Assuming imm is already checked as [1,32].  */
+      unsigned int value = inst.operands[2].imm;
+      inst.instruction |= (value & 0x1c) << 10;
+      inst.instruction |= (value & 0x03) << 6;
+      /* Change last 4 bits from 0xd to 0xf.  */
+      inst.instruction |= 0x2;
+    }
+}
+
 /* MVE instruction encoder helpers.  */
 #define M_MNEM_vabav	0xee800f01
 #define M_MNEM_vmladav	  0xeef00e00
@@ -25137,6 +25172,21 @@ static const struct asm_opcode insns[] =
 
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT & mve_ext
+ ToC("lsll",	ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
+ ToC("lsrl",	ea50011f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
+ ToC("asrl",	ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
+ ToC("uqrshll",	ea51010d, 3, (RRe, RRo, RRnpcsp),     mve_scalar_shift),
+ ToC("sqrshrl",	ea51012d, 3, (RRe, RRo, RRnpcsp),     mve_scalar_shift),
+ ToC("uqshll",	ea51010f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
+ ToC("urshrl",	ea51011f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
+ ToC("srshrl",	ea51012f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
+ ToC("sqshll",	ea51013f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
+ ToC("uqrshl",	ea500f0d, 2, (RRnpcsp, RRnpcsp),      mve_scalar_shift),
+ ToC("sqrshr",	ea500f2d, 2, (RRnpcsp, RRnpcsp),      mve_scalar_shift),
+ ToC("uqshl",	ea500f0f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
+ ToC("urshr",	ea500f1f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
+ ToC("srshr",	ea500f2f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
+ ToC("sqshl",	ea500f3f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
 
  ToC("vpt",	ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
  ToC("vptt",	ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
diff --git a/gas/testsuite/gas/arm/mve-shift-bad.d b/gas/testsuite/gas/arm/mve-shift-bad.d
new file mode 100644
index 0000000..f3aea25
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-shift-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid MVE shift instructions
+#source: mve-shift-bad.s
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-shift-bad.l
diff --git a/gas/testsuite/gas/arm/mve-shift-bad.l b/gas/testsuite/gas/arm/mve-shift-bad.l
new file mode 100644
index 0000000..5e7bfed
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-shift-bad.l
@@ -0,0 +1,12 @@
+.*: Assembler messages:
+.*: immediate value out of range -- `asrl r2,r3,#0'
+.*: immediate value out of range -- `asrl r2,r3,#33'
+.*: Error: Odd register not allowed here -- `asrl r1,r3,r5'
+.*: Error: Even register not allowed here -- `lsll r2,r4,#5'
+.*: Error: r15 not allowed here -- `lsll r2,r15,r5'
+.*: Warning: instruction is UNPREDICTABLE with SP operand
+.*: Error: registers may not be the same -- `sqrshrl r2,r3,r3'
+.*: Error: registers may not be the same -- `sqrshr r2,r2'
+.*: Error: registers may not be the same -- `uqrshll r2,r3,r2'
+.*: Error: thumb conditional instruction should be in IT block -- `uqshlgt r2,#32'
+.*: Error: constant expression required -- `urshrlle r2,r3,r5'
diff --git a/gas/testsuite/gas/arm/mve-shift-bad.s b/gas/testsuite/gas/arm/mve-shift-bad.s
new file mode 100644
index 0000000..7b38359
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-shift-bad.s
@@ -0,0 +1,15 @@
+        .syntax unified
+        .text
+
+foo:
+	asrl	r2, r3, #0
+	asrl	r2, r3, #33
+	asrl	r1, r3, r5
+	lsll	r2, r4, #5
+	lsll	r2, r15, r5
+	lsrl	r2, r13, #5
+	sqrshrl	r2, r3, r3
+	sqrshr	r2, r2
+	uqrshll	r2, r3, r2
+	uqshlgt		r2, #32
+	urshrlle	r2, r3, r5
diff --git a/gas/testsuite/gas/arm/mve-shift.d b/gas/testsuite/gas/arm/mve-shift.d
new file mode 100644
index 0000000..be5cd46
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-shift.d
@@ -0,0 +1,27 @@
+#name: Valid MVE shift instructions
+#source: mve-shift.s
+#as: -march=armv8.1-m.main+mve
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> ea52 136f 	asrl	r2, r3, #5
+0[0-9a-f]+ <[^>]+> ea52 532d 	asrl	r2, r3, r5
+0[0-9a-f]+ <[^>]+> ea52 134f 	lsll	r2, r3, #5
+0[0-9a-f]+ <[^>]+> ea52 530d 	lsll	r2, r3, r5
+0[0-9a-f]+ <[^>]+> ea52 135f 	lsrl	r2, r3, #5
+0[0-9a-f]+ <[^>]+> ea53 532d 	sqrshrl	r2, r3, r5
+0[0-9a-f]+ <[^>]+> ea52 5f2d 	sqrshr	r2, r5
+0[0-9a-f]+ <[^>]+> ea53 137f 	sqshll	r2, r3, #5
+0[0-9a-f]+ <[^>]+> ea52 1f7f 	sqshl	r2, #5
+0[0-9a-f]+ <[^>]+> ea53 73ef 	srshrl	r2, r3, #31
+0[0-9a-f]+ <[^>]+> ea52 7fef 	srshr	r2, #31
+0[0-9a-f]+ <[^>]+> ea53 530d 	uqrshll	r2, r3, r5
+0[0-9a-f]+ <[^>]+> ea52 5f0d 	uqrshl	r2, r5
+0[0-9a-f]+ <[^>]+> ea53 73cf 	uqshll	r2, r3, #31
+0[0-9a-f]+ <[^>]+> bfce      	itee	gt
+0[0-9a-f]+ <[^>]+> ea52 0f0f 	uqshlgt	r2, #32
+0[0-9a-f]+ <[^>]+> ea53 031f 	urshrlle	r2, r3, #32
+0[0-9a-f]+ <[^>]+> ea52 0f1f 	urshrle	r2, #32
+#...
diff --git a/gas/testsuite/gas/arm/mve-shift.s b/gas/testsuite/gas/arm/mve-shift.s
new file mode 100644
index 0000000..267e3fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-shift.s
@@ -0,0 +1,21 @@
+        .syntax unified
+        .text
+foo:
+	asrl	r2, r3, #5
+	asrl	r2, r3, r5
+	lsll	r2, r3, #5
+	lsll	r2, r3, r5
+	lsrl	r2, r3, #5
+	sqrshrl	r2, r3, r5
+	sqrshr	r2, r5
+	sqshll	r2, r3, #5
+	sqshl	r2, #5
+	srshrl	r2, r3, #31
+	srshr	r2, #31
+	uqrshll	r2, r3, r5
+	uqrshl	r2, r5
+	uqshll	r2, r3, #31
+	itee	gt
+	uqshlgt		r2, #32
+	urshrlle	r2, r3, #32
+	urshrle		r2, #32