gas/

2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* config/tc-ia64.h (unw_r_record): Change type of fr_mem to unsigned
	int.
	(unw_p_record): Remove unused/redundant fields imask and rmask.
	Combine spoff and pspoff into a union. Combine gr and br into a
	union. Change type of grmask and brmask to unsigned char. Change type
	of frmask to unsigned int.
	(unw_x_record): Combine spoff, pspoff, and treg into a union.
	* config/tc-ia64.c (unwind): New field 'pending_saves'.
	(check_pending_save): New.
	(alloc_record): Clear out entire record.
	(output_psp_gr): Use renamed structure fields.
	(output_psp_sprel): Likewise.
	(output_rp_gr): Likewise.
	(output_rp_br): Likewise.
	(output_rp_psprel): Likewise.
	(output_rp_sprel): Likewise.
	(output_pfs_gr): Likewise.
	(output_pfs_psprel): Likewise.
	(output_pfs_sprel): Likewise.
	(output_preds_gr): Likewise.
	(output_preds_psprel): Likewise.
	(output_preds_sprel): Likewise.
	(output_spill_base): Likewise.
	(output_unat_gr): Likewise.
	(output_unat_psprel): Likewise.
	(output_unat_sprel): Likewise.
	(output_lc_gr): Likewise.
	(output_lc_psprel): Likewise.
	(output_lc_sprel): Likewise.
	(output_fpsr_gr): Likewise.
	(output_fpsr_psprel): Likewise.
	(output_fpsr_sprel): Likewise.
	(output_priunat_gr): Likewise.
	(output_priunat_psprel): Likewise.
	(output_priunat_sprel): Likewise.
	(output_bsp_gr): Likewise.
	(output_bsp_psprel): Likewise.
	(output_bsp_sprel): Likewise.
	(output_bspstore_gr): Likewise.
	(output_bspstore_psprel): Likewise.
	(output_bspstore_sprel): Likewise.
	(output_rnat_gr): Likewise.
	(output_rnat_psprel): Likewise.
	(output_rnat_sprel): Likewise.
	(output_spill_psprel): Likewise.
	(output_spill_sprel): Likewise.
	(output_spill_reg): Likewise.
	(output_fr_mem): Likewise. Allocate one unwind record per set mask
	bit.
	(output_frgr_mem): Likewise.
	(output_gr_mem): Likewise.
	(output_br_mem): Likewise.
	(output_gr_gr): Likewise.
	(output_br_gr): Likewise.
	(fixup_unw_records): Likewise.
	(process_one_record): Use renamed structure fields. For gr_gr and
	br_gr, collect mask from chain of records before output.
	(in_prologue): Simplify and eliminate early returns. Call
	check_pending_save.
	(in_body): Simplify and eliminate early returns.
	(dot_body): Call check_pending_save.
	(md_assemble): Update comment. Deal with pending saves.

gas/testsuite/
2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* gas/ia64/unwind-bad.l: Uncomment patterns matching new warnings.
	* gas/ia64/unwind-ok.d: Correct expectations.

3 files changed, 11 insertions, 6 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 892c77a..a1183a8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-07-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/unwind-bad.l: Uncomment patterns matching new warnings.
+	* gas/ia64/unwind-ok.d: Correct expectations.
+
 2005-07-26  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/i386/immed32.[sd]: New.
diff --git a/gas/testsuite/gas/ia64/unwind-bad.l b/gas/testsuite/gas/ia64/unwind-bad.l
index 59a4b20..7009fab 100644
--- a/gas/testsuite/gas/ia64/unwind-bad.l
+++ b/gas/testsuite/gas/ia64/unwind-bad.l
@@ -2,17 +2,17 @@
 .*:8: Error: First operand to \.save\.g must be a positive 4-bit constant
 .*:10: Error: First operand to \.save\.g must be a positive 4-bit constant
 .*:12: Error: First operand to \.save\.g must be a positive 4-bit constant
-#FIXME .*:16: Error: Previous spill incomplete
+.*:16: Warning: Previous .save incomplete
 #FIXME .*:18: Error: Register r4 was already saved
 .*:20: Error: Operand to \.save\.f must be a positive 20-bit constant
 .*:22: Error: Operand to \.save\.f must be a positive 20-bit constant
 .*:24: Error: Operand to \.save\.f must be a positive 20-bit constant
-#FIXME .*:28: Error: Previous spill incomplete
+.*:28: Warning: Previous .save incomplete
 #FIXME .*:30: Error: Register f2 was already saved
 .*:32: Error: First operand to \.save\.b must be a positive 5-bit constant
 .*:34: Error: First operand to \.save\.b must be a positive 5-bit constant
 .*:36: Error: First operand to \.save\.b must be a positive 5-bit constant
-#FIXME .*:40: Error: Previous spill incomplete
+.*:40: Warning: Previous .save incomplete
 #FIXME .*:42: Error: Register b1 was already saved
 .*:44: Error: Operand 2 to \.spillreg must be a writable register
 .*:46: Error: Operand 1 to \.spillreg must be a preserved register
@@ -32,7 +32,7 @@
 .*:82: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant
 .*:84: Error: First operand to \.save\.gf must be a non-negative 4-bit constant
 .*:86: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant
-#FIXME .*:90: Error: Previous spill incomplete
+.*:90: Warning: Previous .save incomplete
 #FIXME .*:92: Error: Register r4 was already saved
 #FIXME .*:94: Error: Register f2 was already saved
 .*:98: Error: Epilogue count of 2 exceeds number of nested prologues \(1\)
diff --git a/gas/testsuite/gas/ia64/unwind-ok.d b/gas/testsuite/gas/ia64/unwind-ok.d
index d35d6de..e60c7cc 100644
--- a/gas/testsuite/gas/ia64/unwind-ok.d
+++ b/gas/testsuite/gas/ia64/unwind-ok.d
@@ -13,7 +13,7 @@ Unwind section '\.IA_64\.unwind' at offset 0x[[:xdigit:]]+ contains 8 entries:
 [[:space:]]*P7:spill_base\(pspoff=0x10-0x10\)
 [[:space:]]*P3:rp_br\(reg=b7\)
 [[:space:]]*P10:unwabi\(abi=@svr4,context=0x00\)
-[[:space:]]*R1:body\(rlen=[[:digit:]]+\)
+[[:space:]]*R1:body\(rlen=25\)
 [[:space:]]*X2:spill_reg\(t=0,reg=r4,treg=r2\)
 [[:space:]]*X4:spill_reg_p\(qp=p1,t=1,reg=r7,treg=r31\)
 [[:space:]]*X1:spill_sprel\(reg=b1,t=2,spoff=0x8\)
@@ -41,7 +41,7 @@ Unwind section '\.IA_64\.unwind' at offset 0x[[:xdigit:]]+ contains 8 entries:
 [[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
 [[:space:]]*R2:prologue_gr\(mask=\[rp,psp,pr\],grsave=r8,rlen=14\)
 [[:space:]]*P5:frgr_mem\(grmask=\[r4,r7\],frmask=\[f2,f31\]\)
-[[:space:]]*P4:spill_mask\(imask=\[b-b,bb-,---,---,--\]\)
+[[:space:]]*P4:spill_mask\(imask=\[frb,bfr,---,---,--\]\)
 [[:space:]]*P7:spill_base\(pspoff=0x10-0x10\)
 [[:space:]]*P2:br_gr\(brmask=\[b1,b5\],gr=r32\)
 [[:space:]]*X2:spill_reg\(t=6,reg=f31,treg=f31\)