RISC-V: Support to add implicit extensions.

We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions.  That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions.  For now we
follow the following rules to add the implicit extensions,

* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.

Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.

	bfd/
	* elfnn-riscv.c (riscv_merge_std_ext): Updated since
	riscv_lookup_subset is changed.
	* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
	extensions' order quickly.
	(riscv_init_ext_order): New function.  Init the riscv_ext_order
	according to the riscv_supported_std_ext and parse_config[i].class
	automatically.
	(riscv_compare_subsets): New function.  Similar to the strcmp, but
	compare the subsets with the specific order.
	(riscv_lookup_subset): Return TRUE and set `current` to the subset
	if it is found.  Otherwise, return FALSE and set `current` to the
	place where we should insert the subset.
	(riscv_add_implicit_subset): New function.  Search the list first,
	and then find the right place to add the implicit_subset.
	(riscv_parse_add_subset): Since We have to add all arch string
	extensions first, and then start to add their implicit extensions.
	We can add arch string extensions in order by the original
	riscv_add_subset, and then add the implicit subsets by the
	riscv_add_implicit_subset.  Besides, do not add the implicit
	extensions if we failed to find their default versions.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_add_implicit_subsets): New function.  Add all implicit
	extensions according to the arch string extensions.
	(riscv_parse_subset): Call riscv_init_ext_order and
	riscv_parse_add_implicit_subsets, before and after parsing the
	arch string.  Remove parts of the ISA conflict checking since
	the implicit extensions are added.
	* elfxx-riscv.h (riscv_lookup_subset): Updated.

	gas/
	* config/tc-riscv.c (riscv_subset_supports): Updated.
	* testsuite/gas/riscv/march-imply-i2p0.d: New testcase.  Need to
	add the implicit zicsr and zifencei when i's version less than 2.1.
	* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
	* testsuite/gas/riscv/march-imply-d.d: Likewise.
	* testsuite/gas/riscv/march-imply-f.d: Likewise.
	* testsuite/gas/riscv/march-imply-q.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
	* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.

10 files changed, 30 insertions, 11 deletions

diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.d b/gas/testsuite/gas/riscv/march-fail-rv32id.d
deleted file mode 100644
index de741cb..0000000
--- a/gas/testsuite/gas/riscv/march-fail-rv32id.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32id
-#source: empty.s
-#error_output: march-fail-rv32id.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32id.l b/gas/testsuite/gas/riscv/march-fail-rv32id.l
deleted file mode 100644
index c5f990c..0000000
--- a/gas/testsuite/gas/riscv/march-fail-rv32id.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*Assembler messages:
-.*Error: .*`d' extension requires `f' extension
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
index 8143dd4..dc201b3 100644
--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
@@ -1,3 +1,2 @@
 .*Assembler messages:
 .*Error: .*rv32 does not support the `q' extension
-.*Error: .*`q' extension requires `d' extension
diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.d b/gas/testsuite/gas/riscv/march-fail-rv64iq.d
deleted file mode 100644
index c97a812..0000000
--- a/gas/testsuite/gas/riscv/march-fail-rv64iq.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64iq
-#source: empty.s
-#error_output: march-fail-rv64iq.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv64iq.l b/gas/testsuite/gas/riscv/march-fail-rv64iq.l
deleted file mode 100644
index 787f46d..0000000
--- a/gas/testsuite/gas/riscv/march-fail-rv64iq.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*Assembler messages:
-.*Error: .*`q' extension requires `d' extension
diff --git a/gas/testsuite/gas/riscv/march-imply-d.d b/gas/testsuite/gas/riscv/march-imply-d.d
new file mode 100644
index 0000000..ce2b479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-d.d
@@ -0,0 +1,6 @@
+#as: -march=rv32id -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-f.d b/gas/testsuite/gas/riscv/march-imply-f.d
new file mode 100644
index 0000000..bc372ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-f.d
@@ -0,0 +1,6 @@
+#as: -march=rv32if -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0.d b/gas/testsuite/gas/riscv/march-imply-i2p0.d
new file mode 100644
index 0000000..17fcc7a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p0.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i2p0 -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1.d b/gas/testsuite/gas/riscv/march-imply-i2p1.d
new file mode 100644
index 0000000..0e9a464
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-i2p1.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1"
diff --git a/gas/testsuite/gas/riscv/march-imply-q.d b/gas/testsuite/gas/riscv/march-imply-q.d
new file mode 100644
index 0000000..d631d6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-q.d
@@ -0,0 +1,6 @@
+#as: -march=rv64iq -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_q2p2_zicsr2p0"