x86: Do not dump DS/CS segment overrides for branch hints

The previous change

  "x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode"

to ignore segment override prefixes in 64-bit mode lead to dumping
branch hints as excessive prefixes:

  ffffffff8109d5a0 <vmx_get_rflags>:
  ...
  ffffffff8109d601:       3e 77 0a                ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e>
  						^^^^^

In this particular case, those prefixes are not excessive but are used
to provide branch hints - taken/not-taken - to the CPU.

Assign active_seg_prefix in that particular case to consume them.

gas/

2002-11-29  Borislav Petkov  <bp@suse.de>

        * testsuite/gas/i386/branch.d: Add new branch insns test.
        * testsuite/gas/i386/branch.s: Likewise.
        * testsuite/gas/i386/i386.exp: Insert the new branch test.
        * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns.
        * testsuite/gas/i386/x86-64-branch.s: Likewise.
        * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.

opcodes/

2020-11-28 Borislav Petkov  <bp@suse.de>

        * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
        to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.

6 files changed, 25 insertions, 0 deletions

diff --git a/gas/testsuite/gas/i386/branch.d b/gas/testsuite/gas/i386/branch.d
new file mode 100644
index 0000000..6d25b95
--- /dev/null
+++ b/gas/testsuite/gas/i386/branch.d
@@ -0,0 +1,12 @@
+#as: -J
+#objdump: -dw
+#name: i386 branch
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	3e 74 03[ 	]+je,pt  +0x[0-9a-f]+
+[ 	]*[a-f0-9]+:	2e 74 00[ 	]+je,pn  +0x[0-9a-f]+
+#pass
diff --git a/gas/testsuite/gas/i386/branch.s b/gas/testsuite/gas/i386/branch.s
new file mode 100644
index 0000000..968a181
--- /dev/null
+++ b/gas/testsuite/gas/i386/branch.s
@@ -0,0 +1,4 @@
+.text
+	jz,pt .Llabel
+	jz,pn .Llabel
+.Llabel:
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index c85ced1..432cf01 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -565,6 +565,7 @@ if [gas_32_check] then {
     run_dump_test "lfence-ret-c"
     run_dump_test "lfence-ret-d"
     run_dump_test "lfence-byte"
+    run_dump_test "branch"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
index 8be91de..d5f2358 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -25,6 +25,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 82 00 00 00 00 	data16 jb 0x37	33: R_X86_64_PLT32	foo-0x4
 [ 	]*[a-f0-9]+:	66 c3                	data16 ret *
 [ 	]*[a-f0-9]+:	66 c2 08 00          	data16 ret \$0x8
+[ 	]*[a-f0-9]+:	3e 74 03[ 	]+je,pt  +0x[0-9a-f]+
+[ 	]*[a-f0-9]+:	2e 74 00[ 	]+je,pn  +0x[0-9a-f]+
 [ 	]*[a-f0-9]+:	ff d0                	call   \*%rax
 [ 	]*[a-f0-9]+:	ff d0                	call   \*%rax
 [ 	]*[a-f0-9]+:	66 ff d0             	data16 call \*%rax
diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
index 2618134..b963f9f 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -24,6 +24,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 82 00 00 00 00 	data16 jb (0x37|37 <.text\+0x37>)
 [ 	]*[a-f0-9]+:	66 c3                	data16 ret *
 [ 	]*[a-f0-9]+:	66 c2 08 00          	data16 ret \$0x8
+[ 	]*[a-f0-9]+:	3e 74 03[ 	]+je,pt  +0x[0-9a-f]+
+[ 	]*[a-f0-9]+:	2e 74 00[ 	]+je,pn  +0x[0-9a-f]+
 [ 	]*[a-f0-9]+:	ff d0                	call   \*%rax
 [ 	]*[a-f0-9]+:	ff d0                	call   \*%rax
 [ 	]*[a-f0-9]+:	66 ff d0             	data16 call \*%rax
diff --git a/gas/testsuite/gas/i386/x86-64-branch.s b/gas/testsuite/gas/i386/x86-64-branch.s
index eb40dd4..496e1bb 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.s
+++ b/gas/testsuite/gas/i386/x86-64-branch.s
@@ -22,6 +22,10 @@
 	retw
 	retw	$8
 
+	jz,pt .Llabel
+	jz,pn .Llabel
+.Llabel:
+
 	.intel_syntax noprefix
 	call	rax
 	callq	rax