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authorRichard Sandiford <rdsandiford@googlemail.com>2004-07-08 15:39:43 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2004-07-08 15:39:43 +0000
commitde7e6852134391ba8229ba9305e575ba34afaf59 (patch)
treef18bf631c0d2b3d6fe9bd969afcea565173bdd2e /gas/testsuite
parent1544280f1d3c2d72202a5daec14e7e7277efbc5a (diff)
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* config/tc-mips.c (mips_fix_adjustable): If the full addend is
going to be split into more than one in-place addend, return 0 for relocations against mergeable sections. Associate comments with code.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/mips/elf-rel19.d6
-rw-r--r--gas/testsuite/gas/mips/elf-rel7.d6
3 files changed, 11 insertions, 6 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 206b718..910c902 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-07-08 Richard Sandiford <rsandifo@redhat.com>
+
+ * gas/mips/elf-rel7.d: Expect relocations against bar to refer to bar.
+ * gas/mips/elf-refl19.d: Likewise L2.
+
2004-07-03 Richard Sandiford <rsandifo@redhat.com>
* config/tc-mips.c (HAVE_IN_PLACE_ADDENDS): New macro.
diff --git a/gas/testsuite/gas/mips/elf-rel19.d b/gas/testsuite/gas/mips/elf-rel19.d
index e80aa61..0a22d00 100644
--- a/gas/testsuite/gas/mips/elf-rel19.d
+++ b/gas/testsuite/gas/mips/elf-rel19.d
@@ -10,10 +10,10 @@ Disassembly of section \.text:
# Relocation agsinst .rodata.str1.1
#
.*: 8f840000 lw a0,0\(gp\)
- .*: R_MIPS_GOT16 \.rodata\.str1\.1
+ .*: R_MIPS_GOT16 L2
.*: 00000000 nop
-.*: 24840004 addiu a0,a0,4
- .*: R_MIPS_LO16 \.rodata\.str1\.1
+.*: 24840000 addiu a0,a0,0
+ .*: R_MIPS_LO16 L2
#
# Relocation agsinst L2 + 2
#
diff --git a/gas/testsuite/gas/mips/elf-rel7.d b/gas/testsuite/gas/mips/elf-rel7.d
index 58d0cff..48464c2 100644
--- a/gas/testsuite/gas/mips/elf-rel7.d
+++ b/gas/testsuite/gas/mips/elf-rel7.d
@@ -6,9 +6,9 @@
Disassembly of section \.text:
0+00 <.*> lui a0,0x0
- 0: R_MIPS_HI16 .barsec
-0+04 <.*> lw a0,8\(a0\)
- 4: R_MIPS_LO16 .barsec
+ 0: R_MIPS_HI16 bar
+0+04 <.*> lw a0,0\(a0\)
+ 4: R_MIPS_LO16 bar
0+08 <.*> lui a0,0x0
8: R_MIPS_HI16 bar
0+0c <.*> lw a0,4\(a0\)