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| author | Tomer Levi <Tomer.Levi@nsc.com> | 2004-10-28 10:19:30 +0000 |
|---|---|---|
| committer | Tomer Levi <Tomer.Levi@nsc.com> | 2004-10-28 10:19:30 +0000 |
| commit | 49c4a1800a5e50d7fdf09c41806b30fea9b002dc (patch) | |
| tree | 67d7344c818017036f7a87ac8d917e860a680834 /gas/testsuite | |
| parent | 3ad3f5ad1ce614306b5290f5b23a4319b3123914 (diff) | |
| download | gdb-49c4a1800a5e50d7fdf09c41806b30fea9b002dc.zip gdb-49c4a1800a5e50d7fdf09c41806b30fea9b002dc.tar.gz gdb-49c4a1800a5e50d7fdf09c41806b30fea9b002dc.tar.bz2 | |
2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
* gas/crx/cop_insn.d: Regenerate (after a bug fix in Assembler).
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/crx/cop_insn.d | 16 |
2 files changed, 12 insertions, 8 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 4047a11a..9ee7fb9 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2004-10-28 Tomer Levi <Tomer.Levi@nsc.com> + + * gas/crx/cop_insn.d: Regenerate (after a bug fix in Assembler). + 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> * gas/crx/cop_insn.s: Test new Co-Processor instruction 'cpi'. diff --git a/gas/testsuite/gas/crx/cop_insn.d b/gas/testsuite/gas/crx/cop_insn.d index 9c73629..1ec8ddf 100644 --- a/gas/testsuite/gas/crx/cop_insn.d +++ b/gas/testsuite/gas/crx/cop_insn.d @@ -12,28 +12,28 @@ Disassembly of section .text: 8: 21 43 0000000a <mtcr>: - a: 1f 30 10 30 mtcr \$0xf, r1, c0 + a: 1f 30 1e 30 mtcr \$0xf, r1, c14 0000000e <mfcr>: - e: 13 30 02 31 mfcr \$0x3, c0, r2 + e: 13 30 72 31 mfcr \$0x3, c7, r2 00000012 <mtcsr>: - 12: 12 30 50 32 mtcsr \$0x2, r5, cs0 + 12: 12 30 51 32 mtcsr \$0x2, r5, cs1 00000016 <mfcsr>: - 16: 11 30 0e 33 mfcsr \$0x1, cs0, r14 + 16: 11 30 ce 33 mfcsr \$0x1, cs12, r14 0000001a <ldcr>: - 1a: 11 30 30 34 ldcr \$0x1, r3, c0 + 1a: 11 30 38 34 ldcr \$0x1, r3, c8 0000001e <stcr>: - 1e: 12 30 04 35 stcr \$0x2, c0, r4 + 1e: 12 30 4b 35 stcr \$0x2, c11, r4 00000022 <ldcsr>: - 22: 14 30 60 36 ldcsr \$0x4, r6, cs0 + 22: 14 30 6c 36 ldcsr \$0x4, r6, cs12 00000026 <stcsr>: - 26: 17 30 0d 37 stcsr \$0x7, cs0, r13 + 26: 17 30 da 37 stcsr \$0x7, cs10, r13 0000002a <loadmcr>: 2a: 13 31 01 30 loadmcr \$0x3, r1, {c0,c12,c13} |