[PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): Add new operand.
	(parse_operands): Handle new operand.
	(do_neon_shl_imm): Accept MVE variants.
	(do_neon_shl): Likewise.
	(do_neon_qshl_imm): Likewise.
	(do_neon_qshl): Likewise.
	(do_neon_qshlu_imm): Likewise.
	(insns): Likewise.
	* testsuite/gas/arm/mve-vqshl-bad.d: New test.
	* testsuite/gas/arm/mve-vqshl-bad.l: New test.
	* testsuite/gas/arm/mve-vqshl-bad.s: New test.
	* testsuite/gas/arm/mve-vshl-bad.d: New test.
	* testsuite/gas/arm/mve-vshl-bad.l: New test.
	* testsuite/gas/arm/mve-vshl-bad.s: New test.

6 files changed, 193 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/mve-vqshl-bad.d b/gas/testsuite/gas/arm/mve-vqshl-bad.d
new file mode 100644
index 0000000..5f6ba29
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqshl-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQSHL instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vqshl-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqshl-bad.l b/gas/testsuite/gas/arm/mve-vqshl-bad.l
new file mode 100644
index 0000000..9331fe6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqshl-bad.l
@@ -0,0 +1,45 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqshl.s64 q0,q0,#0'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqshl.i32 q0,q0,#0'
+[^:]*:12: Error: immediate out of range for shift -- `vqshl.s8 q0,q1,#8'
+[^:]*:13: Error: immediate out of range for shift -- `vqshl.u16 q0,q1,#16'
+[^:]*:14: Error: immediate out of range for shift -- `vqshl.s32 q0,q1,#32'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqshl.s64 q0,r1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqshl.i16 q0,r1'
+[^:]*:17: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:19: Error: bad type in SIMD instruction -- `vqshl.s64 q0,q1,q2'
+[^:]*:20: Error: bad type in SIMD instruction -- `vqshl.i32 q0,q1,q2'
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
+[^:]*:26: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
+[^:]*:28: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
+[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,q1,#0'
+[^:]*:31: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,q1,#0'
+[^:]*:33: Error: syntax error -- `vqshleq.s16 q0,r1'
+[^:]*:34: Error: syntax error -- `vqshleq.s16 q0,r1'
+[^:]*:36: Error: syntax error -- `vqshleq.s16 q0,r1'
+[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,r1'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,r1'
+[^:]*:41: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
+[^:]*:44: Error: syntax error -- `vqshleq.s16 q0,q1,q2'
+[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqshlt.s16 q0,q1,q2'
+[^:]*:47: Error: instruction missing MVE vector predication code -- `vqshl.s16 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqshl-bad.s b/gas/testsuite/gas/arm/mve-vqshl-bad.s
new file mode 100644
index 0000000..e4a8657
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqshl-bad.s
@@ -0,0 +1,48 @@
+.macro cond type, lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vqshl.\type q0, q0, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqshl.s64 q0, q0, #0
+vqshl.i32 q0, q0, #0
+vqshl.s8 q0, q1, #8
+vqshl.u16 q0, q1, #16
+vqshl.s32 q0, q1, #32
+vqshl.s64 q0, r1
+vqshl.i16 q0, r1
+vqshl.u16 q0, sp
+vqshl.s32 q0, pc
+vqshl.s64 q0, q1, q2
+vqshl.i32 q0, q1, q2
+cond u32, #0
+cond s8, r1
+cond s16, q2
+it eq
+vqshleq.s16 q0, q1, #0
+vqshleq.s16 q0, q1, #0
+vpst
+vqshleq.s16 q0, q1, #0
+vqshlt.s16 q0, q1, #0
+vpst
+vqshl.s16 q0, q1, #0
+it eq
+vqshleq.s16 q0, r1
+vqshleq.s16 q0, r1
+vpst
+vqshleq.s16 q0, r1
+vqshlt.s16 q0, r1
+vpst
+vqshl.s16 q0, r1
+it eq
+vqshleq.s16 q0, q1, q2
+vqshleq.s16 q0, q1, q2
+vpst
+vqshleq.s16 q0, q1, q2
+vqshlt.s16 q0, q1, q2
+vpst
+vqshl.s16 q0, q1, q2
+
diff --git a/gas/testsuite/gas/arm/mve-vshl-bad.d b/gas/testsuite/gas/arm/mve-vshl-bad.d
new file mode 100644
index 0000000..04d4a5d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshl-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VSHL instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vshl-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vshl-bad.l b/gas/testsuite/gas/arm/mve-vshl-bad.l
new file mode 100644
index 0000000..d3e4fc6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshl-bad.l
@@ -0,0 +1,44 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vshl.i64 q0,q0,#0'
+[^:]*:11: Error: immediate out of range for shift -- `vshl.i8 q0,q1,#8'
+[^:]*:12: Error: immediate out of range for shift -- `vshl.i16 q0,q1,#16'
+[^:]*:13: Error: immediate out of range for shift -- `vshl.i32 q0,q1,#32'
+[^:]*:14: Error: bad type in SIMD instruction -- `vshl.s64 q0,r1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vshl.i16 q0,r1'
+[^:]*:16: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:18: Error: bad type in SIMD instruction -- `vshl.s64 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vshl.i32 q0,q1,q2'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Error: syntax error -- `vshleq.i16 q0,q1,#0'
+[^:]*:25: Error: syntax error -- `vshleq.i16 q0,q1,#0'
+[^:]*:27: Error: syntax error -- `vshleq.i16 q0,q1,#0'
+[^:]*:28: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.i16 q0,q1,#0'
+[^:]*:30: Error: instruction missing MVE vector predication code -- `vshl.i16 q0,q1,#0'
+[^:]*:32: Error: syntax error -- `vshleq.s16 q0,r1'
+[^:]*:33: Error: syntax error -- `vshleq.s16 q0,r1'
+[^:]*:35: Error: syntax error -- `vshleq.s16 q0,r1'
+[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.s16 q0,r1'
+[^:]*:38: Error: instruction missing MVE vector predication code -- `vshl.s16 q0,r1'
+[^:]*:40: Error: syntax error -- `vshleq.s16 q0,q1,q2'
+[^:]*:41: Error: syntax error -- `vshleq.s16 q0,q1,q2'
+[^:]*:43: Error: syntax error -- `vshleq.s16 q0,q1,q2'
+[^:]*:44: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.s16 q0,q1,q2'
+[^:]*:46: Error: instruction missing MVE vector predication code -- `vshl.s16 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vshl-bad.s b/gas/testsuite/gas/arm/mve-vshl-bad.s
new file mode 100644
index 0000000..70a3f59
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshl-bad.s
@@ -0,0 +1,46 @@
+.macro cond type, lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vshl.\type q0, q0, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vshl.i64 q0, q0, #0
+vshl.i8 q0, q1, #8
+vshl.i16 q0, q1, #16
+vshl.i32 q0, q1, #32
+vshl.s64 q0, r1
+vshl.i16 q0, r1
+vshl.u16 q0, sp
+vshl.s32 q0, pc
+vshl.s64 q0, q1, q2
+vshl.i32 q0, q1, q2
+cond i32, #0
+cond s8, r1
+cond s16, q2
+it eq
+vshleq.i16 q0, q1, #0
+vshleq.i16 q0, q1, #0
+vpst
+vshleq.i16 q0, q1, #0
+vshlt.i16 q0, q1, #0
+vpst
+vshl.i16 q0, q1, #0
+it eq
+vshleq.s16 q0, r1
+vshleq.s16 q0, r1
+vpst
+vshleq.s16 q0, r1
+vshlt.s16 q0, r1
+vpst
+vshl.s16 q0, r1
+it eq
+vshleq.s16 q0, q1, q2
+vshleq.s16 q0, q1, q2
+vpst
+vshleq.s16 q0, q1, q2
+vshlt.s16 q0, q1, q2
+vpst
+vshl.s16 q0, q1, q2