[PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
	 M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.
	(do_mve_vqmovn): New encoding function.
	(do_neon_rshl): Change to accepte MVE variants.
	(insns): Change entries and add new for MVE mnemonics.
	* testsuite/gas/arm/mve-vqmovn-bad.d: New test.
	* testsuite/gas/arm/mve-vqmovn-bad.l: New test.
	* testsuite/gas/arm/mve-vqmovn-bad.s: New test.
	* testsuite/gas/arm/mve-vqrshl-bad.d: New test.
	* testsuite/gas/arm/mve-vqrshl-bad.l: New test.
	* testsuite/gas/arm/mve-vqrshl-bad.s: New test.
	* testsuite/gas/arm/mve-vrshl-bad.d: New test.
	* testsuite/gas/arm/mve-vrshl-bad.l: New test.
	* testsuite/gas/arm/mve-vrshl-bad.s: New test.

9 files changed, 267 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/mve-vqmovn-bad.d b/gas/testsuite/gas/arm/mve-vqmovn-bad.d
new file mode 100644
index 0000000..ebf6026
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqmovn-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQMOVNT and VQMOVNB instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqmovn-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqmovn-bad.l b/gas/testsuite/gas/arm/mve-vqmovn-bad.l
new file mode 100644
index 0000000..f29c30a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqmovn-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqmovnt.s8 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqmovnt.s64 q0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqmovnt.i16 q0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqmovnb.u8 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqmovnb.u64 q0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqmovnb.i16 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqmovunt.s8 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqmovunt.s64 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vqmovunt.i16 q0,q1'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqmovunb.s8 q0,q1'
+[^:]*:20: Error: bad type in SIMD instruction -- `vqmovunb.s64 q0,q1'
+[^:]*:21: Error: bad type in SIMD instruction -- `vqmovunb.i16 q0,q1'
+[^:]*:22: Error: bad type in SIMD instruction -- `vqmovunt.u16 q0,q1'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqmovunt.u32 q0,q1'
+[^:]*:24: Error: bad type in SIMD instruction -- `vqmovunb.u16 q0,q1'
+[^:]*:25: Error: bad type in SIMD instruction -- `vqmovunb.u32 q0,q1'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vqmovnteq.s16 q0,q1'
+[^:]*:32: Error: syntax error -- `vqmovnteq.s16 q0,q1'
+[^:]*:34: Error: syntax error -- `vqmovnteq.s16 q0,q1'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovntt.s16 q0,q1'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqmovnt.s16 q0,q1'
+[^:]*:39: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
+[^:]*:40: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
+[^:]*:42: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovnbt.s16 q0,q1'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqmovnb.s16 q0,q1'
+[^:]*:47: Error: syntax error -- `vqmovunteq.s16 q0,q1'
+[^:]*:48: Error: syntax error -- `vqmovunteq.s16 q0,q1'
+[^:]*:50: Error: syntax error -- `vqmovunteq.s16 q0,q1'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovuntt.s16 q0,q1'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqmovunt.s16 q0,q1'
+[^:]*:55: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
+[^:]*:56: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
+[^:]*:58: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovunbt.s16 q0,q1'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vqmovunb.s16 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vqmovn-bad.s b/gas/testsuite/gas/arm/mve-vqmovn-bad.s
new file mode 100644
index 0000000..a59179c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqmovn-bad.s
@@ -0,0 +1,61 @@
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqmovnt.s8 q0, q1
+vqmovnt.s64 q0, q1
+vqmovnt.i16 q0, q1
+vqmovnb.u8 q0, q1
+vqmovnb.u64 q0, q1
+vqmovnb.i16 q0, q1
+vqmovunt.s8 q0, q1
+vqmovunt.s64 q0, q1
+vqmovunt.i16 q0, q1
+vqmovunb.s8 q0, q1
+vqmovunb.s64 q0, q1
+vqmovunb.i16 q0, q1
+vqmovunt.u16 q0, q1
+vqmovunt.u32 q0, q1
+vqmovunb.u16 q0, q1
+vqmovunb.u32 q0, q1
+cond vqmovnt
+cond vqmovnb
+cond vqmovunt
+cond vqmovunb
+it eq
+vqmovnteq.s16 q0, q1
+vqmovnteq.s16 q0, q1
+vpst
+vqmovnteq.s16 q0, q1
+vqmovntt.s16 q0, q1
+vpst
+vqmovnt.s16 q0, q1
+it eq
+vqmovnbeq.s16 q0, q1
+vqmovnbeq.s16 q0, q1
+vpst
+vqmovnbeq.s16 q0, q1
+vqmovnbt.s16 q0, q1
+vpst
+vqmovnb.s16 q0, q1
+it eq
+vqmovunteq.s16 q0, q1
+vqmovunteq.s16 q0, q1
+vpst
+vqmovunteq.s16 q0, q1
+vqmovuntt.s16 q0, q1
+vpst
+vqmovunt.s16 q0, q1
+it eq
+vqmovunbeq.s16 q0, q1
+vqmovunbeq.s16 q0, q1
+vpst
+vqmovunbeq.s16 q0, q1
+vqmovunbt.s16 q0, q1
+vpst
+vqmovunb.s16 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vqrshl-bad.d b/gas/testsuite/gas/arm/mve-vqrshl-bad.d
new file mode 100644
index 0000000..d1185da
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqrshl-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQRSHL instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqrshl-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqrshl-bad.l b/gas/testsuite/gas/arm/mve-vqrshl-bad.l
new file mode 100644
index 0000000..337cf17
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqrshl-bad.l
@@ -0,0 +1,32 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2'
+[^:]*:16: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2'
+[^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
+[^:]*:23: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
+[^:]*:25: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
+[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,q1,q2'
+[^:]*:28: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,q1,q2'
+[^:]*:30: Error: syntax error -- `vqrshleq.s32 q0,r2'
+[^:]*:31: Error: syntax error -- `vqrshleq.s32 q0,r2'
+[^:]*:33: Error: syntax error -- `vqrshleq.s32 q0,r2'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,r2'
+[^:]*:36: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,r2'
diff --git a/gas/testsuite/gas/arm/mve-vqrshl-bad.s b/gas/testsuite/gas/arm/mve-vqrshl-bad.s
new file mode 100644
index 0000000..fd4b5cc
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqrshl-bad.s
@@ -0,0 +1,36 @@
+.macro cond lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vqrshl.s16 q0, q0, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqrshl.s64 q0, q1, q2
+vqrshl.u64 q0, q1, q2
+vqrshl.i32 q0, q1, q2
+vqrshl.s64 q0, r2
+vqrshl.u64 q0, r2
+vqrshl.i32 q0, r2
+vqrshl.s32 q0, q1, r2
+vqrshl.s32 q0, pc
+vqrshl.s32 q0, sp
+cond q2
+cond r2
+it eq
+vqrshleq.s32 q0, q1, q2
+vqrshleq.s32 q0, q1, q2
+vpst
+vqrshleq.s32 q0, q1, q2
+vqrshlt.s32 q0, q1, q2
+vpst
+vqrshl.s32 q0, q1, q2
+it eq
+vqrshleq.s32 q0, r2
+vqrshleq.s32 q0, r2
+vpst
+vqrshleq.s32 q0, r2
+vqrshlt.s32 q0, r2
+vpst
+vqrshl.s32 q0, r2
diff --git a/gas/testsuite/gas/arm/mve-vrshl-bad.d b/gas/testsuite/gas/arm/mve-vrshl-bad.d
new file mode 100644
index 0000000..163b3a9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrshl-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VRSHL instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vrshl-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vrshl-bad.l b/gas/testsuite/gas/arm/mve-vrshl-bad.l
new file mode 100644
index 0000000..5cb98c2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrshl-bad.l
@@ -0,0 +1,29 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vrshl.i16 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vrshl.i16 q0,r2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vrshl.s64 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vrshl.s64 q0,r2'
+[^:]*:14: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
+[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vrshlt.s32 q0,q1,q2'
+[^:]*:25: Error: instruction missing MVE vector predication code -- `vrshl.s32 q0,q1,q2'
+[^:]*:27: Error: syntax error -- `vrshleq.s32 q0,r2'
+[^:]*:28: Error: syntax error -- `vrshleq.s32 q0,r2'
+[^:]*:30: Error: syntax error -- `vrshleq.s32 q0,r2'
+[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vrshlt.s32 q0,r2'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vrshl.s32 q0,r2'
diff --git a/gas/testsuite/gas/arm/mve-vrshl-bad.s b/gas/testsuite/gas/arm/mve-vrshl-bad.s
new file mode 100644
index 0000000..77ed167
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrshl-bad.s
@@ -0,0 +1,33 @@
+.macro cond lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vrshl.s32 q0, q0, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vrshl.i16 q0, q1, q2
+vrshl.i16 q0, r2
+vrshl.s64 q0, q1, q2
+vrshl.s64 q0, r2
+vrshl.s32 q0, sp
+vrshl.s32 q0, pc
+cond q2
+cond r2
+it eq
+vrshleq.s32 q0, q1, q2
+vrshleq.s32 q0, q1, q2
+vpst
+vrshleq.s32 q0, q1, q2
+vrshlt.s32 q0, q1, q2
+vpst
+vrshl.s32 q0, q1, q2
+it eq
+vrshleq.s32 q0, r2
+vrshleq.s32 q0, r2
+vpst
+vrshleq.s32 q0, r2
+vrshlt.s32 q0, r2
+vpst
+vrshl.s32 q0, r2