Add support for a __gcc_isr pseudo isntruction to the AVR assembler.

    PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.

gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
    (AVR Pseudo Instructions): New node.
    * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
    (md_undefined_symbol): Define to avr_undefined_symbol.
    (avr_pre_output_hook, avr_undefined_symbol): New protos.
    * config/tc-avr.c (struc-symbol.h): Include it.
    (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
    (avr_isr, avr_gccisr_opcode)
    (avr_no_sreg_hash, avr_no_sreg): New static variables.
    (avr_opt_s) <have_gccisr>: Add field.
    (avr_opt): Add initializer for have_gccisr.
    (enum options) <OPTION_HAVE_GCCISR>: Add enum.
    (md_longopts) <"mgcc-isr">: Add entry.
    (md_show_usage): Document -mgcc-isr.
    (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
    (md_undefined_symbol): Remove.
    (avr_undefined_symbol, avr_pre_output_hook): New fuctions.
    (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
    (avr_operand) <pregno>: Add argument and set *pregno if function
    is called for a register constraint.
    [N]: Handle constraint.
    (avr_operands) <avr_operand>: Pass 5th parameter to calls.
    [avr_opt.have_gccisr]: Call avr_update_gccisr.  Call
    avr_gccisr_operands instead of avr_operands.
    (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
    (avr_gccisr_operands, avr_check_gccisr_done): New static functions.
    * testsuite/gas/avr/gccisr-01.d: New test.
    * testsuite/gas/avr/gccisr-01.s: New test.
    * testsuite/gas/avr/gccisr-02.d: New test.
    * testsuite/gas/avr/gccisr-02.s: New test.
    * testsuite/gas/avr/gccisr-03.d: New test.
    * testsuite/gas/avr/gccisr-03.s: New test.

6 files changed, 359 insertions, 0 deletions

diff --git a/gas/testsuite/gas/avr/gccisr-01.d b/gas/testsuite/gas/avr/gccisr-01.d
new file mode 100644
index 0000000..91e1e61
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-01.d
@@ -0,0 +1,141 @@
+#name: gccisr-01: __gcc_isr pseudo instruction
+#as: -mgcc-isr -mavr4
+#objdump: -dz
+#target: avr-*-*
+
+.*: +file format elf32-avr
+
+
+Disassembly of section \.text:
+
+00000000 <__start1>:
+   0:	68 94       	set
+
+00000002 <__vec1_start>:
+   2:	0f 92       	push	r0
+   4:	0f b6       	in	r0, 0x3f	; 63
+   6:	0f 92       	push	r0
+   8:	01 30       	cpi	r16, 0x01	; 1
+   a:	0f 90       	pop	r0
+   c:	0f be       	out	0x3f, r0	; 63
+   e:	0f 90       	pop	r0
+  10:	e8 94       	clt
+
+00000012 <__data1>:
+  12:	00 e0       	ldi	r16, 0x00	; 0
+  14:	08 00       	\.word	0x0008	; \?\?\?\?
+
+00000016 <__start2>:
+  16:	68 94       	set
+
+00000018 <__vec2_start>:
+  18:	e1 e0       	ldi	r30, 0x01	; 1
+  1a:	f0 91 00 00 	lds	r31, 0x0000	; 0x800000 <__data6\+0x7fff40>
+  1e:	f0 93 00 00 	sts	0x0000, r31	; 0x800000 <__data6\+0x7fff40>
+  22:	12 01       	movw	r2, r4
+  24:	12 95       	swap	r17
+  26:	18 95       	reti
+  28:	78 10       	cpse	r7, r8
+  2a:	78 94       	sei
+  2c:	f8 94       	cli
+  2e:	af b6       	in	r10, 0x3f	; 63
+  30:	af be       	out	0x3f, r10	; 63
+  32:	18 95       	reti
+  34:	e8 94       	clt
+
+00000036 <__data2>:
+  36:	00 e0       	ldi	r16, 0x00	; 0
+  38:	0f 00       	\.word	0x000f	; \?\?\?\?
+
+0000003a <__start3>:
+  3a:	68 94       	set
+
+0000003c <__vec3_start>:
+  3c:	1f 92       	push	r1
+  3e:	1f b6       	in	r1, 0x3f	; 63
+  40:	1f 92       	push	r1
+  42:	11 24       	eor	r1, r1
+  44:	8f 93       	push	r24
+  46:	8f 91       	pop	r24
+  48:	1f 90       	pop	r1
+  4a:	1f be       	out	0x3f, r1	; 63
+  4c:	1f 90       	pop	r1
+  4e:	18 95       	reti
+  50:	8f 91       	pop	r24
+  52:	1f 90       	pop	r1
+  54:	1f be       	out	0x3f, r1	; 63
+  56:	1f 90       	pop	r1
+  58:	18 95       	reti
+  5a:	13 94       	inc	r1
+  5c:	e8 94       	clt
+
+0000005e <__data3>:
+  5e:	00 e0       	ldi	r16, 0x00	; 0
+  60:	11 00       	\.word	0x0011	; \?\?\?\?
+
+00000062 <__start4>:
+  62:	68 94       	set
+
+00000064 <__vec4_start>:
+  64:	0f 92       	push	r0
+  66:	0f b6       	in	r0, 0x3f	; 63
+  68:	0f 92       	push	r0
+  6a:	1f 92       	push	r1
+  6c:	11 24       	eor	r1, r1
+  6e:	8f 93       	push	r24
+  70:	8f 91       	pop	r24
+  72:	1f 90       	pop	r1
+  74:	0f 90       	pop	r0
+  76:	0f be       	out	0x3f, r0	; 63
+  78:	0f 90       	pop	r0
+  7a:	18 95       	reti
+  7c:	8f 91       	pop	r24
+  7e:	1f 90       	pop	r1
+  80:	0f 90       	pop	r0
+  82:	0f be       	out	0x3f, r0	; 63
+  84:	0f 90       	pop	r0
+  86:	18 95       	reti
+  88:	01 9f       	mul	r16, r17
+  8a:	e8 94       	clt
+
+0000008c <__data4>:
+  8c:	00 e0       	ldi	r16, 0x00	; 0
+  8e:	14 00       	\.word	0x0014	; \?\?\?\?
+
+00000090 <__start5>:
+  90:	68 94       	set
+
+00000092 <__vec5_start>:
+  92:	0f 92       	push	r0
+  94:	c8 95       	lpm
+  96:	0f 90       	pop	r0
+  98:	18 95       	reti
+  9a:	0f 90       	pop	r0
+  9c:	18 95       	reti
+  9e:	e8 94       	clt
+
+000000a0 <__data5>:
+  a0:	00 e0       	ldi	r16, 0x00	; 0
+  a2:	07 00       	\.word	0x0007	; \?\?\?\?
+
+000000a4 <__start6>:
+  a4:	68 94       	set
+
+000000a6 <__vec6_start>:
+  a6:	af 93       	push	r26
+  a8:	af b7       	in	r26, 0x3f	; 63
+  aa:	af 93       	push	r26
+  ac:	af 91       	pop	r26
+  ae:	af bf       	out	0x3f, r26	; 63
+  b0:	af 91       	pop	r26
+  b2:	18 95       	reti
+  b4:	af 91       	pop	r26
+  b6:	af bf       	out	0x3f, r26	; 63
+  b8:	af 91       	pop	r26
+  ba:	18 95       	reti
+  bc:	88 94       	clc
+  be:	e8 94       	clt
+
+000000c0 <__data6>:
+  c0:	00 e0       	ldi	r16, 0x00	; 0
+  c2:	0d 00       	\.word	0x000d	; \?\?\?\?
diff --git a/gas/testsuite/gas/avr/gccisr-01.s b/gas/testsuite/gas/avr/gccisr-01.s
new file mode 100644
index 0000000..82cf9f6
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-01.s
@@ -0,0 +1,127 @@
+.text
+
+;;; Use SREG
+
+__start1:
+    set
+
+__vec1_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    cpi r16,1
+    __gcc_isr 2
+    __gcc_isr 0,r0
+    clt
+__vec1_end:
+__data1:
+    ldi r16, foo - 2
+    .word (__vec1_end - __vec1_start) / 2
+
+;;; Nothing used.
+
+__start2:
+    set
+
+__vec2_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    ldi r30, 1
+    lds r31, 0
+    sts 0, r31
+    movw r2, r4
+    swap r17
+    __gcc_isr 2
+    reti
+    __gcc_isr 2
+    cpse r7, r8
+    sei
+    cli
+    in  r10, 0x3f
+    out 0x3f, r10
+    reti
+    __gcc_isr 0,r0
+    clt
+__vec2_end:
+__data2:
+    ldi r16, foo - 0
+    .word (__vec2_end - __vec2_start) / 2
+
+;;; Use SREG, ZERO and R24
+
+__start3:
+    set
+
+__vec3_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    __gcc_isr 2
+    reti
+    __gcc_isr 2
+    reti
+    inc r1
+    __gcc_isr 0,r24
+    clt
+__vec3_end:
+__data3:
+    ldi r16, foo - 3
+    .word (__vec3_end - __vec3_start) / 2
+
+;;; Use SREG, ZERO, TMP and R24
+
+__start4:
+    set
+
+__vec4_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    __gcc_isr 2
+    reti
+    __gcc_isr 2
+    reti
+    mul 16, 17
+    __gcc_isr 0,r24
+    clt
+__vec4_end:
+__data4:
+    ldi r16, foo - 4
+    .word (__vec4_end - __vec4_start) / 2
+
+;;; Use TMP
+
+__start5:
+    set
+
+__vec5_start:
+    __gcc_isr 1
+    lpm
+    foo = __gcc_isr.n_pushed
+    __gcc_isr 2
+    reti
+    __gcc_isr 2
+    reti
+    __gcc_isr 0,r0
+    clt
+__vec5_end:
+__data5:
+    ldi r16, foo - 1
+    .word (__vec5_end - __vec5_start) / 2
+
+;;; Use SREG, R26
+
+__start6:
+    set
+
+__vec6_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    __gcc_isr 2
+    reti
+    __gcc_isr 2
+    reti
+    clc
+    __gcc_isr 0,r26
+    clt
+__vec6_end:
+__data6:
+    ldi r16, foo - 2
+    .word (__vec6_end - __vec6_start) / 2
diff --git a/gas/testsuite/gas/avr/gccisr-02.d b/gas/testsuite/gas/avr/gccisr-02.d
new file mode 100644
index 0000000..b0724c4
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-02.d
@@ -0,0 +1,43 @@
+#name: gccisr-02: __gcc_isr pseudo instruction
+#as: -mgcc-isr -mavrtiny
+#objdump: -dz
+#target: avr-*-*
+
+.*: +file format elf32-avr
+
+
+Disassembly of section \.text:
+
+00000000 <__start1>:
+   0:	68 94       	set
+
+00000002 <__vec1_start>:
+   2:	0f 93       	push	r16
+   4:	0f b7       	in	r16, 0x3f	; 63
+   6:	0f 93       	push	r16
+   8:	21 30       	cpi	r18, 0x01	; 1
+   a:	0f 91       	pop	r16
+   c:	0f bf       	out	0x3f, r16	; 63
+   e:	0f 91       	pop	r16
+  10:	e8 94       	clt
+
+00000012 <__data1>:
+  12:	00 e0       	ldi	r16, 0x00	; 0
+  14:	08 00       	\.word	0x0008	; \?\?\?\?
+
+00000016 <__start2>:
+  16:	68 94       	set
+
+00000018 <__vec2_start>:
+  18:	1f 93       	push	r17
+  1a:	10 e0       	ldi	r17, 0x00	; 0
+  1c:	1f 91       	pop	r17
+  1e:	18 95       	reti
+  20:	e1 2f       	mov	r30, r17
+  22:	1f 91       	pop	r17
+  24:	18 95       	reti
+  26:	e8 94       	clt
+
+00000028 <__data2>:
+  28:	00 e0       	ldi	r16, 0x00	; 0
+  2a:	08 00       	\.word	0x0008	; \?\?\?\?
diff --git a/gas/testsuite/gas/avr/gccisr-02.s b/gas/testsuite/gas/avr/gccisr-02.s
new file mode 100644
index 0000000..167c42d1
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-02.s
@@ -0,0 +1,38 @@
+.text
+
+;;; Use SREG
+
+__start1:
+    set
+
+__vec1_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    cpi r18,1
+    __gcc_isr 2
+    __gcc_isr 0,r16
+    clt
+__vec1_end:
+__data1:
+    ldi r16, foo - 2
+    .word (__vec1_end - __vec1_start) / 2
+
+;;; Use ZERO
+
+__start2:
+    set
+
+__vec2_start:
+    __gcc_isr 1
+    foo = __gcc_isr.n_pushed
+    __gcc_isr 2
+    reti
+    mov r30,r17
+    __gcc_isr 2
+    reti
+    __gcc_isr 0,r16
+    clt
+__vec2_end:
+__data2:
+    ldi r16, foo - 1
+    .word (__vec2_end - __vec2_start) / 2
diff --git a/gas/testsuite/gas/avr/gccisr-03.d b/gas/testsuite/gas/avr/gccisr-03.d
new file mode 100644
index 0000000..0eaa28d
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-03.d
@@ -0,0 +1,4 @@
+#name: __gcc_isr pseudo instruction, test gccisr-03
+#as: 
+#error: pseudo instruction `__gcc_isr' not supported
+#target: avr-*-*
diff --git a/gas/testsuite/gas/avr/gccisr-03.s b/gas/testsuite/gas/avr/gccisr-03.s
new file mode 100644
index 0000000..39938c8
--- /dev/null
+++ b/gas/testsuite/gas/avr/gccisr-03.s
@@ -0,0 +1,6 @@
+.text
+
+;;; 
+
+__start1:
+    __gcc_isr 1