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authorPaul Brook <paul@codesourcery.com>2005-08-30 11:21:59 +0000
committerPaul Brook <paul@codesourcery.com>2005-08-30 11:21:59 +0000
commita2dfd01fa7b41122647b654d6abe936f6d3f610e (patch)
tree78122bfbfd23f8c9d3d9c4b9433d972bc189fa31 /gas/testsuite
parent8ec6eebb00dfd319a83c6ee23005d116aedb5e2c (diff)
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2005-08-30 Paul Brook <paul@codesourcery.com>
opcodes/ * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs. gas/testsuite/ * gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn". * gas/arm/thumb32.d: Ditto.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/arm/thumb.d4
-rw-r--r--gas/testsuite/gas/arm/thumb32.d8
3 files changed, 11 insertions, 6 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2bddc36..8769953 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-08-30 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
+ * gas/arm/thumb32.d: Ditto.
+
2005-08-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.s: Adjust.
diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
index 0002a7c..53ea6cc 100644
--- a/gas/testsuite/gas/arm/thumb.d
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -17,8 +17,8 @@ Disassembly of section \.text:
0+00e <[^>]+> 1008 asrs r0, r1, #32
0+010 <[^>]+> 18d1 adds r1, r2, r3
0+012 <[^>]+> 1ca2 adds r2, r4, #2
-0+014 <[^>]+> 1beb sub r3, r5, r7
-0+016 <[^>]+> 1fe2 sub r2, r4, #7
+0+014 <[^>]+> 1beb subs r3, r5, r7
+0+016 <[^>]+> 1fe2 subs r2, r4, #7
0+018 <[^>]+> 24ff movs r4, #255
0+01a <[^>]+> 2bfa cmp r3, #250
0+01c <[^>]+> 367b adds r6, #123
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 707f2da..2fa28c8 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -95,10 +95,10 @@ Disassembly of section .text:
0+13e <[^>]+> f1b0 0005 subs\.w r0, r0, #5 ; 0x5
0+142 <[^>]+> f1b0 0081 subs\.w r0, r0, #129 ; 0x81
0+146 <[^>]+> f1b0 0508 subs\.w r5, r0, #8 ; 0x8
-0+14a <[^>]+> 1a00 sub r0, r0, r0
-0+14c <[^>]+> 1a05 sub r5, r0, r0
-0+14e <[^>]+> 1a28 sub r0, r5, r0
-0+150 <[^>]+> 1b40 sub r0, r0, r5
+0+14a <[^>]+> 1a00 subs r0, r0, r0
+0+14c <[^>]+> 1a05 subs r5, r0, r0
+0+14e <[^>]+> 1a28 subs r0, r5, r0
+0+150 <[^>]+> 1b40 subs r0, r0, r5
0+152 <[^>]+> f5a0 7d82 sub\.w sp, r0, #260 ; 0x104
0+156 <[^>]+> f5ad 7d82 sub\.w sp, sp, #260 ; 0x104
0+15a <[^>]+> ebb8 0800 subs\.w r8, r8, r0