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authorAndrew Bennett <andrew.bennett@imgtec.com>2014-04-23 11:24:30 +0100
committerAndrew Bennett <andrew.bennett@imgtec.com>2014-04-23 13:01:18 +0100
commit7d64c587c15f290d228ca550bb288d53f0eb2ac4 (patch)
tree72600357f6d2371bd27de80b4e69a4216855293a /gas/testsuite
parentcd0449ab05e9045682a81bf521bd0c8732c98feb (diff)
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Add support for the MIPS eXtended Physical Address (XPA) ASE.
ChangeLog: binutils/ * doc/binutils.texi: Document the disassemble MIPS XPA instructions command line option. gas/ * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA. (md_longopts): Add xpa and no-xpa command line options. (mips_ases): Add MIPS XPA ASE. (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE. * doc/as.texinfo: Document the MIPS XPA command line options. * doc/c-mips.texi: Document the MIPS XPA command line options, and assembler directives. gas/testsuite/ * gas/mips/mips.exp: Add xpa tests. * gas/mips/xpa.s: New test. * gas/mips/xpa.d: Likewise. include/ * opcode/mips.h (ASE_XPA): New define. opcodes/ * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2 to allow the MIPS XPA ASE. (parse_mips_dis_option): Process the -Mxpa option. * mips-opc.c (XPA): New define. (mips_builtin_opcodes): Add MIPS XPA instructions and move the locations of the ctc0 and cfc0 instructions.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/mips/mips.exp2
-rw-r--r--gas/testsuite/gas/mips/xpa.d24
-rw-r--r--gas/testsuite/gas/mips/xpa.s29
4 files changed, 61 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 9b3d9c3..492450b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * gas/mips/mips.exp: Add xpa tests.
+ * gas/mips/xpa.s: New test.
+ * gas/mips/xpa.d: Likewise.
+
2014-04-22 Sandra Loosemore <sandra@codesourcery.com>
* gas/nios2/selftest.s: New.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 628f482..b0d8ac2 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1170,6 +1170,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2]
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
+
run_dump_test "pcrel-1"
run_dump_test "pcrel-2"
run_list_test "pcrel-3" "" "Invalid cross-section PC-relative references"
diff --git a/gas/testsuite/gas/mips/xpa.d b/gas/testsuite/gas/mips/xpa.d
new file mode 100644
index 0000000..f1047c9
--- /dev/null
+++ b/gas/testsuite/gas/mips/xpa.d
@@ -0,0 +1,24 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2
+#name: XPA instructions
+#as: -32 -mxpa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 40420800 mfhc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40428000 mfhc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 40420002 mfhc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40420007 mfhc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 40c20800 mthc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40c28000 mthc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 40c20002 mthc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40c20007 mthc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 40620c00 mfhgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40628400 mfhgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 40620402 mfhgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40620407 mfhgc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 40620e00 mthgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40628600 mthgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 40620602 mthgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40620607 mthgc0 v0,\$0,7
+ ...
diff --git a/gas/testsuite/gas/mips/xpa.s b/gas/testsuite/gas/mips/xpa.s
new file mode 100644
index 0000000..4d91f75
--- /dev/null
+++ b/gas/testsuite/gas/mips/xpa.s
@@ -0,0 +1,29 @@
+ .text
+ .set noat
+ .set noreorder
+ .set nomacro
+test_xpa:
+
+ mfhc0 $2, $1
+ mfhc0 $2, $16
+ mfhc0 $2, $0, 2
+ mfhc0 $2, $0, 7
+
+ mthc0 $2, $1
+ mthc0 $2, $16
+ mthc0 $2, $0, 2
+ mthc0 $2, $0, 7
+
+ mfhgc0 $2, $1
+ mfhgc0 $2, $16
+ mfhgc0 $2, $0, 2
+ mfhgc0 $2, $0, 7
+
+ mthgc0 $2, $1
+ mthgc0 $2, $16
+ mthgc0 $2, $0, 2
+ mthgc0 $2, $0, 7
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8