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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:16:39 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:19:42 +0000 |
commit | dd4a72c859a6896d6df824535590ccbb3631fdd7 (patch) | |
tree | 7999561fc2abf2203654a950546803413b3930b8 /gas/testsuite | |
parent | 82503ca7ed8301dc076919d5010bf981e35b1314 (diff) | |
download | gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.zip gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.gz gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.bz2 |
aarch64: Add CSR PDEC instruction
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr.d | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/csre_csr.s | 4 |
5 files changed, 23 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.d b/gas/testsuite/gas/aarch64/csre_csr-invalid.d new file mode 100644 index 0000000..bec71c8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.d @@ -0,0 +1,3 @@ +#name: CSR PDEC instruction +#source: csre_csr-invalid.s +#error_output: csre_csr-invalid.l diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.l b/gas/testsuite/gas/aarch64/csre_csr-invalid.l new file mode 100644 index 0000000..dec38ab --- /dev/null +++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `csr pdec' diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.s b/gas/testsuite/gas/aarch64/csre_csr-invalid.s new file mode 100644 index 0000000..e8520ba --- /dev/null +++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.s @@ -0,0 +1,4 @@ +/* CSR PDEC requires +csre for -march= command line option. */ +.arch armv8-a + + csr pdec diff --git a/gas/testsuite/gas/aarch64/csre_csr.d b/gas/testsuite/gas/aarch64/csre_csr.d new file mode 100644 index 0000000..c242f0a --- /dev/null +++ b/gas/testsuite/gas/aarch64/csre_csr.d @@ -0,0 +1,10 @@ +#name: CSRE extension CSR PDEC instruction +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: d50b721f csr pdec +.*: d50b721f csr pdec diff --git a/gas/testsuite/gas/aarch64/csre_csr.s b/gas/testsuite/gas/aarch64/csre_csr.s new file mode 100644 index 0000000..d0ac90f --- /dev/null +++ b/gas/testsuite/gas/aarch64/csre_csr.s @@ -0,0 +1,4 @@ +.arch armv8-a+csre + + csr pdec + CSR PDEC |