diff options
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:16 +0800 |
| commit | 3b374308d3006407b9571e573e4ccce4e904a4c4 (patch) | |
| tree | 96bfce86a830f793e0ef73924c4b3c1b3788b68a /gas/testsuite | |
| parent | 5fac3f02edacfca458f7eeaaaa33a87e26e0e332 (diff) | |
| download | gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.zip gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.gz gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.bz2 | |
RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/zicbop-fail.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zicbop-fail.l | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zicbop-fail.s | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zicbop.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zicbop.s | 4 |
5 files changed, 27 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d new file mode 100644 index 0000000..d734c7d --- /dev/null +++ b/gas/testsuite/gas/riscv/zicbop-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64g_zicbop +#source: zicbop-fail.s +#error_output: zicbop-fail.l diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l new file mode 100644 index 0000000..4b5d5fc --- /dev/null +++ b/gas/testsuite/gas/riscv/zicbop-fail.l @@ -0,0 +1,4 @@ +.*: Assembler messages: +.*: Error: improper prefetch offset \(2048\) +.*: Error: improper prefetch offset \(-2080\) +.*: Error: improper prefetch offset \(255\) diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s new file mode 100644 index 0000000..0353c5f --- /dev/null +++ b/gas/testsuite/gas/riscv/zicbop-fail.s @@ -0,0 +1,4 @@ +target: + prefetch.i 2048(x1) + prefetch.r -0x820(x16) + prefetch.w +0xff(x31) diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d new file mode 100644 index 0000000..056a8a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zicbop.d @@ -0,0 +1,12 @@ +#as: -march=rv64g_zicbop +#source: zicbop.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\) +[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\) +[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\) diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s new file mode 100644 index 0000000..ffe2014 --- /dev/null +++ b/gas/testsuite/gas/riscv/zicbop.s @@ -0,0 +1,4 @@ +target: + prefetch.i 0x20(x1) + prefetch.r -2048(x16) + prefetch.w +0x7e0(x31) |