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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-17 10:13:41 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-17 10:13:41 +0000
commitdb472d6ff0f438a21b357249a9b48e4b74498076 (patch)
tree89e4361f9af8995b4b1a3375bc119da4dd9ecb03 /gas/testsuite
parent8f8067050f5b34b2fb72d810d98206918281b67c (diff)
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2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/copro.d3
-rw-r--r--gas/testsuite/gas/arm/copro.s3
3 files changed, 11 insertions, 1 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2bd1bec..cd5f25c 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
+ * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
+ add disassembly for test added in copro.s
+
2010-09-17 Andrew Burgess <aburgess@broadcom.com>
PR gas/12011
diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
index e041270..d007c81 100644
--- a/gas/testsuite/gas/arm/copro.d
+++ b/gas/testsuite/gas/arm/copro.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
-0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\}
+0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
@@ -39,3 +39,4 @@ Disassembly of section .text:
0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
0+078 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
0+07c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+080 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s
index b9ef056..0ed0e05 100644
--- a/gas/testsuite/gas/arm/copro.s
+++ b/gas/testsuite/gas/arm/copro.s
@@ -44,3 +44,6 @@ bar:
# Extra instructions to allow for code alignment in arm-aout target.
nop
nop
+
+ # UAL-syntax for MRC with APSR. Pre-UAL was PC
+ mrcge p4, 5, APSR_nzcv, cr1, cr2, 7