aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
diff options
context:
space:
mode:
authorIgor Tsimbalist <igor.v.tsimbalist@intel.com>2016-11-02 12:31:25 -0700
committerH.J. Lu <hjl.tools@gmail.com>2016-11-02 12:31:25 -0700
commit47acf0bd9faef8634d242e19ec3b7f784d10ba76 (patch)
treed189fb03e209c2e35158d7bdc483f2fdfb67f239 /gas/testsuite
parent920d2ddccb72a366140ed28283165b274f7a9045 (diff)
downloadgdb-47acf0bd9faef8634d242e19ec3b7f784d10ba76.zip
gdb-47acf0bd9faef8634d242e19ec3b7f784d10ba76.tar.gz
gdb-47acf0bd9faef8634d242e19ec3b7f784d10ba76.tar.bz2
Enable Intel AVX512_4VNNIW instructions
gas/ * config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw. (cpu_noarch): Add noavx512_4vnniw. * doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw. * testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests. * testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test. * testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4VNNIW. * i386-opc.h (enum): (AVX512_4VNNIW): New. (i386_cpu_flags): Add cpuavx512_4vnniw. * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw-intel.d45
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw.d45
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw.s41
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d79
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw_vl.d79
-rw-r--r--gas/testsuite/gas/i386/avx512_4vnniw_vl.s75
-rw-r--r--gas/testsuite/gas/i386/i386.exp8
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d45
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d45
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s41
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d79
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d79
-rw-r--r--gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s75
13 files changed, 736 insertions, 0 deletions
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw-intel.d b/gas/testsuite/gas/i386/avx512_4vnniw-intel.d
new file mode 100644
index 0000000..ba4299a
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw-intel.d
@@ -0,0 +1,45 @@
+#objdump: -dw -Mintel
+#name: i386 AVX512/4VNNIW insns (Intel disassembly)
+#source: avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm4,XMMWORD PTR \[edx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw.d b/gas/testsuite/gas/i386/avx512_4vnniw.d
new file mode 100644
index 0000000..919f31e
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw.d
@@ -0,0 +1,45 @@
+#objdump: -dw
+#name: i386 AVX512/4VNNIW insns
+#source: avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 52 09[ ]*vp4dpwssd \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 4f 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f cf 53 09[ ]*vp4dpwssds \(%ecx\),%zmm4,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%zmm4,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%zmm4,%zmm1
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw.s b/gas/testsuite/gas/i386/avx512_4vnniw.s
new file mode 100644
index 0000000..a67d854
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw.s
@@ -0,0 +1,41 @@
+# Check 32bit AVX512_4VNNIW instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vp4dpwssd (%ecx), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd (%ecx), %zmm4, %zmm1{%k7} # AVX512_4VNNIW
+ vp4dpwssd (%ecx), %zmm4, %zmm1{%k7}{z} # AVX512_4VNNIW
+ vp4dpwssd -123456(%esp,%esi,8), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd 4064(%edx), %zmm4, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssd 4096(%edx), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd -4096(%edx), %zmm4, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssd -4128(%edx), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds (%ecx), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds (%ecx), %zmm4, %zmm1{%k7} # AVX512_4VNNIW
+ vp4dpwssds (%ecx), %zmm4, %zmm1{%k7}{z} # AVX512_4VNNIW
+ vp4dpwssds -123456(%esp,%esi,8), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds 4064(%edx), %zmm4, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssds 4096(%edx), %zmm4, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds -4096(%edx), %zmm4, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssds -4128(%edx), %zmm4, %zmm1 # AVX512_4VNNIW
+
+ .intel_syntax noprefix
+ vp4dpwssd zmm1, zmm4, [ecx] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssd zmm1{k7}, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssd zmm1{k7}{z}, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [edx+4064] # AVX512_4VNNIW Disp8
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [edx+4096] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [edx-4096] # AVX512_4VNNIW Disp8
+ vp4dpwssd zmm1, zmm4, XMMWORD PTR [edx-4128] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm4, [ecx] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssds zmm1{k7}, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssds zmm1{k7}{z}, zmm4, XMMWORD PTR [ecx] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [edx+4064] # AVX512_4VNNIW Disp8
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [edx+4096] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [edx-4096] # AVX512_4VNNIW Disp8
+ vp4dpwssds zmm1, zmm4, XMMWORD PTR [edx-4128] # AVX512_4VNNIW
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d b/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d
new file mode 100644
index 0000000..a7d3ed9
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl-intel.d
@@ -0,0 +1,79 @@
+#objdump: -dw -Mintel
+#name: i386 AVX512/4VNNIW_VL insns (Intel disassembly)
+#source: avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm4,XMMWORD PTR \[edx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm4,XMMWORD PTR \[edx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl.d b/gas/testsuite/gas/i386/avx512_4vnniw_vl.d
new file mode 100644
index 0000000..e796321
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl.d
@@ -0,0 +1,79 @@
+#objdump: -dw
+#name: i386 AVX512/4VNNIW_VL insns
+#source: avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 52 09[ ]*vp4dpwssd \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 52 09[ ]*vp4dpwssd \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8c f4 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 0f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 8f 53 09[ ]*vp4dpwssds \(%ecx\),%xmm4,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%xmm4,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 2f 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f af 53 09[ ]*vp4dpwssds \(%ecx\),%ymm4,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8c f4 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%esp,%esi,8\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%edx\),%ymm4,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 5f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%edx\),%ymm4,%ymm1
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_4vnniw_vl.s b/gas/testsuite/gas/i386/avx512_4vnniw_vl.s
new file mode 100644
index 0000000..dfdd485
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw_vl.s
@@ -0,0 +1,75 @@
+# Check 32bit AVX512{_4VNNIW,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vp4dpwssd (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssd -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssd -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssds -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssds -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL}
+
+ .intel_syntax noprefix
+ vp4dpwssd xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 89e132a..11c342a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -363,6 +363,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx512_4fmaps_vl-intel"
run_list_test "avx512_4fmaps-warn"
run_list_test "avx512_4fmaps_vl-warn"
+ run_dump_test "avx512_4vnniw"
+ run_dump_test "avx512_4vnniw-intel"
+ run_dump_test "avx512_4vnniw_vl"
+ run_dump_test "avx512_4vnniw_vl-intel"
run_dump_test "clzero"
run_dump_test "disassem"
run_dump_test "mwaitx-bdver4"
@@ -771,6 +775,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx512_4fmaps_vl-intel"
run_list_test "x86-64-avx512_4fmaps-warn"
run_list_test "x86-64-avx512_4fmaps_vl-warn"
+ run_dump_test "x86-64-avx512_4vnniw"
+ run_dump_test "x86-64-avx512_4vnniw-intel"
+ run_dump_test "x86-64-avx512_4vnniw_vl"
+ run_dump_test "x86-64-avx512_4vnniw_vl-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d
new file mode 100644
index 0000000..2165353
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw-intel.d
@@ -0,0 +1,45 @@
+#objdump: -dw -Mintel
+#name: x86_64 AVX512/4VNNIW insns (Intel disassembly)
+#source: x86-64-avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d
new file mode 100644
index 0000000..1938cfe
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.d
@@ -0,0 +1,45 @@
+#objdump: -dw
+#name: x86_64 AVX512/4VNNIW insns
+#source: x86-64-avx512_4vnniw.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s
new file mode 100644
index 0000000..b4295f9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw.s
@@ -0,0 +1,41 @@
+# Check 64bit AVX512_4VNNIW instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vp4dpwssd (%rcx), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd (%rcx), %zmm8, %zmm1{%k7} # AVX512_4VNNIW
+ vp4dpwssd (%rcx), %zmm8, %zmm1{%k7}{z} # AVX512_4VNNIW
+ vp4dpwssd -123456(%rax,%r14,8), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd 4064(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssd 4096(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssd -4096(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssd -4128(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds (%rcx), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds (%rcx), %zmm8, %zmm1{%k7} # AVX512_4VNNIW
+ vp4dpwssds (%rcx), %zmm8, %zmm1{%k7}{z} # AVX512_4VNNIW
+ vp4dpwssds -123456(%rax,%r14,8), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds 4064(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssds 4096(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW
+ vp4dpwssds -4096(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW Disp8
+ vp4dpwssds -4128(%rdx), %zmm8, %zmm1 # AVX512_4VNNIW
+
+ .intel_syntax noprefix
+ vp4dpwssd zmm1, zmm8, [rcx] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssd zmm1{k7}, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssd zmm1{k7}{z}, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rdx+4064] # AVX512_4VNNIW Disp8
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rdx+4096] # AVX512_4VNNIW
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rdx-4096] # AVX512_4VNNIW Disp8
+ vp4dpwssd zmm1, zmm8, XMMWORD PTR [rdx-4128] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm8, [rcx] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssds zmm1{k7}, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssds zmm1{k7}{z}, zmm8, XMMWORD PTR [rcx] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rdx+4064] # AVX512_4VNNIW Disp8
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rdx+4096] # AVX512_4VNNIW
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rdx-4096] # AVX512_4VNNIW Disp8
+ vp4dpwssds zmm1, zmm8, XMMWORD PTR [rdx-4128] # AVX512_4VNNIW
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d
new file mode 100644
index 0000000..d4a7a95
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d
@@ -0,0 +1,79 @@
+#objdump: -dw -Mintel
+#name: x86_64 AVX512/4VNNIW_VL insns (Intel disassembly)
+#source: x86-64-avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds xmm1\{k7\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds xmm1\{k7\}\{z\},xmm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds xmm1,xmm8,XMMWORD PTR \[rdx-0x1020\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds ymm1\{k7\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds ymm1\{k7\}\{z\},ymm8,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds ymm1,ymm8,XMMWORD PTR \[rdx-0x1020\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d
new file mode 100644
index 0000000..df0f522
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d
@@ -0,0 +1,79 @@
+#objdump: -dw
+#name: x86_64 AVX512/4VNNIW_VL insns
+#source: x86-64-avx512_4vnniw_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 52 09[ ]*vp4dpwssd \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 52 09[ ]*vp4dpwssd \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 0f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 8f 53 09[ ]*vp4dpwssds \(%rcx\),%xmm8,%xmm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 08 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 08 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%xmm8,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 2f 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 3f af 53 09[ ]*vp4dpwssds \(%rcx\),%ymm8,%ymm1\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 b2 3f 28 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%ymm8,%ymm1
+[ ]*[a-f0-9]+:[ ]*62 f2 3f 28 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%ymm8,%ymm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s
new file mode 100644
index 0000000..5f1a046
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s
@@ -0,0 +1,75 @@
+# Check 64bit AVX512{_4VNNIW,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vp4dpwssd (%rcx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssd -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd 4064(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd 4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd -4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd -4128(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%rcx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssd (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssd -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd 4064(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd 4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssd -4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd -4128(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %xmm8, %xmm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %xmm8, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssds -123456(%rax,%r14,8), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds 4064(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds 4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds -4096(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds -4128(%rdx), %xmm8, %xmm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %ymm8, %ymm1{%k7} # AVX512{_4VNNIW,VL}
+ vp4dpwssds (%rcx), %ymm8, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL}
+ vp4dpwssds -123456(%rax,%r14,8), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds 4064(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds 4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+ vp4dpwssds -4096(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds -4128(%rdx), %ymm8, %ymm1 # AVX512{_4VNNIW,VL}
+
+ .intel_syntax noprefix
+ vp4dpwssd xmm1, xmm8, [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd xmm1, xmm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm8, [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssd ymm1, ymm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm8, [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1{k7}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1{k7}{z}, xmm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds xmm1, xmm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm8, [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1{k7}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1{k7}{z}, ymm8, XMMWORD PTR [rcx] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rax+r14*8-123456] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx+4064] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx+4096] # AVX512{_4VNNIW,VL}
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx-4096] # AVX512{_4VNNIW,VL} Disp8
+ vp4dpwssds ymm1, ymm8, XMMWORD PTR [rdx-4128] # AVX512{_4VNNIW,VL}