Add clwb instruction

gas/

	* config/tc-i386.c (cpu_arch): Add .clwb.
	* doc/c-i386.texi: Document it.

opcodes/
	* i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
	(prefix_table): Add clwb.
	* i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
	(cpu_flags): Add CpuCLWB.
	* i386-opc.h (enum): Add CpuCLWB.
	(i386_cpu_flags): Add cpuclwb.
	* i386-opc.tbl: Add clwb.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

gas/testsuite/

	* gas/i386/i386.exp: Run new tests.
	* gas/i386/clwb-intel.d: New file.
	* gas/i386/clwb.d: Likewise.
	* gas/i386/clwb.s: Likewise.
	* gas/i386/x86-64-clwb-intel.d: Likewise.
	* gas/i386/x86-64-clwb.d: Likewise.
	* gas/i386/x86-64-clwb.s: Likewise.

8 files changed, 102 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7908363..6fa1604 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+	* gas/i386/i386.exp: Run new tests.
+	* gas/i386/clwb-intel.d: New file.
+	* gas/i386/clwb.d: Likewise.
+	* gas/i386/clwb.s: Likewise.
+	* gas/i386/x86-64-clwb-intel.d: Likewise.
+	* gas/i386/x86-64-clwb.d: Likewise.
+	* gas/i386/x86-64-clwb.s: Likewise.
+
 2014-11-13  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/17598
diff --git a/gas/testsuite/gas/i386/clwb-intel.d b/gas/testsuite/gas/i386/clwb-intel.d
new file mode 100644
index 0000000..395f4c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/clwb-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 CLWB insns (Intel disassembly)
+#source: clwb.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae b4 f4 c0 1d fe ff[ 	]*clwb   BYTE PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae b4 f4 c0 1d fe ff[ 	]*clwb   BYTE PTR \[esp\+esi\*8-0x1e240\]
+#pass
diff --git a/gas/testsuite/gas/i386/clwb.d b/gas/testsuite/gas/i386/clwb.d
new file mode 100644
index 0000000..aa2a2be
--- /dev/null
+++ b/gas/testsuite/gas/i386/clwb.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dw
+#name: i386 CLWB insns
+#source: clwb.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   \(%ecx\)
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae b4 f4 c0 1d fe ff[ 	]*clwb   -0x1e240\(%esp,%esi,8\)
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   \(%ecx\)
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae b4 f4 c0 1d fe ff[ 	]*clwb   -0x1e240\(%esp,%esi,8\)
+#pass
diff --git a/gas/testsuite/gas/i386/clwb.s b/gas/testsuite/gas/i386/clwb.s
new file mode 100644
index 0000000..8132218
--- /dev/null
+++ b/gas/testsuite/gas/i386/clwb.s
@@ -0,0 +1,12 @@
+# Check 32bit CLWB instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+	clwb	(%ecx)	 # CLWB
+	clwb	-123456(%esp,%esi,8)	 # CLWB
+
+	.intel_syntax noprefix
+	clwb	BYTE PTR [ecx]	 # CLWB
+	clwb	BYTE PTR [esp+esi*8-123456]	 # CLWB
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index c55f3bf..4d85105 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -330,6 +330,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx512f-rcigru"
     run_dump_test "avx512f-rcigrz-intel"
     run_dump_test "avx512f-rcigrz"
+    run_dump_test "clwb"
+    run_dump_test "clwb-intel"
     run_dump_test "disassem"
 
     # These tests require support for 8 and 16 bit relocs,
@@ -681,6 +683,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx512f-rcigru"
     run_dump_test "x86-64-avx512f-rcigrz-intel"
     run_dump_test "x86-64-avx512f-rcigrz"
+    run_dump_test "x86-64-clwb"
+    run_dump_test "x86-64-clwb-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/x86-64-clwb-intel.d b/gas/testsuite/gas/i386/x86-64-clwb-intel.d
new file mode 100644
index 0000000..5995c78
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-clwb-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 CLWB insns (Intel disassembly)
+#source: x86-64-clwb.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*66 42 0f ae b4 f0 23 01 00 00[ 	]*clwb   BYTE PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*66 42 0f ae b4 f0 34 12 00 00[ 	]*clwb   BYTE PTR \[rax\+r14\*8\+0x1234\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-clwb.d b/gas/testsuite/gas/i386/x86-64-clwb.d
new file mode 100644
index 0000000..eee47dd
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-clwb.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dw
+#name: x86_64 CLWB insns
+#source: x86-64-clwb.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   \(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]*66 42 0f ae b4 f0 23 01 00 00[ 	]*clwb   0x123\(%rax,%r14,8\)
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae 31[ 	]*clwb   \(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]*66 42 0f ae b4 f0 34 12 00 00[ 	]*clwb   0x1234\(%rax,%r14,8\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-clwb.s b/gas/testsuite/gas/i386/x86-64-clwb.s
new file mode 100644
index 0000000..817fe9e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-clwb.s
@@ -0,0 +1,12 @@
+# Check 64bit CLWB instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+	clwb	(%rcx)	 # CLWB
+	clwb	0x123(%rax,%r14,8)	 # CLWB
+
+	.intel_syntax noprefix
+	clwb	BYTE PTR [rcx]	 # CLWB
+	clwb	BYTE PTR [rax+r14*8+0x1234]	 # CLWB