Support ARM Cortex-M7

include/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro.
	(FPU_VFP_V5D16): Likewise.
	(FPU_VFP_V5_SP_D16): Likewise.
	(FPU_ARCH_VFP_V5D16): Likewise.
	(FPU_ARCH_VFP_V5_SP_D16): Likewise.

bfd/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5.

binutils/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5.

gas/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
	(arm_cpus): Support cortex-m7.
	(arm_fpus): Support fpv5-sp-d16 and fpv5-d16.
	(do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S
	register only target like FPv5-SP-D16.
	(do_neon_cvttb_1): Likewise.
	(do_vfp_nsyn_fpv8): Likewise.
	(do_vrint_1): Likewise.
	(aeabi_set_public_attributes): Set proper FP arch for FPv5.
	* doc/c-arm.texi: Document new cpu and fpu names for cortex-m7.

gas/testsuite/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* gas/arm/armv7e-m+fpv5-d16.s: New.
	* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
	* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
	* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.

ld/testsuite/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
	* ld-arm/attr-merge-vfp-5-sp.s: Likewise.
	* ld-arm/attr-merge-vfp-5.s: Likewise.
	* ld-arm/attr-merge-vfp-8.d: New test.
	* ld-arm/attr-merge-vfp-8r.d: Likewise.
	* ld-arm/attr-merge-vfp-9.d: Likewise.
	* ld-arm/attr-merge-vfp-9r.d: Likewise.
	* ld-arm/attr-merge-vfp-10.d: Likewise.
	* ld-arm/attr-merge-vfp-10r.d: Likewise.
	* ld-arm/attr-merge-vfp-11.d: Likewise.
	* ld-arm/attr-merge-vfp-11r.d: Likewise.
	* ld-arm/attr-merge-vfp-12.d: Likewise.
	* ld-arm/attr-merge-vfp-12r.d: Likewise.
	* ld-arm/attr-merge-vfp-13.d: Likewise.
	* ld-arm/attr-merge-vfp-13r.d: Likewise.
	* ld-arm/attr-merge-vfp-14.d: Likewise.
	* ld-arm/attr-merge-vfp-14r.d: Likewise.
	* ld-arm/arm-elf.exp: Run the new tests.

5 files changed, 184 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 51119a2..59af872 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2014-11-21  Terry Guo  <terry.guo@arm.com>
+
+	* gas/arm/armv7e-m+fpv5-d16.s: New.
+	* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
+	* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
+	* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.
+
 2014-11-19  Ryan Mansfield  <rmansfield@qnx.com>
 
 	* gas/aarch64/diagnostic.s: Add new warnings test patterns.
diff --git a/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.d b/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.d
new file mode 100644
index 0000000..2951b1b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.d
@@ -0,0 +1,60 @@
+#name: Valid v7e-m+fpv5-d16
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe00 0b00 	vseleq.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe18 8b08 	vselvs.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe2f fb0f 	vselge.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe3a ab0a 	vselgt.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 	vmaxnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b08 	vmaxnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb0f 	vmaxnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab0a 	vmaxnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 	vminnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b48 	vminnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb4f 	vminnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab4a 	vminnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> febc 0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0bc8 	vcvtn.s32.f64	s1, d8
+0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
+0[0-9a-f]+ <[^>]+> feff fb4a 	vcvtm.u32.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> eeb6 ab4a 	vrintr.f64	d10, d10
+0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> feba ab4a 	vrintp.f64	d10, d10
+0[0-9a-f]+ <[^>]+> febb ab4a 	vrintm.f64	d10, d10
+0[0-9a-f]+ <[^>]+> eeb3 0bc0 	vcvtt.f16.f64	s0, d0
+0[0-9a-f]+ <[^>]+> eef3 0b48 	vcvtb.f16.f64	s1, d8
+0[0-9a-f]+ <[^>]+> eeb3 fbcf 	vcvtt.f16.f64	s30, d15
+0[0-9a-f]+ <[^>]+> eef3 fb4a 	vcvtb.f16.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb2 0bc0 	vcvtt.f64.f16	d0, s0
+0[0-9a-f]+ <[^>]+> eeb2 8b60 	vcvtb.f64.f16	d8, s1
+0[0-9a-f]+ <[^>]+> eeb2 fbcf 	vcvtt.f64.f16	d15, s30
+0[0-9a-f]+ <[^>]+> eeb2 ab6f 	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s b/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s
new file mode 100644
index 0000000..06fba06
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s
@@ -0,0 +1,60 @@
+	.syntax unified
+	.text
+	.arch armv7e-m
+	.fpu fpv5-d16
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vseleq.f64	d0, d0, d0
+	vselvs.f64	d8, d8, d8
+	vselge.f64	d15, d15, d15
+	vselgt.f64	d10, d10, d10
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vmaxnm.f64	d0, d0, d0
+	vmaxnm.f64	d8, d8, d8
+	vmaxnm.f64	d15, d15, d15
+	vmaxnm.f64	d10, d10, d10
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vminnm.f64	d0, d0, d0
+	vminnm.f64	d8, d8, d8
+	vminnm.f64	d15, d15, d15
+	vminnm.f64	d10, d10, d10
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vcvta.s32.f64	s0, d0
+	vcvtn.s32.f64	s1, d8
+	vcvtp.u32.f64	s30, d15
+	vcvtm.u32.f64	s31, d10
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
+	vrintz.f64	d0, d0
+        vrintx.f64	d1, d1
+        vrintr.f64	d10, d10
+	vrinta.f64	d0, d0
+	vrintn.f64	d1, d1
+	vrintp.f64	d10, d10
+	vrintm.f64	d10, d10
+	vcvtt.f16.f64	s0, d0
+	vcvtb.f16.f64	s1, d8
+	vcvtt.f16.f64	s30, d15
+	vcvtb.f16.f64	s31, d10
+	vcvtt.f64.f16	d0, s0
+	vcvtb.f64.f16	d8, s1
+	vcvtt.f64.f16	d15, s30
+	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.d b/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.d
new file mode 100644
index 0000000..84ed3b0
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.d
@@ -0,0 +1,28 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
diff --git a/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.s b/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.s
new file mode 100644
index 0000000..0fee290
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv7e-m+fpv5-sp-d16.s
@@ -0,0 +1,29 @@
+	.syntax unified
+	.text
+	.arch armv7e-m
+	.fpu fpv5-sp-d16
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31