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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-05-03 13:43:44 +0100 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-05-18 22:22:49 +0100 |
| commit | 3b889a787863d22694bb53eb08160c94ab52c58d (patch) | |
| tree | 3daf3579bfc29fe642bf90aa804a06dd452c416d /gas/testsuite | |
| parent | 45f4ed92d14ddf891be1470556f53de6c94c8dc2 (diff) | |
| download | gdb-3b889a787863d22694bb53eb08160c94ab52c58d.zip gdb-3b889a787863d22694bb53eb08160c94ab52c58d.tar.gz gdb-3b889a787863d22694bb53eb08160c94ab52c58d.tar.bz2 | |
gas/arc: Add guard against operand array overflow.
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.
This change checks that we don't access outside the limits of the
operand array.
gas/ChangeLog:
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/arc/asm-errors.err | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/asm-errors.s | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arc/asm-errors.err b/gas/testsuite/gas/arc/asm-errors.err index 35390fc..e889eb8 100644 --- a/gas/testsuite/gas/arc/asm-errors.err +++ b/gas/testsuite/gas/arc/asm-errors.err @@ -2,3 +2,5 @@ [^:]*:2: Error: inappropriate arguments for opcode 'adc' [^:]*:3: Error: inappropriate arguments for opcode 'adc' [^:]*:4: Error: inappropriate arguments for opcode 'adc' +[^:]*:5: Error: extra comma +[^:]*:5: Error: syntax error diff --git a/gas/testsuite/gas/arc/asm-errors.s b/gas/testsuite/gas/arc/asm-errors.s index 6e0fd6a..d3f16c0 100644 --- a/gas/testsuite/gas/arc/asm-errors.s +++ b/gas/testsuite/gas/arc/asm-errors.s @@ -2,3 +2,4 @@ adc.al.ra r0,r0,r2 adc.eq.eq r0,r0,r2 adc.n.eq r0,r0,r2 + add r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0,r0 |