gas/

	* config/bfin-defs.h (IS_GENREG): Define.
	(IS_DAGREG): Define.
	(IS_SYSREG): Define.
	* config/bfin-parse.y (asm_1): Check illegal register move
	instructions.

	gas/testsuite/
	* gas/bfin/expected_move_errors.s,
	gas/bfin/expected_move_errors.l: Add "LC1 = I0;".
	* gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W".

	opcodes/
	* bfin-dis.c (IS_DREG): Define.
	(IS_PREG): Define.
	(IS_AREG): Define.
	(IS_GENREG): Define.
	(IS_DAGREG): Define.
	(IS_SYSREG): Define.
	(decode_REGMV_0): Check illegal register move instructions.

5 files changed, 55 insertions, 48 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 13c8333..0c8b3e4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,11 @@
 2009-09-03  Jie Zhang  <jie.zhang@analog.com>
 
+	* gas/bfin/expected_move_errors.s,
+	gas/bfin/expected_move_errors.l: Add "LC1 = I0;".
+	* gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W".
+
+2009-09-03  Jie Zhang  <jie.zhang@analog.com>
+
 	* gas/bfin/expected_comparison_errors.l: Expect error on Line 13.
 
 2009-09-03  Jie Zhang  <jie.zhang@analog.com>
diff --git a/gas/testsuite/gas/bfin/expected_move_errors.l b/gas/testsuite/gas/bfin/expected_move_errors.l
index 9b8b1aa..9a98746 100644
--- a/gas/testsuite/gas/bfin/expected_move_errors.l
+++ b/gas/testsuite/gas/bfin/expected_move_errors.l
@@ -3,3 +3,4 @@
 .*:4: Error: Cannot move A0 to high half of register. Input text was A0.
 .*:5: Error: Cannot move A1 to even register.
 .*:6: Error: Cannot move A0 to odd register.
+.*:7: Error: Register mismatch.
diff --git a/gas/testsuite/gas/bfin/expected_move_errors.s b/gas/testsuite/gas/bfin/expected_move_errors.s
index d73525f..91f5578 100644
--- a/gas/testsuite/gas/bfin/expected_move_errors.s
+++ b/gas/testsuite/gas/bfin/expected_move_errors.s
@@ -4,3 +4,4 @@
 	R0.H = A0;
 	R0 = A1;
 	R1 = A0;
+	LC1 = I0;
diff --git a/gas/testsuite/gas/bfin/move.d b/gas/testsuite/gas/bfin/move.d
index 1a83e25..d81f81f 100644
--- a/gas/testsuite/gas/bfin/move.d
+++ b/gas/testsuite/gas/bfin/move.d
@@ -27,56 +27,56 @@ Disassembly of section .text:
   26:	96 31       	R2 = CYCLES;
   28:	9f 31       	R3 = CYCLES2;
   2a:	cf 31       	R1 = EMUDAT;
-  2c:	31 3d       	CYCLES = A0.W;
-  2e:	7f 38       	RETS = FP;
-  30:	e0 3d       	LT1 = USP;
-  32:	72 38       	ASTAT = P2;
-  34:	08 c4 [0|3][0|f] c0 	A0 = A1;
-  38:	08 c4 [0|3][0|f] e0 	A1 = A0;
-  3c:	09 c4 00 20 	A0 = R0;
-  40:	09 c4 08 a0 	A1 = R1;
-  44:	8b c0 00 39 	R4 = A0 \(FU\);
-  48:	2f c1 00 19 	R5 = A1 \(ISS2\);
-  4c:	0b c0 80 39 	R6 = A0;
-  50:	0f c0 80 19 	R7 = A1;
-  54:	0f c0 80 39 	R7 = A1, R6 = A0;
-  58:	8f c0 00 38 	R1 = A1, R0 = A0 \(FU\);
+  2c:	7f 38       	RETS = FP;
+  2e:	e0 3d       	LT1 = USP;
+  30:	72 38       	ASTAT = P2;
+  32:	08 c4 [0|3][0|f] c0 	A0 = A1;
+  36:	08 c4 [0|3][0|f] e0 	A1 = A0;
+  3a:	09 c4 00 20 	A0 = R0;
+  3e:	09 c4 08 a0 	A1 = R1;
+  42:	8b c0 00 39 	R4 = A0 \(FU\);
+  46:	2f c1 00 19 	R5 = A1 \(ISS2\);
+  4a:	0b c0 80 39 	R6 = A0;
+  4e:	0f c0 80 19 	R7 = A1;
+  52:	0f c0 80 39 	R7 = A1, R6 = A0;
+  56:	8f c0 00 38 	R1 = A1, R0 = A0 \(FU\);
 
-0000005c <move_conditional>:
-  5c:	6a 07       	IF CC R5 = P2;
-  5e:	b0 06       	IF !CC SP = R0;
+0000005a <move_conditional>:
+  5a:	6a 07       	IF CC R5 = P2;
+  5c:	b0 06       	IF !CC SP = R0;
 
-00000060 <move_half_to_full_zero_extend>:
-  60:	fa 42       	R2 = R7.L \(Z\);
-  62:	c8 42       	R0 = R1.L \(Z\);
+0000005e <move_half_to_full_zero_extend>:
+  5e:	fa 42       	R2 = R7.L \(Z\);
+  60:	c8 42       	R0 = R1.L \(Z\);
 
-00000064 <move_half_to_full_sign_extend>:
-  64:	8d 42       	R5 = R1.L \(X\);
-  66:	93 42       	R3 = R2.L \(X\);
+00000062 <move_half_to_full_sign_extend>:
+  62:	8d 42       	R5 = R1.L \(X\);
+  64:	93 42       	R3 = R2.L \(X\);
 
-00000068 <move_register_half>:
-  68:	09 c4 28 40 	A0.X = R5.L;
-  6c:	09 c4 10 c0 	A1.X = R2.L;
-  70:	0a c4 [0|3][0|6] 00 	R0.L = A0.X;
-  74:	0a c4 [0|3][0|6] 4e 	R7.L = A1.X;
-  78:	09 c4 18 00 	A0.L = R3.L;
-  7c:	09 c4 20 80 	A1.L = R4.L;
-  80:	29 c4 30 00 	A0.H = R6.H;
-  84:	29 c4 28 80 	A1.H = R5.H;
-  88:	83 c1 00 38 	R0.L = A0 \(IU\);
-  8c:	27 c0 40 18 	R1.H = A1 \(S2RND\);
-  90:	07 c0 40 18 	R1.H = A1;
-  94:	67 c1 80 38 	R2.H = A1, R2.L = A0 \(IH\);
-  98:	07 c0 80 38 	R2.H = A1, R2.L = A0;
-  9c:	47 c0 00 38 	R0.H = A1, R0.L = A0 \(T\);
-  a0:	87 c0 00 38 	R0.H = A1, R0.L = A0 \(FU\);
-  a4:	07 c1 00 38 	R0.H = A1, R0.L = A0 \(IS\);
-  a8:	07 c0 00 38 	R0.H = A1, R0.L = A0;
+00000066 <move_register_half>:
+  66:	09 c4 28 40 	A0.X = R5.L;
+  6a:	09 c4 10 c0 	A1.X = R2.L;
+  6e:	0a c4 [0|3][0|6] 00 	R0.L = A0.X;
+  72:	0a c4 [0|3][0|6] 4e 	R7.L = A1.X;
+  76:	09 c4 18 00 	A0.L = R3.L;
+  7a:	09 c4 20 80 	A1.L = R4.L;
+  7e:	29 c4 30 00 	A0.H = R6.H;
+  82:	29 c4 28 80 	A1.H = R5.H;
+  86:	83 c1 00 38 	R0.L = A0 \(IU\);
+  8a:	27 c0 40 18 	R1.H = A1 \(S2RND\);
+  8e:	07 c0 40 18 	R1.H = A1;
+  92:	67 c1 80 38 	R2.H = A1, R2.L = A0 \(IH\);
+  96:	07 c0 80 38 	R2.H = A1, R2.L = A0;
+  9a:	47 c0 00 38 	R0.H = A1, R0.L = A0 \(T\);
+  9e:	87 c0 00 38 	R0.H = A1, R0.L = A0 \(FU\);
+  a2:	07 c1 00 38 	R0.H = A1, R0.L = A0 \(IS\);
+  a6:	07 c0 00 38 	R0.H = A1, R0.L = A0;
 
-000000ac <move_byte_zero_extend>:
-  ac:	57 43       	R7 = R2.B \(Z\);
-  ae:	48 43       	R0 = R1.B \(Z\);
+000000aa <move_byte_zero_extend>:
+  aa:	57 43       	R7 = R2.B \(Z\);
+  ac:	48 43       	R0 = R1.B \(Z\);
 
-000000b0 <move_byte_sign_extend>:
-  b0:	4e 43       	R6 = R1.B \(Z\);
-  b2:	65 43       	R5 = R4.B \(Z\);
+000000ae <move_byte_sign_extend>:
+  ae:	4e 43       	R6 = R1.B \(Z\);
+  b0:	65 43       	R5 = R4.B \(Z\);
+	...
diff --git a/gas/testsuite/gas/bfin/move.s b/gas/testsuite/gas/bfin/move.s
index 2533671..7eee721 100644
--- a/gas/testsuite/gas/bfin/move.s
+++ b/gas/testsuite/gas/bfin/move.s
@@ -23,7 +23,6 @@ move_register:
 	R2 = Cycles;
 	R3 = Cycles2;
 	r1 = emudat;
-	CYCLES = A0.W;
 	Rets = Fp;
 	Lt1 = USP;
 	ASTAT = P2;