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author | Matthew Wahab <matthew.wahab@arm.com> | 2016-04-20 09:31:49 +0100 |
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committer | Matthew Wahab <matthew.wahab@arm.com> | 2016-04-20 09:31:49 +0100 |
commit | 50cc854c48e79d9b8a2c55c117918d6a719bea38 (patch) | |
tree | 79f5f25f2936ba4594c08a7475bede0e0b2cf19a /gas/testsuite | |
parent | 87d455c042d2236b2afb1d6e13f337df36256bb0 (diff) | |
download | gdb-50cc854c48e79d9b8a2c55c117918d6a719bea38.zip gdb-50cc854c48e79d9b8a2c55c117918d6a719bea38.tar.gz gdb-50cc854c48e79d9b8a2c55c117918d6a719bea38.tar.bz2 |
[AArch64] Support RAS extension for ARMv8 onwards.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.
This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.
gas/
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/gas/aarch64/armv8-ras-1.d | 68 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/armv8-ras-1.s | 73 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ras-1.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ras-1.l | 39 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ras-1.s | 52 |
5 files changed, 236 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/armv8-ras-1.d b/gas/testsuite/gas/aarch64/armv8-ras-1.d new file mode 100644 index 0000000..69db3c2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8-ras-1.d @@ -0,0 +1,68 @@ +#as: -march=armv8-a+ras +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: +[^:]+: d503221f esb +[^:]+: d503221f esb +[^:]+: d5385305 mrs x5, erridr_el1 +[^:]+: d5185327 msr errselr_el1, x7 +[^:]+: d5385327 mrs x7, errselr_el1 +[^:]+: d5385405 mrs x5, erxfr_el1 +[^:]+: d5185425 msr erxctlr_el1, x5 +[^:]+: d5385425 mrs x5, erxctlr_el1 +[^:]+: d5185445 msr erxstatus_el1, x5 +[^:]+: d5385445 mrs x5, erxstatus_el1 +[^:]+: d5185465 msr erxaddr_el1, x5 +[^:]+: d5385465 mrs x5, erxaddr_el1 +[^:]+: d5185505 msr erxmisc0_el1, x5 +[^:]+: d5385505 mrs x5, erxmisc0_el1 +[^:]+: d5185525 msr erxmisc1_el1, x5 +[^:]+: d5385525 mrs x5, erxmisc1_el1 +[^:]+: d53c5265 mrs x5, vsesr_el2 +[^:]+: d518c125 msr disr_el1, x5 +[^:]+: d538c125 mrs x5, disr_el1 +[^:]+: d53cc125 mrs x5, vdisr_el2 +[^:]+: d503221f esb +[^:]+: d503221f esb +[^:]+: d5385305 mrs x5, erridr_el1 +[^:]+: d5185327 msr errselr_el1, x7 +[^:]+: d5385327 mrs x7, errselr_el1 +[^:]+: d5385405 mrs x5, erxfr_el1 +[^:]+: d5185425 msr erxctlr_el1, x5 +[^:]+: d5385425 mrs x5, erxctlr_el1 +[^:]+: d5185445 msr erxstatus_el1, x5 +[^:]+: d5385445 mrs x5, erxstatus_el1 +[^:]+: d5185465 msr erxaddr_el1, x5 +[^:]+: d5385465 mrs x5, erxaddr_el1 +[^:]+: d5185505 msr erxmisc0_el1, x5 +[^:]+: d5385505 mrs x5, erxmisc0_el1 +[^:]+: d5185525 msr erxmisc1_el1, x5 +[^:]+: d5385525 mrs x5, erxmisc1_el1 +[^:]+: d53c5265 mrs x5, vsesr_el2 +[^:]+: d518c125 msr disr_el1, x5 +[^:]+: d538c125 mrs x5, disr_el1 +[^:]+: d53cc125 mrs x5, vdisr_el2 +[^:]+: d503221f esb +[^:]+: d503221f esb +[^:]+: d5385305 mrs x5, erridr_el1 +[^:]+: d5185327 msr errselr_el1, x7 +[^:]+: d5385327 mrs x7, errselr_el1 +[^:]+: d5385405 mrs x5, erxfr_el1 +[^:]+: d5185425 msr erxctlr_el1, x5 +[^:]+: d5385425 mrs x5, erxctlr_el1 +[^:]+: d5185445 msr erxstatus_el1, x5 +[^:]+: d5385445 mrs x5, erxstatus_el1 +[^:]+: d5185465 msr erxaddr_el1, x5 +[^:]+: d5385465 mrs x5, erxaddr_el1 +[^:]+: d5185505 msr erxmisc0_el1, x5 +[^:]+: d5385505 mrs x5, erxmisc0_el1 +[^:]+: d5185525 msr erxmisc1_el1, x5 +[^:]+: d5385525 mrs x5, erxmisc1_el1 +[^:]+: d53c5265 mrs x5, vsesr_el2 +[^:]+: d518c125 msr disr_el1, x5 +[^:]+: d538c125 mrs x5, disr_el1 +[^:]+: d53cc125 mrs x5, vdisr_el2 diff --git a/gas/testsuite/gas/aarch64/armv8-ras-1.s b/gas/testsuite/gas/aarch64/armv8-ras-1.s new file mode 100644 index 0000000..2aedb58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8-ras-1.s @@ -0,0 +1,73 @@ + /* ARMv8 RAS Extension. */ + .text + + .macro rw_sys_reg sys_reg xreg r w + .ifc \w, 1 + msr \sys_reg, \xreg + .endif + .ifc \r, 1 + mrs \xreg, \sys_reg + .endif + .endm + + /* ARMv8-A. */ + .arch armv8-a+ras + esb + hint #0x10 + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 + + /* ARMv8.1-A. */ + + .arch armv8.1-a+ras + esb + hint #0x10 + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 + + /* ARMv8.2-A. */ + + .arch armv8.2-a+ras + esb + hint #0x10 + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 diff --git a/gas/testsuite/gas/aarch64/illegal-ras-1.d b/gas/testsuite/gas/aarch64/illegal-ras-1.d new file mode 100644 index 0000000..b7b72ea --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ras-1.d @@ -0,0 +1,4 @@ +#name: Illegal RAS instruction use. +#source: illegal-ras-1.s +#as: -march=armv8-a -mno-verbose-error +#error-output: illegal-ras-1.l diff --git a/gas/testsuite/gas/aarch64/illegal-ras-1.l b/gas/testsuite/gas/aarch64/illegal-ras-1.l new file mode 100644 index 0000000..e8803e5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ras-1.l @@ -0,0 +1,39 @@ +[^:]+: Assembler messages: +^[^:]+:[0-9]+: Error: selected processor does not support `esb' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2' +^[^:]+:[0-9]+: Error: selected processor does not support `esb' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1' +^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2' diff --git a/gas/testsuite/gas/aarch64/illegal-ras-1.s b/gas/testsuite/gas/aarch64/illegal-ras-1.s new file mode 100644 index 0000000..5d61fb7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ras-1.s @@ -0,0 +1,52 @@ + /* Incorrect use of the RAS extension instructions. */ + .text + + .macro rw_sys_reg sys_reg xreg r w + .ifc \w, 1 + msr \sys_reg, \xreg + .endif + .ifc \r, 1 + mrs \xreg, \sys_reg + .endif + .endm + + /* ARMv8-A. */ + .arch armv8-a + esb + hint #0x10 + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 + + /* ARMv8.1-A. */ + + .arch armv8.1-a + esb + hint #0x10 + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 |