[ARM] Add ARMv8.3 VCMLA and VCADD instructions

Add support for VCMLA and VCADD advanced SIMD complex number instructions.

The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.

In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.

gas/
	* config/tc-arm.c (do_vcmla, do_vcadd): Define.
	(neon_scalar_for_vcmla): Define.
	(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
	(NEON_ENC_TAB): Add DDSI and QQSI variants.
	(insns): Add vcmla and vcadd.
	* testsuite/gas/arm/armv8_3-a-simd.d: New.
	* testsuite/gas/arm/armv8_3-a-simd.s: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
	(print_insn_coprocessor): Add 'V' format for neon D or Q regs.

5 files changed, 188 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d
new file mode 100644
index 0000000..b2060cd
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a+fp16+simd
+#error-output: armv8_3-a-simd-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l
new file mode 100644
index 0000000..2a3ea9b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l
@@ -0,0 +1,39 @@
+[^:]+: Assembler messages:
+[^:]+:6: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
+[^:]+:7: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
+[^:]+:8: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
+[^:]+:9: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
+[^:]+:10: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
+[^:]+:11: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
+[^:]+:13: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
+[^:]+:14: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
+[^:]+:15: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
+[^:]+:16: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
+[^:]+:17: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
+[^:]+:18: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
+[^:]+:19: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
+[^:]+:21: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
+[^:]+:22: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
+[^:]+:23: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
+[^:]+:24: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
+[^:]+:25: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
+[^:]+:26: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
+[^:]+:31: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
+[^:]+:32: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
+[^:]+:33: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
+[^:]+:34: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
+[^:]+:35: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
+[^:]+:36: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
+[^:]+:38: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
+[^:]+:39: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
+[^:]+:40: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
+[^:]+:41: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
+[^:]+:42: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
+[^:]+:43: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
+[^:]+:44: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
+[^:]+:46: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
+[^:]+:47: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
+[^:]+:48: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
+[^:]+:49: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
+[^:]+:50: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
+[^:]+:51: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s
new file mode 100644
index 0000000..9f6934f
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s
@@ -0,0 +1,51 @@
+	.text
+
+A1:
+	.arm
+
+	vcadd d0,d1,d2,#90
+	vcadd.f32 q0,q1,q2,#0
+	vcadd.f32 q0,q1,q2,#180
+	vcadd.f16 s0,s1,s2,#90
+	vcadd.f64 d0,d1,d2,#90
+	vcadd.f64 q0,q1,q2,#90
+
+	vcmla d0,d1,d2,#90
+	vcmla.f32 q0,q1,q2,#-90
+	vcmla.f32 q0,q1,q2,#120
+	vcmla.f32 q0,q1,q2,#360
+	vcmla.f16 s0,s1,s2,#90
+	vcmla.f64 d0,d1,d2,#90
+	vcmla.f64 q0,q1,q2,#90
+
+	vcmla.f16 q0,q1,q2[0],#90
+	vcmla.f32 q0,q1,q2[0],#90
+	vcmla.f16 d0,d1,d2[2],#90
+	vcmla.f16 q0,q1,d2[2],#90
+	vcmla.f16 q0,q1,d16[1],#90
+	vcmla.f32 q0,q1,d2[1],#90
+
+T1:
+	.thumb
+
+	vcadd d0,d1,d2,#90
+	vcadd.f32 q0,q1,q2,#0
+	vcadd.f32 q0,q1,q2,#180
+	vcadd.f16 s0,s1,s2,#90
+	vcadd.f64 d0,d1,d2,#90
+	vcadd.f64 q0,q1,q2,#90
+
+	vcmla d0,d1,d2,#90
+	vcmla.f32 q0,q1,q2,#-90
+	vcmla.f32 q0,q1,q2,#120
+	vcmla.f32 q0,q1,q2,#360
+	vcmla.f16 s0,s1,s2,#90
+	vcmla.f64 d0,d1,d2,#90
+	vcmla.f64 q0,q1,q2,#90
+
+	vcmla.f16 q0,q1,q2[0],#90
+	vcmla.f32 q0,q1,q2[0],#90
+	vcmla.f16 d0,d1,d2[2],#90
+	vcmla.f16 q0,q1,d2[2],#90
+	vcmla.f16 q0,q1,d16[1],#90
+	vcmla.f32 q0,q1,d2[1],#90
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.d b/gas/testsuite/gas/arm/armv8_3-a-simd.d
new file mode 100644
index 0000000..c420cff
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.d
@@ -0,0 +1,47 @@
+#as: -march=armv8.3-a+fp16+simd
+#objdump: -dr
+#skip: *-*-pe *-wince-* *-*-coff
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ +[0-9a-f]+:	fc942846 	vcadd.f32	q1, q2, q3, #90
+ +[0-9a-f]+:	fd942846 	vcadd.f32	q1, q2, q3, #270
+ +[0-9a-f]+:	fcc658a7 	vcadd.f16	d21, d22, d23, #90
+ +[0-9a-f]+:	fc842846 	vcadd.f16	q1, q2, q3, #90
+ +[0-9a-f]+:	fcd658a7 	vcadd.f32	d21, d22, d23, #90
+ +[0-9a-f]+:	fc342846 	vcmla.f32	q1, q2, q3, #0
+ +[0-9a-f]+:	fcb42846 	vcmla.f32	q1, q2, q3, #90
+ +[0-9a-f]+:	fd342846 	vcmla.f32	q1, q2, q3, #180
+ +[0-9a-f]+:	fdb42846 	vcmla.f32	q1, q2, q3, #270
+ +[0-9a-f]+:	fce658a7 	vcmla.f16	d21, d22, d23, #90
+ +[0-9a-f]+:	fca42846 	vcmla.f16	q1, q2, q3, #90
+ +[0-9a-f]+:	fcf658a7 	vcmla.f32	d21, d22, d23, #90
+ +[0-9a-f]+:	fe565883 	vcmla.f16	d21, d22, d3\[0\], #90
+ +[0-9a-f]+:	fe5658a3 	vcmla.f16	d21, d22, d3\[1\], #90
+ +[0-9a-f]+:	fe142843 	vcmla.f16	q1, q2, d3\[0\], #90
+ +[0-9a-f]+:	fe142863 	vcmla.f16	q1, q2, d3\[1\], #90
+ +[0-9a-f]+:	fed658a7 	vcmla.f32	d21, d22, d23\[0\], #90
+ +[0-9a-f]+:	fe942867 	vcmla.f32	q1, q2, d23\[0\], #90
+
+[0-9a-f]+ <.*>:
+ +[0-9a-f]+:	fc94 2846 	vcadd.f32	q1, q2, q3, #90
+ +[0-9a-f]+:	fd94 2846 	vcadd.f32	q1, q2, q3, #270
+ +[0-9a-f]+:	fcc6 58a7 	vcadd.f16	d21, d22, d23, #90
+ +[0-9a-f]+:	fc84 2846 	vcadd.f16	q1, q2, q3, #90
+ +[0-9a-f]+:	fcd6 58a7 	vcadd.f32	d21, d22, d23, #90
+ +[0-9a-f]+:	fc34 2846 	vcmla.f32	q1, q2, q3, #0
+ +[0-9a-f]+:	fcb4 2846 	vcmla.f32	q1, q2, q3, #90
+ +[0-9a-f]+:	fd34 2846 	vcmla.f32	q1, q2, q3, #180
+ +[0-9a-f]+:	fdb4 2846 	vcmla.f32	q1, q2, q3, #270
+ +[0-9a-f]+:	fce6 58a7 	vcmla.f16	d21, d22, d23, #90
+ +[0-9a-f]+:	fca4 2846 	vcmla.f16	q1, q2, q3, #90
+ +[0-9a-f]+:	fcf6 58a7 	vcmla.f32	d21, d22, d23, #90
+ +[0-9a-f]+:	fe56 5883 	vcmla.f16	d21, d22, d3\[0\], #90
+ +[0-9a-f]+:	fe56 58a3 	vcmla.f16	d21, d22, d3\[1\], #90
+ +[0-9a-f]+:	fe14 2843 	vcmla.f16	q1, q2, d3\[0\], #90
+ +[0-9a-f]+:	fe14 2863 	vcmla.f16	q1, q2, d3\[1\], #90
+ +[0-9a-f]+:	fed6 58a7 	vcmla.f32	d21, d22, d23\[0\], #90
+ +[0-9a-f]+:	fe94 2867 	vcmla.f32	q1, q2, d23\[0\], #90
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.s b/gas/testsuite/gas/arm/armv8_3-a-simd.s
new file mode 100644
index 0000000..fde2f76
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.s
@@ -0,0 +1,49 @@
+	.text
+
+A1:
+	.arm
+
+	vcadd.f32 q1,q2,q3,#90
+	vcadd.f32 q1,q2,q3,#270
+	vcadd.f16 d21,d22,d23,#90
+	vcadd.f16 q1,q2,q3,#90
+	vcadd.f32 d21,d22,d23,#90
+
+	vcmla.f32 q1,q2,q3,#0
+	vcmla.f32 q1,q2,q3,#90
+	vcmla.f32 q1,q2,q3,#180
+	vcmla.f32 q1,q2,q3,#270
+	vcmla.f16 d21,d22,d23,#90
+	vcmla.f16 q1,q2,q3,#90
+	vcmla.f32 d21,d22,d23,#90
+
+	vcmla.f16 d21,d22,d3[0],#90
+	vcmla.f16 d21,d22,d3[1],#90
+	vcmla.f16 q1,q2,d3[0],#90
+	vcmla.f16 q1,q2,d3[1],#90
+	vcmla.f32 d21,d22,d23[0],#90
+	vcmla.f32 q1,q2,d23[0],#90
+
+T1:
+	.thumb
+
+	vcadd.f32 q1,q2,q3,#90
+	vcadd.f32 q1,q2,q3,#270
+	vcadd.f16 d21,d22,d23,#90
+	vcadd.f16 q1,q2,q3,#90
+	vcadd.f32 d21,d22,d23,#90
+
+	vcmla.f32 q1,q2,q3,#0
+	vcmla.f32 q1,q2,q3,#90
+	vcmla.f32 q1,q2,q3,#180
+	vcmla.f32 q1,q2,q3,#270
+	vcmla.f16 d21,d22,d23,#90
+	vcmla.f16 q1,q2,q3,#90
+	vcmla.f32 d21,d22,d23,#90
+
+	vcmla.f16 d21,d22,d3[0],#90
+	vcmla.f16 d21,d22,d3[1],#90
+	vcmla.f16 q1,q2,d3[0],#90
+	vcmla.f16 q1,q2,d3[1],#90
+	vcmla.f32 d21,d22,d23[0],#90
+	vcmla.f32 q1,q2,d23[0],#90