MIPS/GAS/testsuite: Implement individual MIPS16 ISA testing

Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit
variants of the base MIPS16 and the MIPS16e ISA each.

	gas/
	* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
	`mips16e' and `mips16' prefixes.
	(run_list_test_arch): Likewise.
	Rename `mips16' architecture to `mips16-32'.  Add `mips16-64',
	`mips16e-32' and `mips16e-64' architectures.  Update `rol64',
	`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
	accordingly.
	* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
	* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
	* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
	* testsuite/gas/mips/mips16e@loc-swap.d: New test.

5 files changed, 163 insertions, 7 deletions

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index ffc08a0..dc632c7 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -324,6 +324,12 @@ proc run_dump_test_arch { name opts arch } {
 
     set proparch [lindex [mips_arch_properties $arch 0] 0]
     set prefixes [list ${proparch}@ ]
+    if { [ string match "mips16e*" $proparch ] } {
+	lappend prefixes mips16e@
+    }
+    if { [ string match "mips16*" $proparch ] } {
+	lappend prefixes mips16@
+    }
     if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
 	lappend prefixes octeon@
     }
@@ -374,6 +380,12 @@ proc run_list_test_arch { name opts arch } {
     set testname "MIPS $name ([concat $opts [mips_arch_displayname $arch]])"
     set proparch [lindex [mips_arch_properties $arch 0] 0]
     set prefixes [list ${proparch}@ ]
+    if { [ string match "mips16e*" $proparch ] } {
+	lappend prefixes mips16e@
+    }
+    if { [ string match "mips16*" $proparch ] } {
+	lappend prefixes mips16@
+    }
     if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
 	lappend prefixes octeon@
     }
@@ -470,8 +482,14 @@ mips_arch_create mips64r6 64	mips64r5 { mips32r6 ror } \
 			{ -march=mips64r6 -mtune=mips64r6 --defsym r6=} \
 			{ -mmips:isa64r6 } \
 			{ mipsisa64r6-*-* mipsisa64r6el-*-* }
-mips_arch_create mips16	32	{}	{} \
-			{ -march=mips1 -mips16 } { -mmips:16 }
+mips_arch_create mips16-32 32	{}	{} \
+			{ -march=mips1 -mips16 } { -mmips:3000 }
+mips_arch_create mips16-64 64	mips16-32	{} \
+			{ -march=mips3 -mips16 } { -mmips:4000 }
+mips_arch_create mips16e-32 32	mips16-32	{} \
+			{ -march=mips32 -mips16 } { -mmips:isa32 }
+mips_arch_create mips16e-64 64	mips16-64 { mips16e-32 } \
+			{ -march=mips64 -mips16 } { -mmips:isa64 }
 mips_arch_create micromips 64	mips64r2 {} \
 			{ -march=mips64r2 -mmicromips } {}
 mips_arch_create r3000 	32	mips1	{} \
@@ -820,7 +838,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "rol"		[mips_arch_list_matching mips1 !ror]
     run_dump_test_arches "rol-hw" 	[mips_arch_list_matching ror]
 
-    run_dump_test_arches "rol64"	[mips_arch_list_matching gpr64 !ror]
+    run_dump_test_arches "rol64" \
+				[mips_arch_list_matching gpr64 !ror !mips16-32]
     run_dump_test_arches "rol64-hw"	[mips_arch_list_matching gpr64 ror]
 
     run_dump_test "sb"
@@ -857,8 +876,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "mips16-macro-t" "{{as} {-march=mips3}}"
     run_dump_test "mips16-macro-e" "{{as} {-march=mips3}}"
     # Check MIPS16e extensions
-    run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips \
-					!mips32r6]
+    run_dump_test_arches "mips16e"	[mips_arch_list_matching mips16e-32]
     # Check jalx handling
     run_dump_test "mips16-jalx"
     run_dump_test "mips-jalx"
@@ -1074,10 +1092,11 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "mips-abi32-pic2"
 
     run_dump_test "elf${el}-rel"
-    run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64 !singlefloat]
+    run_dump_test_arches "elf${el}-rel2" \
+			[mips_arch_list_matching gpr64 !singlefloat !mips16-32]
     run_dump_test "e32${el}-rel2"
     run_dump_test "elf${el}-rel3"
-    run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
+    run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64 !mips16-32]
     run_dump_test "e32-rel4"
     run_dump_test "elf-rel5"
     run_dump_test "elf-rel6"
diff --git a/gas/testsuite/gas/mips/mips16e@branch-swap-3.d b/gas/testsuite/gas/mips/mips16e@branch-swap-3.d
new file mode 100644
index 0000000..513e3e3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e@branch-swap-3.d
@@ -0,0 +1,41 @@
+#objdump: -dr -M reg-names=numeric
+#as: -32 -O2 -aln=branch-swap-lst.lst
+#name: MIPS branch swapping with assembler listing
+#source: branch-swap-3.s
+
+# Check delay slot filling with a listing file works (MIPS16e)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+:	1800 0000 	jal	0 <test>
+[ 	]*[0-9a-f]+: R_MIPS16_26	func
+[ 0-9a-f]+:	6702      	move	\$16,\$2
+[ 0-9a-f]+:	1800 0000 	jal	0 <test>
+[ 	]*[0-9a-f]+: R_MIPS16_26	func
+[ 0-9a-f]+:	4101      	addiu	\$16,\$17,1
+[ 0-9a-f]+:	4101      	addiu	\$16,\$17,1
+[ 0-9a-f]+:	1800 0000 	jal	0 <test>
+[ 	]*[0-9a-f]+: R_MIPS16_26	func
+[ 0-9a-f]+:	6500      	nop
+[ 0-9a-f]+:	f7f7 410f 	addiu	\$16,\$17,16383
+[ 0-9a-f]+:	1800 0000 	jal	0 <test>
+[ 	]*[0-9a-f]+: R_MIPS16_26	func
+[ 0-9a-f]+:	6500      	nop
+[ 0-9a-f]+:	f7f7 410f 	addiu	\$16,\$17,16383
+[ 0-9a-f]+:	1800 0000 	jal	0 <test>
+[ 	]*[0-9a-f]+: R_MIPS16_26	func
+[ 0-9a-f]+:	6500      	nop
+[ 0-9a-f]+:	e820      	jr	\$31
+[ 0-9a-f]+:	6702      	move	\$16,\$2
+[ 0-9a-f]+:	e820      	jr	\$31
+[ 0-9a-f]+:	4101      	addiu	\$16,\$17,1
+[ 0-9a-f]+:	4101      	addiu	\$16,\$17,1
+[ 0-9a-f]+:	e8a0      	jrc	\$31
+[ 0-9a-f]+:	f7f7 410f 	addiu	\$16,\$17,16383
+[ 0-9a-f]+:	e8a0      	jrc	\$31
+[ 0-9a-f]+:	f7f7 410f 	addiu	\$16,\$17,16383
+[ 0-9a-f]+:	e8a0      	jrc	\$31
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips16e@branch-swap-4.d b/gas/testsuite/gas/mips/mips16e@branch-swap-4.d
new file mode 100644
index 0000000..97db5a0
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e@branch-swap-4.d
@@ -0,0 +1,5 @@
+#objdump: -dr -M reg-names=numeric
+#as: -32 -O2
+#name: MIPS branch swapping without assembler listing
+#source: branch-swap-3.s
+#dump: mips16e@branch-swap-3.d
diff --git a/gas/testsuite/gas/mips/mips16e@loc-swap-dis.d b/gas/testsuite/gas/mips/mips16e@loc-swap-dis.d
new file mode 100644
index 0000000..44d196e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e@loc-swap-dis.d
@@ -0,0 +1,30 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DWARF-2 location information with branch swapping disassembly
+#as: -32
+#source: loc-swap.s
+
+# Check branch swapping with DWARF-2 location information (MIPS16e).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6790      	move	a0,s0
+[0-9a-f]+ <[^>]*> ec80      	jrc	a0
+[0-9a-f]+ <[^>]*> ec00      	jr	a0
+[0-9a-f]+ <[^>]*> 65f8      	move	ra,s0
+[0-9a-f]+ <[^>]*> e820      	jr	ra
+[0-9a-f]+ <[^>]*> 6790      	move	a0,s0
+[0-9a-f]+ <[^>]*> 65f8      	move	ra,s0
+[0-9a-f]+ <[^>]*> e8a0      	jrc	ra
+[0-9a-f]+ <[^>]*> 6790      	move	a0,s0
+[0-9a-f]+ <[^>]*> ecc0      	jalrc	a0
+[0-9a-f]+ <[^>]*> 65f8      	move	ra,s0
+[0-9a-f]+ <[^>]*> ecc0      	jalrc	a0
+[0-9a-f]+ <[^>]*> 1800 0000 	jal	0+0000 <foo>
+[ 	]*[0-9a-f]+: R_MIPS16_26	bar
+[0-9a-f]+ <[^>]*> 6790      	move	a0,s0
+[0-9a-f]+ <[^>]*> 65f8      	move	ra,s0
+[0-9a-f]+ <[^>]*> 1800 0000 	jal	0+0000 <foo>
+[ 	]*[0-9a-f]+: R_MIPS16_26	bar
+[0-9a-f]+ <[^>]*> 6500      	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips16e@loc-swap.d b/gas/testsuite/gas/mips/mips16e@loc-swap.d
new file mode 100644
index 0000000..412e45b
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e@loc-swap.d
@@ -0,0 +1,61 @@
+#PROG: readelf
+#readelf: -wl
+#name: MIPS DWARF-2 location information with branch swapping
+#as: -32
+#source: loc-swap.s
+
+# Verify that DWARF-2 location information for instructions reordered
+# into a branch delay slot is updated to point to the branch instead.
+
+Raw dump of debug contents of section \.debug_line:
+
+  Offset:                      0x0
+  Length:                      67
+  DWARF Version:               2
+  Prologue Length:             33
+  Minimum Instruction Length:  1
+  Initial value of 'is_stmt':  1
+  Line Base:                   -5
+  Line Range:                  14
+  Opcode Base:                 13
+
+ Opcodes:
+  Opcode 1 has 0 args
+  Opcode 2 has 1 args
+  Opcode 3 has 1 args
+  Opcode 4 has 1 args
+  Opcode 5 has 1 args
+  Opcode 6 has 0 args
+  Opcode 7 has 0 args
+  Opcode 8 has 0 args
+  Opcode 9 has 1 args
+  Opcode 10 has 0 args
+  Opcode 11 has 0 args
+  Opcode 12 has 1 args
+
+ The Directory Table is empty\.
+
+ The File Name Table \(offset 0x.*\):
+  Entry	Dir	Time	Size	Name
+  1	0	0	0	loc-swap\.s
+
+ Line Number Statements:
+  \[0x.*\]  Extended opcode 2: set Address to 0x1
+  \[0x.*\]  Special opcode 11: advance Address by 0 to 0x1 and Line by 6 to 7
+  \[0x.*\]  Special opcode 35: advance Address by 2 to 0x3 and Line by 2 to 9
+  \[0x.*\]  Special opcode 36: advance Address by 2 to 0x5 and Line by 3 to 12
+  \[0x.*\]  Special opcode 7: advance Address by 0 to 0x5 and Line by 2 to 14
+  \[0x.*\]  Special opcode 64: advance Address by 4 to 0x9 and Line by 3 to 17
+  \[0x.*\]  Special opcode 7: advance Address by 0 to 0x9 and Line by 2 to 19
+  \[0x.*\]  Special opcode 64: advance Address by 4 to 0xd and Line by 3 to 22
+  \[0x.*\]  Special opcode 35: advance Address by 2 to 0xf and Line by 2 to 24
+  \[0x.*\]  Special opcode 36: advance Address by 2 to 0x11 and Line by 3 to 27
+  \[0x.*\]  Special opcode 35: advance Address by 2 to 0x13 and Line by 2 to 29
+  \[0x.*\]  Special opcode 36: advance Address by 2 to 0x15 and Line by 3 to 32
+  \[0x.*\]  Special opcode 35: advance Address by 2 to 0x17 and Line by 2 to 34
+  \[0x.*\]  Special opcode 36: advance Address by 2 to 0x19 and Line by 3 to 37
+  \[0x.*\]  Special opcode 7: advance Address by 0 to 0x19 and Line by 2 to 39
+  \[0x.*\]  Special opcode 92: advance Address by 6 to 0x1f and Line by 3 to 42
+  \[0x.*\]  Special opcode 35: advance Address by 2 to 0x21 and Line by 2 to 44
+  \[0x.*\]  Advance PC by 31 to 0x40
+  \[0x.*\]  Extended opcode 1: End of Sequence