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| author | Alan Modra <amodra@gmail.com> | 2016-12-21 19:13:52 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2016-12-21 19:18:46 +1030 |
| commit | 4e25adb3956f880efc28bfebabe79be7338b413f (patch) | |
| tree | 9e8b41dbf37bac5ab3c6c78abdd26ff6c59019fc /gas/testsuite | |
| parent | 9962fe293d16e1e1e4d05154e751fc7576226954 (diff) | |
| download | gdb-4e25adb3956f880efc28bfebabe79be7338b413f.zip gdb-4e25adb3956f880efc28bfebabe79be7338b413f.tar.gz gdb-4e25adb3956f880efc28bfebabe79be7338b413f.tar.bz2 | |
Remove high bit set characters
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/bfin/vector2.s | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gas/testsuite/gas/bfin/vector2.s b/gas/testsuite/gas/bfin/vector2.s index be1a5b7..204f72d 100644 --- a/gas/testsuite/gas/bfin/vector2.s +++ b/gas/testsuite/gas/bfin/vector2.s @@ -93,7 +93,7 @@ r1=r2 +|+ r3 (SCO); r4=r3 +|+ r5 (SCO); r6=r3 +|+ r7 (SCO); -//Dreg = Dreg –|+ Dreg (opt_mode_0) ; /* subtract | add (b) */ +//Dreg = Dreg -|+ Dreg (opt_mode_0) ; /* subtract | add (b) */ r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */ r0=r1 -|+ r2 ; @@ -125,7 +125,7 @@ r4=r3 -|+ r5 (SCO); r6=r3 -|+ r7 (SCO); -//Dreg = Dreg +|– Dreg (opt_mode_0) ; /* add | subtract (b) */ +//Dreg = Dreg +|- Dreg (opt_mode_0) ; /* add | subtract (b) */ r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */ r0=r1 +|- r2 ; @@ -156,7 +156,7 @@ r1=r2 +|- r3 (SCO); r4=r3 +|- r5 (SCO); r6=r3 +|- r7 (SCO); -//Dreg = Dreg –|– Dreg (opt_mode_0) ; /* subtract | subtract (b) */ +//Dreg = Dreg -|- Dreg (opt_mode_0) ; /* subtract | subtract (b) */ r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */ r0=r1 -|- r2 ; @@ -188,7 +188,7 @@ r4=r3 -|- r5 (SCO); r6=r3 -|- r7 (SCO); //Quad 16-Bit Operations -//Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */ +//Dreg = Dreg +|+ Dreg, Dreg = Dreg -|- Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */ r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */ r0=r1 +|+ r2, r7=r1 -|- r2; @@ -284,7 +284,7 @@ r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL); r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL); -//Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */ +//Dreg = Dreg +|- Dreg, Dreg = Dreg -|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */ r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */ r0=r1 +|- r2, r7=r1 -|+ r2; |