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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-12-05 14:13:27 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-12-05 14:13:27 +0000 |
| commit | 49e8a725825c77aacc7458b9d7771cb2fa2f64c7 (patch) | |
| tree | 1b8e14968dc5332003f9c4403775da01e131e75c /gas/testsuite | |
| parent | a12fd8e1b1c9c6a16e3cc9fc477d7e459776b587 (diff) | |
| download | gdb-49e8a725825c77aacc7458b9d7771cb2fa2f64c7.zip gdb-49e8a725825c77aacc7458b9d7771cb2fa2f64c7.tar.gz gdb-49e8a725825c77aacc7458b9d7771cb2fa2f64c7.tar.bz2 | |
[ARM] Add ARMv8.3 VJCVT instruction
Add support for VJCVT javascript conversion instruction.
gas/
* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
(insns): Add vjcvt.
* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vjcvt.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/arm/armv8_3-a-fp-bad.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv8_3-a-fp-bad.l | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv8_3-a-fp-bad.s | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv8_3-a-fp.d | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv8_3-a-fp.s | 8 |
5 files changed, 40 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d new file mode 100644 index 0000000..a38f6e6 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d @@ -0,0 +1,2 @@ +#as: -march=armv8.3-a+fp +#error-output: armv8_3-a-fp-bad.l diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l new file mode 100644 index 0000000..755b6f7 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l @@ -0,0 +1,7 @@ +[^:]+: Assembler messages: +[^:]+:3: Error: operand types can't be inferred -- `vjcvt s0,d1' +[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1' +[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1' +[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1' +[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1' +[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1' diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s new file mode 100644 index 0000000..dffb726 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s @@ -0,0 +1,8 @@ + .text + .arm + vjcvt s0, d1 + vjcvt.s32.f64 r0, d1 + vjcvt.s32.f64 s0, s1 + vjcvt.s32.f32 s0, s1 + vjcvt.s32.f32 s0, d1 + vjcvt.f32.f64 s0, d1 diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp.d b/gas/testsuite/gas/arm/armv8_3-a-fp.d new file mode 100644 index 0000000..7f60754 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_3-a-fp.d @@ -0,0 +1,15 @@ +#as: -march=armv8.3-a+fp +#objdump: -dr +#skip: *-*-pe *-wince-* *-*-coff + +.*: +file format .*arm.* + +Disassembly of section .text: + +[0-9a-f]+ <.*>: + [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7 + [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7 + +[0-9a-f]+ <.*>: + [0-9a-f]+: eef9 0bc7 vjcvt.s32.f64 s1, d7 + diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp.s b/gas/testsuite/gas/arm/armv8_3-a-fp.s new file mode 100644 index 0000000..f02510e --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_3-a-fp.s @@ -0,0 +1,8 @@ + .text +A1: + .arm + vjcvt.s32.f64 s1, d7 + vjcvtal.s32.f64 s1, d7 +T1: + .thumb + vjcvt.s32.f64 s1, d7 |