diff options
| author | Fred Fish <fnf@specifix.com> | 1997-02-23 03:34:25 +0000 |
|---|---|---|
| committer | Fred Fish <fnf@specifix.com> | 1997-02-23 03:34:25 +0000 |
| commit | ef60d6973c15225f409c804c067569e7367b15f2 (patch) | |
| tree | efbc84210fbb7e7b5586ca8c1f6b00b8812d129a /gas/testsuite | |
| parent | f3cc5a0ea42542dd745389414da0bb37581fa1d8 (diff) | |
| download | gdb-ef60d6973c15225f409c804c067569e7367b15f2.zip gdb-ef60d6973c15225f409c804c067569e7367b15f2.tar.gz gdb-ef60d6973c15225f409c804c067569e7367b15f2.tar.bz2 | |
* gas/tic80/{add.lst, bitnum.lst, ccode.lst, cregops.lst,
endmask.lst, regops.lst}: Remove ^M's from end of lines.
* gas/tic80/bitnum.s: Add comment to each line showing value
that symbolic BITNUM assembles to. Add coverage for raw
numeric values for the BITNUM operand.
* gas/tic80/bitnum.d: Update due to bitnum.s changes.
* gas/tic80/regops.d: Update due to opcode library additions
of floating point test BITNUM values that are ambiguous with
the integral ones.
* gas/tic80/relocs1.s: New test case that tests simple relocs.
* gas/tic80/relocs1.d: Expected output for above.
* gas/tic80/relocs1.lst: TI assembler listing for above.
* gas/tic80/tic80.exp: Add relocs1 test.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/add.lst | 68 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/bitnum.d | 60 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/bitnum.lst | 141 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/bitnum.s | 110 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/ccode.lst | 74 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/cregops.lst | 152 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/endmask.lst | 90 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/regops.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/regops.lst | 528 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/relocs1.d | 64 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/relocs1.lst | 80 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/relocs1.s | 66 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic80/tic80.exp | 1 |
14 files changed, 915 insertions, 541 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index d8a16d7..ff99ebf 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,21 @@ +start-sanitize-tic80 +Sat Feb 22 20:24:23 1997 Fred Fish <fnf@cygnus.com> + + * gas/tic80/{add.lst, bitnum.lst, ccode.lst, cregops.lst, + endmask.lst, regops.lst}: Remove ^M's from end of lines. + * gas/tic80/bitnum.s: Add comment to each line showing value + that symbolic BITNUM assembles to. Add coverage for raw + numeric values for the BITNUM operand. + * gas/tic80/bitnum.d: Update due to bitnum.s changes. + * gas/tic80/regops.d: Update due to opcode library additions + of floating point test BITNUM values that are ambiguous with + the integral ones. + * gas/tic80/relocs1.s: New test case that tests simple relocs. + * gas/tic80/relocs1.d: Expected output for above. + * gas/tic80/relocs1.lst: TI assembler listing for above. + * gas/tic80/tic80.exp: Add relocs1 test. + +end-sanitize-tic80 start-sanitize-d30v Fri Feb 21 14:23:14 1997 Martin M. Hunt <hunt@pizza.cygnus.com> diff --git a/gas/testsuite/gas/tic80/add.lst b/gas/testsuite/gas/tic80/add.lst index cbb6aef..e12b368 100644 --- a/gas/testsuite/gas/tic80/add.lst +++ b/gas/testsuite/gas/tic80/add.lst @@ -1,34 +1,34 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 20:13:33 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-add.s PAGE 1
-
- 1 ; Test signed and unsigned addition instruction.
- 2 ; Test boundary conditions to ensure proper handling.
- 3 ; Note that unsigned addition still uses signed immediates.
- 4
- 5 00000000 62FB000A add r10,r11,r12 ; Register form
- 6 00000004 20AC3FFF add 16383,r2,r4 ; Maximum positive short signed immediate
- 7 00000008 212C4000 add -16384,r4,r4 ; Minimum negative short signed immediate
- 8 0000000C 317B1000 add 16384,r5,r6 ; Minimum positive long signed immediate
- 00000010 00004000
- 9 00000014 41FB1000 add -16385,r7,r8 ; Maximum negative short signed immediate
- 00000018 FFFFBFFF
- 10 0000001C 5ABB1000 add 2147483647,r10,r11 ; Maximum positive long signed immediate
- 00000020 7FFFFFFF
- 11 00000024 6B3B1000 add -2147483648,r12,r13 ; Minimum positive long signed immediate
- 00000028 80000000
- 12
- 13 0000002C 62FB200A addu r10,r11,r12 ; Register form
- 14 00000030 20ACBFFF addu 16383,r2,r4 ; Maximum positive short signed immediate
- 15 00000034 212CC000 addu -16384,r4,r4 ; Minimum negative short signed immediate
- 16 00000038 317B3000 addu 16384,r5,r6 ; Minimum positive long signed immediate
- 0000003C 00004000
- 17 00000040 41FB3000 addu -16385,r7,r8 ; Maximum negative short signed immediate
- 00000044 FFFFBFFF
- 18 00000048 5ABB3000 addu 2147483647,r10,r11 ; Maximum positive long signed immediate
- 0000004C 7FFFFFFF
- 19 00000050 6B3B3000 addu -2147483648,r12,r13 ; Minimum positive long signed immediate
- 00000054 80000000
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Mon Feb 10 20:13:33 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +add.s PAGE 1 + + 1 ; Test signed and unsigned addition instruction. + 2 ; Test boundary conditions to ensure proper handling. + 3 ; Note that unsigned addition still uses signed immediates. + 4 + 5 00000000 62FB000A add r10,r11,r12 ; Register form + 6 00000004 20AC3FFF add 16383,r2,r4 ; Maximum positive short signed immediate + 7 00000008 212C4000 add -16384,r4,r4 ; Minimum negative short signed immediate + 8 0000000C 317B1000 add 16384,r5,r6 ; Minimum positive long signed immediate + 00000010 00004000 + 9 00000014 41FB1000 add -16385,r7,r8 ; Maximum negative short signed immediate + 00000018 FFFFBFFF + 10 0000001C 5ABB1000 add 2147483647,r10,r11 ; Maximum positive long signed immediate + 00000020 7FFFFFFF + 11 00000024 6B3B1000 add -2147483648,r12,r13 ; Minimum positive long signed immediate + 00000028 80000000 + 12 + 13 0000002C 62FB200A addu r10,r11,r12 ; Register form + 14 00000030 20ACBFFF addu 16383,r2,r4 ; Maximum positive short signed immediate + 15 00000034 212CC000 addu -16384,r4,r4 ; Minimum negative short signed immediate + 16 00000038 317B3000 addu 16384,r5,r6 ; Minimum positive long signed immediate + 0000003C 00004000 + 17 00000040 41FB3000 addu -16385,r7,r8 ; Maximum negative short signed immediate + 00000044 FFFFBFFF + 18 00000048 5ABB3000 addu 2147483647,r10,r11 ; Maximum positive long signed immediate + 0000004C 7FFFFFFF + 19 00000050 6B3B3000 addu -2147483648,r12,r13 ; Minimum positive long signed immediate + 00000054 80000000 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/bitnum.d b/gas/testsuite/gas/tic80/bitnum.d index 687b03d..ce51aa2 100644 --- a/gas/testsuite/gas/tic80/bitnum.d +++ b/gas/testsuite/gas/tic80/bitnum.d @@ -26,13 +26,57 @@ Disassembly of section .text: 44: 0a 40 39 72 bbo r10,r8,ls\.h 48: 0a 40 39 6a bbo r10,r8,lo\.h 4c: 0a 40 39 62 bbo r10,r8,hs\.h - 50: 0a 40 39 5a bbo r10,r8,eq\.w - 54: 0a 40 39 52 bbo r10,r8,ne\.w - 58: 0a 40 39 4a bbo r10,r8,gt\.w - 5c: 0a 40 39 42 bbo r10,r8,le\.w - 60: 0a 40 39 3a bbo r10,r8,lt\.w - 64: 0a 40 39 32 bbo r10,r8,ge\.w + 50: 0a 40 39 5a bbo r10,r8,eq\.f + 54: 0a 40 39 52 bbo r10,r8,ne\.f + 58: 0a 40 39 4a bbo r10,r8,gt\.f + 5c: 0a 40 39 42 bbo r10,r8,le\.f + 60: 0a 40 39 3a bbo r10,r8,lt\.f + 64: 0a 40 39 32 bbo r10,r8,ge\.f 68: 0a 40 39 2a bbo r10,r8,hi\.w - 6c: 0a 40 39 22 bbo r10,r8,ls\.w - 70: 0a 40 39 1a bbo r10,r8,lo\.w + 6c: 0a 40 39 22 bbo r10,r8,in\.f + 70: 0a 40 39 1a bbo r10,r8,ib\.f 74: 0a 40 39 12 bbo r10,r8,hs\.w + 78: 0a 40 39 5a bbo r10,r8,eq\.f + 7c: 0a 40 39 52 bbo r10,r8,ne\.f + 80: 0a 40 39 4a bbo r10,r8,gt\.f + 84: 0a 40 39 42 bbo r10,r8,le\.f + 88: 0a 40 39 3a bbo r10,r8,lt\.f + 8c: 0a 40 39 32 bbo r10,r8,ge\.f + 90: 0a 40 39 2a bbo r10,r8,hi\.w + 94: 0a 40 39 22 bbo r10,r8,in\.f + 98: 0a 40 39 1a bbo r10,r8,ib\.f + 9c: 0a 40 39 12 bbo r10,r8,hs\.w + a0: 0a 40 39 0a bbo r10,r8,uo\.f + a4: 0a 40 39 02 bbo r10,r8,or\.f + a8: 0a 40 39 fa bbo r10,r8,eq\.b + ac: 0a 40 39 f2 bbo r10,r8,ne\.b + b0: 0a 40 39 ea bbo r10,r8,gt\.b + b4: 0a 40 39 e2 bbo r10,r8,le\.b + b8: 0a 40 39 da bbo r10,r8,lt\.b + bc: 0a 40 39 d2 bbo r10,r8,ge\.b + c0: 0a 40 39 ca bbo r10,r8,hi\.b + c4: 0a 40 39 c2 bbo r10,r8,ls\.b + c8: 0a 40 39 ba bbo r10,r8,lo\.b + cc: 0a 40 39 b2 bbo r10,r8,hs\.b + d0: 0a 40 39 aa bbo r10,r8,eq\.h + d4: 0a 40 39 a2 bbo r10,r8,ne\.h + d8: 0a 40 39 9a bbo r10,r8,gt\.h + dc: 0a 40 39 92 bbo r10,r8,le\.h + e0: 0a 40 39 8a bbo r10,r8,lt\.h + e4: 0a 40 39 82 bbo r10,r8,ge\.h + e8: 0a 40 39 7a bbo r10,r8,hi\.h + ec: 0a 40 39 72 bbo r10,r8,ls\.h + f0: 0a 40 39 6a bbo r10,r8,lo\.h + f4: 0a 40 39 62 bbo r10,r8,hs\.h + f8: 0a 40 39 5a bbo r10,r8,eq\.f + fc: 0a 40 39 52 bbo r10,r8,ne\.f + 100: 0a 40 39 4a bbo r10,r8,gt\.f + 104: 0a 40 39 42 bbo r10,r8,le\.f + 108: 0a 40 39 3a bbo r10,r8,lt\.f + 10c: 0a 40 39 32 bbo r10,r8,ge\.f + 110: 0a 40 39 2a bbo r10,r8,hi\.w + 114: 0a 40 39 22 bbo r10,r8,in\.f + 118: 0a 40 39 1a bbo r10,r8,ib\.f + 11c: 0a 40 39 12 bbo r10,r8,hs\.w + 120: 0a 40 39 0a bbo r10,r8,uo\.f + 124: 0a 40 39 02 bbo r10,r8,or\.f diff --git a/gas/testsuite/gas/tic80/bitnum.lst b/gas/testsuite/gas/tic80/bitnum.lst index 9b5c54c..acc268b 100644 --- a/gas/testsuite/gas/tic80/bitnum.lst +++ b/gas/testsuite/gas/tic80/bitnum.lst @@ -1,44 +1,97 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:33 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-bitnum.s PAGE 1
-
- 1 ;; Test that all the predefined symbol names for the BITNUM field
- 2 ;; are properly accepted and translated to numeric values. Also
- 3 ;; verifies that they are disassembled correctly as symbolics.
- 4
- 5 00000000 FA39400A bbo r10,r8,eq.b
- 6 00000004 F239400A bbo r10,r8,ne.b
- 7 00000008 EA39400A bbo r10,r8,gt.b
- 8 0000000C E239400A bbo r10,r8,le.b
- 9 00000010 DA39400A bbo r10,r8,lt.b
- 10 00000014 D239400A bbo r10,r8,ge.b
- 11 00000018 CA39400A bbo r10,r8,hi.b
- 12 0000001C C239400A bbo r10,r8,ls.b
- 13 00000020 BA39400A bbo r10,r8,lo.b
- 14 00000024 B239400A bbo r10,r8,hs.b
- 15
- 16 00000028 AA39400A bbo r10,r8,eq.h
- 17 0000002C A239400A bbo r10,r8,ne.h
- 18 00000030 9A39400A bbo r10,r8,gt.h
- 19 00000034 9239400A bbo r10,r8,le.h
- 20 00000038 8A39400A bbo r10,r8,lt.h
- 21 0000003C 8239400A bbo r10,r8,ge.h
- 22 00000040 7A39400A bbo r10,r8,hi.h
- 23 00000044 7239400A bbo r10,r8,ls.h
- 24 00000048 6A39400A bbo r10,r8,lo.h
- 25 0000004C 6239400A bbo r10,r8,hs.h
- 26
- 27 00000050 5A39400A bbo r10,r8,eq.w
- 28 00000054 5239400A bbo r10,r8,ne.w
- 29 00000058 4A39400A bbo r10,r8,gt.w
- 30 0000005C 4239400A bbo r10,r8,le.w
- 31 00000060 3A39400A bbo r10,r8,lt.w
- 32 00000064 3239400A bbo r10,r8,ge.w
- 33 00000068 2A39400A bbo r10,r8,hi.w
- 34 0000006C 2239400A bbo r10,r8,ls.w
- 35 00000070 1A39400A bbo r10,r8,lo.w
- 36 00000074 1239400A bbo r10,r8,hs.w
- 37
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Sat Feb 22 21:37:15 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +bitnum.s PAGE 1 + + 1 ;; Test that all the predefined symbol names for the BITNUM field + 2 ;; are properly accepted and translated to numeric values. Also + 3 ;; verifies that they are disassembled correctly as symbolics, and + 4 ;; that the raw numeric values are handled correctly (stored as + 5 ;; the one's complement of the operand numeric value. + 6 + 7 00000000 FA39400A bbo r10,r8,eq.b ; (~0 & 0x1F) + 8 00000004 F239400A bbo r10,r8,ne.b ; (~1 & 0x1F) + 9 00000008 EA39400A bbo r10,r8,gt.b ; (~2 & 0x1F) + 10 0000000C E239400A bbo r10,r8,le.b ; (~3 & 0x1F) + 11 00000010 DA39400A bbo r10,r8,lt.b ; (~4 & 0x1F) + 12 00000014 D239400A bbo r10,r8,ge.b ; (~5 & 0x1F) + 13 00000018 CA39400A bbo r10,r8,hi.b ; (~6 & 0x1F) + 14 0000001C C239400A bbo r10,r8,ls.b ; (~7 & 0x1F) + 15 00000020 BA39400A bbo r10,r8,lo.b ; (~8 & 0x1F) + 16 00000024 B239400A bbo r10,r8,hs.b ; (~9 & 0x1F) + 17 + 18 00000028 AA39400A bbo r10,r8,eq.h ; (~10 & 0x1F) + 19 0000002C A239400A bbo r10,r8,ne.h ; (~11 & 0x1F) + 20 00000030 9A39400A bbo r10,r8,gt.h ; (~12 & 0x1F) + 21 00000034 9239400A bbo r10,r8,le.h ; (~13 & 0x1F) + 22 00000038 8A39400A bbo r10,r8,lt.h ; (~14 & 0x1F) + 23 0000003C 8239400A bbo r10,r8,ge.h ; (~15 & 0x1F) + 24 00000040 7A39400A bbo r10,r8,hi.h ; (~16 & 0x1F) + 25 00000044 7239400A bbo r10,r8,ls.h ; (~17 & 0x1F) + 26 00000048 6A39400A bbo r10,r8,lo.h ; (~18 & 0x1F) + 27 0000004C 6239400A bbo r10,r8,hs.h ; (~19 & 0x1F) + 28 + 29 00000050 5A39400A bbo r10,r8,eq.w ; (~20 & 0x1F) + 30 00000054 5239400A bbo r10,r8,ne.w ; (~21 & 0x1F) + 31 00000058 4A39400A bbo r10,r8,gt.w ; (~22 & 0x1F) + 32 0000005C 4239400A bbo r10,r8,le.w ; (~23 & 0x1F) + 33 00000060 3A39400A bbo r10,r8,lt.w ; (~24 & 0x1F) + 34 00000064 3239400A bbo r10,r8,ge.w ; (~25 & 0x1F) + 35 00000068 2A39400A bbo r10,r8,hi.w ; (~26 & 0x1F) + 36 0000006C 2239400A bbo r10,r8,ls.w ; (~27 & 0x1F) + 37 00000070 1A39400A bbo r10,r8,lo.w ; (~28 & 0x1F) + 38 00000074 1239400A bbo r10,r8,hs.w ; (~29 & 0x1F) + 39 + 40 00000078 5A39400A bbo r10,r8,eq.f ; (~20 & 0x1F) + 41 0000007C 5239400A bbo r10,r8,ne.f ; (~21 & 0x1F) + 42 00000080 4A39400A bbo r10,r8,gt.f ; (~22 & 0x1F) + 43 00000084 4239400A bbo r10,r8,le.f ; (~23 & 0x1F) + 44 00000088 3A39400A bbo r10,r8,lt.f ; (~24 & 0x1F) + 45 0000008C 3239400A bbo r10,r8,ge.f ; (~25 & 0x1F) + 46 00000090 2A39400A bbo r10,r8,ou.f ; (~26 & 0x1F) + 47 00000094 2239400A bbo r10,r8,in.f ; (~27 & 0x1F) + 48 00000098 1A39400A bbo r10,r8,ib.f ; (~28 & 0x1F) + 49 0000009C 1239400A bbo r10,r8,ob.f ; (~29 & 0x1F) + 50 000000A0 0A39400A bbo r10,r8,uo.f ; (~30 & 0x1F) + 51 000000A4 0239400A bbo r10,r8,or.f ; (~31 & 0x1F) + 52 + 53 000000A8 FA39400A bbo r10,r8,0 + 54 000000AC F239400A bbo r10,r8,1 + 55 000000B0 EA39400A bbo r10,r8,2 + MVP MP Macro Assembler Version 1.13 Sat Feb 22 21:37:15 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +bitnum.s PAGE 2 + + 56 000000B4 E239400A bbo r10,r8,3 + 57 000000B8 DA39400A bbo r10,r8,4 + 58 000000BC D239400A bbo r10,r8,5 + 59 000000C0 CA39400A bbo r10,r8,6 + 60 000000C4 C239400A bbo r10,r8,7 + 61 000000C8 BA39400A bbo r10,r8,8 + 62 000000CC B239400A bbo r10,r8,9 + 63 000000D0 AA39400A bbo r10,r8,10 + 64 000000D4 A239400A bbo r10,r8,11 + 65 000000D8 9A39400A bbo r10,r8,12 + 66 000000DC 9239400A bbo r10,r8,13 + 67 000000E0 8A39400A bbo r10,r8,14 + 68 000000E4 8239400A bbo r10,r8,15 + 69 000000E8 7A39400A bbo r10,r8,16 + 70 000000EC 7239400A bbo r10,r8,17 + 71 000000F0 6A39400A bbo r10,r8,18 + 72 000000F4 6239400A bbo r10,r8,19 + 73 000000F8 5A39400A bbo r10,r8,20 + 74 000000FC 5239400A bbo r10,r8,21 + 75 00000100 4A39400A bbo r10,r8,22 + 76 00000104 4239400A bbo r10,r8,23 + 77 00000108 3A39400A bbo r10,r8,24 + 78 0000010C 3239400A bbo r10,r8,25 + 79 00000110 2A39400A bbo r10,r8,26 + 80 00000114 2239400A bbo r10,r8,27 + 81 00000118 1A39400A bbo r10,r8,28 + 82 0000011C 1239400A bbo r10,r8,29 + 83 00000120 0A39400A bbo r10,r8,30 + 84 00000124 0239400A bbo r10,r8,31 + 85 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/bitnum.s b/gas/testsuite/gas/tic80/bitnum.s index 9689315..2526e06 100644 --- a/gas/testsuite/gas/tic80/bitnum.s +++ b/gas/testsuite/gas/tic80/bitnum.s @@ -1,37 +1,85 @@ ;; Test that all the predefined symbol names for the BITNUM field ;; are properly accepted and translated to numeric values. Also -;; verifies that they are disassembled correctly as symbolics. +;; verifies that they are disassembled correctly as symbolics, and +;; that the raw numeric values are handled correctly (stored as +;; the one's complement of the operand numeric value. - bbo r10,r8,eq.b - bbo r10,r8,ne.b - bbo r10,r8,gt.b - bbo r10,r8,le.b - bbo r10,r8,lt.b - bbo r10,r8,ge.b - bbo r10,r8,hi.b - bbo r10,r8,ls.b - bbo r10,r8,lo.b - bbo r10,r8,hs.b + bbo r10,r8,eq.b ; (~0 & 0x1F) + bbo r10,r8,ne.b ; (~1 & 0x1F) + bbo r10,r8,gt.b ; (~2 & 0x1F) + bbo r10,r8,le.b ; (~3 & 0x1F) + bbo r10,r8,lt.b ; (~4 & 0x1F) + bbo r10,r8,ge.b ; (~5 & 0x1F) + bbo r10,r8,hi.b ; (~6 & 0x1F) + bbo r10,r8,ls.b ; (~7 & 0x1F) + bbo r10,r8,lo.b ; (~8 & 0x1F) + bbo r10,r8,hs.b ; (~9 & 0x1F) - bbo r10,r8,eq.h - bbo r10,r8,ne.h - bbo r10,r8,gt.h - bbo r10,r8,le.h - bbo r10,r8,lt.h - bbo r10,r8,ge.h - bbo r10,r8,hi.h - bbo r10,r8,ls.h - bbo r10,r8,lo.h - bbo r10,r8,hs.h + bbo r10,r8,eq.h ; (~10 & 0x1F) + bbo r10,r8,ne.h ; (~11 & 0x1F) + bbo r10,r8,gt.h ; (~12 & 0x1F) + bbo r10,r8,le.h ; (~13 & 0x1F) + bbo r10,r8,lt.h ; (~14 & 0x1F) + bbo r10,r8,ge.h ; (~15 & 0x1F) + bbo r10,r8,hi.h ; (~16 & 0x1F) + bbo r10,r8,ls.h ; (~17 & 0x1F) + bbo r10,r8,lo.h ; (~18 & 0x1F) + bbo r10,r8,hs.h ; (~19 & 0x1F) - bbo r10,r8,eq.w - bbo r10,r8,ne.w - bbo r10,r8,gt.w - bbo r10,r8,le.w - bbo r10,r8,lt.w - bbo r10,r8,ge.w - bbo r10,r8,hi.w - bbo r10,r8,ls.w - bbo r10,r8,lo.w - bbo r10,r8,hs.w + bbo r10,r8,eq.w ; (~20 & 0x1F) + bbo r10,r8,ne.w ; (~21 & 0x1F) + bbo r10,r8,gt.w ; (~22 & 0x1F) + bbo r10,r8,le.w ; (~23 & 0x1F) + bbo r10,r8,lt.w ; (~24 & 0x1F) + bbo r10,r8,ge.w ; (~25 & 0x1F) + bbo r10,r8,hi.w ; (~26 & 0x1F) + bbo r10,r8,ls.w ; (~27 & 0x1F) + bbo r10,r8,lo.w ; (~28 & 0x1F) + bbo r10,r8,hs.w ; (~29 & 0x1F) + + bbo r10,r8,eq.f ; (~20 & 0x1F) + bbo r10,r8,ne.f ; (~21 & 0x1F) + bbo r10,r8,gt.f ; (~22 & 0x1F) + bbo r10,r8,le.f ; (~23 & 0x1F) + bbo r10,r8,lt.f ; (~24 & 0x1F) + bbo r10,r8,ge.f ; (~25 & 0x1F) + bbo r10,r8,ou.f ; (~26 & 0x1F) + bbo r10,r8,in.f ; (~27 & 0x1F) + bbo r10,r8,ib.f ; (~28 & 0x1F) + bbo r10,r8,ob.f ; (~29 & 0x1F) + bbo r10,r8,uo.f ; (~30 & 0x1F) + bbo r10,r8,or.f ; (~31 & 0x1F) + + bbo r10,r8,0 + bbo r10,r8,1 + bbo r10,r8,2 + bbo r10,r8,3 + bbo r10,r8,4 + bbo r10,r8,5 + bbo r10,r8,6 + bbo r10,r8,7 + bbo r10,r8,8 + bbo r10,r8,9 + bbo r10,r8,10 + bbo r10,r8,11 + bbo r10,r8,12 + bbo r10,r8,13 + bbo r10,r8,14 + bbo r10,r8,15 + bbo r10,r8,16 + bbo r10,r8,17 + bbo r10,r8,18 + bbo r10,r8,19 + bbo r10,r8,20 + bbo r10,r8,21 + bbo r10,r8,22 + bbo r10,r8,23 + bbo r10,r8,24 + bbo r10,r8,25 + bbo r10,r8,26 + bbo r10,r8,27 + bbo r10,r8,28 + bbo r10,r8,29 + bbo r10,r8,30 + bbo r10,r8,31 diff --git a/gas/testsuite/gas/tic80/ccode.lst b/gas/testsuite/gas/tic80/ccode.lst index 26852de..460351c 100644 --- a/gas/testsuite/gas/tic80/ccode.lst +++ b/gas/testsuite/gas/tic80/ccode.lst @@ -1,37 +1,37 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:49 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-ccode.s PAGE 1
-
- 1 ;; Test that all the predefined symbol names for the condition
- 2 ;; codes are properly accepted and translated to numeric values.
- 3 ;; Also verifies that they are disassembled correctly as symbolics.
- 4
- 5 00000000 0179A007 bcnd.a r7,r5,nev.b ; 00000
- 6 00000004 0979A007 bcnd.a r7,r5,gt0.b ; 00001
- 7 00000008 1179A007 bcnd.a r7,r5,eq0.b ; 00010
- 8 0000000C 1979A007 bcnd.a r7,r5,ge0.b ; 00011
- 9 00000010 2179A007 bcnd.a r7,r5,lt0.b ; 00100
- 10 00000014 2979A007 bcnd.a r7,r5,ne0.b ; 00101
- 11 00000018 3179A007 bcnd.a r7,r5,le0.b ; 00110
- 12 0000001C 3979A007 bcnd.a r7,r5,alw.b ; 00111
- 13
- 14 00000020 4179A007 bcnd.a r7,r5,nev.h ; 01000
- 15 00000024 4979A007 bcnd.a r7,r5,gt0.h ; 01001
- 16 00000028 5179A007 bcnd.a r7,r5,eq0.h ; 01010
- 17 0000002C 5979A007 bcnd.a r7,r5,ge0.h ; 01011
- 18 00000030 6179A007 bcnd.a r7,r5,lt0.h ; 01100
- 19 00000034 6979A007 bcnd.a r7,r5,ne0.h ; 01101
- 20 00000038 7179A007 bcnd.a r7,r5,le0.h ; 01110
- 21 0000003C 7979A007 bcnd.a r7,r5,alw.h ; 01111
- 22
- 23 00000040 8179A007 bcnd.a r7,r5,nev.w ; 10000
- 24 00000044 8979A007 bcnd.a r7,r5,gt0.w ; 10001
- 25 00000048 9179A007 bcnd.a r7,r5,eq0.w ; 10010
- 26 0000004C 9979A007 bcnd.a r7,r5,ge0.w ; 10011
- 27 00000050 A179A007 bcnd.a r7,r5,lt0.w ; 10100
- 28 00000054 A979A007 bcnd.a r7,r5,ne0.w ; 10101
- 29 00000058 B179A007 bcnd.a r7,r5,le0.w ; 10110
- 30 0000005C B979A007 bcnd.a r7,r5,alw.w ; 10111
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:49 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +ccode.s PAGE 1 + + 1 ;; Test that all the predefined symbol names for the condition + 2 ;; codes are properly accepted and translated to numeric values. + 3 ;; Also verifies that they are disassembled correctly as symbolics. + 4 + 5 00000000 0179A007 bcnd.a r7,r5,nev.b ; 00000 + 6 00000004 0979A007 bcnd.a r7,r5,gt0.b ; 00001 + 7 00000008 1179A007 bcnd.a r7,r5,eq0.b ; 00010 + 8 0000000C 1979A007 bcnd.a r7,r5,ge0.b ; 00011 + 9 00000010 2179A007 bcnd.a r7,r5,lt0.b ; 00100 + 10 00000014 2979A007 bcnd.a r7,r5,ne0.b ; 00101 + 11 00000018 3179A007 bcnd.a r7,r5,le0.b ; 00110 + 12 0000001C 3979A007 bcnd.a r7,r5,alw.b ; 00111 + 13 + 14 00000020 4179A007 bcnd.a r7,r5,nev.h ; 01000 + 15 00000024 4979A007 bcnd.a r7,r5,gt0.h ; 01001 + 16 00000028 5179A007 bcnd.a r7,r5,eq0.h ; 01010 + 17 0000002C 5979A007 bcnd.a r7,r5,ge0.h ; 01011 + 18 00000030 6179A007 bcnd.a r7,r5,lt0.h ; 01100 + 19 00000034 6979A007 bcnd.a r7,r5,ne0.h ; 01101 + 20 00000038 7179A007 bcnd.a r7,r5,le0.h ; 01110 + 21 0000003C 7979A007 bcnd.a r7,r5,alw.h ; 01111 + 22 + 23 00000040 8179A007 bcnd.a r7,r5,nev.w ; 10000 + 24 00000044 8979A007 bcnd.a r7,r5,gt0.w ; 10001 + 25 00000048 9179A007 bcnd.a r7,r5,eq0.w ; 10010 + 26 0000004C 9979A007 bcnd.a r7,r5,ge0.w ; 10011 + 27 00000050 A179A007 bcnd.a r7,r5,lt0.w ; 10100 + 28 00000054 A979A007 bcnd.a r7,r5,ne0.w ; 10101 + 29 00000058 B179A007 bcnd.a r7,r5,le0.w ; 10110 + 30 0000005C B979A007 bcnd.a r7,r5,alw.w ; 10111 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/cregops.lst b/gas/testsuite/gas/tic80/cregops.lst index e2a2d50..65ea57f 100644 --- a/gas/testsuite/gas/tic80/cregops.lst +++ b/gas/testsuite/gas/tic80/cregops.lst @@ -1,76 +1,76 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-cregops.s PAGE 1
-
- 1 ;; Test that all predefined symbol names for control registers
- 2 ;; are properly accepted and translated to numeric values. Also
- 3 ;; verifies that they are diassembled correctly as symbolics.
- 4
- 5 00000000 10020034 rdcr ANASTAT,r2
- 6 00000004 10020039 rdcr BRK1,r2
- 7 00000008 1002003A rdcr BRK2,r2
- 8 0000000C 10020002 rdcr CONFIG,r2
- 9 00000010 10020500 rdcr DLRU,r2
- 10 00000014 10020400 rdcr DTAG0,r2
- 11 00000018 10020401 rdcr DTAG1,r2
- 12 0000001C 1002040A rdcr DTAG10,r2
- 13 00000020 1002040B rdcr DTAG11,r2
- 14 00000024 1002040C rdcr DTAG12,r2
- 15 00000028 1002040D rdcr DTAG13,r2
- 16 0000002C 1002040E rdcr DTAG14,r2
- 17 00000030 1002040F rdcr DTAG15,r2
- 18 00000034 10020402 rdcr DTAG2,r2
- 19 00000038 10020403 rdcr DTAG3,r2
- 20 0000003C 10020404 rdcr DTAG4,r2
- 21 00000040 10020405 rdcr DTAG5,r2
- 22 00000044 10020406 rdcr DTAG6,r2
- 23 00000048 10020407 rdcr DTAG7,r2
- 24 0000004C 10020408 rdcr DTAG8,r2
- 25 00000050 10020409 rdcr DTAG9,r2
- 26 00000054 10020033 rdcr ECOMCNTL,r2
- 27 00000058 10020001 rdcr EIP,r2
- 28 0000005C 10020000 rdcr EPC,r2
- 29 00000060 10020011 rdcr FLTADR,r2
- 30 00000064 10020014 rdcr FLTDTH,r2
- 31 00000068 10020013 rdcr FLTDTL,r2
- 32 0000006C 10020010 rdcr FLTOP,r2
- 33 00000070 10020012 rdcr FLTTAG,r2
- 34 00000074 10020008 rdcr FPST,r2
- 35 00000078 10020006 rdcr IE,r2
- 36 0000007C 10020300 rdcr ILRU,r2
- 37 00000080 10024000 rdcr IN0P,r2
- 38 00000084 10024001 rdcr IN1P,r2
- 39 00000088 10020004 rdcr INTPEN,r2
- 40 0000008C 10020200 rdcr ITAG0,r2
- 41 00000090 10020201 rdcr ITAG1,r2
- 42 00000094 1002020A rdcr ITAG10,r2
- 43 00000098 1002020B rdcr ITAG11,r2
- 44 0000009C 1002020C rdcr ITAG12,r2
- 45 000000A0 1002020D rdcr ITAG13,r2
- 46 000000A4 1002020E rdcr ITAG14,r2
- 47 000000A8 1002020F rdcr ITAG15,r2
- 48 000000AC 10020202 rdcr ITAG2,r2
- 49 000000B0 10020203 rdcr ITAG3,r2
- 50 000000B4 10020204 rdcr ITAG4,r2
- 51 000000B8 10020205 rdcr ITAG5,r2
- 52 000000BC 10020206 rdcr ITAG6,r2
- 53 000000C0 10020207 rdcr ITAG7,r2
- 54 000000C4 10020208 rdcr ITAG8,r2
- 55 000000C8 10020209 rdcr ITAG9,r2
- MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-cregops.s PAGE 2
-
- 56 000000CC 10020031 rdcr MIP,r2
- 57 000000D0 10020030 rdcr MPC,r2
- 58 000000D4 10024002 rdcr OUTP,r2
- 59 000000D8 1002000D rdcr PKTREQ,r2
- 60 000000DC 1002000A rdcr PPERROR,r2
- 61 000000E0 10020020 rdcr SYSSTK,r2
- 62 000000E4 10020021 rdcr SYSTMP,r2
- 63 000000E8 1002000E rdcr TCOUNT,r2
- 64 000000EC 1002000F rdcr TSCALE,r2
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +cregops.s PAGE 1 + + 1 ;; Test that all predefined symbol names for control registers + 2 ;; are properly accepted and translated to numeric values. Also + 3 ;; verifies that they are diassembled correctly as symbolics. + 4 + 5 00000000 10020034 rdcr ANASTAT,r2 + 6 00000004 10020039 rdcr BRK1,r2 + 7 00000008 1002003A rdcr BRK2,r2 + 8 0000000C 10020002 rdcr CONFIG,r2 + 9 00000010 10020500 rdcr DLRU,r2 + 10 00000014 10020400 rdcr DTAG0,r2 + 11 00000018 10020401 rdcr DTAG1,r2 + 12 0000001C 1002040A rdcr DTAG10,r2 + 13 00000020 1002040B rdcr DTAG11,r2 + 14 00000024 1002040C rdcr DTAG12,r2 + 15 00000028 1002040D rdcr DTAG13,r2 + 16 0000002C 1002040E rdcr DTAG14,r2 + 17 00000030 1002040F rdcr DTAG15,r2 + 18 00000034 10020402 rdcr DTAG2,r2 + 19 00000038 10020403 rdcr DTAG3,r2 + 20 0000003C 10020404 rdcr DTAG4,r2 + 21 00000040 10020405 rdcr DTAG5,r2 + 22 00000044 10020406 rdcr DTAG6,r2 + 23 00000048 10020407 rdcr DTAG7,r2 + 24 0000004C 10020408 rdcr DTAG8,r2 + 25 00000050 10020409 rdcr DTAG9,r2 + 26 00000054 10020033 rdcr ECOMCNTL,r2 + 27 00000058 10020001 rdcr EIP,r2 + 28 0000005C 10020000 rdcr EPC,r2 + 29 00000060 10020011 rdcr FLTADR,r2 + 30 00000064 10020014 rdcr FLTDTH,r2 + 31 00000068 10020013 rdcr FLTDTL,r2 + 32 0000006C 10020010 rdcr FLTOP,r2 + 33 00000070 10020012 rdcr FLTTAG,r2 + 34 00000074 10020008 rdcr FPST,r2 + 35 00000078 10020006 rdcr IE,r2 + 36 0000007C 10020300 rdcr ILRU,r2 + 37 00000080 10024000 rdcr IN0P,r2 + 38 00000084 10024001 rdcr IN1P,r2 + 39 00000088 10020004 rdcr INTPEN,r2 + 40 0000008C 10020200 rdcr ITAG0,r2 + 41 00000090 10020201 rdcr ITAG1,r2 + 42 00000094 1002020A rdcr ITAG10,r2 + 43 00000098 1002020B rdcr ITAG11,r2 + 44 0000009C 1002020C rdcr ITAG12,r2 + 45 000000A0 1002020D rdcr ITAG13,r2 + 46 000000A4 1002020E rdcr ITAG14,r2 + 47 000000A8 1002020F rdcr ITAG15,r2 + 48 000000AC 10020202 rdcr ITAG2,r2 + 49 000000B0 10020203 rdcr ITAG3,r2 + 50 000000B4 10020204 rdcr ITAG4,r2 + 51 000000B8 10020205 rdcr ITAG5,r2 + 52 000000BC 10020206 rdcr ITAG6,r2 + 53 000000C0 10020207 rdcr ITAG7,r2 + 54 000000C4 10020208 rdcr ITAG8,r2 + 55 000000C8 10020209 rdcr ITAG9,r2 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:56 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +cregops.s PAGE 2 + + 56 000000CC 10020031 rdcr MIP,r2 + 57 000000D0 10020030 rdcr MPC,r2 + 58 000000D4 10024002 rdcr OUTP,r2 + 59 000000D8 1002000D rdcr PKTREQ,r2 + 60 000000DC 1002000A rdcr PPERROR,r2 + 61 000000E0 10020020 rdcr SYSSTK,r2 + 62 000000E4 10020021 rdcr SYSTMP,r2 + 63 000000E8 1002000E rdcr TCOUNT,r2 + 64 000000EC 1002000F rdcr TSCALE,r2 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/endmask.lst b/gas/testsuite/gas/tic80/endmask.lst index e41f786..9103b33 100644 --- a/gas/testsuite/gas/tic80/endmask.lst +++ b/gas/testsuite/gas/tic80/endmask.lst @@ -1,45 +1,45 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:29 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-endmask.s PAGE 1
-
- 1 ;; Test all possible combinations of the endmask in bits 5-9.
- 2 ;; The mask that is used is computed as 2**bits-1 where bits
- 3 ;; are the bits 5-9 from the instruction. Note that 0 and 32
- 4 ;; are treated identically, and disassembled as 0.
- 5
- 6 00000000 49C70005 sl.iz 5,0,r7,r9
- 7 00000004 49C70025 sl.iz 5,1,r7,r9
- 8 00000008 49C70045 sl.iz 5,2,r7,r9
- 9 0000000C 49C70065 sl.iz 5,3,r7,r9
- 10 00000010 49C70085 sl.iz 5,4,r7,r9
- 11 00000014 49C700A5 sl.iz 5,5,r7,r9
- 12 00000018 49C700C5 sl.iz 5,6,r7,r9
- 13 0000001C 49C700E5 sl.iz 5,7,r7,r9
- 14 00000020 49C70105 sl.iz 5,8,r7,r9
- 15 00000024 49C70125 sl.iz 5,9,r7,r9
- 16 00000028 49C70145 sl.iz 5,10,r7,r9
- 17 0000002C 49C70165 sl.iz 5,11,r7,r9
- 18 00000030 49C70185 sl.iz 5,12,r7,r9
- 19 00000034 49C701A5 sl.iz 5,13,r7,r9
- 20 00000038 49C701C5 sl.iz 5,14,r7,r9
- 21 0000003C 49C701E5 sl.iz 5,15,r7,r9
- 22 00000040 49C70205 sl.iz 5,16,r7,r9
- 23 00000044 49C70225 sl.iz 5,17,r7,r9
- 24 00000048 49C70245 sl.iz 5,18,r7,r9
- 25 0000004C 49C70265 sl.iz 5,19,r7,r9
- 26 00000050 49C70285 sl.iz 5,20,r7,r9
- 27 00000054 49C702A5 sl.iz 5,21,r7,r9
- 28 00000058 49C702C5 sl.iz 5,22,r7,r9
- 29 0000005C 49C702E5 sl.iz 5,23,r7,r9
- 30 00000060 49C70305 sl.iz 5,24,r7,r9
- 31 00000064 49C70325 sl.iz 5,25,r7,r9
- 32 00000068 49C70345 sl.iz 5,26,r7,r9
- 33 0000006C 49C70365 sl.iz 5,27,r7,r9
- 34 00000070 49C70385 sl.iz 5,28,r7,r9
- 35 00000074 49C703A5 sl.iz 5,29,r7,r9
- 36 00000078 49C703C5 sl.iz 5,30,r7,r9
- 37 0000007C 49C703E5 sl.iz 5,31,r7,r9
- 38 00000080 49C70005 sl.iz 5,32,r7,r9
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:29 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +endmask.s PAGE 1 + + 1 ;; Test all possible combinations of the endmask in bits 5-9. + 2 ;; The mask that is used is computed as 2**bits-1 where bits + 3 ;; are the bits 5-9 from the instruction. Note that 0 and 32 + 4 ;; are treated identically, and disassembled as 0. + 5 + 6 00000000 49C70005 sl.iz 5,0,r7,r9 + 7 00000004 49C70025 sl.iz 5,1,r7,r9 + 8 00000008 49C70045 sl.iz 5,2,r7,r9 + 9 0000000C 49C70065 sl.iz 5,3,r7,r9 + 10 00000010 49C70085 sl.iz 5,4,r7,r9 + 11 00000014 49C700A5 sl.iz 5,5,r7,r9 + 12 00000018 49C700C5 sl.iz 5,6,r7,r9 + 13 0000001C 49C700E5 sl.iz 5,7,r7,r9 + 14 00000020 49C70105 sl.iz 5,8,r7,r9 + 15 00000024 49C70125 sl.iz 5,9,r7,r9 + 16 00000028 49C70145 sl.iz 5,10,r7,r9 + 17 0000002C 49C70165 sl.iz 5,11,r7,r9 + 18 00000030 49C70185 sl.iz 5,12,r7,r9 + 19 00000034 49C701A5 sl.iz 5,13,r7,r9 + 20 00000038 49C701C5 sl.iz 5,14,r7,r9 + 21 0000003C 49C701E5 sl.iz 5,15,r7,r9 + 22 00000040 49C70205 sl.iz 5,16,r7,r9 + 23 00000044 49C70225 sl.iz 5,17,r7,r9 + 24 00000048 49C70245 sl.iz 5,18,r7,r9 + 25 0000004C 49C70265 sl.iz 5,19,r7,r9 + 26 00000050 49C70285 sl.iz 5,20,r7,r9 + 27 00000054 49C702A5 sl.iz 5,21,r7,r9 + 28 00000058 49C702C5 sl.iz 5,22,r7,r9 + 29 0000005C 49C702E5 sl.iz 5,23,r7,r9 + 30 00000060 49C70305 sl.iz 5,24,r7,r9 + 31 00000064 49C70325 sl.iz 5,25,r7,r9 + 32 00000068 49C70345 sl.iz 5,26,r7,r9 + 33 0000006C 49C70365 sl.iz 5,27,r7,r9 + 34 00000070 49C70385 sl.iz 5,28,r7,r9 + 35 00000074 49C703A5 sl.iz 5,29,r7,r9 + 36 00000078 49C703C5 sl.iz 5,30,r7,r9 + 37 0000007C 49C703E5 sl.iz 5,31,r7,r9 + 38 00000080 49C70005 sl.iz 5,32,r7,r9 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/regops.d b/gas/testsuite/gas/tic80/regops.d index 96d8bdb..0df4349 100644 --- a/gas/testsuite/gas/tic80/regops.d +++ b/gas/testsuite/gas/tic80/regops.d @@ -13,9 +13,9 @@ Disassembly of section .text: 10: 0a 00 33 73 and\.ff r10,r12,r14 14: 0a 80 32 73 and\.ft r10,r12,r14 18: 0a 40 32 73 and\.tf r10,r12,r14 - 1c: 0a 40 39 1a bbo r10,r8,lo\.w + 1c: 0a 40 39 1a bbo r10,r8,ib\.f 20: 0a 60 39 fa bbo\.a r10,r8,eq\.b - 24: 0a 00 39 22 bbz r10,r8,ls\.w + 24: 0a 00 39 22 bbz r10,r8,in\.f 28: 0a 20 39 2a bbz\.a r10,r8,hi\.w 2c: 04 80 b9 21 bcnd r4,r6,lt0\.b 30: 04 a0 b9 21 bcnd\.a r4,r6,lt0\.b diff --git a/gas/testsuite/gas/tic80/regops.lst b/gas/testsuite/gas/tic80/regops.lst index 4c78adc..f889dd1 100644 --- a/gas/testsuite/gas/tic80/regops.lst +++ b/gas/testsuite/gas/tic80/regops.lst @@ -1,264 +1,264 @@ -MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-regops.s PAGE 1
-
- 1 ;; Simple register forms
- 2 ;; Those instructions which also use an immediate just use a constant.
- 3
- 4 00000000 .text
- 5
- 6 00000000 293B0003 add r3,r4,r5
- 7 00000004 293B2003 addu r3,r4,r5
- 8 00000008 11322005 and r5,r4,r2
- 9 0000000C 11322005 and.tt r5,r4,r2
- 10 00000010 7333000A and.ff r10,r12,r14
- 11 00000014 7332800A and.ft r10,r12,r14
- 12 00000018 7332400A and.tf r10,r12,r14
- 13 0000001C 1A39400A bbo r10,r8,lo.w
- 14 00000020 FA39600A bbo.a r10,r8,eq.b
- 15 00000024 2239000A bbz r10,r8,ls.w
- 16 00000028 2A39200A bbz.a r10,r8,hi.w
- 17 0000002C 21B98004 bcnd r4,r6,lt0.b
- 18 00000030 21B9A004 bcnd.a r4,r6,lt0.b
- 19 00000034 00390006 br r6
- 20 00000038 00392006 br.a r6
- 21 0000003C 0003000A brcr 10
- 22 00000040 F8380006 bsr r6,r31
- 23 00000044 F8382006 bsr.a r6,r31
- 24 00000048 00304007 cmnd r7
- 25 0000004C 293A0003 cmp r3,r4,r5
- 26 00000050 02B70008 dcachec r8(r10)
- 27 00000054 0AB70008 dcachef r8(r10)
- 28 00000058 41B40404 dld.b r4(r6),r8
- 29 0000005C 41B42404 dld.h r4(r6),r8
- 30 00000060 41B44404 dld r4(r6),r8
- 31 00000064 41B46404 dld.d r4(r6),r8
- 32 00000068 41B50404 dld.ub r4(r6),r8
- 33 0000006C 41B52404 dld.uh r4(r6),r8
- 34 00000070 41B60404 dst.b r4(r6),r8
- 35 00000074 41B62404 dst.h r4(r6),r8
- 36 00000078 41B64404 dst r4(r6),r8
- 37 0000007C 41B66404 dst.d r4(r6),r8
- 38 00000080 08302005 etrap r5
- 39 00000084 317147E3 exts r3,31,r5,r6
- 40 00000088 497107C2 extu r2,30,r5,r9
- 41 0000008C 313E0002 fadd.sss r2,r4,r6
- 42 00000090 313E0202 fadd.ssd r2,r4,r6
- 43 00000094 313E0282 fadd.sdd r2,r4,r6
- 44 00000098 313E0222 fadd.dsd r2,r4,r6
- 45 0000009C 313E02A2 fadd.ddd r2,r4,r6
- 46 000000A0 41BEA004 fcmp.ss r4,r6,r8
- 47 000000A4 41BEA084 fcmp.sd r4,r6,r8
- 48 000000A8 41BEA024 fcmp.ds r4,r6,r8
- 49 000000AC 41BEA0A4 fcmp.dd r4,r6,r8
- 50 000000B0 313E6002 fdiv.sss r2,r4,r6
- 51 000000B4 313E6202 fdiv.ssd r2,r4,r6
- 52 000000B8 313E6282 fdiv.sdd r2,r4,r6
- 53 000000BC 313E6222 fdiv.dsd r2,r4,r6
- 54 000000C0 313E62A2 fdiv.ddd r2,r4,r6
- 55 000000C4 313E4002 fmpy.sss r2,r4,r6
- MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-regops.s PAGE 2
-
- 56 000000C8 313E4202 fmpy.ssd r2,r4,r6
- 57 000000CC 313E4282 fmpy.sdd r2,r4,r6
- 58 000000D0 313E4222 fmpy.dsd r2,r4,r6
- 59 000000D4 313E42A2 fmpy.ddd r2,r4,r6
- 60 000000D8 313E4542 fmpy.iii r2,r4,r6
- 61 000000DC 313E47E2 fmpy.uuu r2,r4,r6
- 62 000000E0 303E8184 frndm.ss r4,r6
- 63 000000E4 303E8384 frndm.sd r4,r6
- 64 000000E8 303E8584 frndm.si r4,r6
- 65 000000EC 303E8784 frndm.su r4,r6
- 66 000000F0 403E81A2 frndm.ds r2,r8
- 67 000000F4 403E83A2 frndm.dd r2,r8
- 68 000000F8 403E85A2 frndm.di r2,r8
- 69 000000FC 403E87A2 frndm.du r2,r8
- 70 00000100 303E81C4 frndm.is r4,r6
- 71 00000104 303E83C4 frndm.id r4,r6
- 72 00000108 403E81E2 frndm.us r2,r8
- 73 0000010C 403E83E2 frndm.ud r2,r8
- 74 00000110 303E8004 frndn.ss r4,r6
- 75 00000114 303E8204 frndn.sd r4,r6
- 76 00000118 303E8404 frndn.si r4,r6
- 77 0000011C 303E8604 frndn.su r4,r6
- 78 00000120 403E8022 frndn.ds r2,r8
- 79 00000124 403E8222 frndn.dd r2,r8
- 80 00000128 403E8422 frndn.di r2,r8
- 81 0000012C 403E8622 frndn.du r2,r8
- 82 00000130 303E8044 frndn.is r4,r6
- 83 00000134 303E8244 frndn.id r4,r6
- 84 00000138 403E8062 frndn.us r2,r8
- 85 0000013C 403E8262 frndn.ud r2,r8
- 86 00000140 303E8104 frndp.ss r4,r6
- 87 00000144 303E8304 frndp.sd r4,r6
- 88 00000148 303E8504 frndp.si r4,r6
- 89 0000014C 303E8704 frndp.su r4,r6
- 90 00000150 403E8122 frndp.ds r2,r8
- 91 00000154 403E8322 frndp.dd r2,r8
- 92 00000158 403E8522 frndp.di r2,r8
- 93 0000015C 403E8722 frndp.du r2,r8
- 94 00000160 303E8144 frndp.is r4,r6
- 95 00000164 303E8344 frndp.id r4,r6
- 96 00000168 403E8162 frndp.us r2,r8
- 97 0000016C 403E8362 frndp.ud r2,r8
- 98 00000170 303E8084 frndz.ss r4,r6
- 99 00000174 303E8284 frndz.sd r4,r6
- 100 00000178 303E8484 frndz.si r4,r6
- 101 0000017C 303E8684 frndz.su r4,r6
- 102 00000180 403E80A2 frndz.ds r2,r8
- 103 00000184 403E82A2 frndz.dd r2,r8
- 104 00000188 403E84A2 frndz.di r2,r8
- 105 0000018C 403E86A2 frndz.du r2,r8
- 106 00000190 303E80C4 frndz.is r4,r6
- 107 00000194 303E82C4 frndz.id r4,r6
- 108 00000198 403E80E2 frndz.us r2,r8
- 109 0000019C 403E82E2 frndz.ud r2,r8
- 110 000001A0 403EE006 fsqrt.ss r6,r8
- MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-regops.s PAGE 3
-
- 111 000001A4 403EE206 fsqrt.sd r6,r8
- 112 000001A8 403EE226 fsqrt.dd r6,r8
- 113 000001AC 313E2002 fsub.sss r2,r4,r6
- 114 000001B0 313E2202 fsub.ssd r2,r4,r6
- 115 000001B4 313E2282 fsub.sdd r2,r4,r6
- 116 000001B8 313E2222 fsub.dsd r2,r4,r6
- 117 000001BC 313E22A2 fsub.ddd r2,r4,r6
- 118 000001C0 5231E3E4 ins r4,31,r8,r10
- 119 000001C4 41B88004 jsr r4(r6),r8
- 120 000001C8 41B8A004 jsr.a r4(r6),r8
- 121 000001CC 41B40004 ld.b r4(r6),r8
- 122 000001D0 41B42004 ld.h r4(r6),r8
- 123 000001D4 41B44004 ld r4(r6),r8
- 124 000001D8 41B46004 ld.d r4(r6),r8
- 125 000001DC 41B50004 ld.ub r4(r6),r8
- 126 000001E0 41B52004 ld.uh r4(r6),r8
- 127 000001E4 41FF0007 lmo r7,r8
- 128 000001E8 18B2E001 or r1,r2,r3
- 129 000001EC 18B2E001 or.tt r1,r2,r3
- 130 000001F0 18B3C001 or.ff r1,r2,r3
- 131 000001F4 18B3A001 or.ft r1,r2,r3
- 132 000001F8 18B36001 or.tf r1,r2,r3
- 133 000001FC 20308006 rdcr r6,r4
- 134 00000200 293F2004 rmo r4,r5
- 135 00000204 523103E2 rotl r2,31,r8,r10
- 136 00000208 30B107E8 rotr r8,31,r2,r6
- 137 0000020C 30B1C3E4 shl r4,31,r2,r6
- 138 00000210 31710184 sl.dz r4,12,r5,r6
- 139 00000214 31712184 sl.dm r4,12,r5,r6
- 140 00000218 31714184 sl.ds r4,12,r5,r6
- 141 0000021C 31716184 sl.ez r4,12,r5,r6
- 142 00000220 31718184 sl.em r4,12,r5,r6
- 143 00000224 3171A184 sl.es r4,12,r5,r6
- 144 00000228 3171C184 sl.iz r4,12,r5,r6
- 145 0000022C 3171E184 sl.im r4,12,r5,r6
- 146 00000230 31710984 sli.dz r4,12,r5,r6
- 147 00000234 31712984 sli.dm r4,12,r5,r6
- 148 00000238 31714984 sli.ds r4,12,r5,r6
- 149 0000023C 31716984 sli.ez r4,12,r5,r6
- 150 00000240 31718984 sli.em r4,12,r5,r6
- 151 00000244 3171A984 sli.es r4,12,r5,r6
- 152 00000248 3171C984 sli.iz r4,12,r5,r6
- 153 0000024C 3171E984 sli.im r4,12,r5,r6
- 154 00000250 31710584 sr.dz r4,12,r5,r6
- 155 00000254 31712584 sr.dm r4,12,r5,r6
- 156 00000258 31714584 sr.ds r4,12,r5,r6
- 157 0000025C 31716584 sr.ez r4,12,r5,r6
- 158 00000260 31718584 sr.em r4,12,r5,r6
- 159 00000264 3171A584 sr.es r4,12,r5,r6
- 160 00000268 3171C584 sr.iz r4,12,r5,r6
- 161 0000026C 3171E584 sr.im r4,12,r5,r6
- 162 00000270 41B1A404 sra r4,32,r6,r8
- 163 00000274 31710D84 sri.dz r4,12,r5,r6
- 164 00000278 31712D84 sri.dm r4,12,r5,r6
- 165 0000027C 31714D84 sri.ds r4,12,r5,r6
- MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-regops.s PAGE 4
-
- 166 00000280 31716D84 sri.ez r4,12,r5,r6
- 167 00000284 31718D84 sri.em r4,12,r5,r6
- 168 00000288 3171AD84 sri.es r4,12,r5,r6
- 169 0000028C 3171CD84 sri.iz r4,12,r5,r6
- 170 00000290 3171ED84 sri.im r4,12,r5,r6
- 171 00000294 41B16404 srl r4,32,r6,r8
- 172 00000298 41B60004 st.b r4(r6),r8
- 173 0000029C 41B62004 st.h r4(r6),r8
- 174 000002A0 41B64004 st r4(r6),r8
- 175 000002A4 41B66004 st.d r4(r6),r8
- 176 000002A8 4A3B4007 sub r7,r8,r9
- 177 000002AC 4A3B6007 subu r7,r8,r9
- 178 000002B0 21B0A008 swcr r8,r6,r4
- 179 000002B4 0030200A trap r10
- 180 000002B8 013C0002 vadd.ss r2,r4,r4
- 181 000002BC 01BC0082 vadd.sd r2,r6,r6
- 182 000002C0 02BC00A2 vadd.dd r2,r10,r10
- 183 ; vld0.s r6
- 184 ; vld1.s r7
- 185 ; vld0.d r6
- 186 ; vld1.d r8
- 187 ; vmac.sss r7,r9,0,a3
- 188 ; vmac.sss r7,r9,0,r10
- 189 ; vmac.sss r7,r9,a1,a3
- 190 ; vmac.sss r7,r9,a3,r10
- 191 ; vmac.ssd r7,r9,0,a0
- 192 ; vmac.ssd r7,r9,0,r10
- 193 ; vmac.ssd r7,r9,a1,a2
- 194 ; vmac.ssd r7,r9,a3,r10
- 195 ; vmpy.ss r1,r3,r3
- 196 ; vmpy.sd r5,r6,r6
- 197 ; vmpy.dd r2,r4,r4
- 198 ; vmsc.sss r7,r9,0,a0
- 199 ; vmsc.sss r7,r9,0,r10
- 200 ; vmsc.sss r7,r9,a0,a1
- 201 ; vmsc.sss r7,r9,a3,r10
- 202 ; vmsc.ssd r7,r9,0,a0
- 203 ; vmsc.ssd r7,r9,0,r10
- 204 ; vmsc.ssd r7,r9,a0,a1
- 205 ; vmsc.ssd r7,r9,a3,r10
- 206 ; vmsub.ss r6,a2,a4
- 207 ; vmsub.sd r6,a2,a4
- 208 ; vmsub.ss r4,a4,r6
- 209 ; vmsub.sd r4,a4,r6
- 210 ; vrnd.si r4,r6
- 211 ; vrnd.si r4,a0
- 212 ; vrnd.su r4,r6
- 213 ; vrnd.su r4,a0
- 214 ; vrnd.ss r4,r6
- 215 ; vrnd.ss r4,a0
- 216 ; vrnd.sd r4,r6
- 217 ; vrnd.sd r4,a0
- 218 ; vrnd.di r4,r6
- 219 ; vrnd.di r4,a0
- 220 ; vrnd.du r4,r6
- MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995 Texas Instruments Incorporated
-
-regops.s PAGE 5
-
- 221 ; vrnd.du r4,a0
- 222 ; vrnd.ds r4,r6
- 223 ; vrnd.ds r4,a0
- 224 ; vrnd.dd r4,r6
- 225 ; vrnd.dd r4,a0
- 226 ; vrnd.is r4,r6
- 227 ; vrnd.id r4,r6
- 228 ; vrnd.us r4,r6
- 229 ; vrnd.ud r4,r6
- 230 ; vst.s r6
- 231 ; vst.d r6
- 232 ; vsub.ss r2,r4,r6
- 233 ; vsub.sd r2,r4,r6
- 234 ; vsub.dd r2,r4,r6
- 235 000002C4 0170A006 wrcr r6,r5
- 236 000002C8 39B32005 xnor r5,r6,r7
- 237 000002CC 4A32C007 xor r7,r8,r9
-
- No Errors, No Warnings
+MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 1 + + 1 ;; Simple register forms + 2 ;; Those instructions which also use an immediate just use a constant. + 3 + 4 00000000 .text + 5 + 6 00000000 293B0003 add r3,r4,r5 + 7 00000004 293B2003 addu r3,r4,r5 + 8 00000008 11322005 and r5,r4,r2 + 9 0000000C 11322005 and.tt r5,r4,r2 + 10 00000010 7333000A and.ff r10,r12,r14 + 11 00000014 7332800A and.ft r10,r12,r14 + 12 00000018 7332400A and.tf r10,r12,r14 + 13 0000001C 1A39400A bbo r10,r8,lo.w + 14 00000020 FA39600A bbo.a r10,r8,eq.b + 15 00000024 2239000A bbz r10,r8,ls.w + 16 00000028 2A39200A bbz.a r10,r8,hi.w + 17 0000002C 21B98004 bcnd r4,r6,lt0.b + 18 00000030 21B9A004 bcnd.a r4,r6,lt0.b + 19 00000034 00390006 br r6 + 20 00000038 00392006 br.a r6 + 21 0000003C 0003000A brcr 10 + 22 00000040 F8380006 bsr r6,r31 + 23 00000044 F8382006 bsr.a r6,r31 + 24 00000048 00304007 cmnd r7 + 25 0000004C 293A0003 cmp r3,r4,r5 + 26 00000050 02B70008 dcachec r8(r10) + 27 00000054 0AB70008 dcachef r8(r10) + 28 00000058 41B40404 dld.b r4(r6),r8 + 29 0000005C 41B42404 dld.h r4(r6),r8 + 30 00000060 41B44404 dld r4(r6),r8 + 31 00000064 41B46404 dld.d r4(r6),r8 + 32 00000068 41B50404 dld.ub r4(r6),r8 + 33 0000006C 41B52404 dld.uh r4(r6),r8 + 34 00000070 41B60404 dst.b r4(r6),r8 + 35 00000074 41B62404 dst.h r4(r6),r8 + 36 00000078 41B64404 dst r4(r6),r8 + 37 0000007C 41B66404 dst.d r4(r6),r8 + 38 00000080 08302005 etrap r5 + 39 00000084 317147E3 exts r3,31,r5,r6 + 40 00000088 497107C2 extu r2,30,r5,r9 + 41 0000008C 313E0002 fadd.sss r2,r4,r6 + 42 00000090 313E0202 fadd.ssd r2,r4,r6 + 43 00000094 313E0282 fadd.sdd r2,r4,r6 + 44 00000098 313E0222 fadd.dsd r2,r4,r6 + 45 0000009C 313E02A2 fadd.ddd r2,r4,r6 + 46 000000A0 41BEA004 fcmp.ss r4,r6,r8 + 47 000000A4 41BEA084 fcmp.sd r4,r6,r8 + 48 000000A8 41BEA024 fcmp.ds r4,r6,r8 + 49 000000AC 41BEA0A4 fcmp.dd r4,r6,r8 + 50 000000B0 313E6002 fdiv.sss r2,r4,r6 + 51 000000B4 313E6202 fdiv.ssd r2,r4,r6 + 52 000000B8 313E6282 fdiv.sdd r2,r4,r6 + 53 000000BC 313E6222 fdiv.dsd r2,r4,r6 + 54 000000C0 313E62A2 fdiv.ddd r2,r4,r6 + 55 000000C4 313E4002 fmpy.sss r2,r4,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 2 + + 56 000000C8 313E4202 fmpy.ssd r2,r4,r6 + 57 000000CC 313E4282 fmpy.sdd r2,r4,r6 + 58 000000D0 313E4222 fmpy.dsd r2,r4,r6 + 59 000000D4 313E42A2 fmpy.ddd r2,r4,r6 + 60 000000D8 313E4542 fmpy.iii r2,r4,r6 + 61 000000DC 313E47E2 fmpy.uuu r2,r4,r6 + 62 000000E0 303E8184 frndm.ss r4,r6 + 63 000000E4 303E8384 frndm.sd r4,r6 + 64 000000E8 303E8584 frndm.si r4,r6 + 65 000000EC 303E8784 frndm.su r4,r6 + 66 000000F0 403E81A2 frndm.ds r2,r8 + 67 000000F4 403E83A2 frndm.dd r2,r8 + 68 000000F8 403E85A2 frndm.di r2,r8 + 69 000000FC 403E87A2 frndm.du r2,r8 + 70 00000100 303E81C4 frndm.is r4,r6 + 71 00000104 303E83C4 frndm.id r4,r6 + 72 00000108 403E81E2 frndm.us r2,r8 + 73 0000010C 403E83E2 frndm.ud r2,r8 + 74 00000110 303E8004 frndn.ss r4,r6 + 75 00000114 303E8204 frndn.sd r4,r6 + 76 00000118 303E8404 frndn.si r4,r6 + 77 0000011C 303E8604 frndn.su r4,r6 + 78 00000120 403E8022 frndn.ds r2,r8 + 79 00000124 403E8222 frndn.dd r2,r8 + 80 00000128 403E8422 frndn.di r2,r8 + 81 0000012C 403E8622 frndn.du r2,r8 + 82 00000130 303E8044 frndn.is r4,r6 + 83 00000134 303E8244 frndn.id r4,r6 + 84 00000138 403E8062 frndn.us r2,r8 + 85 0000013C 403E8262 frndn.ud r2,r8 + 86 00000140 303E8104 frndp.ss r4,r6 + 87 00000144 303E8304 frndp.sd r4,r6 + 88 00000148 303E8504 frndp.si r4,r6 + 89 0000014C 303E8704 frndp.su r4,r6 + 90 00000150 403E8122 frndp.ds r2,r8 + 91 00000154 403E8322 frndp.dd r2,r8 + 92 00000158 403E8522 frndp.di r2,r8 + 93 0000015C 403E8722 frndp.du r2,r8 + 94 00000160 303E8144 frndp.is r4,r6 + 95 00000164 303E8344 frndp.id r4,r6 + 96 00000168 403E8162 frndp.us r2,r8 + 97 0000016C 403E8362 frndp.ud r2,r8 + 98 00000170 303E8084 frndz.ss r4,r6 + 99 00000174 303E8284 frndz.sd r4,r6 + 100 00000178 303E8484 frndz.si r4,r6 + 101 0000017C 303E8684 frndz.su r4,r6 + 102 00000180 403E80A2 frndz.ds r2,r8 + 103 00000184 403E82A2 frndz.dd r2,r8 + 104 00000188 403E84A2 frndz.di r2,r8 + 105 0000018C 403E86A2 frndz.du r2,r8 + 106 00000190 303E80C4 frndz.is r4,r6 + 107 00000194 303E82C4 frndz.id r4,r6 + 108 00000198 403E80E2 frndz.us r2,r8 + 109 0000019C 403E82E2 frndz.ud r2,r8 + 110 000001A0 403EE006 fsqrt.ss r6,r8 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 3 + + 111 000001A4 403EE206 fsqrt.sd r6,r8 + 112 000001A8 403EE226 fsqrt.dd r6,r8 + 113 000001AC 313E2002 fsub.sss r2,r4,r6 + 114 000001B0 313E2202 fsub.ssd r2,r4,r6 + 115 000001B4 313E2282 fsub.sdd r2,r4,r6 + 116 000001B8 313E2222 fsub.dsd r2,r4,r6 + 117 000001BC 313E22A2 fsub.ddd r2,r4,r6 + 118 000001C0 5231E3E4 ins r4,31,r8,r10 + 119 000001C4 41B88004 jsr r4(r6),r8 + 120 000001C8 41B8A004 jsr.a r4(r6),r8 + 121 000001CC 41B40004 ld.b r4(r6),r8 + 122 000001D0 41B42004 ld.h r4(r6),r8 + 123 000001D4 41B44004 ld r4(r6),r8 + 124 000001D8 41B46004 ld.d r4(r6),r8 + 125 000001DC 41B50004 ld.ub r4(r6),r8 + 126 000001E0 41B52004 ld.uh r4(r6),r8 + 127 000001E4 41FF0007 lmo r7,r8 + 128 000001E8 18B2E001 or r1,r2,r3 + 129 000001EC 18B2E001 or.tt r1,r2,r3 + 130 000001F0 18B3C001 or.ff r1,r2,r3 + 131 000001F4 18B3A001 or.ft r1,r2,r3 + 132 000001F8 18B36001 or.tf r1,r2,r3 + 133 000001FC 20308006 rdcr r6,r4 + 134 00000200 293F2004 rmo r4,r5 + 135 00000204 523103E2 rotl r2,31,r8,r10 + 136 00000208 30B107E8 rotr r8,31,r2,r6 + 137 0000020C 30B1C3E4 shl r4,31,r2,r6 + 138 00000210 31710184 sl.dz r4,12,r5,r6 + 139 00000214 31712184 sl.dm r4,12,r5,r6 + 140 00000218 31714184 sl.ds r4,12,r5,r6 + 141 0000021C 31716184 sl.ez r4,12,r5,r6 + 142 00000220 31718184 sl.em r4,12,r5,r6 + 143 00000224 3171A184 sl.es r4,12,r5,r6 + 144 00000228 3171C184 sl.iz r4,12,r5,r6 + 145 0000022C 3171E184 sl.im r4,12,r5,r6 + 146 00000230 31710984 sli.dz r4,12,r5,r6 + 147 00000234 31712984 sli.dm r4,12,r5,r6 + 148 00000238 31714984 sli.ds r4,12,r5,r6 + 149 0000023C 31716984 sli.ez r4,12,r5,r6 + 150 00000240 31718984 sli.em r4,12,r5,r6 + 151 00000244 3171A984 sli.es r4,12,r5,r6 + 152 00000248 3171C984 sli.iz r4,12,r5,r6 + 153 0000024C 3171E984 sli.im r4,12,r5,r6 + 154 00000250 31710584 sr.dz r4,12,r5,r6 + 155 00000254 31712584 sr.dm r4,12,r5,r6 + 156 00000258 31714584 sr.ds r4,12,r5,r6 + 157 0000025C 31716584 sr.ez r4,12,r5,r6 + 158 00000260 31718584 sr.em r4,12,r5,r6 + 159 00000264 3171A584 sr.es r4,12,r5,r6 + 160 00000268 3171C584 sr.iz r4,12,r5,r6 + 161 0000026C 3171E584 sr.im r4,12,r5,r6 + 162 00000270 41B1A404 sra r4,32,r6,r8 + 163 00000274 31710D84 sri.dz r4,12,r5,r6 + 164 00000278 31712D84 sri.dm r4,12,r5,r6 + 165 0000027C 31714D84 sri.ds r4,12,r5,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 4 + + 166 00000280 31716D84 sri.ez r4,12,r5,r6 + 167 00000284 31718D84 sri.em r4,12,r5,r6 + 168 00000288 3171AD84 sri.es r4,12,r5,r6 + 169 0000028C 3171CD84 sri.iz r4,12,r5,r6 + 170 00000290 3171ED84 sri.im r4,12,r5,r6 + 171 00000294 41B16404 srl r4,32,r6,r8 + 172 00000298 41B60004 st.b r4(r6),r8 + 173 0000029C 41B62004 st.h r4(r6),r8 + 174 000002A0 41B64004 st r4(r6),r8 + 175 000002A4 41B66004 st.d r4(r6),r8 + 176 000002A8 4A3B4007 sub r7,r8,r9 + 177 000002AC 4A3B6007 subu r7,r8,r9 + 178 000002B0 21B0A008 swcr r8,r6,r4 + 179 000002B4 0030200A trap r10 + 180 000002B8 013C0002 vadd.ss r2,r4,r4 + 181 000002BC 01BC0082 vadd.sd r2,r6,r6 + 182 000002C0 02BC00A2 vadd.dd r2,r10,r10 + 183 ; vld0.s r6 + 184 ; vld1.s r7 + 185 ; vld0.d r6 + 186 ; vld1.d r8 + 187 ; vmac.sss r7,r9,0,a3 + 188 ; vmac.sss r7,r9,0,r10 + 189 ; vmac.sss r7,r9,a1,a3 + 190 ; vmac.sss r7,r9,a3,r10 + 191 ; vmac.ssd r7,r9,0,a0 + 192 ; vmac.ssd r7,r9,0,r10 + 193 ; vmac.ssd r7,r9,a1,a2 + 194 ; vmac.ssd r7,r9,a3,r10 + 195 ; vmpy.ss r1,r3,r3 + 196 ; vmpy.sd r5,r6,r6 + 197 ; vmpy.dd r2,r4,r4 + 198 ; vmsc.sss r7,r9,0,a0 + 199 ; vmsc.sss r7,r9,0,r10 + 200 ; vmsc.sss r7,r9,a0,a1 + 201 ; vmsc.sss r7,r9,a3,r10 + 202 ; vmsc.ssd r7,r9,0,a0 + 203 ; vmsc.ssd r7,r9,0,r10 + 204 ; vmsc.ssd r7,r9,a0,a1 + 205 ; vmsc.ssd r7,r9,a3,r10 + 206 ; vmsub.ss r6,a2,a4 + 207 ; vmsub.sd r6,a2,a4 + 208 ; vmsub.ss r4,a4,r6 + 209 ; vmsub.sd r4,a4,r6 + 210 ; vrnd.si r4,r6 + 211 ; vrnd.si r4,a0 + 212 ; vrnd.su r4,r6 + 213 ; vrnd.su r4,a0 + 214 ; vrnd.ss r4,r6 + 215 ; vrnd.ss r4,a0 + 216 ; vrnd.sd r4,r6 + 217 ; vrnd.sd r4,a0 + 218 ; vrnd.di r4,r6 + 219 ; vrnd.di r4,a0 + 220 ; vrnd.du r4,r6 + MVP MP Macro Assembler Version 1.13 Mon Feb 10 17:00:24 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +regops.s PAGE 5 + + 221 ; vrnd.du r4,a0 + 222 ; vrnd.ds r4,r6 + 223 ; vrnd.ds r4,a0 + 224 ; vrnd.dd r4,r6 + 225 ; vrnd.dd r4,a0 + 226 ; vrnd.is r4,r6 + 227 ; vrnd.id r4,r6 + 228 ; vrnd.us r4,r6 + 229 ; vrnd.ud r4,r6 + 230 ; vst.s r6 + 231 ; vst.d r6 + 232 ; vsub.ss r2,r4,r6 + 233 ; vsub.sd r2,r4,r6 + 234 ; vsub.dd r2,r4,r6 + 235 000002C4 0170A006 wrcr r6,r5 + 236 000002C8 39B32005 xnor r5,r6,r7 + 237 000002CC 4A32C007 xor r7,r8,r9 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/relocs1.d b/gas/testsuite/gas/tic80/relocs1.d new file mode 100644 index 0000000..71794e1 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs1.d @@ -0,0 +1,64 @@ +#objdump: -dr +#name: TIc80 simple relocs, global/local funcs & branches + +.*: +file format .*tic80.* + +Disassembly of section .text: + +00000000 <_sfunc>: + 0: f0 ff 6c 08 addu -16,r1,r1 + 4: 0c 00 59 f8 st 12\(r1\),r31 + 8: 00 00 59 10 st 0\(r1\),r2 + c: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 + 10: 00 00 00 00 + 10: 32 _xfunc + 14: 00 00 51 10 ld 0\(r1\),r2 + 18: 0c 00 51 f8 ld 12\(r1\),r31 + 1c: 1f 80 38 00 jsr r31\(r0\),r0 + 20: 10 80 6c 08 addu 16,r1,r1 + +00000024 <_gfunc>: + 24: f0 ff 6c 08 addu -16,r1,r1 + 28: 0c 00 59 f8 st 12\(r1\),r31 + 2c: 00 00 59 10 st 0\(r1\),r2 + 30: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 + 34: 00 00 00 00 + 34: 32 *ABS* + 38: 00 00 51 10 ld 0\(r1\),r2 + 3c: 0c 00 51 f8 ld 12\(r1\),r31 + 40: 1f 80 38 00 jsr r31\(r0\),r0 + 44: 10 80 6c 08 addu 16,r1,r1 + +00000048 <_branches>: + 48: f0 ff 6c 08 addu -16,r1,r1 + 4c: 0c 00 59 f8 st 12\(r1\),r31 + 50: 00 00 59 10 st 0\(r1\),r2 + 54: 00 00 51 10 ld 0\(r1\),r2 + 58: 04 00 59 10 st 4\(r1\),r2 + 5c: 00 00 51 10 ld 0\(r1\),r2 + 60: 04 00 51 18 ld 4\(r1\),r3 + 64: 0a 80 ac 10 addu 10,r2,r2 + 68: 03 00 ba 10 cmp r3,r2,r2 + 6c: 12 80 a5 30 bbo\.a b4 <_branches+6c>,r2,ge\.f + 70: 04 00 51 10 ld 4\(r1\),r2 + 74: 05 80 a4 f8 bbz\.a 88 <_branches+40>,r2,eq\.b + 78: 00 90 38 f8 jsr 24 <_gfunc>\(r0\),r31 + 7c: 24 00 00 00 + 7c: 32 *ABS* + 80: 04 00 51 10 ld 4\(r1\),r2 + 84: 04 80 24 00 br\.a 94 <_branches+4c> + 88: 00 90 38 f8 jsr 0 <_sfunc>\(r0\),r31 + 8c: 00 00 00 00 + 8c: 32 _xfunc + 90: 04 00 51 10 ld 4\(r1\),r2 + 94: 04 00 51 10 ld 4\(r1\),r2 + 98: 01 80 ac 10 addu 1,r2,r2 + 9c: 04 00 59 10 st 4\(r1\),r2 + a0: 00 00 51 18 ld 0\(r1\),r3 + a4: 04 00 51 10 ld 4\(r1\),r2 + a8: 0a 80 ec 18 addu 10,r3,r3 + ac: 02 00 fa 10 cmp r2,r3,r2 + b0: f0 ff a5 38 bbo\.a 70 <_branches+28>,r2,lt\.f + b4: 0c 00 51 f8 ld 12\(r1\),r31 + b8: 1f 80 38 00 jsr r31\(r0\),r0 + bc: 10 80 6c 08 addu 16,r1,r1 diff --git a/gas/testsuite/gas/tic80/relocs1.lst b/gas/testsuite/gas/tic80/relocs1.lst new file mode 100644 index 0000000..9faeb1a --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs1.lst @@ -0,0 +1,80 @@ +MVP MP Macro Assembler Version 1.13 Sat Feb 22 13:19:28 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +relocs1.s PAGE 1 + + 1 ;; This is the hand hacked output of the TI C compiler for a simple + 2 ;; test program that contains local/global functions, local/global + 3 ;; function calls, and an "if" and "for" statement. + 4 + 5 .global _xfunc + 6 + 7 00000000 _sfunc: + 8 00000000 086CFFF0 addu -16,r1,r1 + 9 00000004 F859000C st 12(r1),r31 + 10 00000008 10590000 st 0(r1),r2 + 11 0000000C F8389000 jsr _xfunc(r0),r31 + 00000010 00000000 + 12 00000014 10510000 ld 0(r1),r2 + 13 00000018 F851000C ld 12(r1),r31 + 14 0000001C 0038801F jsr r31(r0),r0 + 15 00000020 086C8010 addu 16,r1,r1 + 16 + 17 .global _gfunc + 18 + 19 00000024 _gfunc: + 20 00000024 086CFFF0 addu -16,r1,r1 + 21 00000028 F859000C st 12(r1),r31 + 22 0000002C 10590000 st 0(r1),r2 + 23 00000030 F8389000 jsr _sfunc(r0),r31 + 00000034 00000000 + 24 00000038 10510000 ld 0(r1),r2 + 25 0000003C F851000C ld 12(r1),r31 + 26 00000040 0038801F jsr r31(r0),r0 + 27 00000044 086C8010 addu 16,r1,r1 + 28 + 29 + 30 .global _branches + 31 + 32 00000048 _branches: + 33 00000048 086CFFF0 addu -16,r1,r1 + 34 0000004C F859000C st 12(r1),r31 + 35 00000050 10590000 st 0(r1),r2 + 36 00000054 10510000 ld 0(r1),r2 + 37 00000058 10590004 st 4(r1),r2 + 38 0000005C 10510000 ld 0(r1),r2 + 39 00000060 18510004 ld 4(r1),r3 + 40 00000064 10AC800A addu 10,r2,r2 + 41 00000068 10BA0003 cmp r3,r2,r2 + 42 0000006C 30A58012 bbo.a L12,r2,ge.w + 43 00000070 L8: + 44 00000070 10510004 ld 4(r1),r2 + 45 00000074 F8A48005 bbz.a L10,r2,0 + 46 00000078 F8389000 jsr _gfunc(r0),r31 + 0000007C 00000024 + 47 00000080 10510004 ld 4(r1),r2 + 48 00000084 00248004 br.a L11 + 49 00000088 L10: + 50 00000088 F8389000 jsr _xfunc(r0),r31 + 0000008C 00000000 + 51 00000090 10510004 ld 4(r1),r2 + MVP MP Macro Assembler Version 1.13 Sat Feb 22 13:19:28 1997 +Copyright (c) 1993-1995 Texas Instruments Incorporated + +relocs1.s PAGE 2 + + 52 00000094 L11: + 53 00000094 10510004 ld 4(r1),r2 + 54 00000098 10AC8001 addu 1,r2,r2 + 55 0000009C 10590004 st 4(r1),r2 + 56 000000A0 18510000 ld 0(r1),r3 + 57 000000A4 10510004 ld 4(r1),r2 + 58 000000A8 18EC800A addu 10,r3,r3 + 59 000000AC 10FA0002 cmp r2,r3,r2 + 60 000000B0 38A5FFF0 bbo.a L8,r2,lt.w + 61 000000B4 L12: + 62 000000B4 F851000C ld 12(r1),r31 + 63 000000B8 0038801F jsr r31(r0),r0 + 64 000000BC 086C8010 addu 16,r1,r1 + + No Errors, No Warnings diff --git a/gas/testsuite/gas/tic80/relocs1.s b/gas/testsuite/gas/tic80/relocs1.s new file mode 100644 index 0000000..149e395 --- /dev/null +++ b/gas/testsuite/gas/tic80/relocs1.s @@ -0,0 +1,66 @@ +;; This is the hand hacked output of the TI C compiler for a simple +;; test program that contains local/global functions, local/global +;; function calls, and an "if" and "for" statement. + + .file "relocs1.s" + + .global _xfunc + +_sfunc: + addu -16,r1,r1 + st 12(r1),r31 + st 0(r1),r2 + jsr _xfunc(r0),r31 + ld 0(r1),r2 + ld 12(r1),r31 + jsr r31(r0),r0 + addu 16,r1,r1 + + .global _gfunc + +_gfunc: + addu -16,r1,r1 + st 12(r1),r31 + st 0(r1),r2 + jsr _sfunc(r0),r31 + ld 0(r1),r2 + ld 12(r1),r31 + jsr r31(r0),r0 + addu 16,r1,r1 + + + .global _branches + +_branches: + addu -16,r1,r1 + st 12(r1),r31 + st 0(r1),r2 + ld 0(r1),r2 + st 4(r1),r2 + ld 0(r1),r2 + ld 4(r1),r3 + addu 10,r2,r2 + cmp r3,r2,r2 + bbo.a L12,r2,ge.w +L8: + ld 4(r1),r2 + bbz.a L10,r2,0 + jsr _gfunc(r0),r31 + ld 4(r1),r2 + br.a L11 +L10: + jsr _xfunc(r0),r31 + ld 4(r1),r2 +L11: + ld 4(r1),r2 + addu 1,r2,r2 + st 4(r1),r2 + ld 0(r1),r3 + ld 4(r1),r2 + addu 10,r3,r3 + cmp r2,r3,r2 + bbo.a L8,r2,lt.w +L12: + ld 12(r1),r31 + jsr r31(r0),r0 + addu 16,r1,r1 diff --git a/gas/testsuite/gas/tic80/tic80.exp b/gas/testsuite/gas/tic80/tic80.exp index 2d55777..5d2ec6e 100644 --- a/gas/testsuite/gas/tic80/tic80.exp +++ b/gas/testsuite/gas/tic80/tic80.exp @@ -9,4 +9,5 @@ if [istarget tic80*-*-*] then { run_dump_test "bitnum" run_dump_test "ccode" run_dump_test "add" + run_dump_test "relocs1" } |