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| author | Jie Zhang <jie.zhang@analog.com> | 2010-08-25 05:25:09 +0000 |
|---|---|---|
| committer | Jie Zhang <jie.zhang@analog.com> | 2010-08-25 05:25:09 +0000 |
| commit | 23a10334b22d9edadb33826da1d193121f2eda93 (patch) | |
| tree | fd373763dbdf319aaf73adb4ca6ee9702bf694aa /gas/testsuite | |
| parent | 673bfd454bcb059022eb237ccae068c6a4446e49 (diff) | |
| download | gdb-23a10334b22d9edadb33826da1d193121f2eda93.zip gdb-23a10334b22d9edadb33826da1d193121f2eda93.tar.gz gdb-23a10334b22d9edadb33826da1d193121f2eda93.tar.bz2 | |
* config/tc-arm.c (encode_arm_addr_mode_2): Fix
BAD_PC_ADDRESSING condition.
testsuite/
* gas/arm/ldst-pc.d: New test.
* gas/arm/ldst-pc.s: New test.
* gas/arm/sp-pc-validations-bad.s: `str r0,[pc,#4]' is valid.
* gas/arm/sp-pc-validations-bad.l: Adjust accordingly.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/ldst-pc.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/ldst-pc.s | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/sp-pc-validations-bad.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/sp-pc-validations-bad.s | 4 |
5 files changed, 40 insertions, 3 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 449e138..4c5e015 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2010-08-25 Jie Zhang <jie@codesourcery.com> + + * gas/arm/ldst-pc.d: New test. + * gas/arm/ldst-pc.s: New test. + * gas/arm/sp-pc-validations-bad.s: `str r0,[pc,#4]' is valid. + * gas/arm/sp-pc-validations-bad.l: Adjust accordingly. + 2010-08-17 Roland McGrath <roland@redhat.com> * gas/elf/groupauto.s: New file. diff --git a/gas/testsuite/gas/arm/ldst-pc.d b/gas/testsuite/gas/arm/ldst-pc.d new file mode 100644 index 0000000..333d8a0 --- /dev/null +++ b/gas/testsuite/gas/arm/ldst-pc.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM load/store with pc base register +#as: -mno-warn-deprecated + +# Test the standard ARM instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> e51f1008 ldr r1, \[pc, #-8\] ; 0+000 <[^>]*> +0+004 <[^>]*> e79f1002 ldr r1, \[pc, r2\] +0+008 <[^>]*> f55ff008 pld \[pc, #-8\] ; 0+008 <[^>]*> +0+00c <[^>]*> f7dff001 pld \[pc, r1\] +0+010 <[^>]*> f45ff008 pli \[pc, #-8\] ; 0+010 <[^>]*> +0+014 <[^>]*> f6dff001 pli \[pc, r1\] +0+018 <[^>]*> e58f1004 str r1, \[pc, #4\] ; 0+024 <[^>]*> diff --git a/gas/testsuite/gas/arm/ldst-pc.s b/gas/testsuite/gas/arm/ldst-pc.s new file mode 100644 index 0000000..eac55fa --- /dev/null +++ b/gas/testsuite/gas/arm/ldst-pc.s @@ -0,0 +1,15 @@ +@ Test file for ARM load/store instructions with pc as the base register + + .text + .syntax unified + .align 2 + ldr r1, [pc, #-8] + ldr r1, [pc, r2] + + pld [pc, #-8] + pld [pc, r1] + + pli [pc, #-8] + pli [pc, r1] + + str r1, [pc, #4] diff --git a/gas/testsuite/gas/arm/sp-pc-validations-bad.l b/gas/testsuite/gas/arm/sp-pc-validations-bad.l index 002dbb2..048841f 100644 --- a/gas/testsuite/gas/arm/sp-pc-validations-bad.l +++ b/gas/testsuite/gas/arm/sp-pc-validations-bad.l @@ -101,7 +101,6 @@ [^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL#4' [^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4' [^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL#4' -[^:]*:165: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]' [^:]*:166: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc\],#4' [^:]*:167: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]!' [^:]*:170: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]' diff --git a/gas/testsuite/gas/arm/sp-pc-validations-bad.s b/gas/testsuite/gas/arm/sp-pc-validations-bad.s index 94ecdac..70c7bb0 100644 --- a/gas/testsuite/gas/arm/sp-pc-validations-bad.s +++ b/gas/testsuite/gas/arm/sp-pc-validations-bad.s @@ -159,11 +159,11 @@ ldrt pc,[r0],r1, LSL #4 @ ditto ldrt r0,[pc],r1, LSL #4 @ ditto ldrt r0,[r1],pc, LSL #4 @ ditto + @ Stores, ARM ================================================================ @ STR (immediate, ARM) -str r0,[pc,#4] @ Unpredictable -str r0,[pc],#4 @ ditto +str r0,[pc],#4 @ Unpredictable str r0,[pc,#4]! @ ditto @ STR (register) |